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1.1 root 1: /*
2: * QEMU Sun4m iommu emulation
3: *
4: * Copyright (c) 2003-2005 Fabrice Bellard
5: *
6: * Permission is hereby granted, free of charge, to any person obtaining a copy
7: * of this software and associated documentation files (the "Software"), to deal
8: * in the Software without restriction, including without limitation the rights
9: * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10: * copies of the Software, and to permit persons to whom the Software is
11: * furnished to do so, subject to the following conditions:
12: *
13: * The above copyright notice and this permission notice shall be included in
14: * all copies or substantial portions of the Software.
15: *
16: * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17: * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18: * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19: * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20: * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21: * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22: * THE SOFTWARE.
23: */
24:
25: #include "sun4m.h"
26: #include "sysbus.h"
1.1.1.2 root 27: #include "trace.h"
1.1 root 28:
29: /*
30: * I/O MMU used by Sun4m systems
31: *
32: * Chipset docs:
33: * "Sun-4M System Architecture (revision 2.0) by Chuck Narad", 950-1373-01,
34: * http://mediacast.sun.com/users/Barton808/media/Sun4M_SystemArchitecture_edited2.pdf
35: */
36:
37: #define IOMMU_NREGS (4*4096/4)
38: #define IOMMU_CTRL (0x0000 >> 2)
39: #define IOMMU_CTRL_IMPL 0xf0000000 /* Implementation */
40: #define IOMMU_CTRL_VERS 0x0f000000 /* Version */
41: #define IOMMU_CTRL_RNGE 0x0000001c /* Mapping RANGE */
42: #define IOMMU_RNGE_16MB 0x00000000 /* 0xff000000 -> 0xffffffff */
43: #define IOMMU_RNGE_32MB 0x00000004 /* 0xfe000000 -> 0xffffffff */
44: #define IOMMU_RNGE_64MB 0x00000008 /* 0xfc000000 -> 0xffffffff */
45: #define IOMMU_RNGE_128MB 0x0000000c /* 0xf8000000 -> 0xffffffff */
46: #define IOMMU_RNGE_256MB 0x00000010 /* 0xf0000000 -> 0xffffffff */
47: #define IOMMU_RNGE_512MB 0x00000014 /* 0xe0000000 -> 0xffffffff */
48: #define IOMMU_RNGE_1GB 0x00000018 /* 0xc0000000 -> 0xffffffff */
49: #define IOMMU_RNGE_2GB 0x0000001c /* 0x80000000 -> 0xffffffff */
50: #define IOMMU_CTRL_ENAB 0x00000001 /* IOMMU Enable */
51: #define IOMMU_CTRL_MASK 0x0000001d
52:
53: #define IOMMU_BASE (0x0004 >> 2)
54: #define IOMMU_BASE_MASK 0x07fffc00
55:
56: #define IOMMU_TLBFLUSH (0x0014 >> 2)
57: #define IOMMU_TLBFLUSH_MASK 0xffffffff
58:
59: #define IOMMU_PGFLUSH (0x0018 >> 2)
60: #define IOMMU_PGFLUSH_MASK 0xffffffff
61:
62: #define IOMMU_AFSR (0x1000 >> 2)
63: #define IOMMU_AFSR_ERR 0x80000000 /* LE, TO, or BE asserted */
64: #define IOMMU_AFSR_LE 0x40000000 /* SBUS reports error after
65: transaction */
66: #define IOMMU_AFSR_TO 0x20000000 /* Write access took more than
67: 12.8 us. */
68: #define IOMMU_AFSR_BE 0x10000000 /* Write access received error
69: acknowledge */
70: #define IOMMU_AFSR_SIZE 0x0e000000 /* Size of transaction causing error */
71: #define IOMMU_AFSR_S 0x01000000 /* Sparc was in supervisor mode */
72: #define IOMMU_AFSR_RESV 0x00800000 /* Reserved, forced to 0x8 by
73: hardware */
74: #define IOMMU_AFSR_ME 0x00080000 /* Multiple errors occurred */
75: #define IOMMU_AFSR_RD 0x00040000 /* A read operation was in progress */
76: #define IOMMU_AFSR_FAV 0x00020000 /* IOMMU afar has valid contents */
77: #define IOMMU_AFSR_MASK 0xff0fffff
78:
79: #define IOMMU_AFAR (0x1004 >> 2)
80:
81: #define IOMMU_AER (0x1008 >> 2) /* Arbiter Enable Register */
82: #define IOMMU_AER_EN_P0_ARB 0x00000001 /* MBus master 0x8 (Always 1) */
83: #define IOMMU_AER_EN_P1_ARB 0x00000002 /* MBus master 0x9 */
84: #define IOMMU_AER_EN_P2_ARB 0x00000004 /* MBus master 0xa */
85: #define IOMMU_AER_EN_P3_ARB 0x00000008 /* MBus master 0xb */
86: #define IOMMU_AER_EN_0 0x00010000 /* SBus slot 0 */
87: #define IOMMU_AER_EN_1 0x00020000 /* SBus slot 1 */
88: #define IOMMU_AER_EN_2 0x00040000 /* SBus slot 2 */
89: #define IOMMU_AER_EN_3 0x00080000 /* SBus slot 3 */
90: #define IOMMU_AER_EN_F 0x00100000 /* SBus on-board */
91: #define IOMMU_AER_SBW 0x80000000 /* S-to-M asynchronous writes */
92: #define IOMMU_AER_MASK 0x801f000f
93:
94: #define IOMMU_SBCFG0 (0x1010 >> 2) /* SBUS configration per-slot */
95: #define IOMMU_SBCFG1 (0x1014 >> 2) /* SBUS configration per-slot */
96: #define IOMMU_SBCFG2 (0x1018 >> 2) /* SBUS configration per-slot */
97: #define IOMMU_SBCFG3 (0x101c >> 2) /* SBUS configration per-slot */
98: #define IOMMU_SBCFG_SAB30 0x00010000 /* Phys-address bit 30 when
99: bypass enabled */
100: #define IOMMU_SBCFG_BA16 0x00000004 /* Slave supports 16 byte bursts */
101: #define IOMMU_SBCFG_BA8 0x00000002 /* Slave supports 8 byte bursts */
102: #define IOMMU_SBCFG_BYPASS 0x00000001 /* Bypass IOMMU, treat all addresses
103: produced by this device as pure
104: physical. */
105: #define IOMMU_SBCFG_MASK 0x00010003
106:
107: #define IOMMU_ARBEN (0x2000 >> 2) /* SBUS arbitration enable */
108: #define IOMMU_ARBEN_MASK 0x001f0000
109: #define IOMMU_MID 0x00000008
110:
111: #define IOMMU_MASK_ID (0x3018 >> 2) /* Mask ID */
112: #define IOMMU_MASK_ID_MASK 0x00ffffff
113:
114: #define IOMMU_MSII_MASK 0x26000000 /* microSPARC II mask number */
115: #define IOMMU_TS_MASK 0x23000000 /* turboSPARC mask number */
116:
117: /* The format of an iopte in the page tables */
118: #define IOPTE_PAGE 0xffffff00 /* Physical page number (PA[35:12]) */
119: #define IOPTE_CACHE 0x00000080 /* Cached (in vme IOCACHE or
120: Viking/MXCC) */
1.1.1.3 root 121: #define IOPTE_WRITE 0x00000004 /* Writable */
1.1 root 122: #define IOPTE_VALID 0x00000002 /* IOPTE is valid */
123: #define IOPTE_WAZ 0x00000001 /* Write as zeros */
124:
125: #define IOMMU_PAGE_SHIFT 12
126: #define IOMMU_PAGE_SIZE (1 << IOMMU_PAGE_SHIFT)
127: #define IOMMU_PAGE_MASK ~(IOMMU_PAGE_SIZE - 1)
128:
129: typedef struct IOMMUState {
130: SysBusDevice busdev;
1.1.1.5 ! root 131: MemoryRegion iomem;
1.1 root 132: uint32_t regs[IOMMU_NREGS];
133: target_phys_addr_t iostart;
134: qemu_irq irq;
1.1.1.4 root 135: uint32_t version;
1.1 root 136: } IOMMUState;
137:
1.1.1.5 ! root 138: static uint64_t iommu_mem_read(void *opaque, target_phys_addr_t addr,
! 139: unsigned size)
1.1 root 140: {
141: IOMMUState *s = opaque;
142: target_phys_addr_t saddr;
143: uint32_t ret;
144:
145: saddr = addr >> 2;
146: switch (saddr) {
147: default:
148: ret = s->regs[saddr];
149: break;
150: case IOMMU_AFAR:
151: case IOMMU_AFSR:
152: ret = s->regs[saddr];
153: qemu_irq_lower(s->irq);
154: break;
155: }
1.1.1.2 root 156: trace_sun4m_iommu_mem_readl(saddr, ret);
1.1 root 157: return ret;
158: }
159:
1.1.1.5 ! root 160: static void iommu_mem_write(void *opaque, target_phys_addr_t addr,
! 161: uint64_t val, unsigned size)
1.1 root 162: {
163: IOMMUState *s = opaque;
164: target_phys_addr_t saddr;
165:
166: saddr = addr >> 2;
1.1.1.2 root 167: trace_sun4m_iommu_mem_writel(saddr, val);
1.1 root 168: switch (saddr) {
169: case IOMMU_CTRL:
170: switch (val & IOMMU_CTRL_RNGE) {
171: case IOMMU_RNGE_16MB:
172: s->iostart = 0xffffffffff000000ULL;
173: break;
174: case IOMMU_RNGE_32MB:
175: s->iostart = 0xfffffffffe000000ULL;
176: break;
177: case IOMMU_RNGE_64MB:
178: s->iostart = 0xfffffffffc000000ULL;
179: break;
180: case IOMMU_RNGE_128MB:
181: s->iostart = 0xfffffffff8000000ULL;
182: break;
183: case IOMMU_RNGE_256MB:
184: s->iostart = 0xfffffffff0000000ULL;
185: break;
186: case IOMMU_RNGE_512MB:
187: s->iostart = 0xffffffffe0000000ULL;
188: break;
189: case IOMMU_RNGE_1GB:
190: s->iostart = 0xffffffffc0000000ULL;
191: break;
192: default:
193: case IOMMU_RNGE_2GB:
194: s->iostart = 0xffffffff80000000ULL;
195: break;
196: }
1.1.1.2 root 197: trace_sun4m_iommu_mem_writel_ctrl(s->iostart);
1.1 root 198: s->regs[saddr] = ((val & IOMMU_CTRL_MASK) | s->version);
199: break;
200: case IOMMU_BASE:
201: s->regs[saddr] = val & IOMMU_BASE_MASK;
202: break;
203: case IOMMU_TLBFLUSH:
1.1.1.2 root 204: trace_sun4m_iommu_mem_writel_tlbflush(val);
1.1 root 205: s->regs[saddr] = val & IOMMU_TLBFLUSH_MASK;
206: break;
207: case IOMMU_PGFLUSH:
1.1.1.2 root 208: trace_sun4m_iommu_mem_writel_pgflush(val);
1.1 root 209: s->regs[saddr] = val & IOMMU_PGFLUSH_MASK;
210: break;
211: case IOMMU_AFAR:
212: s->regs[saddr] = val;
213: qemu_irq_lower(s->irq);
214: break;
215: case IOMMU_AER:
216: s->regs[saddr] = (val & IOMMU_AER_MASK) | IOMMU_AER_EN_P0_ARB;
217: break;
218: case IOMMU_AFSR:
219: s->regs[saddr] = (val & IOMMU_AFSR_MASK) | IOMMU_AFSR_RESV;
220: qemu_irq_lower(s->irq);
221: break;
222: case IOMMU_SBCFG0:
223: case IOMMU_SBCFG1:
224: case IOMMU_SBCFG2:
225: case IOMMU_SBCFG3:
226: s->regs[saddr] = val & IOMMU_SBCFG_MASK;
227: break;
228: case IOMMU_ARBEN:
229: // XXX implement SBus probing: fault when reading unmapped
230: // addresses, fault cause and address stored to MMU/IOMMU
231: s->regs[saddr] = (val & IOMMU_ARBEN_MASK) | IOMMU_MID;
232: break;
233: case IOMMU_MASK_ID:
234: s->regs[saddr] |= val & IOMMU_MASK_ID_MASK;
235: break;
236: default:
237: s->regs[saddr] = val;
238: break;
239: }
240: }
241:
1.1.1.5 ! root 242: static const MemoryRegionOps iommu_mem_ops = {
! 243: .read = iommu_mem_read,
! 244: .write = iommu_mem_write,
! 245: .endianness = DEVICE_NATIVE_ENDIAN,
! 246: .valid = {
! 247: .min_access_size = 4,
! 248: .max_access_size = 4,
! 249: },
1.1 root 250: };
251:
252: static uint32_t iommu_page_get_flags(IOMMUState *s, target_phys_addr_t addr)
253: {
254: uint32_t ret;
255: target_phys_addr_t iopte;
256: target_phys_addr_t pa = addr;
257:
258: iopte = s->regs[IOMMU_BASE] << 4;
259: addr &= ~s->iostart;
260: iopte += (addr >> (IOMMU_PAGE_SHIFT - 2)) & ~3;
261: cpu_physical_memory_read(iopte, (uint8_t *)&ret, 4);
262: tswap32s(&ret);
1.1.1.2 root 263: trace_sun4m_iommu_page_get_flags(pa, iopte, ret);
1.1 root 264: return ret;
265: }
266:
267: static target_phys_addr_t iommu_translate_pa(target_phys_addr_t addr,
268: uint32_t pte)
269: {
270: target_phys_addr_t pa;
271:
272: pa = ((pte & IOPTE_PAGE) << 4) + (addr & ~IOMMU_PAGE_MASK);
1.1.1.2 root 273: trace_sun4m_iommu_translate_pa(addr, pa, pte);
1.1 root 274: return pa;
275: }
276:
277: static void iommu_bad_addr(IOMMUState *s, target_phys_addr_t addr,
278: int is_write)
279: {
1.1.1.2 root 280: trace_sun4m_iommu_bad_addr(addr);
1.1 root 281: s->regs[IOMMU_AFSR] = IOMMU_AFSR_ERR | IOMMU_AFSR_LE | IOMMU_AFSR_RESV |
282: IOMMU_AFSR_FAV;
283: if (!is_write)
284: s->regs[IOMMU_AFSR] |= IOMMU_AFSR_RD;
285: s->regs[IOMMU_AFAR] = addr;
286: qemu_irq_raise(s->irq);
287: }
288:
289: void sparc_iommu_memory_rw(void *opaque, target_phys_addr_t addr,
290: uint8_t *buf, int len, int is_write)
291: {
292: int l;
293: uint32_t flags;
294: target_phys_addr_t page, phys_addr;
295:
296: while (len > 0) {
297: page = addr & IOMMU_PAGE_MASK;
298: l = (page + IOMMU_PAGE_SIZE) - addr;
299: if (l > len)
300: l = len;
301: flags = iommu_page_get_flags(opaque, page);
302: if (!(flags & IOPTE_VALID)) {
303: iommu_bad_addr(opaque, page, is_write);
304: return;
305: }
306: phys_addr = iommu_translate_pa(addr, flags);
307: if (is_write) {
308: if (!(flags & IOPTE_WRITE)) {
309: iommu_bad_addr(opaque, page, is_write);
310: return;
311: }
312: cpu_physical_memory_write(phys_addr, buf, l);
313: } else {
314: cpu_physical_memory_read(phys_addr, buf, l);
315: }
316: len -= l;
317: buf += l;
318: addr += l;
319: }
320: }
321:
322: static const VMStateDescription vmstate_iommu = {
323: .name ="iommu",
324: .version_id = 2,
325: .minimum_version_id = 2,
326: .minimum_version_id_old = 2,
327: .fields = (VMStateField []) {
328: VMSTATE_UINT32_ARRAY(regs, IOMMUState, IOMMU_NREGS),
329: VMSTATE_UINT64(iostart, IOMMUState),
330: VMSTATE_END_OF_LIST()
331: }
332: };
333:
334: static void iommu_reset(DeviceState *d)
335: {
336: IOMMUState *s = container_of(d, IOMMUState, busdev.qdev);
337:
338: memset(s->regs, 0, IOMMU_NREGS * 4);
339: s->iostart = 0;
340: s->regs[IOMMU_CTRL] = s->version;
341: s->regs[IOMMU_ARBEN] = IOMMU_MID;
342: s->regs[IOMMU_AFSR] = IOMMU_AFSR_RESV;
343: s->regs[IOMMU_AER] = IOMMU_AER_EN_P0_ARB | IOMMU_AER_EN_P1_ARB;
344: s->regs[IOMMU_MASK_ID] = IOMMU_TS_MASK;
345: }
346:
347: static int iommu_init1(SysBusDevice *dev)
348: {
349: IOMMUState *s = FROM_SYSBUS(IOMMUState, dev);
350:
351: sysbus_init_irq(dev, &s->irq);
352:
1.1.1.5 ! root 353: memory_region_init_io(&s->iomem, &iommu_mem_ops, s, "iommu",
! 354: IOMMU_NREGS * sizeof(uint32_t));
! 355: sysbus_init_mmio(dev, &s->iomem);
1.1 root 356:
357: return 0;
358: }
359:
1.1.1.5 ! root 360: static Property iommu_properties[] = {
! 361: DEFINE_PROP_HEX32("version", IOMMUState, version, 0),
! 362: DEFINE_PROP_END_OF_LIST(),
! 363: };
! 364:
! 365: static void iommu_class_init(ObjectClass *klass, void *data)
! 366: {
! 367: DeviceClass *dc = DEVICE_CLASS(klass);
! 368: SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
! 369:
! 370: k->init = iommu_init1;
! 371: dc->reset = iommu_reset;
! 372: dc->vmsd = &vmstate_iommu;
! 373: dc->props = iommu_properties;
! 374: }
! 375:
! 376: static TypeInfo iommu_info = {
! 377: .name = "iommu",
! 378: .parent = TYPE_SYS_BUS_DEVICE,
! 379: .instance_size = sizeof(IOMMUState),
! 380: .class_init = iommu_class_init,
1.1 root 381: };
382:
1.1.1.5 ! root 383: static void iommu_register_types(void)
1.1 root 384: {
1.1.1.5 ! root 385: type_register_static(&iommu_info);
1.1 root 386: }
387:
1.1.1.5 ! root 388: type_init(iommu_register_types)
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