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1.1 root 1: /*
2: * QEMU Sun4u System Emulator
3: *
4: * Copyright (c) 2005 Fabrice Bellard
5: *
6: * Permission is hereby granted, free of charge, to any person obtaining a copy
7: * of this software and associated documentation files (the "Software"), to deal
8: * in the Software without restriction, including without limitation the rights
9: * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10: * copies of the Software, and to permit persons to whom the Software is
11: * furnished to do so, subject to the following conditions:
12: *
13: * The above copyright notice and this permission notice shall be included in
14: * all copies or substantial portions of the Software.
15: *
16: * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17: * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18: * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19: * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20: * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21: * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22: * THE SOFTWARE.
23: */
24: #include "vl.h"
25: #include "m48t59.h"
26:
27: #define KERNEL_LOAD_ADDR 0x00404000
28: #define CMDLINE_ADDR 0x003ff000
29: #define INITRD_LOAD_ADDR 0x00300000
30: #define PROM_ADDR 0x1fff0000000ULL
31: #define APB_SPECIAL_BASE 0x1fe00000000ULL
32: #define APB_MEM_BASE 0x1ff00000000ULL
33: #define VGA_BASE (APB_MEM_BASE + 0x400000ULL)
34: #define PROM_FILENAMEB "proll-sparc64.bin"
35: #define PROM_FILENAMEE "proll-sparc64.elf"
36: #define NVRAM_SIZE 0x2000
37:
38: /* TSC handling */
39:
40: uint64_t cpu_get_tsc()
41: {
42: return qemu_get_clock(vm_clock);
43: }
44:
45: int DMA_get_channel_mode (int nchan)
46: {
47: return 0;
48: }
49: int DMA_read_memory (int nchan, void *buf, int pos, int size)
50: {
51: return 0;
52: }
53: int DMA_write_memory (int nchan, void *buf, int pos, int size)
54: {
55: return 0;
56: }
57: void DMA_hold_DREQ (int nchan) {}
58: void DMA_release_DREQ (int nchan) {}
59: void DMA_schedule(int nchan) {}
60: void DMA_run (void) {}
61: void DMA_init (int high_page_enable) {}
62: void DMA_register_channel (int nchan,
63: DMA_transfer_handler transfer_handler,
64: void *opaque)
65: {
66: }
67:
68: /* NVRAM helpers */
69: void NVRAM_set_byte (m48t59_t *nvram, uint32_t addr, uint8_t value)
70: {
1.1.1.2 ! root 71: m48t59_write(nvram, addr, value);
1.1 root 72: }
73:
74: uint8_t NVRAM_get_byte (m48t59_t *nvram, uint32_t addr)
75: {
1.1.1.2 ! root 76: return m48t59_read(nvram, addr);
1.1 root 77: }
78:
79: void NVRAM_set_word (m48t59_t *nvram, uint32_t addr, uint16_t value)
80: {
1.1.1.2 ! root 81: m48t59_write(nvram, addr, value >> 8);
! 82: m48t59_write(nvram, addr + 1, value & 0xFF);
1.1 root 83: }
84:
85: uint16_t NVRAM_get_word (m48t59_t *nvram, uint32_t addr)
86: {
87: uint16_t tmp;
88:
1.1.1.2 ! root 89: tmp = m48t59_read(nvram, addr) << 8;
! 90: tmp |= m48t59_read(nvram, addr + 1);
1.1 root 91:
92: return tmp;
93: }
94:
95: void NVRAM_set_lword (m48t59_t *nvram, uint32_t addr, uint32_t value)
96: {
1.1.1.2 ! root 97: m48t59_write(nvram, addr, value >> 24);
! 98: m48t59_write(nvram, addr + 1, (value >> 16) & 0xFF);
! 99: m48t59_write(nvram, addr + 2, (value >> 8) & 0xFF);
! 100: m48t59_write(nvram, addr + 3, value & 0xFF);
1.1 root 101: }
102:
103: uint32_t NVRAM_get_lword (m48t59_t *nvram, uint32_t addr)
104: {
105: uint32_t tmp;
106:
1.1.1.2 ! root 107: tmp = m48t59_read(nvram, addr) << 24;
! 108: tmp |= m48t59_read(nvram, addr + 1) << 16;
! 109: tmp |= m48t59_read(nvram, addr + 2) << 8;
! 110: tmp |= m48t59_read(nvram, addr + 3);
1.1 root 111:
112: return tmp;
113: }
114:
115: void NVRAM_set_string (m48t59_t *nvram, uint32_t addr,
116: const unsigned char *str, uint32_t max)
117: {
118: int i;
119:
120: for (i = 0; i < max && str[i] != '\0'; i++) {
1.1.1.2 ! root 121: m48t59_write(nvram, addr + i, str[i]);
1.1 root 122: }
1.1.1.2 ! root 123: m48t59_write(nvram, addr + max - 1, '\0');
1.1 root 124: }
125:
126: int NVRAM_get_string (m48t59_t *nvram, uint8_t *dst, uint16_t addr, int max)
127: {
128: int i;
129:
130: memset(dst, 0, max);
131: for (i = 0; i < max; i++) {
132: dst[i] = NVRAM_get_byte(nvram, addr + i);
133: if (dst[i] == '\0')
134: break;
135: }
136:
137: return i;
138: }
139:
140: static uint16_t NVRAM_crc_update (uint16_t prev, uint16_t value)
141: {
142: uint16_t tmp;
143: uint16_t pd, pd1, pd2;
144:
145: tmp = prev >> 8;
146: pd = prev ^ value;
147: pd1 = pd & 0x000F;
148: pd2 = ((pd >> 4) & 0x000F) ^ pd1;
149: tmp ^= (pd1 << 3) | (pd1 << 8);
150: tmp ^= pd2 | (pd2 << 7) | (pd2 << 12);
151:
152: return tmp;
153: }
154:
155: uint16_t NVRAM_compute_crc (m48t59_t *nvram, uint32_t start, uint32_t count)
156: {
157: uint32_t i;
158: uint16_t crc = 0xFFFF;
159: int odd;
160:
161: odd = count & 1;
162: count &= ~1;
163: for (i = 0; i != count; i++) {
164: crc = NVRAM_crc_update(crc, NVRAM_get_word(nvram, start + i));
165: }
166: if (odd) {
167: crc = NVRAM_crc_update(crc, NVRAM_get_byte(nvram, start + i) << 8);
168: }
169:
170: return crc;
171: }
172:
173: extern int nographic;
174:
175: int sun4u_NVRAM_set_params (m48t59_t *nvram, uint16_t NVRAM_size,
176: const unsigned char *arch,
177: uint32_t RAM_size, int boot_device,
178: uint32_t kernel_image, uint32_t kernel_size,
179: const char *cmdline,
180: uint32_t initrd_image, uint32_t initrd_size,
181: uint32_t NVRAM_image,
182: int width, int height, int depth)
183: {
184: uint16_t crc;
185:
186: /* Set parameters for Open Hack'Ware BIOS */
187: NVRAM_set_string(nvram, 0x00, "QEMU_BIOS", 16);
188: NVRAM_set_lword(nvram, 0x10, 0x00000002); /* structure v2 */
189: NVRAM_set_word(nvram, 0x14, NVRAM_size);
190: NVRAM_set_string(nvram, 0x20, arch, 16);
191: NVRAM_set_byte(nvram, 0x2f, nographic & 0xff);
192: NVRAM_set_lword(nvram, 0x30, RAM_size);
193: NVRAM_set_byte(nvram, 0x34, boot_device);
194: NVRAM_set_lword(nvram, 0x38, kernel_image);
195: NVRAM_set_lword(nvram, 0x3C, kernel_size);
196: if (cmdline) {
197: /* XXX: put the cmdline in NVRAM too ? */
198: strcpy(phys_ram_base + CMDLINE_ADDR, cmdline);
199: NVRAM_set_lword(nvram, 0x40, CMDLINE_ADDR);
200: NVRAM_set_lword(nvram, 0x44, strlen(cmdline));
201: } else {
202: NVRAM_set_lword(nvram, 0x40, 0);
203: NVRAM_set_lword(nvram, 0x44, 0);
204: }
205: NVRAM_set_lword(nvram, 0x48, initrd_image);
206: NVRAM_set_lword(nvram, 0x4C, initrd_size);
207: NVRAM_set_lword(nvram, 0x50, NVRAM_image);
208:
209: NVRAM_set_word(nvram, 0x54, width);
210: NVRAM_set_word(nvram, 0x56, height);
211: NVRAM_set_word(nvram, 0x58, depth);
212: crc = NVRAM_compute_crc(nvram, 0x00, 0xF8);
213: NVRAM_set_word(nvram, 0xFC, crc);
214:
215: return 0;
216: }
217:
218: void pic_info()
219: {
220: }
221:
222: void irq_info()
223: {
224: }
225:
226: void pic_set_irq(int irq, int level)
227: {
228: }
229:
230: void pic_set_irq_new(void *opaque, int irq, int level)
231: {
232: }
233:
234: void qemu_system_powerdown(void)
235: {
236: }
237:
1.1.1.2 ! root 238: static void main_cpu_reset(void *opaque)
! 239: {
! 240: CPUState *env = opaque;
! 241: cpu_reset(env);
! 242: }
! 243:
1.1 root 244: static const int ide_iobase[2] = { 0x1f0, 0x170 };
245: static const int ide_iobase2[2] = { 0x3f6, 0x376 };
246: static const int ide_irq[2] = { 14, 15 };
247:
248: static const int serial_io[MAX_SERIAL_PORTS] = { 0x3f8, 0x2f8, 0x3e8, 0x2e8 };
249: static const int serial_irq[MAX_SERIAL_PORTS] = { 4, 3, 4, 3 };
250:
251: static const int parallel_io[MAX_PARALLEL_PORTS] = { 0x378, 0x278, 0x3bc };
252: static const int parallel_irq[MAX_PARALLEL_PORTS] = { 7, 7, 7 };
253:
254: static fdctrl_t *floppy_controller;
255:
256: /* Sun4u hardware initialisation */
257: static void sun4u_init(int ram_size, int vga_ram_size, int boot_device,
258: DisplayState *ds, const char **fd_filename, int snapshot,
259: const char *kernel_filename, const char *kernel_cmdline,
260: const char *initrd_filename)
261: {
1.1.1.2 ! root 262: CPUState *env;
1.1 root 263: char buf[1024];
264: m48t59_t *nvram;
265: int ret, linux_boot;
266: unsigned int i;
267: long prom_offset, initrd_size, kernel_size;
268: PCIBus *pci_bus;
269:
270: linux_boot = (kernel_filename != NULL);
271:
1.1.1.2 ! root 272: env = cpu_init();
! 273: register_savevm("cpu", 0, 3, cpu_save, cpu_load, env);
! 274: qemu_register_reset(main_cpu_reset, env);
! 275:
1.1 root 276: /* allocate RAM */
277: cpu_register_physical_memory(0, ram_size, 0);
278:
279: prom_offset = ram_size + vga_ram_size;
280:
281: snprintf(buf, sizeof(buf), "%s/%s", bios_dir, PROM_FILENAMEE);
282: ret = load_elf(buf, phys_ram_base + prom_offset);
283: if (ret < 0) {
284: snprintf(buf, sizeof(buf), "%s/%s", bios_dir, PROM_FILENAMEB);
285: ret = load_image(buf, phys_ram_base + prom_offset);
286: }
287: if (ret < 0) {
288: fprintf(stderr, "qemu: could not load prom '%s'\n",
289: buf);
290: exit(1);
291: }
292: cpu_register_physical_memory(PROM_ADDR, (ret + TARGET_PAGE_SIZE) & TARGET_PAGE_MASK,
293: prom_offset | IO_MEM_ROM);
294:
295: kernel_size = 0;
296: initrd_size = 0;
297: if (linux_boot) {
298: kernel_size = load_elf(kernel_filename, phys_ram_base + KERNEL_LOAD_ADDR);
299: if (kernel_size < 0)
300: kernel_size = load_aout(kernel_filename, phys_ram_base + KERNEL_LOAD_ADDR);
301: if (kernel_size < 0)
302: kernel_size = load_image(kernel_filename, phys_ram_base + KERNEL_LOAD_ADDR);
303: if (kernel_size < 0) {
304: fprintf(stderr, "qemu: could not load kernel '%s'\n",
305: kernel_filename);
306: exit(1);
307: }
308:
309: /* load initrd */
310: if (initrd_filename) {
311: initrd_size = load_image(initrd_filename, phys_ram_base + INITRD_LOAD_ADDR);
312: if (initrd_size < 0) {
313: fprintf(stderr, "qemu: could not load initial ram disk '%s'\n",
314: initrd_filename);
315: exit(1);
316: }
317: }
318: if (initrd_size > 0) {
319: for (i = 0; i < 64 * TARGET_PAGE_SIZE; i += TARGET_PAGE_SIZE) {
320: if (ldl_raw(phys_ram_base + KERNEL_LOAD_ADDR + i)
321: == 0x48647253) { // HdrS
322: stl_raw(phys_ram_base + KERNEL_LOAD_ADDR + i + 16, INITRD_LOAD_ADDR);
323: stl_raw(phys_ram_base + KERNEL_LOAD_ADDR + i + 20, initrd_size);
324: break;
325: }
326: }
327: }
328: }
329: pci_bus = pci_apb_init(APB_SPECIAL_BASE, APB_MEM_BASE);
330: isa_mem_base = VGA_BASE;
331: vga_initialize(pci_bus, ds, phys_ram_base + ram_size, ram_size,
332: vga_ram_size, 0, 0);
333: cpu_register_physical_memory(VGA_BASE, vga_ram_size, ram_size);
334: //pci_cirrus_vga_init(pci_bus, ds, phys_ram_base + ram_size, ram_size, vga_ram_size);
335:
336: for(i = 0; i < MAX_SERIAL_PORTS; i++) {
337: if (serial_hds[i]) {
1.1.1.2 ! root 338: serial_init(&pic_set_irq_new, NULL,
! 339: serial_io[i], serial_irq[i], serial_hds[i]);
1.1 root 340: }
341: }
342:
343: for(i = 0; i < MAX_PARALLEL_PORTS; i++) {
344: if (parallel_hds[i]) {
345: parallel_init(parallel_io[i], parallel_irq[i], parallel_hds[i]);
346: }
347: }
348:
349: for(i = 0; i < nb_nics; i++) {
350: pci_ne2000_init(pci_bus, &nd_table[i]);
351: }
352:
353: pci_cmd646_ide_init(pci_bus, bs_table, 1);
354: kbd_init();
355: floppy_controller = fdctrl_init(6, 2, 0, 0x3f0, fd_table);
1.1.1.2 ! root 356: nvram = m48t59_init(8, 0, 0x0074, NVRAM_SIZE, 59);
1.1 root 357: sun4u_NVRAM_set_params(nvram, NVRAM_SIZE, "Sun4u", ram_size, boot_device,
358: KERNEL_LOAD_ADDR, kernel_size,
359: kernel_cmdline,
360: INITRD_LOAD_ADDR, initrd_size,
361: /* XXX: need an option to load a NVRAM image */
362: 0,
363: graphic_width, graphic_height, graphic_depth);
364:
365: }
366:
367: QEMUMachine sun4u_machine = {
368: "sun4u",
369: "Sun4u platform",
370: sun4u_init,
371: };
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