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1.1 root 1: /*
2: * QEMU Sun4u System Emulator
1.1.1.6 ! root 3: *
1.1 root 4: * Copyright (c) 2005 Fabrice Bellard
1.1.1.6 ! root 5: *
1.1 root 6: * Permission is hereby granted, free of charge, to any person obtaining a copy
7: * of this software and associated documentation files (the "Software"), to deal
8: * in the Software without restriction, including without limitation the rights
9: * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10: * copies of the Software, and to permit persons to whom the Software is
11: * furnished to do so, subject to the following conditions:
12: *
13: * The above copyright notice and this permission notice shall be included in
14: * all copies or substantial portions of the Software.
15: *
16: * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17: * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18: * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19: * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20: * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21: * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22: * THE SOFTWARE.
23: */
1.1.1.6 ! root 24: #include "hw.h"
! 25: #include "pci.h"
! 26: #include "pc.h"
! 27: #include "nvram.h"
! 28: #include "fdc.h"
! 29: #include "net.h"
! 30: #include "qemu-timer.h"
! 31: #include "sysemu.h"
! 32: #include "boards.h"
! 33: #include "firmware_abi.h"
1.1 root 34:
35: #define KERNEL_LOAD_ADDR 0x00404000
36: #define CMDLINE_ADDR 0x003ff000
37: #define INITRD_LOAD_ADDR 0x00300000
1.1.1.4 root 38: #define PROM_SIZE_MAX (512 * 1024)
1.1.1.6 ! root 39: #define PROM_ADDR 0x1fff0000000ULL
! 40: #define PROM_VADDR 0x000ffd00000ULL
1.1 root 41: #define APB_SPECIAL_BASE 0x1fe00000000ULL
1.1.1.6 ! root 42: #define APB_MEM_BASE 0x1ff00000000ULL
! 43: #define VGA_BASE (APB_MEM_BASE + 0x400000ULL)
! 44: #define PROM_FILENAME "openbios-sparc64"
1.1 root 45: #define NVRAM_SIZE 0x2000
1.1.1.6 ! root 46: #define MAX_IDE_BUS 2
1.1 root 47:
48: /* TSC handling */
49:
50: uint64_t cpu_get_tsc()
51: {
52: return qemu_get_clock(vm_clock);
53: }
54:
55: int DMA_get_channel_mode (int nchan)
56: {
57: return 0;
58: }
59: int DMA_read_memory (int nchan, void *buf, int pos, int size)
60: {
61: return 0;
62: }
63: int DMA_write_memory (int nchan, void *buf, int pos, int size)
64: {
65: return 0;
66: }
67: void DMA_hold_DREQ (int nchan) {}
68: void DMA_release_DREQ (int nchan) {}
69: void DMA_schedule(int nchan) {}
70: void DMA_run (void) {}
71: void DMA_init (int high_page_enable) {}
72: void DMA_register_channel (int nchan,
73: DMA_transfer_handler transfer_handler,
74: void *opaque)
75: {
76: }
77:
1.1.1.6 ! root 78: extern int nographic;
1.1 root 79:
1.1.1.6 ! root 80: static int sun4u_NVRAM_set_params (m48t59_t *nvram, uint16_t NVRAM_size,
! 81: const unsigned char *arch,
! 82: uint32_t RAM_size, const char *boot_devices,
! 83: uint32_t kernel_image, uint32_t kernel_size,
! 84: const char *cmdline,
! 85: uint32_t initrd_image, uint32_t initrd_size,
! 86: uint32_t NVRAM_image,
! 87: int width, int height, int depth)
1.1 root 88: {
1.1.1.6 ! root 89: unsigned int i;
! 90: uint32_t start, end;
! 91: uint8_t image[0x1ff0];
! 92: ohwcfg_v3_t *header = (ohwcfg_v3_t *)ℑ
! 93: struct sparc_arch_cfg *sparc_header;
! 94: struct OpenBIOS_nvpart_v1 *part_header;
! 95:
! 96: memset(image, '\0', sizeof(image));
! 97:
! 98: // Try to match PPC NVRAM
! 99: strcpy(header->struct_ident, "QEMU_BIOS");
! 100: header->struct_version = cpu_to_be32(3); /* structure v3 */
! 101:
! 102: header->nvram_size = cpu_to_be16(NVRAM_size);
! 103: header->nvram_arch_ptr = cpu_to_be16(sizeof(ohwcfg_v3_t));
! 104: header->nvram_arch_size = cpu_to_be16(sizeof(struct sparc_arch_cfg));
! 105: strcpy(header->arch, arch);
! 106: header->nb_cpus = smp_cpus & 0xff;
! 107: header->RAM0_base = 0;
! 108: header->RAM0_size = cpu_to_be64((uint64_t)RAM_size);
! 109: strcpy(header->boot_devices, boot_devices);
! 110: header->nboot_devices = strlen(boot_devices) & 0xff;
! 111: header->kernel_image = cpu_to_be64((uint64_t)kernel_image);
! 112: header->kernel_size = cpu_to_be64((uint64_t)kernel_size);
! 113: if (cmdline) {
! 114: strcpy(phys_ram_base + CMDLINE_ADDR, cmdline);
! 115: header->cmdline = cpu_to_be64((uint64_t)CMDLINE_ADDR);
! 116: header->cmdline_size = cpu_to_be64((uint64_t)strlen(cmdline));
! 117: }
! 118: header->initrd_image = cpu_to_be64((uint64_t)initrd_image);
! 119: header->initrd_size = cpu_to_be64((uint64_t)initrd_size);
! 120: header->NVRAM_image = cpu_to_be64((uint64_t)NVRAM_image);
! 121:
! 122: header->width = cpu_to_be16(width);
! 123: header->height = cpu_to_be16(height);
! 124: header->depth = cpu_to_be16(depth);
! 125: if (nographic)
! 126: header->graphic_flags = cpu_to_be16(OHW_GF_NOGRAPHICS);
! 127:
! 128: header->crc = cpu_to_be16(OHW_compute_crc(header, 0x00, 0xF8));
! 129:
! 130: // Architecture specific header
! 131: start = sizeof(ohwcfg_v3_t);
! 132: sparc_header = (struct sparc_arch_cfg *)&image[start];
! 133: sparc_header->valid = 0;
! 134: start += sizeof(struct sparc_arch_cfg);
! 135:
! 136: // OpenBIOS nvram variables
! 137: // Variable partition
! 138: part_header = (struct OpenBIOS_nvpart_v1 *)&image[start];
! 139: part_header->signature = OPENBIOS_PART_SYSTEM;
! 140: strcpy(part_header->name, "system");
! 141:
! 142: end = start + sizeof(struct OpenBIOS_nvpart_v1);
! 143: for (i = 0; i < nb_prom_envs; i++)
! 144: end = OpenBIOS_set_var(image, end, prom_envs[i]);
! 145:
! 146: // End marker
! 147: image[end++] = '\0';
! 148:
! 149: end = start + ((end - start + 15) & ~15);
! 150: OpenBIOS_finish_partition(part_header, end - start);
! 151:
! 152: // free partition
! 153: start = end;
! 154: part_header = (struct OpenBIOS_nvpart_v1 *)&image[start];
! 155: part_header->signature = OPENBIOS_PART_FREE;
! 156: strcpy(part_header->name, "free");
1.1 root 157:
1.1.1.6 ! root 158: end = 0x1fd0;
! 159: OpenBIOS_finish_partition(part_header, end - start);
1.1 root 160:
1.1.1.6 ! root 161: for (i = 0; i < sizeof(image); i++)
! 162: m48t59_write(nvram, i, image[i]);
1.1 root 163:
1.1.1.6 ! root 164: return 0;
1.1 root 165: }
166:
1.1.1.6 ! root 167: void pic_info()
1.1 root 168: {
169: }
170:
1.1.1.6 ! root 171: void irq_info()
1.1 root 172: {
173: }
174:
1.1.1.6 ! root 175: void qemu_system_powerdown(void)
1.1 root 176: {
177: }
178:
1.1.1.6 ! root 179: static void main_cpu_reset(void *opaque)
1.1 root 180: {
1.1.1.6 ! root 181: CPUState *env = opaque;
1.1 root 182:
1.1.1.6 ! root 183: cpu_reset(env);
! 184: ptimer_set_limit(env->tick, 0x7fffffffffffffffULL, 1);
! 185: ptimer_run(env->tick, 0);
! 186: ptimer_set_limit(env->stick, 0x7fffffffffffffffULL, 1);
! 187: ptimer_run(env->stick, 0);
! 188: ptimer_set_limit(env->hstick, 0x7fffffffffffffffULL, 1);
! 189: ptimer_run(env->hstick, 0);
1.1 root 190: }
191:
1.1.1.6 ! root 192: void tick_irq(void *opaque)
1.1 root 193: {
1.1.1.6 ! root 194: CPUState *env = opaque;
1.1 root 195:
1.1.1.6 ! root 196: cpu_interrupt(env, CPU_INTERRUPT_TIMER);
1.1 root 197: }
198:
1.1.1.6 ! root 199: void stick_irq(void *opaque)
1.1 root 200: {
1.1.1.6 ! root 201: CPUState *env = opaque;
1.1 root 202:
1.1.1.6 ! root 203: cpu_interrupt(env, CPU_INTERRUPT_TIMER);
1.1 root 204: }
205:
1.1.1.6 ! root 206: void hstick_irq(void *opaque)
1.1 root 207: {
1.1.1.6 ! root 208: CPUState *env = opaque;
1.1 root 209:
1.1.1.6 ! root 210: cpu_interrupt(env, CPU_INTERRUPT_TIMER);
1.1 root 211: }
212:
1.1.1.6 ! root 213: static void dummy_cpu_set_irq(void *opaque, int irq, int level)
1.1.1.2 root 214: {
215: }
216:
1.1 root 217: static const int ide_iobase[2] = { 0x1f0, 0x170 };
218: static const int ide_iobase2[2] = { 0x3f6, 0x376 };
219: static const int ide_irq[2] = { 14, 15 };
220:
221: static const int serial_io[MAX_SERIAL_PORTS] = { 0x3f8, 0x2f8, 0x3e8, 0x2e8 };
222: static const int serial_irq[MAX_SERIAL_PORTS] = { 4, 3, 4, 3 };
223:
224: static const int parallel_io[MAX_PARALLEL_PORTS] = { 0x378, 0x278, 0x3bc };
225: static const int parallel_irq[MAX_PARALLEL_PORTS] = { 7, 7, 7 };
226:
227: static fdctrl_t *floppy_controller;
228:
229: /* Sun4u hardware initialisation */
1.1.1.6 ! root 230: static void sun4u_init(int ram_size, int vga_ram_size,
! 231: const char *boot_devices, DisplayState *ds,
! 232: const char *kernel_filename, const char *kernel_cmdline,
! 233: const char *initrd_filename, const char *cpu_model)
1.1 root 234: {
1.1.1.2 root 235: CPUState *env;
1.1 root 236: char buf[1024];
237: m48t59_t *nvram;
238: int ret, linux_boot;
239: unsigned int i;
240: long prom_offset, initrd_size, kernel_size;
241: PCIBus *pci_bus;
1.1.1.6 ! root 242: QEMUBH *bh;
! 243: qemu_irq *irq;
! 244: int index;
! 245: BlockDriverState *hd[MAX_IDE_BUS * MAX_IDE_DEVS];
! 246: BlockDriverState *fd[MAX_FD];
1.1 root 247:
248: linux_boot = (kernel_filename != NULL);
249:
1.1.1.6 ! root 250: /* init CPUs */
! 251: if (cpu_model == NULL)
! 252: cpu_model = "TI UltraSparc II";
! 253: env = cpu_init(cpu_model);
! 254: if (!env) {
! 255: fprintf(stderr, "Unable to find Sparc CPU definition\n");
! 256: exit(1);
! 257: }
! 258: bh = qemu_bh_new(tick_irq, env);
! 259: env->tick = ptimer_init(bh);
! 260: ptimer_set_period(env->tick, 1ULL);
! 261:
! 262: bh = qemu_bh_new(stick_irq, env);
! 263: env->stick = ptimer_init(bh);
! 264: ptimer_set_period(env->stick, 1ULL);
! 265:
! 266: bh = qemu_bh_new(hstick_irq, env);
! 267: env->hstick = ptimer_init(bh);
! 268: ptimer_set_period(env->hstick, 1ULL);
1.1.1.2 root 269: register_savevm("cpu", 0, 3, cpu_save, cpu_load, env);
270: qemu_register_reset(main_cpu_reset, env);
1.1.1.6 ! root 271: main_cpu_reset(env);
1.1.1.2 root 272:
1.1 root 273: /* allocate RAM */
274: cpu_register_physical_memory(0, ram_size, 0);
275:
276: prom_offset = ram_size + vga_ram_size;
1.1.1.6 ! root 277: cpu_register_physical_memory(PROM_ADDR,
! 278: (PROM_SIZE_MAX + TARGET_PAGE_SIZE) & TARGET_PAGE_MASK,
1.1.1.3 root 279: prom_offset | IO_MEM_ROM);
1.1 root 280:
1.1.1.6 ! root 281: if (bios_name == NULL)
! 282: bios_name = PROM_FILENAME;
! 283: snprintf(buf, sizeof(buf), "%s/%s", bios_dir, bios_name);
! 284: ret = load_elf(buf, PROM_ADDR - PROM_VADDR, NULL, NULL, NULL);
1.1 root 285: if (ret < 0) {
1.1.1.6 ! root 286: fprintf(stderr, "qemu: could not load prom '%s'\n",
! 287: buf);
! 288: exit(1);
1.1 root 289: }
290:
291: kernel_size = 0;
292: initrd_size = 0;
293: if (linux_boot) {
1.1.1.3 root 294: /* XXX: put correct offset */
1.1.1.6 ! root 295: kernel_size = load_elf(kernel_filename, 0, NULL, NULL, NULL);
1.1 root 296: if (kernel_size < 0)
1.1.1.6 ! root 297: kernel_size = load_aout(kernel_filename, phys_ram_base + KERNEL_LOAD_ADDR);
! 298: if (kernel_size < 0)
! 299: kernel_size = load_image(kernel_filename, phys_ram_base + KERNEL_LOAD_ADDR);
1.1 root 300: if (kernel_size < 0) {
1.1.1.6 ! root 301: fprintf(stderr, "qemu: could not load kernel '%s'\n",
1.1 root 302: kernel_filename);
1.1.1.6 ! root 303: exit(1);
1.1 root 304: }
305:
306: /* load initrd */
307: if (initrd_filename) {
308: initrd_size = load_image(initrd_filename, phys_ram_base + INITRD_LOAD_ADDR);
309: if (initrd_size < 0) {
1.1.1.6 ! root 310: fprintf(stderr, "qemu: could not load initial ram disk '%s'\n",
1.1 root 311: initrd_filename);
312: exit(1);
313: }
314: }
315: if (initrd_size > 0) {
1.1.1.6 ! root 316: for (i = 0; i < 64 * TARGET_PAGE_SIZE; i += TARGET_PAGE_SIZE) {
! 317: if (ldl_raw(phys_ram_base + KERNEL_LOAD_ADDR + i)
! 318: == 0x48647253) { // HdrS
! 319: stl_raw(phys_ram_base + KERNEL_LOAD_ADDR + i + 16, INITRD_LOAD_ADDR);
! 320: stl_raw(phys_ram_base + KERNEL_LOAD_ADDR + i + 20, initrd_size);
! 321: break;
! 322: }
! 323: }
1.1 root 324: }
325: }
1.1.1.4 root 326: pci_bus = pci_apb_init(APB_SPECIAL_BASE, APB_MEM_BASE, NULL);
1.1 root 327: isa_mem_base = VGA_BASE;
1.1.1.4 root 328: pci_cirrus_vga_init(pci_bus, ds, phys_ram_base + ram_size, ram_size, vga_ram_size);
1.1 root 329:
330: for(i = 0; i < MAX_SERIAL_PORTS; i++) {
331: if (serial_hds[i]) {
1.1.1.6 ! root 332: serial_init(serial_io[i], NULL/*serial_irq[i]*/, serial_hds[i]);
1.1 root 333: }
334: }
335:
336: for(i = 0; i < MAX_PARALLEL_PORTS; i++) {
337: if (parallel_hds[i]) {
1.1.1.6 ! root 338: parallel_init(parallel_io[i], NULL/*parallel_irq[i]*/, parallel_hds[i]);
1.1 root 339: }
340: }
341:
342: for(i = 0; i < nb_nics; i++) {
1.1.1.3 root 343: if (!nd_table[i].model)
344: nd_table[i].model = "ne2k_pci";
1.1.1.6 ! root 345: pci_nic_init(pci_bus, &nd_table[i], -1);
1.1 root 346: }
347:
1.1.1.6 ! root 348: irq = qemu_allocate_irqs(dummy_cpu_set_irq, NULL, 32);
! 349: if (drive_get_max_bus(IF_IDE) >= MAX_IDE_BUS) {
! 350: fprintf(stderr, "qemu: too many IDE bus\n");
! 351: exit(1);
! 352: }
! 353: for(i = 0; i < MAX_IDE_BUS * MAX_IDE_DEVS; i++) {
! 354: index = drive_get_index(IF_IDE, i / MAX_IDE_DEVS, i % MAX_IDE_DEVS);
! 355: if (index != -1)
! 356: hd[i] = drives_table[index].bdrv;
! 357: else
! 358: hd[i] = NULL;
! 359: }
! 360:
! 361: // XXX pci_cmd646_ide_init(pci_bus, hd, 1);
! 362: pci_piix3_ide_init(pci_bus, hd, -1, irq);
! 363: /* FIXME: wire up interrupts. */
! 364: i8042_init(NULL/*1*/, NULL/*12*/, 0x60);
! 365: for(i = 0; i < MAX_FD; i++) {
! 366: index = drive_get_index(IF_FLOPPY, 0, i);
! 367: if (index != -1)
! 368: fd[i] = drives_table[index].bdrv;
! 369: else
! 370: fd[i] = NULL;
! 371: }
! 372: floppy_controller = fdctrl_init(NULL/*6*/, 2, 0, 0x3f0, fd);
! 373: nvram = m48t59_init(NULL/*8*/, 0, 0x0074, NVRAM_SIZE, 59);
! 374: sun4u_NVRAM_set_params(nvram, NVRAM_SIZE, "Sun4u", ram_size, boot_devices,
1.1 root 375: KERNEL_LOAD_ADDR, kernel_size,
376: kernel_cmdline,
377: INITRD_LOAD_ADDR, initrd_size,
378: /* XXX: need an option to load a NVRAM image */
379: 0,
380: graphic_width, graphic_height, graphic_depth);
381:
382: }
383:
384: QEMUMachine sun4u_machine = {
385: "sun4u",
386: "Sun4u platform",
387: sun4u_init,
388: };
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