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1.1 root 1: /*
1.1.1.7 root 2: * QEMU Sun4u/Sun4v System Emulator
1.1.1.6 root 3: *
1.1 root 4: * Copyright (c) 2005 Fabrice Bellard
1.1.1.6 root 5: *
1.1 root 6: * Permission is hereby granted, free of charge, to any person obtaining a copy
7: * of this software and associated documentation files (the "Software"), to deal
8: * in the Software without restriction, including without limitation the rights
9: * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10: * copies of the Software, and to permit persons to whom the Software is
11: * furnished to do so, subject to the following conditions:
12: *
13: * The above copyright notice and this permission notice shall be included in
14: * all copies or substantial portions of the Software.
15: *
16: * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17: * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18: * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19: * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20: * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21: * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22: * THE SOFTWARE.
23: */
1.1.1.6 root 24: #include "hw.h"
25: #include "pci.h"
26: #include "pc.h"
27: #include "nvram.h"
28: #include "fdc.h"
29: #include "net.h"
30: #include "qemu-timer.h"
31: #include "sysemu.h"
32: #include "boards.h"
33: #include "firmware_abi.h"
1.1.1.7 root 34: #include "fw_cfg.h"
35:
36: //#define DEBUG_IRQ
37:
38: #ifdef DEBUG_IRQ
1.1.1.8 ! root 39: #define DPRINTF(fmt, ...) \
! 40: do { printf("CPUIRQ: " fmt , ## __VA_ARGS__); } while (0)
1.1.1.7 root 41: #else
1.1.1.8 ! root 42: #define DPRINTF(fmt, ...)
1.1.1.7 root 43: #endif
1.1 root 44:
45: #define KERNEL_LOAD_ADDR 0x00404000
46: #define CMDLINE_ADDR 0x003ff000
47: #define INITRD_LOAD_ADDR 0x00300000
1.1.1.7 root 48: #define PROM_SIZE_MAX (4 * 1024 * 1024)
1.1.1.6 root 49: #define PROM_VADDR 0x000ffd00000ULL
1.1 root 50: #define APB_SPECIAL_BASE 0x1fe00000000ULL
1.1.1.6 root 51: #define APB_MEM_BASE 0x1ff00000000ULL
52: #define VGA_BASE (APB_MEM_BASE + 0x400000ULL)
53: #define PROM_FILENAME "openbios-sparc64"
1.1 root 54: #define NVRAM_SIZE 0x2000
1.1.1.6 root 55: #define MAX_IDE_BUS 2
1.1.1.7 root 56: #define BIOS_CFG_IOPORT 0x510
1.1 root 57:
1.1.1.7 root 58: #define MAX_PILS 16
1.1 root 59:
1.1.1.7 root 60: #define TICK_INT_DIS 0x8000000000000000ULL
61: #define TICK_MAX 0x7fffffffffffffffULL
62:
63: struct hwdef {
64: const char * const default_cpu_model;
65: uint16_t machine_id;
66: uint64_t prom_addr;
67: uint64_t console_serial_base;
68: };
1.1 root 69:
70: int DMA_get_channel_mode (int nchan)
71: {
72: return 0;
73: }
74: int DMA_read_memory (int nchan, void *buf, int pos, int size)
75: {
76: return 0;
77: }
78: int DMA_write_memory (int nchan, void *buf, int pos, int size)
79: {
80: return 0;
81: }
82: void DMA_hold_DREQ (int nchan) {}
83: void DMA_release_DREQ (int nchan) {}
84: void DMA_schedule(int nchan) {}
85: void DMA_init (int high_page_enable) {}
86: void DMA_register_channel (int nchan,
87: DMA_transfer_handler transfer_handler,
88: void *opaque)
89: {
90: }
91:
1.1.1.8 ! root 92: static int fw_cfg_boot_set(void *opaque, const char *boot_device)
1.1.1.7 root 93: {
1.1.1.8 ! root 94: fw_cfg_add_i16(opaque, FW_CFG_BOOT_DEVICE, boot_device[0]);
1.1.1.7 root 95: return 0;
96: }
1.1 root 97:
1.1.1.6 root 98: static int sun4u_NVRAM_set_params (m48t59_t *nvram, uint16_t NVRAM_size,
1.1.1.7 root 99: const char *arch,
100: ram_addr_t RAM_size,
101: const char *boot_devices,
1.1.1.6 root 102: uint32_t kernel_image, uint32_t kernel_size,
103: const char *cmdline,
104: uint32_t initrd_image, uint32_t initrd_size,
105: uint32_t NVRAM_image,
1.1.1.7 root 106: int width, int height, int depth,
107: const uint8_t *macaddr)
1.1 root 108: {
1.1.1.6 root 109: unsigned int i;
110: uint32_t start, end;
111: uint8_t image[0x1ff0];
112: struct OpenBIOS_nvpart_v1 *part_header;
113:
114: memset(image, '\0', sizeof(image));
115:
1.1.1.8 ! root 116: start = 0;
1.1.1.6 root 117:
118: // OpenBIOS nvram variables
119: // Variable partition
120: part_header = (struct OpenBIOS_nvpart_v1 *)&image[start];
121: part_header->signature = OPENBIOS_PART_SYSTEM;
1.1.1.7 root 122: pstrcpy(part_header->name, sizeof(part_header->name), "system");
1.1.1.6 root 123:
124: end = start + sizeof(struct OpenBIOS_nvpart_v1);
125: for (i = 0; i < nb_prom_envs; i++)
126: end = OpenBIOS_set_var(image, end, prom_envs[i]);
127:
128: // End marker
129: image[end++] = '\0';
130:
131: end = start + ((end - start + 15) & ~15);
132: OpenBIOS_finish_partition(part_header, end - start);
133:
134: // free partition
135: start = end;
136: part_header = (struct OpenBIOS_nvpart_v1 *)&image[start];
137: part_header->signature = OPENBIOS_PART_FREE;
1.1.1.7 root 138: pstrcpy(part_header->name, sizeof(part_header->name), "free");
1.1 root 139:
1.1.1.6 root 140: end = 0x1fd0;
141: OpenBIOS_finish_partition(part_header, end - start);
1.1 root 142:
1.1.1.7 root 143: Sun_init_header((struct Sun_nvram *)&image[0x1fd8], macaddr, 0x80);
144:
1.1.1.6 root 145: for (i = 0; i < sizeof(image); i++)
146: m48t59_write(nvram, i, image[i]);
1.1 root 147:
1.1.1.6 root 148: return 0;
1.1 root 149: }
150:
1.1.1.8 ! root 151: void pic_info(Monitor *mon)
1.1 root 152: {
153: }
154:
1.1.1.8 ! root 155: void irq_info(Monitor *mon)
1.1 root 156: {
157: }
158:
1.1.1.7 root 159: void cpu_check_irqs(CPUState *env)
160: {
161: uint32_t pil = env->pil_in | (env->softint & ~SOFTINT_TIMER) |
162: ((env->softint & SOFTINT_TIMER) << 14);
163:
164: if (pil && (env->interrupt_index == 0 ||
165: (env->interrupt_index & ~15) == TT_EXTINT)) {
166: unsigned int i;
167:
168: for (i = 15; i > 0; i--) {
169: if (pil & (1 << i)) {
170: int old_interrupt = env->interrupt_index;
171:
172: env->interrupt_index = TT_EXTINT | i;
173: if (old_interrupt != env->interrupt_index) {
174: DPRINTF("Set CPU IRQ %d\n", i);
175: cpu_interrupt(env, CPU_INTERRUPT_HARD);
176: }
177: break;
178: }
179: }
180: } else if (!pil && (env->interrupt_index & ~15) == TT_EXTINT) {
181: DPRINTF("Reset CPU IRQ %d\n", env->interrupt_index & 15);
182: env->interrupt_index = 0;
183: cpu_reset_interrupt(env, CPU_INTERRUPT_HARD);
184: }
185: }
186:
187: static void cpu_set_irq(void *opaque, int irq, int level)
188: {
189: CPUState *env = opaque;
190:
191: if (level) {
192: DPRINTF("Raise CPU IRQ %d\n", irq);
193: env->halted = 0;
194: env->pil_in |= 1 << irq;
195: cpu_check_irqs(env);
196: } else {
197: DPRINTF("Lower CPU IRQ %d\n", irq);
198: env->pil_in &= ~(1 << irq);
199: cpu_check_irqs(env);
200: }
201: }
202:
1.1.1.6 root 203: void qemu_system_powerdown(void)
1.1 root 204: {
205: }
206:
1.1.1.7 root 207: typedef struct ResetData {
208: CPUState *env;
209: uint64_t reset_addr;
210: } ResetData;
211:
1.1.1.6 root 212: static void main_cpu_reset(void *opaque)
1.1 root 213: {
1.1.1.7 root 214: ResetData *s = (ResetData *)opaque;
215: CPUState *env = s->env;
1.1 root 216:
1.1.1.6 root 217: cpu_reset(env);
1.1.1.7 root 218: env->tick_cmpr = TICK_INT_DIS | 0;
219: ptimer_set_limit(env->tick, TICK_MAX, 1);
220: ptimer_run(env->tick, 1);
221: env->stick_cmpr = TICK_INT_DIS | 0;
222: ptimer_set_limit(env->stick, TICK_MAX, 1);
223: ptimer_run(env->stick, 1);
224: env->hstick_cmpr = TICK_INT_DIS | 0;
225: ptimer_set_limit(env->hstick, TICK_MAX, 1);
226: ptimer_run(env->hstick, 1);
227: env->gregs[1] = 0; // Memory start
228: env->gregs[2] = ram_size; // Memory size
229: env->gregs[3] = 0; // Machine description XXX
230: env->pc = s->reset_addr;
231: env->npc = env->pc + 4;
1.1 root 232: }
233:
1.1.1.7 root 234: static void tick_irq(void *opaque)
1.1 root 235: {
1.1.1.6 root 236: CPUState *env = opaque;
1.1 root 237:
1.1.1.7 root 238: if (!(env->tick_cmpr & TICK_INT_DIS)) {
239: env->softint |= SOFTINT_TIMER;
240: cpu_interrupt(env, CPU_INTERRUPT_TIMER);
241: }
1.1 root 242: }
243:
1.1.1.7 root 244: static void stick_irq(void *opaque)
1.1 root 245: {
1.1.1.6 root 246: CPUState *env = opaque;
1.1 root 247:
1.1.1.7 root 248: if (!(env->stick_cmpr & TICK_INT_DIS)) {
249: env->softint |= SOFTINT_STIMER;
250: cpu_interrupt(env, CPU_INTERRUPT_TIMER);
251: }
1.1 root 252: }
253:
1.1.1.7 root 254: static void hstick_irq(void *opaque)
1.1 root 255: {
1.1.1.6 root 256: CPUState *env = opaque;
1.1 root 257:
1.1.1.7 root 258: if (!(env->hstick_cmpr & TICK_INT_DIS)) {
259: cpu_interrupt(env, CPU_INTERRUPT_TIMER);
260: }
261: }
262:
263: void cpu_tick_set_count(void *opaque, uint64_t count)
264: {
265: ptimer_set_count(opaque, -count);
1.1 root 266: }
267:
1.1.1.7 root 268: uint64_t cpu_tick_get_count(void *opaque)
1.1.1.2 root 269: {
1.1.1.7 root 270: return -ptimer_get_count(opaque);
271: }
272:
273: void cpu_tick_set_limit(void *opaque, uint64_t limit)
274: {
275: ptimer_set_limit(opaque, -limit, 0);
1.1.1.2 root 276: }
277:
1.1 root 278: static const int ide_iobase[2] = { 0x1f0, 0x170 };
279: static const int ide_iobase2[2] = { 0x3f6, 0x376 };
280: static const int ide_irq[2] = { 14, 15 };
281:
282: static const int serial_io[MAX_SERIAL_PORTS] = { 0x3f8, 0x2f8, 0x3e8, 0x2e8 };
283: static const int serial_irq[MAX_SERIAL_PORTS] = { 4, 3, 4, 3 };
284:
285: static const int parallel_io[MAX_PARALLEL_PORTS] = { 0x378, 0x278, 0x3bc };
286: static const int parallel_irq[MAX_PARALLEL_PORTS] = { 7, 7, 7 };
287:
288: static fdctrl_t *floppy_controller;
289:
1.1.1.7 root 290: static void ebus_mmio_mapfunc(PCIDevice *pci_dev, int region_num,
291: uint32_t addr, uint32_t size, int type)
292: {
293: DPRINTF("Mapping region %d registers at %08x\n", region_num, addr);
294: switch (region_num) {
295: case 0:
296: isa_mmio_init(addr, 0x1000000);
297: break;
298: case 1:
299: isa_mmio_init(addr, 0x800000);
300: break;
301: }
302: }
303:
304: /* EBUS (Eight bit bus) bridge */
305: static void
306: pci_ebus_init(PCIBus *bus, int devfn)
307: {
1.1.1.8 ! root 308: pci_create_simple(bus, devfn, "ebus");
! 309: }
1.1.1.7 root 310:
1.1.1.8 ! root 311: static void
! 312: pci_ebus_init1(PCIDevice *s)
! 313: {
1.1.1.7 root 314: pci_config_set_vendor_id(s->config, PCI_VENDOR_ID_SUN);
315: pci_config_set_device_id(s->config, PCI_DEVICE_ID_SUN_EBUS);
316: s->config[0x04] = 0x06; // command = bus master, pci mem
317: s->config[0x05] = 0x00;
318: s->config[0x06] = 0xa0; // status = fast back-to-back, 66MHz, no error
319: s->config[0x07] = 0x03; // status = medium devsel
320: s->config[0x08] = 0x01; // revision
321: s->config[0x09] = 0x00; // programming i/f
322: pci_config_set_class(s->config, PCI_CLASS_BRIDGE_OTHER);
323: s->config[0x0D] = 0x0a; // latency_timer
1.1.1.8 ! root 324: s->config[PCI_HEADER_TYPE] = PCI_HEADER_TYPE_NORMAL; // header_type
1.1.1.7 root 325:
1.1.1.8 ! root 326: pci_register_bar(s, 0, 0x1000000, PCI_ADDRESS_SPACE_MEM,
1.1.1.7 root 327: ebus_mmio_mapfunc);
1.1.1.8 ! root 328: pci_register_bar(s, 1, 0x800000, PCI_ADDRESS_SPACE_MEM,
1.1.1.7 root 329: ebus_mmio_mapfunc);
330: }
331:
1.1.1.8 ! root 332: static PCIDeviceInfo ebus_info = {
! 333: .qdev.name = "ebus",
! 334: .qdev.size = sizeof(PCIDevice),
! 335: .init = pci_ebus_init1,
! 336: };
! 337:
! 338: static void pci_ebus_register(void)
! 339: {
! 340: pci_qdev_register(&ebus_info);
! 341: }
! 342:
! 343: device_init(pci_ebus_register);
! 344:
! 345: static void sun4uv_init(ram_addr_t RAM_size,
1.1.1.7 root 346: const char *boot_devices,
347: const char *kernel_filename, const char *kernel_cmdline,
348: const char *initrd_filename, const char *cpu_model,
349: const struct hwdef *hwdef)
1.1 root 350: {
1.1.1.2 root 351: CPUState *env;
1.1.1.8 ! root 352: char *filename;
1.1 root 353: m48t59_t *nvram;
354: int ret, linux_boot;
355: unsigned int i;
1.1.1.8 ! root 356: ram_addr_t ram_offset, prom_offset;
1.1.1.7 root 357: long initrd_size, kernel_size;
358: PCIBus *pci_bus, *pci_bus2, *pci_bus3;
1.1.1.6 root 359: QEMUBH *bh;
360: qemu_irq *irq;
1.1.1.7 root 361: int drive_index;
1.1.1.6 root 362: BlockDriverState *hd[MAX_IDE_BUS * MAX_IDE_DEVS];
363: BlockDriverState *fd[MAX_FD];
1.1.1.7 root 364: void *fw_cfg;
365: ResetData *reset_info;
1.1 root 366:
367: linux_boot = (kernel_filename != NULL);
368:
1.1.1.6 root 369: /* init CPUs */
1.1.1.7 root 370: if (!cpu_model)
371: cpu_model = hwdef->default_cpu_model;
372:
1.1.1.6 root 373: env = cpu_init(cpu_model);
374: if (!env) {
375: fprintf(stderr, "Unable to find Sparc CPU definition\n");
376: exit(1);
377: }
378: bh = qemu_bh_new(tick_irq, env);
379: env->tick = ptimer_init(bh);
380: ptimer_set_period(env->tick, 1ULL);
381:
382: bh = qemu_bh_new(stick_irq, env);
383: env->stick = ptimer_init(bh);
384: ptimer_set_period(env->stick, 1ULL);
385:
386: bh = qemu_bh_new(hstick_irq, env);
387: env->hstick = ptimer_init(bh);
388: ptimer_set_period(env->hstick, 1ULL);
1.1.1.7 root 389:
390: reset_info = qemu_mallocz(sizeof(ResetData));
391: reset_info->env = env;
392: reset_info->reset_addr = hwdef->prom_addr + 0x40ULL;
393: qemu_register_reset(main_cpu_reset, reset_info);
394: main_cpu_reset(reset_info);
395: // Override warm reset address with cold start address
396: env->pc = hwdef->prom_addr + 0x20ULL;
397: env->npc = env->pc + 4;
1.1.1.2 root 398:
1.1 root 399: /* allocate RAM */
1.1.1.7 root 400: ram_offset = qemu_ram_alloc(RAM_size);
401: cpu_register_physical_memory(0, RAM_size, ram_offset);
1.1 root 402:
1.1.1.7 root 403: prom_offset = qemu_ram_alloc(PROM_SIZE_MAX);
404: cpu_register_physical_memory(hwdef->prom_addr,
405: (PROM_SIZE_MAX + TARGET_PAGE_SIZE) &
406: TARGET_PAGE_MASK,
1.1.1.3 root 407: prom_offset | IO_MEM_ROM);
1.1 root 408:
1.1.1.6 root 409: if (bios_name == NULL)
410: bios_name = PROM_FILENAME;
1.1.1.8 ! root 411: filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
! 412: if (filename) {
! 413: ret = load_elf(filename, hwdef->prom_addr - PROM_VADDR,
! 414: NULL, NULL, NULL);
1.1.1.7 root 415: if (ret < 0) {
1.1.1.8 ! root 416: ret = load_image_targphys(filename, hwdef->prom_addr,
! 417: (PROM_SIZE_MAX + TARGET_PAGE_SIZE) &
! 418: TARGET_PAGE_MASK);
1.1.1.7 root 419: }
1.1.1.8 ! root 420: qemu_free(filename);
! 421: } else {
! 422: ret = -1;
! 423: }
! 424: if (ret < 0) {
! 425: fprintf(stderr, "qemu: could not load prom '%s'\n",
! 426: bios_name);
! 427: exit(1);
1.1 root 428: }
429:
430: kernel_size = 0;
431: initrd_size = 0;
432: if (linux_boot) {
1.1.1.3 root 433: /* XXX: put correct offset */
1.1.1.6 root 434: kernel_size = load_elf(kernel_filename, 0, NULL, NULL, NULL);
1.1 root 435: if (kernel_size < 0)
1.1.1.7 root 436: kernel_size = load_aout(kernel_filename, KERNEL_LOAD_ADDR,
437: ram_size - KERNEL_LOAD_ADDR);
1.1.1.6 root 438: if (kernel_size < 0)
1.1.1.7 root 439: kernel_size = load_image_targphys(kernel_filename,
440: KERNEL_LOAD_ADDR,
441: ram_size - KERNEL_LOAD_ADDR);
1.1 root 442: if (kernel_size < 0) {
1.1.1.6 root 443: fprintf(stderr, "qemu: could not load kernel '%s'\n",
1.1 root 444: kernel_filename);
1.1.1.6 root 445: exit(1);
1.1 root 446: }
447:
448: /* load initrd */
449: if (initrd_filename) {
1.1.1.7 root 450: initrd_size = load_image_targphys(initrd_filename,
451: INITRD_LOAD_ADDR,
452: ram_size - INITRD_LOAD_ADDR);
1.1 root 453: if (initrd_size < 0) {
1.1.1.6 root 454: fprintf(stderr, "qemu: could not load initial ram disk '%s'\n",
1.1 root 455: initrd_filename);
456: exit(1);
457: }
458: }
459: if (initrd_size > 0) {
1.1.1.6 root 460: for (i = 0; i < 64 * TARGET_PAGE_SIZE; i += TARGET_PAGE_SIZE) {
1.1.1.7 root 461: if (ldl_phys(KERNEL_LOAD_ADDR + i) == 0x48647253) { // HdrS
462: stl_phys(KERNEL_LOAD_ADDR + i + 16, INITRD_LOAD_ADDR);
463: stl_phys(KERNEL_LOAD_ADDR + i + 20, initrd_size);
1.1.1.6 root 464: break;
465: }
466: }
1.1 root 467: }
468: }
1.1.1.8 ! root 469:
! 470: irq = qemu_allocate_irqs(cpu_set_irq, env, MAX_PILS);
! 471: pci_bus = pci_apb_init(APB_SPECIAL_BASE, APB_MEM_BASE, irq, &pci_bus2,
1.1.1.7 root 472: &pci_bus3);
1.1 root 473: isa_mem_base = VGA_BASE;
1.1.1.8 ! root 474: pci_vga_init(pci_bus, 0, 0);
1.1.1.7 root 475:
476: // XXX Should be pci_bus3
477: pci_ebus_init(pci_bus, -1);
478:
479: i = 0;
480: if (hwdef->console_serial_base) {
481: serial_mm_init(hwdef->console_serial_base, 0, NULL, 115200,
482: serial_hds[i], 1);
483: i++;
484: }
485: for(; i < MAX_SERIAL_PORTS; i++) {
1.1 root 486: if (serial_hds[i]) {
1.1.1.7 root 487: serial_init(serial_io[i], NULL/*serial_irq[i]*/, 115200,
488: serial_hds[i]);
1.1 root 489: }
490: }
491:
492: for(i = 0; i < MAX_PARALLEL_PORTS; i++) {
493: if (parallel_hds[i]) {
1.1.1.7 root 494: parallel_init(parallel_io[i], NULL/*parallel_irq[i]*/,
495: parallel_hds[i]);
1.1 root 496: }
497: }
498:
1.1.1.7 root 499: for(i = 0; i < nb_nics; i++)
1.1.1.8 ! root 500: pci_nic_init(&nd_table[i], "ne2k_pci", NULL);
1.1 root 501:
1.1.1.6 root 502: if (drive_get_max_bus(IF_IDE) >= MAX_IDE_BUS) {
503: fprintf(stderr, "qemu: too many IDE bus\n");
504: exit(1);
505: }
506: for(i = 0; i < MAX_IDE_BUS * MAX_IDE_DEVS; i++) {
1.1.1.7 root 507: drive_index = drive_get_index(IF_IDE, i / MAX_IDE_DEVS,
508: i % MAX_IDE_DEVS);
509: if (drive_index != -1)
510: hd[i] = drives_table[drive_index].bdrv;
1.1.1.6 root 511: else
512: hd[i] = NULL;
513: }
514:
1.1.1.7 root 515: pci_cmd646_ide_init(pci_bus, hd, 1);
516:
1.1.1.6 root 517: /* FIXME: wire up interrupts. */
518: i8042_init(NULL/*1*/, NULL/*12*/, 0x60);
519: for(i = 0; i < MAX_FD; i++) {
1.1.1.7 root 520: drive_index = drive_get_index(IF_FLOPPY, 0, i);
521: if (drive_index != -1)
522: fd[i] = drives_table[drive_index].bdrv;
1.1.1.6 root 523: else
524: fd[i] = NULL;
525: }
526: floppy_controller = fdctrl_init(NULL/*6*/, 2, 0, 0x3f0, fd);
527: nvram = m48t59_init(NULL/*8*/, 0, 0x0074, NVRAM_SIZE, 59);
1.1.1.7 root 528: sun4u_NVRAM_set_params(nvram, NVRAM_SIZE, "Sun4u", RAM_size, boot_devices,
529: KERNEL_LOAD_ADDR, kernel_size,
530: kernel_cmdline,
531: INITRD_LOAD_ADDR, initrd_size,
532: /* XXX: need an option to load a NVRAM image */
533: 0,
534: graphic_width, graphic_height, graphic_depth,
535: (uint8_t *)&nd_table[0].macaddr);
536:
537: fw_cfg = fw_cfg_init(BIOS_CFG_IOPORT, BIOS_CFG_IOPORT + 1, 0, 0);
538: fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1);
539: fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
540: fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, hwdef->machine_id);
1.1.1.8 ! root 541: fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, KERNEL_LOAD_ADDR);
! 542: fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size);
! 543: if (kernel_cmdline) {
! 544: fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, CMDLINE_ADDR);
! 545: pstrcpy_targphys(CMDLINE_ADDR, TARGET_PAGE_SIZE, kernel_cmdline);
! 546: } else {
! 547: fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, 0);
! 548: }
! 549: fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, INITRD_LOAD_ADDR);
! 550: fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size);
! 551: fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, boot_devices[0]);
! 552: qemu_register_boot_set(fw_cfg_boot_set, fw_cfg);
1.1.1.7 root 553: }
554:
555: enum {
556: sun4u_id = 0,
557: sun4v_id = 64,
558: niagara_id,
559: };
1.1 root 560:
1.1.1.7 root 561: static const struct hwdef hwdefs[] = {
562: /* Sun4u generic PC-like machine */
563: {
564: .default_cpu_model = "TI UltraSparc II",
565: .machine_id = sun4u_id,
566: .prom_addr = 0x1fff0000000ULL,
567: .console_serial_base = 0,
568: },
569: /* Sun4v generic PC-like machine */
570: {
571: .default_cpu_model = "Sun UltraSparc T1",
572: .machine_id = sun4v_id,
573: .prom_addr = 0x1fff0000000ULL,
574: .console_serial_base = 0,
575: },
576: /* Sun4v generic Niagara machine */
577: {
578: .default_cpu_model = "Sun UltraSparc T1",
579: .machine_id = niagara_id,
580: .prom_addr = 0xfff0000000ULL,
581: .console_serial_base = 0xfff0c2c000ULL,
582: },
583: };
584:
585: /* Sun4u hardware initialisation */
1.1.1.8 ! root 586: static void sun4u_init(ram_addr_t RAM_size,
1.1.1.7 root 587: const char *boot_devices,
588: const char *kernel_filename, const char *kernel_cmdline,
589: const char *initrd_filename, const char *cpu_model)
590: {
1.1.1.8 ! root 591: sun4uv_init(RAM_size, boot_devices, kernel_filename,
1.1.1.7 root 592: kernel_cmdline, initrd_filename, cpu_model, &hwdefs[0]);
593: }
594:
595: /* Sun4v hardware initialisation */
1.1.1.8 ! root 596: static void sun4v_init(ram_addr_t RAM_size,
1.1.1.7 root 597: const char *boot_devices,
598: const char *kernel_filename, const char *kernel_cmdline,
599: const char *initrd_filename, const char *cpu_model)
600: {
1.1.1.8 ! root 601: sun4uv_init(RAM_size, boot_devices, kernel_filename,
1.1.1.7 root 602: kernel_cmdline, initrd_filename, cpu_model, &hwdefs[1]);
603: }
604:
605: /* Niagara hardware initialisation */
1.1.1.8 ! root 606: static void niagara_init(ram_addr_t RAM_size,
1.1.1.7 root 607: const char *boot_devices,
608: const char *kernel_filename, const char *kernel_cmdline,
609: const char *initrd_filename, const char *cpu_model)
610: {
1.1.1.8 ! root 611: sun4uv_init(RAM_size, boot_devices, kernel_filename,
1.1.1.7 root 612: kernel_cmdline, initrd_filename, cpu_model, &hwdefs[2]);
1.1 root 613: }
614:
1.1.1.8 ! root 615: static QEMUMachine sun4u_machine = {
1.1.1.7 root 616: .name = "sun4u",
617: .desc = "Sun4u platform",
618: .init = sun4u_init,
619: .max_cpus = 1, // XXX for now
1.1.1.8 ! root 620: .is_default = 1,
1.1.1.7 root 621: };
622:
1.1.1.8 ! root 623: static QEMUMachine sun4v_machine = {
1.1.1.7 root 624: .name = "sun4v",
625: .desc = "Sun4v platform",
626: .init = sun4v_init,
627: .max_cpus = 1, // XXX for now
628: };
629:
1.1.1.8 ! root 630: static QEMUMachine niagara_machine = {
1.1.1.7 root 631: .name = "Niagara",
632: .desc = "Sun4v platform, Niagara",
633: .init = niagara_init,
634: .max_cpus = 1, // XXX for now
1.1 root 635: };
1.1.1.8 ! root 636:
! 637: static void sun4u_machine_init(void)
! 638: {
! 639: qemu_register_machine(&sun4u_machine);
! 640: qemu_register_machine(&sun4v_machine);
! 641: qemu_register_machine(&niagara_machine);
! 642: }
! 643:
! 644: machine_init(sun4u_machine_init);
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