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1.1 root 1: /*
2: * QEMU Uninorth PCI host (for all Mac99 and newer machines)
3: *
4: * Copyright (c) 2006 Fabrice Bellard
5: *
6: * Permission is hereby granted, free of charge, to any person obtaining a copy
7: * of this software and associated documentation files (the "Software"), to deal
8: * in the Software without restriction, including without limitation the rights
9: * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10: * copies of the Software, and to permit persons to whom the Software is
11: * furnished to do so, subject to the following conditions:
12: *
13: * The above copyright notice and this permission notice shall be included in
14: * all copies or substantial portions of the Software.
15: *
16: * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17: * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18: * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19: * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20: * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21: * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22: * THE SOFTWARE.
23: */
24: #include "vl.h"
25: typedef target_phys_addr_t pci_addr_t;
26: #include "pci_host.h"
27:
28: typedef PCIHostState UNINState;
29:
30: static void pci_unin_main_config_writel (void *opaque, target_phys_addr_t addr,
31: uint32_t val)
32: {
33: UNINState *s = opaque;
34: int i;
35:
36: #ifdef TARGET_WORDS_BIGENDIAN
37: val = bswap32(val);
38: #endif
39:
40: for (i = 11; i < 32; i++) {
41: if ((val & (1 << i)) != 0)
42: break;
43: }
44: #if 0
45: s->config_reg = 0x80000000 | (1 << 16) | (val & 0x7FC) | (i << 11);
46: #else
47: s->config_reg = 0x80000000 | (0 << 16) | (val & 0x7FC) | (i << 11);
48: #endif
49: }
50:
51: static uint32_t pci_unin_main_config_readl (void *opaque,
52: target_phys_addr_t addr)
53: {
54: UNINState *s = opaque;
55: uint32_t val;
56: int devfn;
57:
58: devfn = (s->config_reg >> 8) & 0xFF;
59: val = (1 << (devfn >> 3)) | ((devfn & 0x07) << 8) | (s->config_reg & 0xFC);
60: #ifdef TARGET_WORDS_BIGENDIAN
61: val = bswap32(val);
62: #endif
63:
64: return val;
65: }
66:
67: static CPUWriteMemoryFunc *pci_unin_main_config_write[] = {
68: &pci_unin_main_config_writel,
69: &pci_unin_main_config_writel,
70: &pci_unin_main_config_writel,
71: };
72:
73: static CPUReadMemoryFunc *pci_unin_main_config_read[] = {
74: &pci_unin_main_config_readl,
75: &pci_unin_main_config_readl,
76: &pci_unin_main_config_readl,
77: };
78:
79: static CPUWriteMemoryFunc *pci_unin_main_write[] = {
80: &pci_host_data_writeb,
81: &pci_host_data_writew,
82: &pci_host_data_writel,
83: };
84:
85: static CPUReadMemoryFunc *pci_unin_main_read[] = {
86: &pci_host_data_readb,
87: &pci_host_data_readw,
88: &pci_host_data_readl,
89: };
90:
91: #if 0
92:
93: static void pci_unin_config_writel (void *opaque, target_phys_addr_t addr,
94: uint32_t val)
95: {
96: UNINState *s = opaque;
97:
98: #ifdef TARGET_WORDS_BIGENDIAN
99: val = bswap32(val);
100: #endif
101: s->config_reg = 0x80000000 | (val & ~0x00000001);
102: }
103:
104: static uint32_t pci_unin_config_readl (void *opaque,
105: target_phys_addr_t addr)
106: {
107: UNINState *s = opaque;
108: uint32_t val;
109:
110: val = (s->config_reg | 0x00000001) & ~0x80000000;
111: #ifdef TARGET_WORDS_BIGENDIAN
112: val = bswap32(val);
113: #endif
114:
115: return val;
116: }
117:
118: static CPUWriteMemoryFunc *pci_unin_config_write[] = {
119: &pci_unin_config_writel,
120: &pci_unin_config_writel,
121: &pci_unin_config_writel,
122: };
123:
124: static CPUReadMemoryFunc *pci_unin_config_read[] = {
125: &pci_unin_config_readl,
126: &pci_unin_config_readl,
127: &pci_unin_config_readl,
128: };
129:
130: static CPUWriteMemoryFunc *pci_unin_write[] = {
131: &pci_host_pci_writeb,
132: &pci_host_pci_writew,
133: &pci_host_pci_writel,
134: };
135:
136: static CPUReadMemoryFunc *pci_unin_read[] = {
137: &pci_host_pci_readb,
138: &pci_host_pci_readw,
139: &pci_host_pci_readl,
140: };
141: #endif
142:
143: static void pci_unin_set_irq(PCIDevice *d, void *pic, int irq_num, int level)
144: {
145: openpic_set_irq(pic, d->config[PCI_INTERRUPT_LINE], level);
146: }
147:
148: PCIBus *pci_pmac_init(void *pic)
149: {
150: UNINState *s;
151: PCIDevice *d;
152: int pci_mem_config, pci_mem_data;
153:
154: /* Use values found on a real PowerMac */
155: /* Uninorth main bus */
156: s = qemu_mallocz(sizeof(UNINState));
157: s->bus = pci_register_bus(pci_unin_set_irq, NULL, 11 << 3);
158:
159: pci_mem_config = cpu_register_io_memory(0, pci_unin_main_config_read,
160: pci_unin_main_config_write, s);
161: pci_mem_data = cpu_register_io_memory(0, pci_unin_main_read,
162: pci_unin_main_write, s);
163: cpu_register_physical_memory(0xf2800000, 0x1000, pci_mem_config);
164: cpu_register_physical_memory(0xf2c00000, 0x1000, pci_mem_data);
165: d = pci_register_device(s->bus, "Uni-north main", sizeof(PCIDevice),
166: 11 << 3, NULL, NULL);
167: d->config[0x00] = 0x6b; // vendor_id : Apple
168: d->config[0x01] = 0x10;
169: d->config[0x02] = 0x1F; // device_id
170: d->config[0x03] = 0x00;
171: d->config[0x08] = 0x00; // revision
172: d->config[0x0A] = 0x00; // class_sub = pci host
173: d->config[0x0B] = 0x06; // class_base = PCI_bridge
174: d->config[0x0C] = 0x08; // cache_line_size
175: d->config[0x0D] = 0x10; // latency_timer
176: d->config[0x0E] = 0x00; // header_type
177: d->config[0x34] = 0x00; // capabilities_pointer
178:
179: #if 0 // XXX: not activated as PPC BIOS doesn't handle mutiple buses properly
180: /* pci-to-pci bridge */
181: d = pci_register_device("Uni-north bridge", sizeof(PCIDevice), 0, 13 << 3,
182: NULL, NULL);
183: d->config[0x00] = 0x11; // vendor_id : TI
184: d->config[0x01] = 0x10;
185: d->config[0x02] = 0x26; // device_id
186: d->config[0x03] = 0x00;
187: d->config[0x08] = 0x05; // revision
188: d->config[0x0A] = 0x04; // class_sub = pci2pci
189: d->config[0x0B] = 0x06; // class_base = PCI_bridge
190: d->config[0x0C] = 0x08; // cache_line_size
191: d->config[0x0D] = 0x20; // latency_timer
192: d->config[0x0E] = 0x01; // header_type
193:
194: d->config[0x18] = 0x01; // primary_bus
195: d->config[0x19] = 0x02; // secondary_bus
196: d->config[0x1A] = 0x02; // subordinate_bus
197: d->config[0x1B] = 0x20; // secondary_latency_timer
198: d->config[0x1C] = 0x11; // io_base
199: d->config[0x1D] = 0x01; // io_limit
200: d->config[0x20] = 0x00; // memory_base
201: d->config[0x21] = 0x80;
202: d->config[0x22] = 0x00; // memory_limit
203: d->config[0x23] = 0x80;
204: d->config[0x24] = 0x01; // prefetchable_memory_base
205: d->config[0x25] = 0x80;
206: d->config[0x26] = 0xF1; // prefectchable_memory_limit
207: d->config[0x27] = 0x7F;
208: // d->config[0x34] = 0xdc // capabilities_pointer
209: #endif
210: #if 0 // XXX: not needed for now
211: /* Uninorth AGP bus */
212: s = &pci_bridge[1];
213: pci_mem_config = cpu_register_io_memory(0, pci_unin_config_read,
214: pci_unin_config_write, s);
215: pci_mem_data = cpu_register_io_memory(0, pci_unin_read,
216: pci_unin_write, s);
217: cpu_register_physical_memory(0xf0800000, 0x1000, pci_mem_config);
218: cpu_register_physical_memory(0xf0c00000, 0x1000, pci_mem_data);
219:
220: d = pci_register_device("Uni-north AGP", sizeof(PCIDevice), 0, 11 << 3,
221: NULL, NULL);
222: d->config[0x00] = 0x6b; // vendor_id : Apple
223: d->config[0x01] = 0x10;
224: d->config[0x02] = 0x20; // device_id
225: d->config[0x03] = 0x00;
226: d->config[0x08] = 0x00; // revision
227: d->config[0x0A] = 0x00; // class_sub = pci host
228: d->config[0x0B] = 0x06; // class_base = PCI_bridge
229: d->config[0x0C] = 0x08; // cache_line_size
230: d->config[0x0D] = 0x10; // latency_timer
231: d->config[0x0E] = 0x00; // header_type
232: // d->config[0x34] = 0x80; // capabilities_pointer
233: #endif
234:
235: #if 0 // XXX: not needed for now
236: /* Uninorth internal bus */
237: s = &pci_bridge[2];
238: pci_mem_config = cpu_register_io_memory(0, pci_unin_config_read,
239: pci_unin_config_write, s);
240: pci_mem_data = cpu_register_io_memory(0, pci_unin_read,
241: pci_unin_write, s);
242: cpu_register_physical_memory(0xf4800000, 0x1000, pci_mem_config);
243: cpu_register_physical_memory(0xf4c00000, 0x1000, pci_mem_data);
244:
245: d = pci_register_device("Uni-north internal", sizeof(PCIDevice),
246: 3, 11 << 3, NULL, NULL);
247: d->config[0x00] = 0x6b; // vendor_id : Apple
248: d->config[0x01] = 0x10;
249: d->config[0x02] = 0x1E; // device_id
250: d->config[0x03] = 0x00;
251: d->config[0x08] = 0x00; // revision
252: d->config[0x0A] = 0x00; // class_sub = pci host
253: d->config[0x0B] = 0x06; // class_base = PCI_bridge
254: d->config[0x0C] = 0x08; // cache_line_size
255: d->config[0x0D] = 0x10; // latency_timer
256: d->config[0x0E] = 0x00; // header_type
257: d->config[0x34] = 0x00; // capabilities_pointer
258: #endif
259: return s->bus;
260: }
261:
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