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1.1 root 1: /*
2: * QEMU Uninorth PCI host (for all Mac99 and newer machines)
3: *
4: * Copyright (c) 2006 Fabrice Bellard
1.1.1.3 root 5: *
1.1 root 6: * Permission is hereby granted, free of charge, to any person obtaining a copy
7: * of this software and associated documentation files (the "Software"), to deal
8: * in the Software without restriction, including without limitation the rights
9: * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10: * copies of the Software, and to permit persons to whom the Software is
11: * furnished to do so, subject to the following conditions:
12: *
13: * The above copyright notice and this permission notice shall be included in
14: * all copies or substantial portions of the Software.
15: *
16: * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17: * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18: * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19: * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20: * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21: * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22: * THE SOFTWARE.
23: */
1.1.1.3 root 24: #include "hw.h"
25: #include "ppc_mac.h"
26: #include "pci.h"
1.1.1.7 root 27: #include "pci_host.h"
1.1.1.3 root 28:
1.1.1.4 root 29: /* debug UniNorth */
30: //#define DEBUG_UNIN
31:
32: #ifdef DEBUG_UNIN
1.1.1.5 root 33: #define UNIN_DPRINTF(fmt, ...) \
34: do { printf("UNIN: " fmt , ## __VA_ARGS__); } while (0)
1.1.1.4 root 35: #else
1.1.1.5 root 36: #define UNIN_DPRINTF(fmt, ...)
1.1.1.4 root 37: #endif
38:
1.1.1.8 root 39: static const int unin_irq_line[] = { 0x1b, 0x1c, 0x1d, 0x1e };
40:
1.1.1.7 root 41: typedef struct UNINState {
42: PCIHostState host_state;
1.1.1.11 root 43: MemoryRegion pci_mmio;
44: MemoryRegion pci_hole;
1.1.1.7 root 45: } UNINState;
1.1 root 46:
1.1.1.7 root 47: static int pci_unin_map_irq(PCIDevice *pci_dev, int irq_num)
1.1 root 48: {
1.1.1.8 root 49: int retval;
50: int devfn = pci_dev->devfn & 0x00FFFFFF;
51:
52: retval = (((devfn >> 11) & 0x1F) + irq_num) & 3;
53:
54: return retval;
1.1 root 55: }
56:
1.1.1.7 root 57: static void pci_unin_set_irq(void *opaque, int irq_num, int level)
1.1 root 58: {
1.1.1.7 root 59: qemu_irq *pic = opaque;
1.1 root 60:
1.1.1.8 root 61: UNIN_DPRINTF("%s: setting INT %d = %d\n", __func__,
62: unin_irq_line[irq_num], level);
63: qemu_set_irq(pic[unin_irq_line[irq_num]], level);
1.1 root 64: }
65:
1.1.1.8 root 66: static uint32_t unin_get_config_reg(uint32_t reg, uint32_t addr)
67: {
68: uint32_t retval;
69:
70: if (reg & (1u << 31)) {
71: /* XXX OpenBIOS compatibility hack */
72: retval = reg | (addr & 3);
73: } else if (reg & 1) {
74: /* CFA1 style */
75: retval = (reg & ~7u) | (addr & 7);
76: } else {
77: uint32_t slot, func;
78:
79: /* Grab CFA0 style values */
80: slot = ffs(reg & 0xfffff800) - 1;
81: func = (reg >> 8) & 7;
82:
83: /* ... and then convert them to x86 format */
84: /* config pointer */
85: retval = (reg & (0xff - 7)) | (addr & 7);
86: /* slot */
87: retval |= slot << 11;
88: /* fn */
89: retval |= func << 8;
90: }
91:
92:
93: UNIN_DPRINTF("Converted config space accessor %08x/%08x -> %08x\n",
94: reg, addr, retval);
95:
96: return retval;
97: }
98:
1.1.1.11 root 99: static void unin_data_write(void *opaque, target_phys_addr_t addr,
100: uint64_t val, unsigned len)
1.1.1.8 root 101: {
1.1.1.11 root 102: UNINState *s = opaque;
103: UNIN_DPRINTF("write addr %" TARGET_FMT_plx " len %d val %"PRIx64"\n",
104: addr, len, val);
1.1.1.8 root 105: pci_data_write(s->host_state.bus,
106: unin_get_config_reg(s->host_state.config_reg, addr),
107: val, len);
108: }
109:
1.1.1.11 root 110: static uint64_t unin_data_read(void *opaque, target_phys_addr_t addr,
111: unsigned len)
1.1.1.8 root 112: {
1.1.1.11 root 113: UNINState *s = opaque;
1.1.1.8 root 114: uint32_t val;
115:
116: val = pci_data_read(s->host_state.bus,
117: unin_get_config_reg(s->host_state.config_reg, addr),
118: len);
1.1.1.11 root 119: UNIN_DPRINTF("read addr %" TARGET_FMT_plx " len %d val %x\n",
120: addr, len, val);
1.1.1.8 root 121: return val;
122: }
123:
1.1.1.11 root 124: static const MemoryRegionOps unin_data_ops = {
125: .read = unin_data_read,
126: .write = unin_data_write,
127: .endianness = DEVICE_LITTLE_ENDIAN,
128: };
129:
1.1.1.7 root 130: static int pci_unin_main_init_device(SysBusDevice *dev)
1.1.1.2 root 131: {
1.1.1.12! root 132: PCIHostState *h;
1.1.1.7 root 133: UNINState *s;
134:
135: /* Use values found on a real PowerMac */
136: /* Uninorth main bus */
1.1.1.12! root 137: h = FROM_SYSBUS(PCIHostState, dev);
! 138: s = DO_UPCAST(UNINState, host_state, h);
1.1.1.7 root 139:
1.1.1.11 root 140: memory_region_init_io(&s->host_state.conf_mem, &pci_host_conf_le_ops,
141: &s->host_state, "pci-conf-idx", 0x1000);
142: memory_region_init_io(&s->host_state.data_mem, &unin_data_ops, s,
143: "pci-conf-data", 0x1000);
1.1.1.12! root 144: sysbus_init_mmio(dev, &s->host_state.conf_mem);
! 145: sysbus_init_mmio(dev, &s->host_state.data_mem);
1.1.1.7 root 146:
147: return 0;
1.1 root 148: }
149:
1.1.1.11 root 150:
1.1.1.8 root 151: static int pci_u3_agp_init_device(SysBusDevice *dev)
1.1.1.4 root 152: {
1.1.1.12! root 153: PCIHostState *h;
1.1.1.7 root 154: UNINState *s;
1.1.1.4 root 155:
1.1.1.8 root 156: /* Uninorth U3 AGP bus */
1.1.1.12! root 157: h = FROM_SYSBUS(PCIHostState, dev);
! 158: s = DO_UPCAST(UNINState, host_state, h);
1.1.1.7 root 159:
1.1.1.11 root 160: memory_region_init_io(&s->host_state.conf_mem, &pci_host_conf_le_ops,
161: &s->host_state, "pci-conf-idx", 0x1000);
162: memory_region_init_io(&s->host_state.data_mem, &unin_data_ops, s,
163: "pci-conf-data", 0x1000);
1.1.1.12! root 164: sysbus_init_mmio(dev, &s->host_state.conf_mem);
! 165: sysbus_init_mmio(dev, &s->host_state.data_mem);
1.1.1.8 root 166:
1.1.1.7 root 167: return 0;
1.1.1.4 root 168: }
169:
1.1.1.7 root 170: static int pci_unin_agp_init_device(SysBusDevice *dev)
1.1.1.4 root 171: {
1.1.1.12! root 172: PCIHostState *h;
1.1.1.7 root 173: UNINState *s;
1.1.1.4 root 174:
1.1.1.7 root 175: /* Uninorth AGP bus */
1.1.1.12! root 176: h = FROM_SYSBUS(PCIHostState, dev);
! 177: s = DO_UPCAST(UNINState, host_state, h);
1.1.1.4 root 178:
1.1.1.11 root 179: memory_region_init_io(&s->host_state.conf_mem, &pci_host_conf_le_ops,
180: &s->host_state, "pci-conf-idx", 0x1000);
181: memory_region_init_io(&s->host_state.data_mem, &pci_host_data_le_ops,
182: &s->host_state, "pci-conf-data", 0x1000);
1.1.1.12! root 183: sysbus_init_mmio(dev, &s->host_state.conf_mem);
! 184: sysbus_init_mmio(dev, &s->host_state.data_mem);
1.1.1.7 root 185: return 0;
1.1.1.4 root 186: }
187:
1.1.1.7 root 188: static int pci_unin_internal_init_device(SysBusDevice *dev)
1.1.1.4 root 189: {
1.1.1.12! root 190: PCIHostState *h;
1.1.1.7 root 191: UNINState *s;
192:
193: /* Uninorth internal bus */
1.1.1.12! root 194: h = FROM_SYSBUS(PCIHostState, dev);
! 195: s = DO_UPCAST(UNINState, host_state, h);
1.1.1.7 root 196:
1.1.1.11 root 197: memory_region_init_io(&s->host_state.conf_mem, &pci_host_conf_le_ops,
198: &s->host_state, "pci-conf-idx", 0x1000);
199: memory_region_init_io(&s->host_state.data_mem, &pci_host_data_le_ops,
200: &s->host_state, "pci-conf-data", 0x1000);
1.1.1.12! root 201: sysbus_init_mmio(dev, &s->host_state.conf_mem);
! 202: sysbus_init_mmio(dev, &s->host_state.data_mem);
1.1.1.7 root 203: return 0;
1.1.1.4 root 204: }
205:
1.1.1.11 root 206: PCIBus *pci_pmac_init(qemu_irq *pic,
207: MemoryRegion *address_space_mem,
208: MemoryRegion *address_space_io)
1.1 root 209: {
1.1.1.7 root 210: DeviceState *dev;
211: SysBusDevice *s;
1.1.1.12! root 212: PCIHostState *h;
1.1.1.7 root 213: UNINState *d;
1.1 root 214:
215: /* Use values found on a real PowerMac */
216: /* Uninorth main bus */
1.1.1.12! root 217: dev = qdev_create(NULL, "uni-north-pci-pcihost");
1.1.1.7 root 218: qdev_init_nofail(dev);
219: s = sysbus_from_qdev(dev);
1.1.1.12! root 220: h = FROM_SYSBUS(PCIHostState, s);
! 221: d = DO_UPCAST(UNINState, host_state, h);
1.1.1.11 root 222: memory_region_init(&d->pci_mmio, "pci-mmio", 0x100000000ULL);
223: memory_region_init_alias(&d->pci_hole, "pci-hole", &d->pci_mmio,
224: 0x80000000ULL, 0x70000000ULL);
225: memory_region_add_subregion(address_space_mem, 0x80000000ULL,
226: &d->pci_hole);
227:
1.1.1.12! root 228: d->host_state.bus = pci_register_bus(dev, "pci",
1.1.1.7 root 229: pci_unin_set_irq, pci_unin_map_irq,
1.1.1.11 root 230: pic,
231: &d->pci_mmio,
232: address_space_io,
233: PCI_DEVFN(11, 0), 4);
1.1.1.7 root 234:
235: #if 0
1.1.1.8 root 236: pci_create_simple(d->host_state.bus, PCI_DEVFN(11, 0), "uni-north");
1.1.1.7 root 237: #endif
238:
239: sysbus_mmio_map(s, 0, 0xf2800000);
240: sysbus_mmio_map(s, 1, 0xf2c00000);
241:
242: /* DEC 21154 bridge */
243: #if 0
244: /* XXX: not activated as PPC BIOS doesn't handle multiple buses properly */
1.1.1.8 root 245: pci_create_simple(d->host_state.bus, PCI_DEVFN(12, 0), "dec-21154");
1.1.1.7 root 246: #endif
247:
248: /* Uninorth AGP bus */
1.1.1.8 root 249: pci_create_simple(d->host_state.bus, PCI_DEVFN(11, 0), "uni-north-agp");
1.1.1.12! root 250: dev = qdev_create(NULL, "uni-north-agp-pcihost");
1.1.1.7 root 251: qdev_init_nofail(dev);
252: s = sysbus_from_qdev(dev);
253: sysbus_mmio_map(s, 0, 0xf0800000);
254: sysbus_mmio_map(s, 1, 0xf0c00000);
255:
256: /* Uninorth internal bus */
257: #if 0
258: /* XXX: not needed for now */
1.1.1.12! root 259: pci_create_simple(d->host_state.bus, PCI_DEVFN(14, 0),
! 260: "uni-north-internal-pci");
! 261: dev = qdev_create(NULL, "uni-north-internal-pci-pcihost");
1.1.1.7 root 262: qdev_init_nofail(dev);
263: s = sysbus_from_qdev(dev);
264: sysbus_mmio_map(s, 0, 0xf4800000);
265: sysbus_mmio_map(s, 1, 0xf4c00000);
266: #endif
267:
268: return d->host_state.bus;
269: }
270:
1.1.1.11 root 271: PCIBus *pci_pmac_u3_init(qemu_irq *pic,
272: MemoryRegion *address_space_mem,
273: MemoryRegion *address_space_io)
1.1.1.8 root 274: {
275: DeviceState *dev;
276: SysBusDevice *s;
1.1.1.12! root 277: PCIHostState *h;
1.1.1.8 root 278: UNINState *d;
279:
280: /* Uninorth AGP bus */
281:
1.1.1.12! root 282: dev = qdev_create(NULL, "u3-agp-pcihost");
1.1.1.8 root 283: qdev_init_nofail(dev);
284: s = sysbus_from_qdev(dev);
1.1.1.12! root 285: h = FROM_SYSBUS(PCIHostState, s);
! 286: d = DO_UPCAST(UNINState, host_state, h);
1.1.1.8 root 287:
1.1.1.11 root 288: memory_region_init(&d->pci_mmio, "pci-mmio", 0x100000000ULL);
289: memory_region_init_alias(&d->pci_hole, "pci-hole", &d->pci_mmio,
290: 0x80000000ULL, 0x70000000ULL);
291: memory_region_add_subregion(address_space_mem, 0x80000000ULL,
292: &d->pci_hole);
293:
1.1.1.12! root 294: d->host_state.bus = pci_register_bus(dev, "pci",
1.1.1.8 root 295: pci_unin_set_irq, pci_unin_map_irq,
1.1.1.11 root 296: pic,
297: &d->pci_mmio,
298: address_space_io,
299: PCI_DEVFN(11, 0), 4);
1.1.1.8 root 300:
301: sysbus_mmio_map(s, 0, 0xf0800000);
302: sysbus_mmio_map(s, 1, 0xf0c00000);
303:
304: pci_create_simple(d->host_state.bus, 11 << 3, "u3-agp");
305:
306: return d->host_state.bus;
307: }
308:
1.1.1.7 root 309: static int unin_main_pci_host_init(PCIDevice *d)
310: {
1.1 root 311: d->config[0x0C] = 0x08; // cache_line_size
312: d->config[0x0D] = 0x10; // latency_timer
313: d->config[0x34] = 0x00; // capabilities_pointer
1.1.1.7 root 314: return 0;
315: }
1.1 root 316:
1.1.1.7 root 317: static int unin_agp_pci_host_init(PCIDevice *d)
318: {
1.1 root 319: d->config[0x0C] = 0x08; // cache_line_size
320: d->config[0x0D] = 0x10; // latency_timer
321: // d->config[0x34] = 0x80; // capabilities_pointer
1.1.1.7 root 322: return 0;
323: }
1.1 root 324:
1.1.1.8 root 325: static int u3_agp_pci_host_init(PCIDevice *d)
326: {
327: /* cache line size */
328: d->config[0x0C] = 0x08;
329: /* latency timer */
330: d->config[0x0D] = 0x10;
331: return 0;
332: }
333:
1.1.1.7 root 334: static int unin_internal_pci_host_init(PCIDevice *d)
335: {
1.1 root 336: d->config[0x0C] = 0x08; // cache_line_size
337: d->config[0x0D] = 0x10; // latency_timer
338: d->config[0x34] = 0x00; // capabilities_pointer
1.1.1.7 root 339: return 0;
340: }
341:
1.1.1.12! root 342: static void unin_main_pci_host_class_init(ObjectClass *klass, void *data)
! 343: {
! 344: PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
! 345:
! 346: k->init = unin_main_pci_host_init;
! 347: k->vendor_id = PCI_VENDOR_ID_APPLE;
! 348: k->device_id = PCI_DEVICE_ID_APPLE_UNI_N_PCI;
! 349: k->revision = 0x00;
! 350: k->class_id = PCI_CLASS_BRIDGE_HOST;
! 351: }
! 352:
! 353: static TypeInfo unin_main_pci_host_info = {
! 354: .name = "uni-north-pci",
! 355: .parent = TYPE_PCI_DEVICE,
! 356: .instance_size = sizeof(PCIDevice),
! 357: .class_init = unin_main_pci_host_class_init,
1.1.1.7 root 358: };
359:
1.1.1.12! root 360: static void u3_agp_pci_host_class_init(ObjectClass *klass, void *data)
! 361: {
! 362: PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
! 363:
! 364: k->init = u3_agp_pci_host_init;
! 365: k->vendor_id = PCI_VENDOR_ID_APPLE;
! 366: k->device_id = PCI_DEVICE_ID_APPLE_U3_AGP;
! 367: k->revision = 0x00;
! 368: k->class_id = PCI_CLASS_BRIDGE_HOST;
! 369: }
! 370:
! 371: static TypeInfo u3_agp_pci_host_info = {
! 372: .name = "u3-agp",
! 373: .parent = TYPE_PCI_DEVICE,
! 374: .instance_size = sizeof(PCIDevice),
! 375: .class_init = u3_agp_pci_host_class_init,
1.1.1.7 root 376: };
377:
1.1.1.12! root 378: static void unin_agp_pci_host_class_init(ObjectClass *klass, void *data)
! 379: {
! 380: PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
! 381:
! 382: k->init = unin_agp_pci_host_init;
! 383: k->vendor_id = PCI_VENDOR_ID_APPLE;
! 384: k->device_id = PCI_DEVICE_ID_APPLE_UNI_N_AGP;
! 385: k->revision = 0x00;
! 386: k->class_id = PCI_CLASS_BRIDGE_HOST;
! 387: }
! 388:
! 389: static TypeInfo unin_agp_pci_host_info = {
! 390: .name = "uni-north-agp",
! 391: .parent = TYPE_PCI_DEVICE,
! 392: .instance_size = sizeof(PCIDevice),
! 393: .class_init = unin_agp_pci_host_class_init,
1.1.1.7 root 394: };
1.1.1.4 root 395:
1.1.1.12! root 396: static void unin_internal_pci_host_class_init(ObjectClass *klass, void *data)
! 397: {
! 398: PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
! 399:
! 400: k->init = unin_internal_pci_host_init;
! 401: k->vendor_id = PCI_VENDOR_ID_APPLE;
! 402: k->device_id = PCI_DEVICE_ID_APPLE_UNI_N_I_PCI;
! 403: k->revision = 0x00;
! 404: k->class_id = PCI_CLASS_BRIDGE_HOST;
! 405: }
! 406:
! 407: static TypeInfo unin_internal_pci_host_info = {
! 408: .name = "uni-north-internal-pci",
! 409: .parent = TYPE_PCI_DEVICE,
! 410: .instance_size = sizeof(PCIDevice),
! 411: .class_init = unin_internal_pci_host_class_init,
1.1.1.7 root 412: };
413:
1.1.1.12! root 414: static void pci_unin_main_class_init(ObjectClass *klass, void *data)
1.1.1.7 root 415: {
1.1.1.12! root 416: SysBusDeviceClass *sbc = SYS_BUS_DEVICE_CLASS(klass);
! 417:
! 418: sbc->init = pci_unin_main_init_device;
! 419: }
! 420:
! 421: static TypeInfo pci_unin_main_info = {
! 422: .name = "uni-north-pci-pcihost",
! 423: .parent = TYPE_SYS_BUS_DEVICE,
! 424: .instance_size = sizeof(UNINState),
! 425: .class_init = pci_unin_main_class_init,
! 426: };
! 427:
! 428: static void pci_u3_agp_class_init(ObjectClass *klass, void *data)
! 429: {
! 430: SysBusDeviceClass *sbc = SYS_BUS_DEVICE_CLASS(klass);
! 431:
! 432: sbc->init = pci_u3_agp_init_device;
! 433: }
! 434:
! 435: static TypeInfo pci_u3_agp_info = {
! 436: .name = "u3-agp-pcihost",
! 437: .parent = TYPE_SYS_BUS_DEVICE,
! 438: .instance_size = sizeof(UNINState),
! 439: .class_init = pci_u3_agp_class_init,
! 440: };
! 441:
! 442: static void pci_unin_agp_class_init(ObjectClass *klass, void *data)
! 443: {
! 444: SysBusDeviceClass *sbc = SYS_BUS_DEVICE_CLASS(klass);
! 445:
! 446: sbc->init = pci_unin_agp_init_device;
! 447: }
! 448:
! 449: static TypeInfo pci_unin_agp_info = {
! 450: .name = "uni-north-agp-pcihost",
! 451: .parent = TYPE_SYS_BUS_DEVICE,
! 452: .instance_size = sizeof(UNINState),
! 453: .class_init = pci_unin_agp_class_init,
! 454: };
! 455:
! 456: static void pci_unin_internal_class_init(ObjectClass *klass, void *data)
! 457: {
! 458: SysBusDeviceClass *sbc = SYS_BUS_DEVICE_CLASS(klass);
! 459:
! 460: sbc->init = pci_unin_internal_init_device;
! 461: }
! 462:
! 463: static TypeInfo pci_unin_internal_info = {
! 464: .name = "uni-north-internal-pci-pcihost",
! 465: .parent = TYPE_SYS_BUS_DEVICE,
! 466: .instance_size = sizeof(UNINState),
! 467: .class_init = pci_unin_internal_class_init,
! 468: };
! 469:
! 470: static void unin_register_types(void)
! 471: {
! 472: type_register_static(&unin_main_pci_host_info);
! 473: type_register_static(&u3_agp_pci_host_info);
! 474: type_register_static(&unin_agp_pci_host_info);
! 475: type_register_static(&unin_internal_pci_host_info);
! 476:
! 477: type_register_static(&pci_unin_main_info);
! 478: type_register_static(&pci_u3_agp_info);
! 479: type_register_static(&pci_unin_agp_info);
! 480: type_register_static(&pci_unin_internal_info);
1.1 root 481: }
1.1.1.7 root 482:
1.1.1.12! root 483: type_init(unin_register_types)
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