![[BACK]](/cvsweb/icons/back.gif){kind=icon}
Return to unin_pci.c CVS log ![[TXT]](/cvsweb/icons/text.gif){kind=icon}
![[DIR]](/cvsweb/icons/dir.gif){kind=icon}
Up to [Qemu by Fabrice Bellard] / qemu / hw|
Return to unin_pci.c CVS log | Up to [Qemu by Fabrice Bellard] / qemu / hw |
1.1 root 1: /*
2: * QEMU Uninorth PCI host (for all Mac99 and newer machines)
3: *
4: * Copyright (c) 2006 Fabrice Bellard
1.1.1.3 root 5: *
1.1 root 6: * Permission is hereby granted, free of charge, to any person obtaining a copy
7: * of this software and associated documentation files (the "Software"), to deal
8: * in the Software without restriction, including without limitation the rights
9: * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10: * copies of the Software, and to permit persons to whom the Software is
11: * furnished to do so, subject to the following conditions:
12: *
13: * The above copyright notice and this permission notice shall be included in
14: * all copies or substantial portions of the Software.
15: *
16: * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17: * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18: * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19: * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20: * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21: * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22: * THE SOFTWARE.
23: */
1.1.1.3 root 24: #include "hw.h"
25: #include "ppc_mac.h"
26: #include "pci.h"
27:
1.1.1.4 ! root 28: /* debug UniNorth */
! 29: //#define DEBUG_UNIN
! 30:
! 31: #ifdef DEBUG_UNIN
! 32: #define UNIN_DPRINTF(fmt, args...) \
! 33: do { printf("UNIN: " fmt , ##args); } while (0)
! 34: #else
! 35: #define UNIN_DPRINTF(fmt, args...)
! 36: #endif
! 37:
1.1 root 38: typedef target_phys_addr_t pci_addr_t;
39: #include "pci_host.h"
40:
41: typedef PCIHostState UNINState;
42:
43: static void pci_unin_main_config_writel (void *opaque, target_phys_addr_t addr,
44: uint32_t val)
45: {
46: UNINState *s = opaque;
47:
1.1.1.4 ! root 48: UNIN_DPRINTF("config_writel addr " TARGET_FMT_plx " val %x\n", addr, val);
1.1 root 49: #ifdef TARGET_WORDS_BIGENDIAN
50: val = bswap32(val);
51: #endif
52:
1.1.1.4 ! root 53: s->config_reg = val;
1.1 root 54: }
55:
56: static uint32_t pci_unin_main_config_readl (void *opaque,
57: target_phys_addr_t addr)
58: {
59: UNINState *s = opaque;
60: uint32_t val;
61:
1.1.1.4 ! root 62: val = s->config_reg;
1.1 root 63: #ifdef TARGET_WORDS_BIGENDIAN
64: val = bswap32(val);
65: #endif
1.1.1.4 ! root 66: UNIN_DPRINTF("config_readl addr " TARGET_FMT_plx " val %x\n", addr, val);
1.1 root 67:
68: return val;
69: }
70:
71: static CPUWriteMemoryFunc *pci_unin_main_config_write[] = {
72: &pci_unin_main_config_writel,
73: &pci_unin_main_config_writel,
74: &pci_unin_main_config_writel,
75: };
76:
77: static CPUReadMemoryFunc *pci_unin_main_config_read[] = {
78: &pci_unin_main_config_readl,
79: &pci_unin_main_config_readl,
80: &pci_unin_main_config_readl,
81: };
82:
83: static CPUWriteMemoryFunc *pci_unin_main_write[] = {
84: &pci_host_data_writeb,
85: &pci_host_data_writew,
86: &pci_host_data_writel,
87: };
88:
89: static CPUReadMemoryFunc *pci_unin_main_read[] = {
90: &pci_host_data_readb,
91: &pci_host_data_readw,
92: &pci_host_data_readl,
93: };
94:
95: #if 0
96:
97: static void pci_unin_config_writel (void *opaque, target_phys_addr_t addr,
98: uint32_t val)
99: {
100: UNINState *s = opaque;
101:
102: #ifdef TARGET_WORDS_BIGENDIAN
103: val = bswap32(val);
104: #endif
105: s->config_reg = 0x80000000 | (val & ~0x00000001);
106: }
107:
108: static uint32_t pci_unin_config_readl (void *opaque,
109: target_phys_addr_t addr)
110: {
111: UNINState *s = opaque;
112: uint32_t val;
113:
114: val = (s->config_reg | 0x00000001) & ~0x80000000;
115: #ifdef TARGET_WORDS_BIGENDIAN
116: val = bswap32(val);
117: #endif
118:
119: return val;
120: }
121:
122: static CPUWriteMemoryFunc *pci_unin_config_write[] = {
123: &pci_unin_config_writel,
124: &pci_unin_config_writel,
125: &pci_unin_config_writel,
126: };
127:
128: static CPUReadMemoryFunc *pci_unin_config_read[] = {
129: &pci_unin_config_readl,
130: &pci_unin_config_readl,
131: &pci_unin_config_readl,
132: };
133:
134: static CPUWriteMemoryFunc *pci_unin_write[] = {
135: &pci_host_pci_writeb,
136: &pci_host_pci_writew,
137: &pci_host_pci_writel,
138: };
139:
140: static CPUReadMemoryFunc *pci_unin_read[] = {
141: &pci_host_pci_readb,
142: &pci_host_pci_readw,
143: &pci_host_pci_readl,
144: };
145: #endif
146:
1.1.1.2 root 147: /* Don't know if this matches real hardware, but it agrees with OHW. */
148: static int pci_unin_map_irq(PCIDevice *pci_dev, int irq_num)
1.1 root 149: {
1.1.1.2 root 150: return (irq_num + (pci_dev->devfn >> 3)) & 3;
151: }
152:
1.1.1.3 root 153: static void pci_unin_set_irq(qemu_irq *pic, int irq_num, int level)
1.1.1.2 root 154: {
1.1.1.3 root 155: qemu_set_irq(pic[irq_num + 8], level);
1.1 root 156: }
157:
1.1.1.4 ! root 158: static void pci_unin_save(QEMUFile* f, void *opaque)
! 159: {
! 160: PCIDevice *d = opaque;
! 161:
! 162: pci_device_save(d, f);
! 163: }
! 164:
! 165: static int pci_unin_load(QEMUFile* f, void *opaque, int version_id)
! 166: {
! 167: PCIDevice *d = opaque;
! 168:
! 169: if (version_id != 1)
! 170: return -EINVAL;
! 171:
! 172: return pci_device_load(d, f);
! 173: }
! 174:
! 175: static void pci_unin_reset(void *opaque)
! 176: {
! 177: }
! 178:
1.1.1.3 root 179: PCIBus *pci_pmac_init(qemu_irq *pic)
1.1 root 180: {
181: UNINState *s;
182: PCIDevice *d;
183: int pci_mem_config, pci_mem_data;
184:
185: /* Use values found on a real PowerMac */
186: /* Uninorth main bus */
187: s = qemu_mallocz(sizeof(UNINState));
1.1.1.2 root 188: s->bus = pci_register_bus(pci_unin_set_irq, pci_unin_map_irq,
189: pic, 11 << 3, 4);
1.1 root 190:
1.1.1.3 root 191: pci_mem_config = cpu_register_io_memory(0, pci_unin_main_config_read,
1.1 root 192: pci_unin_main_config_write, s);
193: pci_mem_data = cpu_register_io_memory(0, pci_unin_main_read,
194: pci_unin_main_write, s);
195: cpu_register_physical_memory(0xf2800000, 0x1000, pci_mem_config);
196: cpu_register_physical_memory(0xf2c00000, 0x1000, pci_mem_data);
1.1.1.3 root 197: d = pci_register_device(s->bus, "Uni-north main", sizeof(PCIDevice),
1.1 root 198: 11 << 3, NULL, NULL);
1.1.1.4 ! root 199: pci_config_set_vendor_id(d->config, PCI_VENDOR_ID_APPLE);
! 200: pci_config_set_device_id(d->config, PCI_DEVICE_ID_APPLE_UNI_N_PCI);
1.1 root 201: d->config[0x08] = 0x00; // revision
1.1.1.4 ! root 202: pci_config_set_class(d->config, PCI_CLASS_BRIDGE_HOST);
1.1 root 203: d->config[0x0C] = 0x08; // cache_line_size
204: d->config[0x0D] = 0x10; // latency_timer
205: d->config[0x0E] = 0x00; // header_type
206: d->config[0x34] = 0x00; // capabilities_pointer
207:
1.1.1.2 root 208: #if 0 // XXX: not activated as PPC BIOS doesn't handle multiple buses properly
1.1 root 209: /* pci-to-pci bridge */
210: d = pci_register_device("Uni-north bridge", sizeof(PCIDevice), 0, 13 << 3,
211: NULL, NULL);
1.1.1.4 ! root 212: pci_config_set_vendor_id(d->config, PCI_VENDOR_ID_DEC);
! 213: pci_config_set_device_id(d->config, PCI_DEVICE_ID_DEC_21154);
1.1 root 214: d->config[0x08] = 0x05; // revision
1.1.1.4 ! root 215: pci_config_set_class(d->config, PCI_CLASS_BRIDGE_PCI);
1.1 root 216: d->config[0x0C] = 0x08; // cache_line_size
217: d->config[0x0D] = 0x20; // latency_timer
218: d->config[0x0E] = 0x01; // header_type
219:
220: d->config[0x18] = 0x01; // primary_bus
221: d->config[0x19] = 0x02; // secondary_bus
222: d->config[0x1A] = 0x02; // subordinate_bus
223: d->config[0x1B] = 0x20; // secondary_latency_timer
224: d->config[0x1C] = 0x11; // io_base
225: d->config[0x1D] = 0x01; // io_limit
226: d->config[0x20] = 0x00; // memory_base
227: d->config[0x21] = 0x80;
228: d->config[0x22] = 0x00; // memory_limit
229: d->config[0x23] = 0x80;
230: d->config[0x24] = 0x01; // prefetchable_memory_base
231: d->config[0x25] = 0x80;
232: d->config[0x26] = 0xF1; // prefectchable_memory_limit
233: d->config[0x27] = 0x7F;
234: // d->config[0x34] = 0xdc // capabilities_pointer
235: #endif
236: #if 0 // XXX: not needed for now
237: /* Uninorth AGP bus */
238: s = &pci_bridge[1];
1.1.1.3 root 239: pci_mem_config = cpu_register_io_memory(0, pci_unin_config_read,
1.1 root 240: pci_unin_config_write, s);
241: pci_mem_data = cpu_register_io_memory(0, pci_unin_read,
242: pci_unin_write, s);
243: cpu_register_physical_memory(0xf0800000, 0x1000, pci_mem_config);
244: cpu_register_physical_memory(0xf0c00000, 0x1000, pci_mem_data);
245:
246: d = pci_register_device("Uni-north AGP", sizeof(PCIDevice), 0, 11 << 3,
247: NULL, NULL);
1.1.1.4 ! root 248: pci_config_set_vendor_id(d->config, PCI_VENDOR_ID_APPLE);
! 249: pci_config_set_device_id(d->config, PCI_DEVICE_ID_APPLE_UNI_N_AGP);
1.1 root 250: d->config[0x08] = 0x00; // revision
1.1.1.4 ! root 251: pci_config_set_class(d->config, PCI_CLASS_BRIDGE_HOST);
1.1 root 252: d->config[0x0C] = 0x08; // cache_line_size
253: d->config[0x0D] = 0x10; // latency_timer
254: d->config[0x0E] = 0x00; // header_type
255: // d->config[0x34] = 0x80; // capabilities_pointer
256: #endif
257:
258: #if 0 // XXX: not needed for now
259: /* Uninorth internal bus */
260: s = &pci_bridge[2];
1.1.1.3 root 261: pci_mem_config = cpu_register_io_memory(0, pci_unin_config_read,
1.1 root 262: pci_unin_config_write, s);
263: pci_mem_data = cpu_register_io_memory(0, pci_unin_read,
264: pci_unin_write, s);
265: cpu_register_physical_memory(0xf4800000, 0x1000, pci_mem_config);
266: cpu_register_physical_memory(0xf4c00000, 0x1000, pci_mem_data);
267:
268: d = pci_register_device("Uni-north internal", sizeof(PCIDevice),
269: 3, 11 << 3, NULL, NULL);
1.1.1.4 ! root 270: pci_config_set_vendor_id(d->config, PCI_VENDOR_ID_APPLE);
! 271: pci_config_set_device_id(d->config, PCI_DEVICE_ID_APPLE_UNI_N_I_PCI);
1.1 root 272: d->config[0x08] = 0x00; // revision
1.1.1.4 ! root 273: pci_config_set_class(d->config, PCI_CLASS_BRIDGE_HOST);
1.1 root 274: d->config[0x0C] = 0x08; // cache_line_size
275: d->config[0x0D] = 0x10; // latency_timer
276: d->config[0x0E] = 0x00; // header_type
277: d->config[0x34] = 0x00; // capabilities_pointer
278: #endif
1.1.1.4 ! root 279: register_savevm("uninorth", 0, 1, pci_unin_save, pci_unin_load, d);
! 280: qemu_register_reset(pci_unin_reset, d);
! 281: pci_unin_reset(d);
! 282:
1.1 root 283: return s->bus;
284: }
This archive runs on limited infrastructure. Preserving old code on modern bandwidth. Automated agents are requested to crawl responsibly.