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1.1 root 1: /*
2: * QEMU Uninorth PCI host (for all Mac99 and newer machines)
3: *
4: * Copyright (c) 2006 Fabrice Bellard
1.1.1.3 root 5: *
1.1 root 6: * Permission is hereby granted, free of charge, to any person obtaining a copy
7: * of this software and associated documentation files (the "Software"), to deal
8: * in the Software without restriction, including without limitation the rights
9: * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10: * copies of the Software, and to permit persons to whom the Software is
11: * furnished to do so, subject to the following conditions:
12: *
13: * The above copyright notice and this permission notice shall be included in
14: * all copies or substantial portions of the Software.
15: *
16: * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17: * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18: * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19: * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20: * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21: * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22: * THE SOFTWARE.
23: */
1.1.1.3 root 24: #include "hw.h"
25: #include "ppc_mac.h"
26: #include "pci.h"
1.1.1.7 ! root 27: #include "pci_host.h"
1.1.1.3 root 28:
1.1.1.4 root 29: /* debug UniNorth */
30: //#define DEBUG_UNIN
31:
32: #ifdef DEBUG_UNIN
1.1.1.5 root 33: #define UNIN_DPRINTF(fmt, ...) \
34: do { printf("UNIN: " fmt , ## __VA_ARGS__); } while (0)
1.1.1.4 root 35: #else
1.1.1.5 root 36: #define UNIN_DPRINTF(fmt, ...)
1.1.1.4 root 37: #endif
38:
1.1.1.7 ! root 39: typedef struct UNINState {
! 40: SysBusDevice busdev;
! 41: PCIHostState host_state;
! 42: } UNINState;
1.1 root 43:
1.1.1.7 ! root 44: /* Don't know if this matches real hardware, but it agrees with OHW. */
! 45: static int pci_unin_map_irq(PCIDevice *pci_dev, int irq_num)
1.1 root 46: {
1.1.1.7 ! root 47: return (irq_num + (pci_dev->devfn >> 3)) & 3;
1.1 root 48: }
49:
1.1.1.7 ! root 50: static void pci_unin_set_irq(void *opaque, int irq_num, int level)
1.1 root 51: {
1.1.1.7 ! root 52: qemu_irq *pic = opaque;
1.1 root 53:
1.1.1.7 ! root 54: qemu_set_irq(pic[irq_num + 8], level);
1.1 root 55: }
56:
1.1.1.7 ! root 57: static void pci_unin_save(QEMUFile* f, void *opaque)
1.1 root 58: {
1.1.1.7 ! root 59: PCIDevice *d = opaque;
1.1 root 60:
1.1.1.7 ! root 61: pci_device_save(d, f);
1.1 root 62: }
63:
1.1.1.7 ! root 64: static int pci_unin_load(QEMUFile* f, void *opaque, int version_id)
1.1 root 65: {
1.1.1.7 ! root 66: PCIDevice *d = opaque;
1.1 root 67:
1.1.1.7 ! root 68: if (version_id != 1)
! 69: return -EINVAL;
1.1 root 70:
1.1.1.7 ! root 71: return pci_device_load(d, f);
! 72: }
1.1 root 73:
1.1.1.7 ! root 74: static void pci_unin_reset(void *opaque)
1.1 root 75: {
1.1.1.2 root 76: }
77:
1.1.1.7 ! root 78: static int pci_unin_main_init_device(SysBusDevice *dev)
1.1.1.2 root 79: {
1.1.1.7 ! root 80: UNINState *s;
! 81: int pci_mem_config, pci_mem_data;
! 82:
! 83: /* Use values found on a real PowerMac */
! 84: /* Uninorth main bus */
! 85: s = FROM_SYSBUS(UNINState, dev);
! 86:
! 87: pci_mem_config = pci_host_conf_register_mmio(&s->host_state);
! 88: pci_mem_data = pci_host_data_register_mmio(&s->host_state);
! 89: sysbus_init_mmio(dev, 0x1000, pci_mem_config);
! 90: sysbus_init_mmio(dev, 0x1000, pci_mem_data);
! 91:
! 92: register_savevm("uninorth", 0, 1, pci_unin_save, pci_unin_load, &s->host_state);
! 93: qemu_register_reset(pci_unin_reset, &s->host_state);
! 94: return 0;
1.1 root 95: }
96:
1.1.1.7 ! root 97: static int pci_dec_21154_init_device(SysBusDevice *dev)
1.1.1.4 root 98: {
1.1.1.7 ! root 99: UNINState *s;
! 100: int pci_mem_config, pci_mem_data;
1.1.1.4 root 101:
1.1.1.7 ! root 102: /* Uninorth bridge */
! 103: s = FROM_SYSBUS(UNINState, dev);
! 104:
! 105: // XXX: s = &pci_bridge[2];
! 106: pci_mem_config = pci_host_conf_register_mmio_noswap(&s->host_state);
! 107: pci_mem_data = pci_host_data_register_mmio(&s->host_state);
! 108: sysbus_init_mmio(dev, 0x1000, pci_mem_config);
! 109: sysbus_init_mmio(dev, 0x1000, pci_mem_data);
! 110: return 0;
1.1.1.4 root 111: }
112:
1.1.1.7 ! root 113: static int pci_unin_agp_init_device(SysBusDevice *dev)
1.1.1.4 root 114: {
1.1.1.7 ! root 115: UNINState *s;
! 116: int pci_mem_config, pci_mem_data;
1.1.1.4 root 117:
1.1.1.7 ! root 118: /* Uninorth AGP bus */
! 119: s = FROM_SYSBUS(UNINState, dev);
1.1.1.4 root 120:
1.1.1.7 ! root 121: pci_mem_config = pci_host_conf_register_mmio_noswap(&s->host_state);
! 122: pci_mem_data = pci_host_data_register_mmio(&s->host_state);
! 123: sysbus_init_mmio(dev, 0x1000, pci_mem_config);
! 124: sysbus_init_mmio(dev, 0x1000, pci_mem_data);
! 125: return 0;
1.1.1.4 root 126: }
127:
1.1.1.7 ! root 128: static int pci_unin_internal_init_device(SysBusDevice *dev)
1.1.1.4 root 129: {
1.1.1.7 ! root 130: UNINState *s;
! 131: int pci_mem_config, pci_mem_data;
! 132:
! 133: /* Uninorth internal bus */
! 134: s = FROM_SYSBUS(UNINState, dev);
! 135:
! 136: pci_mem_config = pci_host_conf_register_mmio_noswap(&s->host_state);
! 137: pci_mem_data = pci_host_data_register_mmio(&s->host_state);
! 138: sysbus_init_mmio(dev, 0x1000, pci_mem_config);
! 139: sysbus_init_mmio(dev, 0x1000, pci_mem_data);
! 140: return 0;
1.1.1.4 root 141: }
142:
1.1.1.3 root 143: PCIBus *pci_pmac_init(qemu_irq *pic)
1.1 root 144: {
1.1.1.7 ! root 145: DeviceState *dev;
! 146: SysBusDevice *s;
! 147: UNINState *d;
1.1 root 148:
149: /* Use values found on a real PowerMac */
150: /* Uninorth main bus */
1.1.1.7 ! root 151: dev = qdev_create(NULL, "uni-north");
! 152: qdev_init_nofail(dev);
! 153: s = sysbus_from_qdev(dev);
! 154: d = FROM_SYSBUS(UNINState, s);
! 155: d->host_state.bus = pci_register_bus(&d->busdev.qdev, "pci",
! 156: pci_unin_set_irq, pci_unin_map_irq,
! 157: pic, 11 << 3, 4);
! 158:
! 159: #if 0
! 160: pci_create_simple(d->host_state.bus, 11 << 3, "uni-north");
! 161: #endif
! 162:
! 163: sysbus_mmio_map(s, 0, 0xf2800000);
! 164: sysbus_mmio_map(s, 1, 0xf2c00000);
! 165:
! 166: /* DEC 21154 bridge */
! 167: #if 0
! 168: /* XXX: not activated as PPC BIOS doesn't handle multiple buses properly */
! 169: pci_create_simple(d->host_state.bus, 12 << 3, "dec-21154");
! 170: #endif
! 171:
! 172: /* Uninorth AGP bus */
! 173: pci_create_simple(d->host_state.bus, 11 << 3, "uni-north-agp");
! 174: dev = qdev_create(NULL, "uni-north-agp");
! 175: qdev_init_nofail(dev);
! 176: s = sysbus_from_qdev(dev);
! 177: sysbus_mmio_map(s, 0, 0xf0800000);
! 178: sysbus_mmio_map(s, 1, 0xf0c00000);
! 179:
! 180: /* Uninorth internal bus */
! 181: #if 0
! 182: /* XXX: not needed for now */
! 183: pci_create_simple(d->host_state.bus, 14 << 3, "uni-north-pci");
! 184: dev = qdev_create(NULL, "uni-north-pci");
! 185: qdev_init_nofail(dev);
! 186: s = sysbus_from_qdev(dev);
! 187: sysbus_mmio_map(s, 0, 0xf4800000);
! 188: sysbus_mmio_map(s, 1, 0xf4c00000);
! 189: #endif
! 190:
! 191: return d->host_state.bus;
! 192: }
! 193:
! 194: static int unin_main_pci_host_init(PCIDevice *d)
! 195: {
1.1.1.4 root 196: pci_config_set_vendor_id(d->config, PCI_VENDOR_ID_APPLE);
197: pci_config_set_device_id(d->config, PCI_DEVICE_ID_APPLE_UNI_N_PCI);
1.1 root 198: d->config[0x08] = 0x00; // revision
1.1.1.4 root 199: pci_config_set_class(d->config, PCI_CLASS_BRIDGE_HOST);
1.1 root 200: d->config[0x0C] = 0x08; // cache_line_size
201: d->config[0x0D] = 0x10; // latency_timer
1.1.1.5 root 202: d->config[PCI_HEADER_TYPE] = PCI_HEADER_TYPE_NORMAL; // header_type
1.1 root 203: d->config[0x34] = 0x00; // capabilities_pointer
1.1.1.7 ! root 204: return 0;
! 205: }
1.1 root 206:
1.1.1.7 ! root 207: static int dec_21154_pci_host_init(PCIDevice *d)
! 208: {
1.1 root 209: /* pci-to-pci bridge */
1.1.1.4 root 210: pci_config_set_vendor_id(d->config, PCI_VENDOR_ID_DEC);
211: pci_config_set_device_id(d->config, PCI_DEVICE_ID_DEC_21154);
1.1 root 212: d->config[0x08] = 0x05; // revision
1.1.1.4 root 213: pci_config_set_class(d->config, PCI_CLASS_BRIDGE_PCI);
1.1 root 214: d->config[0x0C] = 0x08; // cache_line_size
215: d->config[0x0D] = 0x20; // latency_timer
1.1.1.5 root 216: d->config[PCI_HEADER_TYPE] = PCI_HEADER_TYPE_BRIDGE; // header_type
1.1 root 217:
218: d->config[0x18] = 0x01; // primary_bus
219: d->config[0x19] = 0x02; // secondary_bus
220: d->config[0x1A] = 0x02; // subordinate_bus
221: d->config[0x1B] = 0x20; // secondary_latency_timer
222: d->config[0x1C] = 0x11; // io_base
223: d->config[0x1D] = 0x01; // io_limit
224: d->config[0x20] = 0x00; // memory_base
225: d->config[0x21] = 0x80;
226: d->config[0x22] = 0x00; // memory_limit
227: d->config[0x23] = 0x80;
228: d->config[0x24] = 0x01; // prefetchable_memory_base
229: d->config[0x25] = 0x80;
230: d->config[0x26] = 0xF1; // prefectchable_memory_limit
231: d->config[0x27] = 0x7F;
232: // d->config[0x34] = 0xdc // capabilities_pointer
1.1.1.7 ! root 233: return 0;
! 234: }
1.1 root 235:
1.1.1.7 ! root 236: static int unin_agp_pci_host_init(PCIDevice *d)
! 237: {
1.1.1.4 root 238: pci_config_set_vendor_id(d->config, PCI_VENDOR_ID_APPLE);
239: pci_config_set_device_id(d->config, PCI_DEVICE_ID_APPLE_UNI_N_AGP);
1.1 root 240: d->config[0x08] = 0x00; // revision
1.1.1.4 root 241: pci_config_set_class(d->config, PCI_CLASS_BRIDGE_HOST);
1.1 root 242: d->config[0x0C] = 0x08; // cache_line_size
243: d->config[0x0D] = 0x10; // latency_timer
1.1.1.5 root 244: d->config[PCI_HEADER_TYPE] = PCI_HEADER_TYPE_NORMAL; // header_type
1.1 root 245: // d->config[0x34] = 0x80; // capabilities_pointer
1.1.1.7 ! root 246: return 0;
! 247: }
1.1 root 248:
1.1.1.7 ! root 249: static int unin_internal_pci_host_init(PCIDevice *d)
! 250: {
1.1.1.4 root 251: pci_config_set_vendor_id(d->config, PCI_VENDOR_ID_APPLE);
252: pci_config_set_device_id(d->config, PCI_DEVICE_ID_APPLE_UNI_N_I_PCI);
1.1 root 253: d->config[0x08] = 0x00; // revision
1.1.1.4 root 254: pci_config_set_class(d->config, PCI_CLASS_BRIDGE_HOST);
1.1 root 255: d->config[0x0C] = 0x08; // cache_line_size
256: d->config[0x0D] = 0x10; // latency_timer
1.1.1.5 root 257: d->config[PCI_HEADER_TYPE] = PCI_HEADER_TYPE_NORMAL; // header_type
1.1 root 258: d->config[0x34] = 0x00; // capabilities_pointer
1.1.1.7 ! root 259: return 0;
! 260: }
! 261:
! 262: static PCIDeviceInfo unin_main_pci_host_info = {
! 263: .qdev.name = "uni-north",
! 264: .qdev.size = sizeof(PCIDevice),
! 265: .init = unin_main_pci_host_init,
! 266: };
! 267:
! 268: static PCIDeviceInfo dec_21154_pci_host_info = {
! 269: .qdev.name = "dec-21154",
! 270: .qdev.size = sizeof(PCIDevice),
! 271: .init = dec_21154_pci_host_init,
! 272: };
! 273:
! 274: static PCIDeviceInfo unin_agp_pci_host_info = {
! 275: .qdev.name = "uni-north-agp",
! 276: .qdev.size = sizeof(PCIDevice),
! 277: .init = unin_agp_pci_host_init,
! 278: };
1.1.1.4 root 279:
1.1.1.7 ! root 280: static PCIDeviceInfo unin_internal_pci_host_info = {
! 281: .qdev.name = "uni-north-pci",
! 282: .qdev.size = sizeof(PCIDevice),
! 283: .init = unin_internal_pci_host_init,
! 284: };
! 285:
! 286: static void unin_register_devices(void)
! 287: {
! 288: sysbus_register_dev("uni-north", sizeof(UNINState),
! 289: pci_unin_main_init_device);
! 290: pci_qdev_register(&unin_main_pci_host_info);
! 291: sysbus_register_dev("dec-21154", sizeof(UNINState),
! 292: pci_dec_21154_init_device);
! 293: pci_qdev_register(&dec_21154_pci_host_info);
! 294: sysbus_register_dev("uni-north-agp", sizeof(UNINState),
! 295: pci_unin_agp_init_device);
! 296: pci_qdev_register(&unin_agp_pci_host_info);
! 297: sysbus_register_dev("uni-north-pci", sizeof(UNINState),
! 298: pci_unin_internal_init_device);
! 299: pci_qdev_register(&unin_internal_pci_host_info);
1.1 root 300: }
1.1.1.7 ! root 301:
! 302: device_init(unin_register_devices)
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