Diff for /qemu/hw/versatile_pci.c between versions 1.1.1.3 and 1.1.1.4

version 1.1.1.3, 2018/04/24 16:48:25 version 1.1.1.4, 2018/04/24 16:52:35
Line 124  PCIBus *pci_vpb_init(qemu_irq *pic, int  Line 124  PCIBus *pci_vpb_init(qemu_irq *pic, int 
         isa_mmio_init(base + 0x03000000, 0x00100000);          isa_mmio_init(base + 0x03000000, 0x00100000);
     }      }
   
     d->config[0x00] = 0xee; // vendor_id      pci_config_set_vendor_id(d->config, PCI_VENDOR_ID_XILINX);
     d->config[0x01] = 0x10;  
     /* Both boards have the same device ID.  Oh well.  */      /* Both boards have the same device ID.  Oh well.  */
     d->config[0x02] = 0x00; // device_id      pci_config_set_device_id(d->config, 0x0300); // device_id
     d->config[0x03] = 0x03;  
     d->config[0x04] = 0x00;      d->config[0x04] = 0x00;
     d->config[0x05] = 0x00;      d->config[0x05] = 0x00;
     d->config[0x06] = 0x20;      d->config[0x06] = 0x20;
     d->config[0x07] = 0x02;      d->config[0x07] = 0x02;
     d->config[0x08] = 0x00; // revision      d->config[0x08] = 0x00; // revision
     d->config[0x09] = 0x00; // programming i/f      d->config[0x09] = 0x00; // programming i/f
     d->config[0x0A] = 0x40; // class_sub = pci host      pci_config_set_class(d->config, PCI_CLASS_PROCESSOR_CO);
     d->config[0x0B] = 0x0b; // class_base = PCI_bridge  
     d->config[0x0D] = 0x10; // latency_timer      d->config[0x0D] = 0x10; // latency_timer
   
     return s;      return s;
 }  }
   

Removed from v.1.1.1.3  
changed lines
  Added in v.1.1.1.4


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