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1.1.1.4 root 1: /*
1.1 root 2: * ARM Versatile Platform/Application Baseboard System emulation.
3: *
1.1.1.4 root 4: * Copyright (c) 2005-2007 CodeSourcery.
1.1 root 5: * Written by Paul Brook
6: *
1.1.1.10 root 7: * This code is licensed under the GPL.
1.1 root 8: */
9:
1.1.1.6 root 10: #include "sysbus.h"
1.1.1.4 root 11: #include "arm-misc.h"
12: #include "devices.h"
13: #include "net.h"
14: #include "sysemu.h"
15: #include "pci.h"
1.1.1.12! root 16: #include "i2c.h"
1.1.1.4 root 17: #include "boards.h"
1.1.1.9 root 18: #include "blockdev.h"
1.1.1.12! root 19: #include "exec-memory.h"
! 20: #include "flash.h"
! 21:
! 22: #define VERSATILE_FLASH_ADDR 0x34000000
! 23: #define VERSATILE_FLASH_SIZE (64 * 1024 * 1024)
! 24: #define VERSATILE_FLASH_SECT_SIZE (256 * 1024)
1.1 root 25:
26: /* Primary interrupt controller. */
27:
28: typedef struct vpb_sic_state
29: {
1.1.1.6 root 30: SysBusDevice busdev;
1.1.1.12! root 31: MemoryRegion iomem;
1.1 root 32: uint32_t level;
33: uint32_t mask;
34: uint32_t pic_enable;
1.1.1.6 root 35: qemu_irq parent[32];
1.1 root 36: int irq;
37: } vpb_sic_state;
38:
1.1.1.9 root 39: static const VMStateDescription vmstate_vpb_sic = {
40: .name = "versatilepb_sic",
41: .version_id = 1,
42: .minimum_version_id = 1,
43: .fields = (VMStateField[]) {
44: VMSTATE_UINT32(level, vpb_sic_state),
45: VMSTATE_UINT32(mask, vpb_sic_state),
46: VMSTATE_UINT32(pic_enable, vpb_sic_state),
47: VMSTATE_END_OF_LIST()
48: }
49: };
50:
1.1 root 51: static void vpb_sic_update(vpb_sic_state *s)
52: {
53: uint32_t flags;
54:
55: flags = s->level & s->mask;
1.1.1.4 root 56: qemu_set_irq(s->parent[s->irq], flags != 0);
1.1 root 57: }
58:
59: static void vpb_sic_update_pic(vpb_sic_state *s)
60: {
61: int i;
62: uint32_t mask;
63:
64: for (i = 21; i <= 30; i++) {
65: mask = 1u << i;
66: if (!(s->pic_enable & mask))
67: continue;
1.1.1.4 root 68: qemu_set_irq(s->parent[i], (s->level & mask) != 0);
1.1 root 69: }
70: }
71:
72: static void vpb_sic_set_irq(void *opaque, int irq, int level)
73: {
74: vpb_sic_state *s = (vpb_sic_state *)opaque;
75: if (level)
76: s->level |= 1u << irq;
77: else
78: s->level &= ~(1u << irq);
79: if (s->pic_enable & (1u << irq))
1.1.1.4 root 80: qemu_set_irq(s->parent[irq], level);
1.1 root 81: vpb_sic_update(s);
82: }
83:
1.1.1.12! root 84: static uint64_t vpb_sic_read(void *opaque, target_phys_addr_t offset,
! 85: unsigned size)
1.1 root 86: {
87: vpb_sic_state *s = (vpb_sic_state *)opaque;
88:
89: switch (offset >> 2) {
90: case 0: /* STATUS */
91: return s->level & s->mask;
92: case 1: /* RAWSTAT */
93: return s->level;
94: case 2: /* ENABLE */
95: return s->mask;
96: case 4: /* SOFTINT */
97: return s->level & 1;
98: case 8: /* PICENABLE */
99: return s->pic_enable;
100: default:
1.1.1.3 root 101: printf ("vpb_sic_read: Bad register offset 0x%x\n", (int)offset);
1.1 root 102: return 0;
103: }
104: }
105:
106: static void vpb_sic_write(void *opaque, target_phys_addr_t offset,
1.1.1.12! root 107: uint64_t value, unsigned size)
1.1 root 108: {
109: vpb_sic_state *s = (vpb_sic_state *)opaque;
110:
111: switch (offset >> 2) {
112: case 2: /* ENSET */
113: s->mask |= value;
114: break;
115: case 3: /* ENCLR */
116: s->mask &= ~value;
117: break;
118: case 4: /* SOFTINTSET */
119: if (value)
120: s->mask |= 1;
121: break;
122: case 5: /* SOFTINTCLR */
123: if (value)
124: s->mask &= ~1u;
125: break;
126: case 8: /* PICENSET */
127: s->pic_enable |= (value & 0x7fe00000);
128: vpb_sic_update_pic(s);
129: break;
130: case 9: /* PICENCLR */
131: s->pic_enable &= ~value;
132: vpb_sic_update_pic(s);
133: break;
134: default:
1.1.1.3 root 135: printf ("vpb_sic_write: Bad register offset 0x%x\n", (int)offset);
1.1 root 136: return;
137: }
138: vpb_sic_update(s);
139: }
140:
1.1.1.12! root 141: static const MemoryRegionOps vpb_sic_ops = {
! 142: .read = vpb_sic_read,
! 143: .write = vpb_sic_write,
! 144: .endianness = DEVICE_NATIVE_ENDIAN,
1.1 root 145: };
146:
1.1.1.7 root 147: static int vpb_sic_init(SysBusDevice *dev)
1.1 root 148: {
1.1.1.6 root 149: vpb_sic_state *s = FROM_SYSBUS(vpb_sic_state, dev);
150: int i;
1.1 root 151:
1.1.1.6 root 152: qdev_init_gpio_in(&dev->qdev, vpb_sic_set_irq, 32);
153: for (i = 0; i < 32; i++) {
154: sysbus_init_irq(dev, &s->parent[i]);
155: }
156: s->irq = 31;
1.1.1.12! root 157: memory_region_init_io(&s->iomem, &vpb_sic_ops, s, "vpb-sic", 0x1000);
! 158: sysbus_init_mmio(dev, &s->iomem);
1.1.1.7 root 159: return 0;
1.1 root 160: }
161:
162: /* Board init. */
163:
164: /* The AB and PB boards both use the same core, just with different
165: peripherans and expansion busses. For now we emulate a subset of the
166: PB peripherals and just change the board ID. */
167:
1.1.1.5 root 168: static struct arm_boot_info versatile_binfo;
169:
1.1.1.6 root 170: static void versatile_init(ram_addr_t ram_size,
1.1.1.5 root 171: const char *boot_device,
1.1 root 172: const char *kernel_filename, const char *kernel_cmdline,
1.1.1.4 root 173: const char *initrd_filename, const char *cpu_model,
174: int board_id)
1.1 root 175: {
1.1.1.12! root 176: CPUARMState *env;
! 177: MemoryRegion *sysmem = get_system_memory();
! 178: MemoryRegion *ram = g_new(MemoryRegion, 1);
1.1.1.6 root 179: qemu_irq *cpu_pic;
180: qemu_irq pic[32];
181: qemu_irq sic[32];
1.1.1.11 root 182: DeviceState *dev, *sysctl;
183: SysBusDevice *busdev;
184: DeviceState *pl041;
1.1.1.2 root 185: PCIBus *pci_bus;
186: NICInfo *nd;
1.1.1.12! root 187: i2c_bus *i2c;
1.1.1.2 root 188: int n;
189: int done_smc = 0;
1.1.1.12! root 190: DriveInfo *dinfo;
1.1 root 191:
1.1.1.4 root 192: if (!cpu_model)
193: cpu_model = "arm926";
194: env = cpu_init(cpu_model);
195: if (!env) {
196: fprintf(stderr, "Unable to find CPU definition\n");
197: exit(1);
198: }
1.1.1.12! root 199: memory_region_init_ram(ram, "versatile.ram", ram_size);
! 200: vmstate_register_ram_global(ram);
1.1.1.5 root 201: /* ??? RAM should repeat to fill physical memory space. */
1.1 root 202: /* SDRAM at address zero. */
1.1.1.12! root 203: memory_region_add_subregion(sysmem, 0, ram);
1.1 root 204:
1.1.1.11 root 205: sysctl = qdev_create(NULL, "realview_sysctl");
206: qdev_prop_set_uint32(sysctl, "sys_id", 0x41007004);
207: qdev_prop_set_uint32(sysctl, "proc_id", 0x02000000);
1.1.1.12! root 208: qdev_init_nofail(sysctl);
1.1.1.11 root 209: sysbus_mmio_map(sysbus_from_qdev(sysctl), 0, 0x10000000);
210:
1.1.1.6 root 211: cpu_pic = arm_pic_init_cpu(env);
212: dev = sysbus_create_varargs("pl190", 0x10140000,
213: cpu_pic[0], cpu_pic[1], NULL);
214: for (n = 0; n < 32; n++) {
215: pic[n] = qdev_get_gpio_in(dev, n);
216: }
217: dev = sysbus_create_simple("versatilepb_sic", 0x10003000, NULL);
218: for (n = 0; n < 32; n++) {
219: sysbus_connect_irq(sysbus_from_qdev(dev), n, pic[n]);
220: sic[n] = qdev_get_gpio_in(dev, n);
221: }
222:
223: sysbus_create_simple("pl050_keyboard", 0x10006000, sic[3]);
224: sysbus_create_simple("pl050_mouse", 0x10007000, sic[4]);
225:
1.1.1.11 root 226: dev = qdev_create(NULL, "versatile_pci");
227: busdev = sysbus_from_qdev(dev);
228: qdev_init_nofail(dev);
229: sysbus_mmio_map(busdev, 0, 0x41000000); /* PCI self-config */
230: sysbus_mmio_map(busdev, 1, 0x42000000); /* PCI config */
231: sysbus_connect_irq(busdev, 0, sic[27]);
232: sysbus_connect_irq(busdev, 1, sic[28]);
233: sysbus_connect_irq(busdev, 2, sic[29]);
234: sysbus_connect_irq(busdev, 3, sic[30]);
1.1.1.6 root 235: pci_bus = (PCIBus *)qdev_get_child_bus(dev, "pci");
1.1 root 236:
1.1.1.2 root 237: /* The Versatile PCI bridge does not provide access to PCI IO space,
238: so many of the qemu PCI devices are not useable. */
239: for(n = 0; n < nb_nics; n++) {
240: nd = &nd_table[n];
1.1.1.5 root 241:
1.1.1.10 root 242: if (!done_smc && (!nd->model || strcmp(nd->model, "smc91c111") == 0)) {
1.1.1.4 root 243: smc91c111_init(nd, 0x10010000, sic[25]);
1.1.1.5 root 244: done_smc = 1;
1.1 root 245: } else {
1.1.1.7 root 246: pci_nic_init_nofail(nd, "rtl8139", NULL);
1.1.1.2 root 247: }
248: }
249: if (usb_enabled) {
1.1.1.12! root 250: pci_create_simple(pci_bus, -1, "pci-ohci");
1.1.1.4 root 251: }
1.1.1.6 root 252: n = drive_get_max_bus(IF_SCSI);
253: while (n >= 0) {
254: pci_create_simple(pci_bus, -1, "lsi53c895a");
255: n--;
1.1 root 256: }
257:
1.1.1.6 root 258: sysbus_create_simple("pl011", 0x101f1000, pic[12]);
259: sysbus_create_simple("pl011", 0x101f2000, pic[13]);
260: sysbus_create_simple("pl011", 0x101f3000, pic[14]);
261: sysbus_create_simple("pl011", 0x10009000, sic[6]);
262:
263: sysbus_create_simple("pl080", 0x10130000, pic[17]);
264: sysbus_create_simple("sp804", 0x101e2000, pic[4]);
265: sysbus_create_simple("sp804", 0x101e3000, pic[5]);
1.1 root 266:
267: /* The versatile/PB actually has a modified Color LCD controller
268: that includes hardware cursor support from the PL111. */
1.1.1.11 root 269: dev = sysbus_create_simple("pl110_versatile", 0x10120000, pic[16]);
270: /* Wire up the mux control signals from the SYS_CLCD register */
271: qdev_connect_gpio_out(sysctl, 0, qdev_get_gpio_in(dev, 0));
1.1.1.4 root 272:
1.1.1.6 root 273: sysbus_create_varargs("pl181", 0x10005000, sic[22], sic[1], NULL);
274: sysbus_create_varargs("pl181", 0x1000b000, sic[23], sic[2], NULL);
1.1.1.4 root 275:
276: /* Add PL031 Real Time Clock. */
1.1.1.6 root 277: sysbus_create_simple("pl031", 0x101e8000, pic[10]);
1.1 root 278:
1.1.1.12! root 279: dev = sysbus_create_simple("versatile_i2c", 0x10002000, NULL);
! 280: i2c = (i2c_bus *)qdev_get_child_bus(dev, "i2c");
! 281: i2c_create_slave(i2c, "ds1338", 0x68);
! 282:
1.1.1.11 root 283: /* Add PL041 AACI Interface to the LM4549 codec */
284: pl041 = qdev_create(NULL, "pl041");
285: qdev_prop_set_uint32(pl041, "nc_fifo_depth", 512);
286: qdev_init_nofail(pl041);
287: sysbus_mmio_map(sysbus_from_qdev(pl041), 0, 0x10004000);
288: sysbus_connect_irq(sysbus_from_qdev(pl041), 0, sic[24]);
289:
1.1 root 290: /* Memory map for Versatile/PB: */
291: /* 0x10000000 System registers. */
292: /* 0x10001000 PCI controller config registers. */
293: /* 0x10002000 Serial bus interface. */
294: /* 0x10003000 Secondary interrupt controller. */
295: /* 0x10004000 AACI (audio). */
1.1.1.4 root 296: /* 0x10005000 MMCI0. */
1.1 root 297: /* 0x10006000 KMI0 (keyboard). */
298: /* 0x10007000 KMI1 (mouse). */
299: /* 0x10008000 Character LCD Interface. */
300: /* 0x10009000 UART3. */
301: /* 0x1000a000 Smart card 1. */
1.1.1.4 root 302: /* 0x1000b000 MMCI1. */
1.1 root 303: /* 0x10010000 Ethernet. */
304: /* 0x10020000 USB. */
305: /* 0x10100000 SSMC. */
306: /* 0x10110000 MPMC. */
307: /* 0x10120000 CLCD Controller. */
308: /* 0x10130000 DMA Controller. */
309: /* 0x10140000 Vectored interrupt controller. */
310: /* 0x101d0000 AHB Monitor Interface. */
311: /* 0x101e0000 System Controller. */
312: /* 0x101e1000 Watchdog Interface. */
313: /* 0x101e2000 Timer 0/1. */
314: /* 0x101e3000 Timer 2/3. */
315: /* 0x101e4000 GPIO port 0. */
316: /* 0x101e5000 GPIO port 1. */
317: /* 0x101e6000 GPIO port 2. */
318: /* 0x101e7000 GPIO port 3. */
319: /* 0x101e8000 RTC. */
320: /* 0x101f0000 Smart card 0. */
321: /* 0x101f1000 UART0. */
322: /* 0x101f2000 UART1. */
323: /* 0x101f3000 UART2. */
324: /* 0x101f4000 SSPI. */
1.1.1.12! root 325: /* 0x34000000 NOR Flash */
! 326:
! 327: dinfo = drive_get(IF_PFLASH, 0, 0);
! 328: if (!pflash_cfi01_register(VERSATILE_FLASH_ADDR, NULL, "versatile.flash",
! 329: VERSATILE_FLASH_SIZE, dinfo ? dinfo->bdrv : NULL,
! 330: VERSATILE_FLASH_SECT_SIZE,
! 331: VERSATILE_FLASH_SIZE / VERSATILE_FLASH_SECT_SIZE,
! 332: 4, 0x0089, 0x0018, 0x0000, 0x0, 0)) {
! 333: fprintf(stderr, "qemu: Error registering flash memory.\n");
! 334: }
1.1 root 335:
1.1.1.5 root 336: versatile_binfo.ram_size = ram_size;
337: versatile_binfo.kernel_filename = kernel_filename;
338: versatile_binfo.kernel_cmdline = kernel_cmdline;
339: versatile_binfo.initrd_filename = initrd_filename;
340: versatile_binfo.board_id = board_id;
341: arm_load_kernel(env, &versatile_binfo);
1.1 root 342: }
343:
1.1.1.6 root 344: static void vpb_init(ram_addr_t ram_size,
1.1.1.5 root 345: const char *boot_device,
1.1 root 346: const char *kernel_filename, const char *kernel_cmdline,
1.1.1.4 root 347: const char *initrd_filename, const char *cpu_model)
1.1 root 348: {
1.1.1.6 root 349: versatile_init(ram_size,
1.1.1.5 root 350: boot_device,
1.1 root 351: kernel_filename, kernel_cmdline,
1.1.1.4 root 352: initrd_filename, cpu_model, 0x183);
1.1 root 353: }
354:
1.1.1.6 root 355: static void vab_init(ram_addr_t ram_size,
1.1.1.5 root 356: const char *boot_device,
1.1 root 357: const char *kernel_filename, const char *kernel_cmdline,
1.1.1.4 root 358: const char *initrd_filename, const char *cpu_model)
1.1 root 359: {
1.1.1.6 root 360: versatile_init(ram_size,
1.1.1.5 root 361: boot_device,
1.1 root 362: kernel_filename, kernel_cmdline,
1.1.1.4 root 363: initrd_filename, cpu_model, 0x25e);
1.1 root 364: }
365:
1.1.1.6 root 366: static QEMUMachine versatilepb_machine = {
1.1.1.5 root 367: .name = "versatilepb",
368: .desc = "ARM Versatile/PB (ARM926EJ-S)",
369: .init = vpb_init,
370: .use_scsi = 1,
1.1 root 371: };
372:
1.1.1.6 root 373: static QEMUMachine versatileab_machine = {
1.1.1.5 root 374: .name = "versatileab",
375: .desc = "ARM Versatile/AB (ARM926EJ-S)",
376: .init = vab_init,
377: .use_scsi = 1,
1.1 root 378: };
1.1.1.6 root 379:
380: static void versatile_machine_init(void)
381: {
382: qemu_register_machine(&versatilepb_machine);
383: qemu_register_machine(&versatileab_machine);
384: }
385:
386: machine_init(versatile_machine_init);
387:
1.1.1.12! root 388: static void vpb_sic_class_init(ObjectClass *klass, void *data)
! 389: {
! 390: DeviceClass *dc = DEVICE_CLASS(klass);
! 391: SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
! 392:
! 393: k->init = vpb_sic_init;
! 394: dc->no_user = 1;
! 395: dc->vmsd = &vmstate_vpb_sic;
! 396: }
! 397:
! 398: static TypeInfo vpb_sic_info = {
! 399: .name = "versatilepb_sic",
! 400: .parent = TYPE_SYS_BUS_DEVICE,
! 401: .instance_size = sizeof(vpb_sic_state),
! 402: .class_init = vpb_sic_class_init,
1.1.1.9 root 403: };
404:
1.1.1.12! root 405: static void versatilepb_register_types(void)
1.1.1.6 root 406: {
1.1.1.12! root 407: type_register_static(&vpb_sic_info);
1.1.1.6 root 408: }
409:
1.1.1.12! root 410: type_init(versatilepb_register_types)
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