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1.1.1.4 root 1: /*
1.1 root 2: * ARM Versatile Platform/Application Baseboard System emulation.
3: *
1.1.1.4 root 4: * Copyright (c) 2005-2007 CodeSourcery.
1.1 root 5: * Written by Paul Brook
6: *
7: * This code is licenced under the GPL.
8: */
9:
1.1.1.4 root 10: #include "hw.h"
11: #include "arm-misc.h"
12: #include "primecell.h"
13: #include "devices.h"
14: #include "net.h"
15: #include "sysemu.h"
16: #include "pci.h"
17: #include "boards.h"
1.1 root 18:
19: /* Primary interrupt controller. */
20:
21: typedef struct vpb_sic_state
22: {
23: uint32_t level;
24: uint32_t mask;
25: uint32_t pic_enable;
1.1.1.4 root 26: qemu_irq *parent;
1.1 root 27: int irq;
28: } vpb_sic_state;
29:
30: static void vpb_sic_update(vpb_sic_state *s)
31: {
32: uint32_t flags;
33:
34: flags = s->level & s->mask;
1.1.1.4 root 35: qemu_set_irq(s->parent[s->irq], flags != 0);
1.1 root 36: }
37:
38: static void vpb_sic_update_pic(vpb_sic_state *s)
39: {
40: int i;
41: uint32_t mask;
42:
43: for (i = 21; i <= 30; i++) {
44: mask = 1u << i;
45: if (!(s->pic_enable & mask))
46: continue;
1.1.1.4 root 47: qemu_set_irq(s->parent[i], (s->level & mask) != 0);
1.1 root 48: }
49: }
50:
51: static void vpb_sic_set_irq(void *opaque, int irq, int level)
52: {
53: vpb_sic_state *s = (vpb_sic_state *)opaque;
54: if (level)
55: s->level |= 1u << irq;
56: else
57: s->level &= ~(1u << irq);
58: if (s->pic_enable & (1u << irq))
1.1.1.4 root 59: qemu_set_irq(s->parent[irq], level);
1.1 root 60: vpb_sic_update(s);
61: }
62:
63: static uint32_t vpb_sic_read(void *opaque, target_phys_addr_t offset)
64: {
65: vpb_sic_state *s = (vpb_sic_state *)opaque;
66:
67: switch (offset >> 2) {
68: case 0: /* STATUS */
69: return s->level & s->mask;
70: case 1: /* RAWSTAT */
71: return s->level;
72: case 2: /* ENABLE */
73: return s->mask;
74: case 4: /* SOFTINT */
75: return s->level & 1;
76: case 8: /* PICENABLE */
77: return s->pic_enable;
78: default:
1.1.1.3 root 79: printf ("vpb_sic_read: Bad register offset 0x%x\n", (int)offset);
1.1 root 80: return 0;
81: }
82: }
83:
84: static void vpb_sic_write(void *opaque, target_phys_addr_t offset,
85: uint32_t value)
86: {
87: vpb_sic_state *s = (vpb_sic_state *)opaque;
88:
89: switch (offset >> 2) {
90: case 2: /* ENSET */
91: s->mask |= value;
92: break;
93: case 3: /* ENCLR */
94: s->mask &= ~value;
95: break;
96: case 4: /* SOFTINTSET */
97: if (value)
98: s->mask |= 1;
99: break;
100: case 5: /* SOFTINTCLR */
101: if (value)
102: s->mask &= ~1u;
103: break;
104: case 8: /* PICENSET */
105: s->pic_enable |= (value & 0x7fe00000);
106: vpb_sic_update_pic(s);
107: break;
108: case 9: /* PICENCLR */
109: s->pic_enable &= ~value;
110: vpb_sic_update_pic(s);
111: break;
112: default:
1.1.1.3 root 113: printf ("vpb_sic_write: Bad register offset 0x%x\n", (int)offset);
1.1 root 114: return;
115: }
116: vpb_sic_update(s);
117: }
118:
119: static CPUReadMemoryFunc *vpb_sic_readfn[] = {
120: vpb_sic_read,
121: vpb_sic_read,
122: vpb_sic_read
123: };
124:
125: static CPUWriteMemoryFunc *vpb_sic_writefn[] = {
126: vpb_sic_write,
127: vpb_sic_write,
128: vpb_sic_write
129: };
130:
1.1.1.4 root 131: static qemu_irq *vpb_sic_init(uint32_t base, qemu_irq *parent, int irq)
1.1 root 132: {
133: vpb_sic_state *s;
1.1.1.4 root 134: qemu_irq *qi;
1.1 root 135: int iomemtype;
136:
137: s = (vpb_sic_state *)qemu_mallocz(sizeof(vpb_sic_state));
1.1.1.4 root 138: qi = qemu_allocate_irqs(vpb_sic_set_irq, s, 32);
1.1 root 139: s->parent = parent;
140: s->irq = irq;
141: iomemtype = cpu_register_io_memory(0, vpb_sic_readfn,
142: vpb_sic_writefn, s);
1.1.1.4 root 143: cpu_register_physical_memory(base, 0x00001000, iomemtype);
1.1 root 144: /* ??? Save/restore. */
1.1.1.4 root 145: return qi;
1.1 root 146: }
147:
148: /* Board init. */
149:
150: /* The AB and PB boards both use the same core, just with different
151: peripherans and expansion busses. For now we emulate a subset of the
152: PB peripherals and just change the board ID. */
153:
1.1.1.5 ! root 154: static struct arm_boot_info versatile_binfo;
! 155:
! 156: static void versatile_init(ram_addr_t ram_size, int vga_ram_size,
! 157: const char *boot_device,
1.1 root 158: const char *kernel_filename, const char *kernel_cmdline,
1.1.1.4 root 159: const char *initrd_filename, const char *cpu_model,
160: int board_id)
1.1 root 161: {
162: CPUState *env;
1.1.1.4 root 163: qemu_irq *pic;
164: qemu_irq *sic;
1.1.1.2 root 165: void *scsi_hba;
166: PCIBus *pci_bus;
167: NICInfo *nd;
168: int n;
169: int done_smc = 0;
1.1.1.4 root 170: int index;
1.1 root 171:
1.1.1.4 root 172: if (!cpu_model)
173: cpu_model = "arm926";
174: env = cpu_init(cpu_model);
175: if (!env) {
176: fprintf(stderr, "Unable to find CPU definition\n");
177: exit(1);
178: }
1.1.1.5 ! root 179: /* ??? RAM should repeat to fill physical memory space. */
1.1 root 180: /* SDRAM at address zero. */
181: cpu_register_physical_memory(0, ram_size, IO_MEM_RAM);
182:
1.1.1.3 root 183: arm_sysctl_init(0x10000000, 0x41007004);
1.1 root 184: pic = arm_pic_init_cpu(env);
1.1.1.4 root 185: pic = pl190_init(0x10140000, pic[0], pic[1]);
1.1 root 186: sic = vpb_sic_init(0x10003000, pic, 31);
1.1.1.4 root 187: pl050_init(0x10006000, sic[3], 0);
188: pl050_init(0x10007000, sic[4], 1);
1.1 root 189:
1.1.1.3 root 190: pci_bus = pci_vpb_init(sic, 27, 0);
1.1.1.2 root 191: /* The Versatile PCI bridge does not provide access to PCI IO space,
192: so many of the qemu PCI devices are not useable. */
193: for(n = 0; n < nb_nics; n++) {
194: nd = &nd_table[n];
1.1.1.5 ! root 195:
! 196: if ((!nd->model && !done_smc) || strcmp(nd->model, "smc91c111") == 0) {
1.1.1.4 root 197: smc91c111_init(nd, 0x10010000, sic[25]);
1.1.1.5 ! root 198: done_smc = 1;
1.1 root 199: } else {
1.1.1.5 ! root 200: pci_nic_init(pci_bus, nd, -1, "rtl8139");
1.1.1.2 root 201: }
202: }
203: if (usb_enabled) {
1.1.1.4 root 204: usb_ohci_init_pci(pci_bus, 3, -1);
205: }
206: if (drive_get_max_bus(IF_SCSI) > 0) {
207: fprintf(stderr, "qemu: too many SCSI bus\n");
208: exit(1);
1.1.1.2 root 209: }
210: scsi_hba = lsi_scsi_init(pci_bus, -1);
1.1.1.4 root 211: for (n = 0; n < LSI_MAX_DEVS; n++) {
212: index = drive_get_index(IF_SCSI, 0, n);
213: if (index == -1)
214: continue;
215: lsi_scsi_attach(scsi_hba, drives_table[index].bdrv, n);
1.1 root 216: }
217:
1.1.1.4 root 218: pl011_init(0x101f1000, pic[12], serial_hds[0], PL011_ARM);
219: pl011_init(0x101f2000, pic[13], serial_hds[1], PL011_ARM);
220: pl011_init(0x101f3000, pic[14], serial_hds[2], PL011_ARM);
221: pl011_init(0x10009000, sic[6], serial_hds[3], PL011_ARM);
222:
223: pl080_init(0x10130000, pic[17], 8);
224: sp804_init(0x101e2000, pic[4]);
225: sp804_init(0x101e3000, pic[5]);
1.1 root 226:
227: /* The versatile/PB actually has a modified Color LCD controller
228: that includes hardware cursor support from the PL111. */
1.1.1.5 ! root 229: pl110_init(0x10120000, pic[16], 1);
1.1.1.4 root 230:
231: index = drive_get_index(IF_SD, 0, 0);
232: if (index == -1) {
233: fprintf(stderr, "qemu: missing SecureDigital card\n");
234: exit(1);
235: }
236:
237: pl181_init(0x10005000, drives_table[index].bdrv, sic[22], sic[1]);
238: #if 0
239: /* Disabled because there's no way of specifying a block device. */
240: pl181_init(0x1000b000, NULL, sic, 23, 2);
241: #endif
242:
243: /* Add PL031 Real Time Clock. */
244: pl031_init(0x101e8000,pic[10]);
1.1 root 245:
246: /* Memory map for Versatile/PB: */
247: /* 0x10000000 System registers. */
248: /* 0x10001000 PCI controller config registers. */
249: /* 0x10002000 Serial bus interface. */
250: /* 0x10003000 Secondary interrupt controller. */
251: /* 0x10004000 AACI (audio). */
1.1.1.4 root 252: /* 0x10005000 MMCI0. */
1.1 root 253: /* 0x10006000 KMI0 (keyboard). */
254: /* 0x10007000 KMI1 (mouse). */
255: /* 0x10008000 Character LCD Interface. */
256: /* 0x10009000 UART3. */
257: /* 0x1000a000 Smart card 1. */
1.1.1.4 root 258: /* 0x1000b000 MMCI1. */
1.1 root 259: /* 0x10010000 Ethernet. */
260: /* 0x10020000 USB. */
261: /* 0x10100000 SSMC. */
262: /* 0x10110000 MPMC. */
263: /* 0x10120000 CLCD Controller. */
264: /* 0x10130000 DMA Controller. */
265: /* 0x10140000 Vectored interrupt controller. */
266: /* 0x101d0000 AHB Monitor Interface. */
267: /* 0x101e0000 System Controller. */
268: /* 0x101e1000 Watchdog Interface. */
269: /* 0x101e2000 Timer 0/1. */
270: /* 0x101e3000 Timer 2/3. */
271: /* 0x101e4000 GPIO port 0. */
272: /* 0x101e5000 GPIO port 1. */
273: /* 0x101e6000 GPIO port 2. */
274: /* 0x101e7000 GPIO port 3. */
275: /* 0x101e8000 RTC. */
276: /* 0x101f0000 Smart card 0. */
277: /* 0x101f1000 UART0. */
278: /* 0x101f2000 UART1. */
279: /* 0x101f3000 UART2. */
280: /* 0x101f4000 SSPI. */
281:
1.1.1.5 ! root 282: versatile_binfo.ram_size = ram_size;
! 283: versatile_binfo.kernel_filename = kernel_filename;
! 284: versatile_binfo.kernel_cmdline = kernel_cmdline;
! 285: versatile_binfo.initrd_filename = initrd_filename;
! 286: versatile_binfo.board_id = board_id;
! 287: arm_load_kernel(env, &versatile_binfo);
1.1 root 288: }
289:
1.1.1.5 ! root 290: static void vpb_init(ram_addr_t ram_size, int vga_ram_size,
! 291: const char *boot_device,
1.1 root 292: const char *kernel_filename, const char *kernel_cmdline,
1.1.1.4 root 293: const char *initrd_filename, const char *cpu_model)
1.1 root 294: {
1.1.1.4 root 295: versatile_init(ram_size, vga_ram_size,
1.1.1.5 ! root 296: boot_device,
1.1 root 297: kernel_filename, kernel_cmdline,
1.1.1.4 root 298: initrd_filename, cpu_model, 0x183);
1.1 root 299: }
300:
1.1.1.5 ! root 301: static void vab_init(ram_addr_t ram_size, int vga_ram_size,
! 302: const char *boot_device,
1.1 root 303: const char *kernel_filename, const char *kernel_cmdline,
1.1.1.4 root 304: const char *initrd_filename, const char *cpu_model)
1.1 root 305: {
1.1.1.4 root 306: versatile_init(ram_size, vga_ram_size,
1.1.1.5 ! root 307: boot_device,
1.1 root 308: kernel_filename, kernel_cmdline,
1.1.1.4 root 309: initrd_filename, cpu_model, 0x25e);
1.1 root 310: }
311:
312: QEMUMachine versatilepb_machine = {
1.1.1.5 ! root 313: .name = "versatilepb",
! 314: .desc = "ARM Versatile/PB (ARM926EJ-S)",
! 315: .init = vpb_init,
! 316: .use_scsi = 1,
1.1 root 317: };
318:
319: QEMUMachine versatileab_machine = {
1.1.1.5 ! root 320: .name = "versatileab",
! 321: .desc = "ARM Versatile/AB (ARM926EJ-S)",
! 322: .init = vab_init,
! 323: .use_scsi = 1,
1.1 root 324: };
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