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1.1 root 1: /*
2: * QEMU internal VGA defines.
1.1.1.4 root 3: *
1.1 root 4: * Copyright (c) 2003-2004 Fabrice Bellard
1.1.1.4 root 5: *
1.1 root 6: * Permission is hereby granted, free of charge, to any person obtaining a copy
7: * of this software and associated documentation files (the "Software"), to deal
8: * in the Software without restriction, including without limitation the rights
9: * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10: * copies of the Software, and to permit persons to whom the Software is
11: * furnished to do so, subject to the following conditions:
12: *
13: * The above copyright notice and this permission notice shall be included in
14: * all copies or substantial portions of the Software.
15: *
16: * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17: * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18: * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19: * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20: * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21: * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22: * THE SOFTWARE.
23: */
1.1.1.8 root 24:
25: #include <hw/hw.h>
26:
1.1 root 27: #define MSR_COLOR_EMULATION 0x01
28: #define MSR_PAGE_SELECT 0x20
29:
30: #define ST01_V_RETRACE 0x08
31: #define ST01_DISP_ENABLE 0x01
32:
33: /* bochs VBE support */
34: #define CONFIG_BOCHS_VBE
35:
1.1.1.2 root 36: #define VBE_DISPI_MAX_XRES 1600
37: #define VBE_DISPI_MAX_YRES 1200
38: #define VBE_DISPI_MAX_BPP 32
1.1 root 39:
40: #define VBE_DISPI_INDEX_ID 0x0
41: #define VBE_DISPI_INDEX_XRES 0x1
42: #define VBE_DISPI_INDEX_YRES 0x2
43: #define VBE_DISPI_INDEX_BPP 0x3
44: #define VBE_DISPI_INDEX_ENABLE 0x4
45: #define VBE_DISPI_INDEX_BANK 0x5
46: #define VBE_DISPI_INDEX_VIRT_WIDTH 0x6
47: #define VBE_DISPI_INDEX_VIRT_HEIGHT 0x7
48: #define VBE_DISPI_INDEX_X_OFFSET 0x8
49: #define VBE_DISPI_INDEX_Y_OFFSET 0x9
1.1.1.9 root 50: #define VBE_DISPI_INDEX_NB 0xa /* size of vbe_regs[] */
51: #define VBE_DISPI_INDEX_VIDEO_MEMORY_64K 0xa /* read-only, not in vbe_regs */
1.1.1.4 root 52:
1.1 root 53: #define VBE_DISPI_ID0 0xB0C0
54: #define VBE_DISPI_ID1 0xB0C1
55: #define VBE_DISPI_ID2 0xB0C2
1.1.1.3 root 56: #define VBE_DISPI_ID3 0xB0C3
57: #define VBE_DISPI_ID4 0xB0C4
1.1.1.9 root 58: #define VBE_DISPI_ID5 0xB0C5
1.1.1.4 root 59:
1.1 root 60: #define VBE_DISPI_DISABLED 0x00
61: #define VBE_DISPI_ENABLED 0x01
1.1.1.2 root 62: #define VBE_DISPI_GETCAPS 0x02
63: #define VBE_DISPI_8BIT_DAC 0x20
1.1 root 64: #define VBE_DISPI_LFB_ENABLED 0x40
65: #define VBE_DISPI_NOCLEARMEM 0x80
1.1.1.4 root 66:
1.1 root 67: #define VBE_DISPI_LFB_PHYSICAL_ADDRESS 0xE0000000
68:
69: #ifdef CONFIG_BOCHS_VBE
70:
71: #define VGA_STATE_COMMON_BOCHS_VBE \
72: uint16_t vbe_index; \
73: uint16_t vbe_regs[VBE_DISPI_INDEX_NB]; \
74: uint32_t vbe_start_addr; \
75: uint32_t vbe_line_offset; \
1.1.1.8 root 76: uint32_t vbe_bank_mask; \
77: int vbe_mapped;
1.1 root 78: #else
79:
80: #define VGA_STATE_COMMON_BOCHS_VBE
81:
82: #endif /* !CONFIG_BOCHS_VBE */
83:
84: #define CH_ATTR_SIZE (160 * 100)
1.1.1.2 root 85: #define VGA_MAX_HEIGHT 2048
1.1 root 86:
1.1.1.5 root 87: struct vga_precise_retrace {
88: int64_t ticks_per_char;
89: int64_t total_chars;
90: int htotal;
91: int hstart;
92: int hend;
93: int vstart;
94: int vend;
95: int freq;
96: };
97:
98: union vga_retrace {
99: struct vga_precise_retrace precise;
100: };
101:
1.1.1.6 root 102: struct VGACommonState;
103: typedef uint8_t (* vga_retrace_fn)(struct VGACommonState *s);
104: typedef void (* vga_update_retrace_info_fn)(struct VGACommonState *s);
105:
106: typedef struct VGACommonState {
107: uint8_t *vram_ptr;
108: ram_addr_t vram_offset;
1.1.1.11! root 109: target_phys_addr_t lfb_addr;
! 110: target_phys_addr_t lfb_end;
! 111: target_phys_addr_t map_addr;
! 112: target_phys_addr_t map_end;
1.1.1.10 root 113: uint32_t vram_size;
1.1.1.6 root 114: uint32_t latch;
1.1.1.11! root 115: uint32_t lfb_vram_mapped; /* whether 0xa0000 is mapped as ram */
1.1.1.6 root 116: uint8_t sr_index;
117: uint8_t sr[256];
118: uint8_t gr_index;
119: uint8_t gr[256];
120: uint8_t ar_index;
121: uint8_t ar[21];
122: int ar_flip_flop;
123: uint8_t cr_index;
124: uint8_t cr[256]; /* CRT registers */
125: uint8_t msr; /* Misc Output Register */
126: uint8_t fcr; /* Feature Control Register */
127: uint8_t st00; /* status 0 */
128: uint8_t st01; /* status 1 */
129: uint8_t dac_state;
130: uint8_t dac_sub_index;
131: uint8_t dac_read_index;
132: uint8_t dac_write_index;
133: uint8_t dac_cache[3]; /* used when writing */
134: int dac_8bit;
135: uint8_t palette[768];
136: int32_t bank_offset;
137: int vga_io_memory;
138: int (*get_bpp)(struct VGACommonState *s);
139: void (*get_offsets)(struct VGACommonState *s,
140: uint32_t *pline_offset,
141: uint32_t *pstart_addr,
142: uint32_t *pline_compare);
143: void (*get_resolution)(struct VGACommonState *s,
144: int *pwidth,
145: int *pheight);
146: VGA_STATE_COMMON_BOCHS_VBE
147: /* display refresh support */
148: DisplayState *ds;
149: uint32_t font_offsets[2];
150: int graphic_mode;
151: uint8_t shift_control;
152: uint8_t double_scan;
153: uint32_t line_offset;
154: uint32_t line_compare;
155: uint32_t start_addr;
156: uint32_t plane_updated;
157: uint32_t last_line_offset;
158: uint8_t last_cw, last_ch;
159: uint32_t last_width, last_height; /* in chars or pixels */
160: uint32_t last_scr_width, last_scr_height; /* in pixels */
161: uint32_t last_depth; /* in bits */
162: uint8_t cursor_start, cursor_end;
163: uint32_t cursor_offset;
164: unsigned int (*rgb_to_pixel)(unsigned int r,
165: unsigned int g, unsigned b);
166: vga_hw_update_ptr update;
167: vga_hw_invalidate_ptr invalidate;
168: vga_hw_screen_dump_ptr screen_dump;
169: vga_hw_text_update_ptr text_update;
170: /* hardware mouse cursor support */
171: uint32_t invalidated_y_table[VGA_MAX_HEIGHT / 32];
172: void (*cursor_invalidate)(struct VGACommonState *s);
173: void (*cursor_draw_line)(struct VGACommonState *s, uint8_t *d, int y);
174: /* tell for each page if it has been updated since the last time */
175: uint32_t last_palette[256];
176: uint32_t last_ch_attr[CH_ATTR_SIZE]; /* XXX: make it dynamic */
177: /* retrace */
178: vga_retrace_fn retrace;
179: vga_update_retrace_info_fn update_retrace_info;
1.1.1.5 root 180: union vga_retrace retrace_info;
1.1.1.8 root 181: uint8_t is_vbe_vmstate;
1.1.1.6 root 182: } VGACommonState;
1.1 root 183:
184: static inline int c6_to_8(int v)
185: {
186: int b;
187: v &= 0x3f;
188: b = v & 1;
189: return (v << 2) | (b << 1) | b;
190: }
191:
1.1.1.8 root 192: void vga_common_init(VGACommonState *s, int vga_ram_size);
193: void vga_init(VGACommonState *s);
1.1.1.11! root 194: int vga_init_io(VGACommonState *s);
1.1.1.8 root 195: void vga_common_reset(VGACommonState *s);
196:
197: void vga_dirty_log_start(VGACommonState *s);
198: void vga_dirty_log_stop(VGACommonState *s);
199: void vga_dirty_log_restart(VGACommonState *s);
200:
201: extern const VMStateDescription vmstate_vga_common;
202: uint32_t vga_ioport_read(void *opaque, uint32_t addr);
203: void vga_ioport_write(void *opaque, uint32_t addr, uint32_t val);
1.1 root 204: uint32_t vga_mem_readb(void *opaque, target_phys_addr_t addr);
205: void vga_mem_writeb(void *opaque, target_phys_addr_t addr, uint32_t val);
1.1.1.8 root 206: void vga_invalidate_scanlines(VGACommonState *s, int y1, int y2);
1.1.1.5 root 207: int ppm_save(const char *filename, struct DisplaySurface *ds);
1.1 root 208:
1.1.1.4 root 209: void vga_draw_cursor_line_8(uint8_t *d1, const uint8_t *src1,
210: int poffset, int w,
1.1 root 211: unsigned int color0, unsigned int color1,
212: unsigned int color_xor);
1.1.1.4 root 213: void vga_draw_cursor_line_16(uint8_t *d1, const uint8_t *src1,
214: int poffset, int w,
1.1 root 215: unsigned int color0, unsigned int color1,
216: unsigned int color_xor);
1.1.1.4 root 217: void vga_draw_cursor_line_32(uint8_t *d1, const uint8_t *src1,
218: int poffset, int w,
1.1 root 219: unsigned int color0, unsigned int color1,
220: unsigned int color_xor);
221:
1.1.1.8 root 222: int vga_ioport_invalid(VGACommonState *s, uint32_t addr);
223: void vga_init_vbe(VGACommonState *s);
224:
1.1 root 225: extern const uint8_t sr_mask[8];
226: extern const uint8_t gr_mask[16];
1.1.1.6 root 227:
228: #define VGA_RAM_SIZE (8192 * 1024)
1.1.1.8 root 229: #define VGABIOS_FILENAME "vgabios.bin"
230: #define VGABIOS_CIRRUS_FILENAME "vgabios-cirrus.bin"
1.1.1.6 root 231:
1.1.1.8 root 232: extern CPUReadMemoryFunc * const vga_mem_read[3];
233: extern CPUWriteMemoryFunc * const vga_mem_write[3];
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