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1.1 root 1: /*
2: * QEMU internal VGA defines.
1.1.1.4 root 3: *
1.1 root 4: * Copyright (c) 2003-2004 Fabrice Bellard
1.1.1.4 root 5: *
1.1 root 6: * Permission is hereby granted, free of charge, to any person obtaining a copy
7: * of this software and associated documentation files (the "Software"), to deal
8: * in the Software without restriction, including without limitation the rights
9: * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10: * copies of the Software, and to permit persons to whom the Software is
11: * furnished to do so, subject to the following conditions:
12: *
13: * The above copyright notice and this permission notice shall be included in
14: * all copies or substantial portions of the Software.
15: *
16: * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17: * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18: * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19: * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20: * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21: * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22: * THE SOFTWARE.
23: */
1.1.1.8 root 24:
25: #include <hw/hw.h>
1.1.1.12 root 26: #include "memory.h"
1.1.1.8 root 27:
1.1 root 28: #define ST01_V_RETRACE 0x08
29: #define ST01_DISP_ENABLE 0x01
30:
31: /* bochs VBE support */
32: #define CONFIG_BOCHS_VBE
33:
1.1.1.2 root 34: #define VBE_DISPI_MAX_XRES 1600
35: #define VBE_DISPI_MAX_YRES 1200
36: #define VBE_DISPI_MAX_BPP 32
1.1 root 37:
38: #define VBE_DISPI_INDEX_ID 0x0
39: #define VBE_DISPI_INDEX_XRES 0x1
40: #define VBE_DISPI_INDEX_YRES 0x2
41: #define VBE_DISPI_INDEX_BPP 0x3
42: #define VBE_DISPI_INDEX_ENABLE 0x4
43: #define VBE_DISPI_INDEX_BANK 0x5
44: #define VBE_DISPI_INDEX_VIRT_WIDTH 0x6
45: #define VBE_DISPI_INDEX_VIRT_HEIGHT 0x7
46: #define VBE_DISPI_INDEX_X_OFFSET 0x8
47: #define VBE_DISPI_INDEX_Y_OFFSET 0x9
1.1.1.9 root 48: #define VBE_DISPI_INDEX_NB 0xa /* size of vbe_regs[] */
49: #define VBE_DISPI_INDEX_VIDEO_MEMORY_64K 0xa /* read-only, not in vbe_regs */
1.1.1.4 root 50:
1.1 root 51: #define VBE_DISPI_ID0 0xB0C0
52: #define VBE_DISPI_ID1 0xB0C1
53: #define VBE_DISPI_ID2 0xB0C2
1.1.1.3 root 54: #define VBE_DISPI_ID3 0xB0C3
55: #define VBE_DISPI_ID4 0xB0C4
1.1.1.9 root 56: #define VBE_DISPI_ID5 0xB0C5
1.1.1.4 root 57:
1.1 root 58: #define VBE_DISPI_DISABLED 0x00
59: #define VBE_DISPI_ENABLED 0x01
1.1.1.2 root 60: #define VBE_DISPI_GETCAPS 0x02
61: #define VBE_DISPI_8BIT_DAC 0x20
1.1 root 62: #define VBE_DISPI_LFB_ENABLED 0x40
63: #define VBE_DISPI_NOCLEARMEM 0x80
1.1.1.4 root 64:
1.1 root 65: #define VBE_DISPI_LFB_PHYSICAL_ADDRESS 0xE0000000
66:
67: #ifdef CONFIG_BOCHS_VBE
68:
69: #define VGA_STATE_COMMON_BOCHS_VBE \
70: uint16_t vbe_index; \
71: uint16_t vbe_regs[VBE_DISPI_INDEX_NB]; \
72: uint32_t vbe_start_addr; \
73: uint32_t vbe_line_offset; \
1.1.1.8 root 74: uint32_t vbe_bank_mask; \
75: int vbe_mapped;
1.1 root 76: #else
77:
78: #define VGA_STATE_COMMON_BOCHS_VBE
79:
80: #endif /* !CONFIG_BOCHS_VBE */
81:
82: #define CH_ATTR_SIZE (160 * 100)
1.1.1.2 root 83: #define VGA_MAX_HEIGHT 2048
1.1 root 84:
1.1.1.5 root 85: struct vga_precise_retrace {
86: int64_t ticks_per_char;
87: int64_t total_chars;
88: int htotal;
89: int hstart;
90: int hend;
91: int vstart;
92: int vend;
93: int freq;
94: };
95:
96: union vga_retrace {
97: struct vga_precise_retrace precise;
98: };
99:
1.1.1.6 root 100: struct VGACommonState;
101: typedef uint8_t (* vga_retrace_fn)(struct VGACommonState *s);
102: typedef void (* vga_update_retrace_info_fn)(struct VGACommonState *s);
103:
104: typedef struct VGACommonState {
1.1.1.12 root 105: MemoryRegion *legacy_address_space;
1.1.1.6 root 106: uint8_t *vram_ptr;
1.1.1.12 root 107: MemoryRegion vram;
1.1.1.13! root 108: MemoryRegion vram_vbe;
1.1.1.10 root 109: uint32_t vram_size;
1.1.1.6 root 110: uint32_t latch;
1.1.1.12 root 111: MemoryRegion *chain4_alias;
1.1.1.6 root 112: uint8_t sr_index;
113: uint8_t sr[256];
114: uint8_t gr_index;
115: uint8_t gr[256];
116: uint8_t ar_index;
117: uint8_t ar[21];
118: int ar_flip_flop;
119: uint8_t cr_index;
120: uint8_t cr[256]; /* CRT registers */
121: uint8_t msr; /* Misc Output Register */
122: uint8_t fcr; /* Feature Control Register */
123: uint8_t st00; /* status 0 */
124: uint8_t st01; /* status 1 */
125: uint8_t dac_state;
126: uint8_t dac_sub_index;
127: uint8_t dac_read_index;
128: uint8_t dac_write_index;
129: uint8_t dac_cache[3]; /* used when writing */
130: int dac_8bit;
131: uint8_t palette[768];
132: int32_t bank_offset;
133: int (*get_bpp)(struct VGACommonState *s);
134: void (*get_offsets)(struct VGACommonState *s,
135: uint32_t *pline_offset,
136: uint32_t *pstart_addr,
137: uint32_t *pline_compare);
138: void (*get_resolution)(struct VGACommonState *s,
139: int *pwidth,
140: int *pheight);
141: VGA_STATE_COMMON_BOCHS_VBE
142: /* display refresh support */
143: DisplayState *ds;
144: uint32_t font_offsets[2];
145: int graphic_mode;
146: uint8_t shift_control;
147: uint8_t double_scan;
148: uint32_t line_offset;
149: uint32_t line_compare;
150: uint32_t start_addr;
151: uint32_t plane_updated;
152: uint32_t last_line_offset;
153: uint8_t last_cw, last_ch;
154: uint32_t last_width, last_height; /* in chars or pixels */
155: uint32_t last_scr_width, last_scr_height; /* in pixels */
156: uint32_t last_depth; /* in bits */
157: uint8_t cursor_start, cursor_end;
158: uint32_t cursor_offset;
159: unsigned int (*rgb_to_pixel)(unsigned int r,
160: unsigned int g, unsigned b);
161: vga_hw_update_ptr update;
162: vga_hw_invalidate_ptr invalidate;
163: vga_hw_screen_dump_ptr screen_dump;
164: vga_hw_text_update_ptr text_update;
165: /* hardware mouse cursor support */
166: uint32_t invalidated_y_table[VGA_MAX_HEIGHT / 32];
167: void (*cursor_invalidate)(struct VGACommonState *s);
168: void (*cursor_draw_line)(struct VGACommonState *s, uint8_t *d, int y);
169: /* tell for each page if it has been updated since the last time */
170: uint32_t last_palette[256];
171: uint32_t last_ch_attr[CH_ATTR_SIZE]; /* XXX: make it dynamic */
172: /* retrace */
173: vga_retrace_fn retrace;
174: vga_update_retrace_info_fn update_retrace_info;
1.1.1.5 root 175: union vga_retrace retrace_info;
1.1.1.8 root 176: uint8_t is_vbe_vmstate;
1.1.1.6 root 177: } VGACommonState;
1.1 root 178:
179: static inline int c6_to_8(int v)
180: {
181: int b;
182: v &= 0x3f;
183: b = v & 1;
184: return (v << 2) | (b << 1) | b;
185: }
186:
1.1.1.8 root 187: void vga_common_init(VGACommonState *s, int vga_ram_size);
1.1.1.12 root 188: void vga_init(VGACommonState *s, MemoryRegion *address_space,
189: MemoryRegion *address_space_io, bool init_vga_ports);
190: MemoryRegion *vga_init_io(VGACommonState *s,
191: const MemoryRegionPortio **vga_ports,
192: const MemoryRegionPortio **vbe_ports);
1.1.1.8 root 193: void vga_common_reset(VGACommonState *s);
194:
195: void vga_dirty_log_start(VGACommonState *s);
196: void vga_dirty_log_stop(VGACommonState *s);
197:
198: extern const VMStateDescription vmstate_vga_common;
199: uint32_t vga_ioport_read(void *opaque, uint32_t addr);
200: void vga_ioport_write(void *opaque, uint32_t addr, uint32_t val);
1.1.1.12 root 201: uint32_t vga_mem_readb(VGACommonState *s, target_phys_addr_t addr);
202: void vga_mem_writeb(VGACommonState *s, target_phys_addr_t addr, uint32_t val);
1.1.1.8 root 203: void vga_invalidate_scanlines(VGACommonState *s, int y1, int y2);
1.1.1.5 root 204: int ppm_save(const char *filename, struct DisplaySurface *ds);
1.1 root 205:
1.1.1.8 root 206: int vga_ioport_invalid(VGACommonState *s, uint32_t addr);
1.1.1.12 root 207: void vga_init_vbe(VGACommonState *s, MemoryRegion *address_space);
1.1.1.8 root 208:
1.1 root 209: extern const uint8_t sr_mask[8];
210: extern const uint8_t gr_mask[16];
1.1.1.6 root 211:
212: #define VGA_RAM_SIZE (8192 * 1024)
1.1.1.8 root 213: #define VGABIOS_FILENAME "vgabios.bin"
214: #define VGABIOS_CIRRUS_FILENAME "vgabios-cirrus.bin"
1.1.1.6 root 215:
1.1.1.12 root 216: extern const MemoryRegionOps vga_mem_ops;
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