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1.1 root 1: /*
2: * QEMU internal VGA defines.
3: *
4: * Copyright (c) 2003-2004 Fabrice Bellard
5: *
6: * Permission is hereby granted, free of charge, to any person obtaining a copy
7: * of this software and associated documentation files (the "Software"), to deal
8: * in the Software without restriction, including without limitation the rights
9: * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10: * copies of the Software, and to permit persons to whom the Software is
11: * furnished to do so, subject to the following conditions:
12: *
13: * The above copyright notice and this permission notice shall be included in
14: * all copies or substantial portions of the Software.
15: *
16: * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17: * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18: * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19: * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20: * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21: * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22: * THE SOFTWARE.
23: */
24: #define MSR_COLOR_EMULATION 0x01
25: #define MSR_PAGE_SELECT 0x20
26:
27: #define ST01_V_RETRACE 0x08
28: #define ST01_DISP_ENABLE 0x01
29:
30: /* bochs VBE support */
31: #define CONFIG_BOCHS_VBE
32:
1.1.1.2 ! root 33: #define VBE_DISPI_MAX_XRES 1600
! 34: #define VBE_DISPI_MAX_YRES 1200
! 35: #define VBE_DISPI_MAX_BPP 32
1.1 root 36:
37: #define VBE_DISPI_INDEX_ID 0x0
38: #define VBE_DISPI_INDEX_XRES 0x1
39: #define VBE_DISPI_INDEX_YRES 0x2
40: #define VBE_DISPI_INDEX_BPP 0x3
41: #define VBE_DISPI_INDEX_ENABLE 0x4
42: #define VBE_DISPI_INDEX_BANK 0x5
43: #define VBE_DISPI_INDEX_VIRT_WIDTH 0x6
44: #define VBE_DISPI_INDEX_VIRT_HEIGHT 0x7
45: #define VBE_DISPI_INDEX_X_OFFSET 0x8
46: #define VBE_DISPI_INDEX_Y_OFFSET 0x9
47: #define VBE_DISPI_INDEX_NB 0xa
48:
49: #define VBE_DISPI_ID0 0xB0C0
50: #define VBE_DISPI_ID1 0xB0C1
51: #define VBE_DISPI_ID2 0xB0C2
52:
53: #define VBE_DISPI_DISABLED 0x00
54: #define VBE_DISPI_ENABLED 0x01
1.1.1.2 ! root 55: #define VBE_DISPI_GETCAPS 0x02
! 56: #define VBE_DISPI_8BIT_DAC 0x20
1.1 root 57: #define VBE_DISPI_LFB_ENABLED 0x40
58: #define VBE_DISPI_NOCLEARMEM 0x80
59:
60: #define VBE_DISPI_LFB_PHYSICAL_ADDRESS 0xE0000000
61:
62: #ifdef CONFIG_BOCHS_VBE
63:
64: #define VGA_STATE_COMMON_BOCHS_VBE \
65: uint16_t vbe_index; \
66: uint16_t vbe_regs[VBE_DISPI_INDEX_NB]; \
67: uint32_t vbe_start_addr; \
68: uint32_t vbe_line_offset; \
69: uint32_t vbe_bank_mask;
70:
71: #else
72:
73: #define VGA_STATE_COMMON_BOCHS_VBE
74:
75: #endif /* !CONFIG_BOCHS_VBE */
76:
77: #define CH_ATTR_SIZE (160 * 100)
1.1.1.2 ! root 78: #define VGA_MAX_HEIGHT 2048
1.1 root 79:
80: #define VGA_STATE_COMMON \
81: uint8_t *vram_ptr; \
82: unsigned long vram_offset; \
83: unsigned int vram_size; \
84: unsigned long bios_offset; \
85: unsigned int bios_size; \
86: uint32_t latch; \
87: uint8_t sr_index; \
88: uint8_t sr[256]; \
89: uint8_t gr_index; \
90: uint8_t gr[256]; \
91: uint8_t ar_index; \
92: uint8_t ar[21]; \
93: int ar_flip_flop; \
94: uint8_t cr_index; \
95: uint8_t cr[256]; /* CRT registers */ \
96: uint8_t msr; /* Misc Output Register */ \
97: uint8_t fcr; /* Feature Control Register */ \
98: uint8_t st00; /* status 0 */ \
99: uint8_t st01; /* status 1 */ \
100: uint8_t dac_state; \
101: uint8_t dac_sub_index; \
102: uint8_t dac_read_index; \
103: uint8_t dac_write_index; \
104: uint8_t dac_cache[3]; /* used when writing */ \
105: uint8_t palette[768]; \
106: int32_t bank_offset; \
107: int (*get_bpp)(struct VGAState *s); \
108: void (*get_offsets)(struct VGAState *s, \
109: uint32_t *pline_offset, \
110: uint32_t *pstart_addr); \
111: void (*get_resolution)(struct VGAState *s, \
112: int *pwidth, \
113: int *pheight); \
114: VGA_STATE_COMMON_BOCHS_VBE \
115: /* display refresh support */ \
116: DisplayState *ds; \
117: uint32_t font_offsets[2]; \
118: int graphic_mode; \
119: uint8_t shift_control; \
120: uint8_t double_scan; \
121: uint32_t line_offset; \
122: uint32_t line_compare; \
123: uint32_t start_addr; \
124: uint32_t plane_updated; \
125: uint8_t last_cw, last_ch; \
126: uint32_t last_width, last_height; /* in chars or pixels */ \
127: uint32_t last_scr_width, last_scr_height; /* in pixels */ \
128: uint8_t cursor_start, cursor_end; \
129: uint32_t cursor_offset; \
130: unsigned int (*rgb_to_pixel)(unsigned int r, \
131: unsigned int g, unsigned b); \
132: /* hardware mouse cursor support */ \
133: uint32_t invalidated_y_table[VGA_MAX_HEIGHT / 32]; \
134: void (*cursor_invalidate)(struct VGAState *s); \
135: void (*cursor_draw_line)(struct VGAState *s, uint8_t *d, int y); \
136: /* tell for each page if it has been updated since the last time */ \
137: uint32_t last_palette[256]; \
138: uint32_t last_ch_attr[CH_ATTR_SIZE]; /* XXX: make it dynamic */
139:
140:
141: typedef struct VGAState {
142: VGA_STATE_COMMON
143: } VGAState;
144:
145: static inline int c6_to_8(int v)
146: {
147: int b;
148: v &= 0x3f;
149: b = v & 1;
150: return (v << 2) | (b << 1) | b;
151: }
152:
153: void vga_common_init(VGAState *s, DisplayState *ds, uint8_t *vga_ram_base,
154: unsigned long vga_ram_offset, int vga_ram_size);
155: uint32_t vga_mem_readb(void *opaque, target_phys_addr_t addr);
156: void vga_mem_writeb(void *opaque, target_phys_addr_t addr, uint32_t val);
157: void vga_invalidate_scanlines(VGAState *s, int y1, int y2);
158:
159: void vga_draw_cursor_line_8(uint8_t *d1, const uint8_t *src1,
160: int poffset, int w,
161: unsigned int color0, unsigned int color1,
162: unsigned int color_xor);
163: void vga_draw_cursor_line_16(uint8_t *d1, const uint8_t *src1,
164: int poffset, int w,
165: unsigned int color0, unsigned int color1,
166: unsigned int color_xor);
167: void vga_draw_cursor_line_32(uint8_t *d1, const uint8_t *src1,
168: int poffset, int w,
169: unsigned int color0, unsigned int color1,
170: unsigned int color_xor);
171:
172: extern const uint8_t sr_mask[8];
173: extern const uint8_t gr_mask[16];
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