Diff for /qemu/hw/xen_platform.c between versions 1.1.1.1 and 1.1.1.2

version 1.1.1.1, 2018/04/24 19:00:18 version 1.1.1.2, 2018/04/24 19:28:02
Line 32 Line 32
 #include "xen_common.h"  #include "xen_common.h"
 #include "net.h"  #include "net.h"
 #include "xen_backend.h"  #include "xen_backend.h"
 #include "rwhandler.h"  
 #include "trace.h"  #include "trace.h"
   #include "exec-memory.h"
   
 #include <xenguest.h>  #include <xenguest.h>
   
Line 51 Line 51
   
 typedef struct PCIXenPlatformState {  typedef struct PCIXenPlatformState {
     PCIDevice  pci_dev;      PCIDevice  pci_dev;
       MemoryRegion fixed_io;
       MemoryRegion bar;
       MemoryRegion mmio_bar;
     uint8_t flags; /* used only for version_id == 2 */      uint8_t flags; /* used only for version_id == 2 */
     int drivers_blacklisted;      int drivers_blacklisted;
     uint16_t driver_product_version;      uint16_t driver_product_version;
Line 76  static void log_writeb(PCIXenPlatformSta Line 79  static void log_writeb(PCIXenPlatformSta
 }  }
   
 /* Xen Platform, Fixed IOPort */  /* Xen Platform, Fixed IOPort */
   #define UNPLUG_ALL_IDE_DISKS 1
   #define UNPLUG_ALL_NICS 2
   #define UNPLUG_AUX_IDE_DISKS 4
   
   static void unplug_nic(PCIBus *b, PCIDevice *d)
   {
       if (pci_get_word(d->config + PCI_CLASS_DEVICE) ==
               PCI_CLASS_NETWORK_ETHERNET) {
           qdev_unplug(&(d->qdev));
       }
   }
   
   static void pci_unplug_nics(PCIBus *bus)
   {
       pci_for_each_device(bus, 0, unplug_nic);
   }
   
   static void unplug_disks(PCIBus *b, PCIDevice *d)
   {
       if (pci_get_word(d->config + PCI_CLASS_DEVICE) ==
               PCI_CLASS_STORAGE_IDE) {
           qdev_unplug(&(d->qdev));
       }
   }
   
   static void pci_unplug_disks(PCIBus *bus)
   {
       pci_for_each_device(bus, 0, unplug_disks);
   }
   
 static void platform_fixed_ioport_writew(void *opaque, uint32_t addr, uint32_t val)  static void platform_fixed_ioport_writew(void *opaque, uint32_t addr, uint32_t val)
 {  {
     PCIXenPlatformState *s = opaque;      PCIXenPlatformState *s = opaque;
   
     switch (addr - XEN_PLATFORM_IOPORT) {      switch (addr) {
     case 0:      case 0:
         /* TODO: */  
         /* Unplug devices.  Value is a bitmask of which devices to          /* Unplug devices.  Value is a bitmask of which devices to
            unplug, with bit 0 the IDE devices, bit 1 the network             unplug, with bit 0 the IDE devices, bit 1 the network
            devices, and bit 2 the non-primary-master IDE devices. */             devices, and bit 2 the non-primary-master IDE devices. */
           if (val & UNPLUG_ALL_IDE_DISKS) {
               DPRINTF("unplug disks\n");
               qemu_aio_flush();
               bdrv_flush_all();
               pci_unplug_disks(s->pci_dev.bus);
           }
           if (val & UNPLUG_ALL_NICS) {
               DPRINTF("unplug nics\n");
               pci_unplug_nics(s->pci_dev.bus);
           }
           if (val & UNPLUG_AUX_IDE_DISKS) {
               DPRINTF("unplug auxiliary disks not supported\n");
           }
         break;          break;
     case 2:      case 2:
         switch (val) {          switch (val) {
Line 108  static void platform_fixed_ioport_writew Line 152  static void platform_fixed_ioport_writew
 static void platform_fixed_ioport_writel(void *opaque, uint32_t addr,  static void platform_fixed_ioport_writel(void *opaque, uint32_t addr,
                                          uint32_t val)                                           uint32_t val)
 {  {
     switch (addr - XEN_PLATFORM_IOPORT) {      switch (addr) {
     case 0:      case 0:
         /* PV driver version */          /* PV driver version */
         break;          break;
Line 119  static void platform_fixed_ioport_writeb Line 163  static void platform_fixed_ioport_writeb
 {  {
     PCIXenPlatformState *s = opaque;      PCIXenPlatformState *s = opaque;
   
     switch (addr - XEN_PLATFORM_IOPORT) {      switch (addr) {
     case 0: /* Platform flags */ {      case 0: /* Platform flags */ {
         hvmmem_type_t mem_type = (val & PFFLAG_ROM_LOCK) ?          hvmmem_type_t mem_type = (val & PFFLAG_ROM_LOCK) ?
             HVMMEM_ram_ro : HVMMEM_ram_rw;              HVMMEM_ram_ro : HVMMEM_ram_rw;
Line 142  static uint32_t platform_fixed_ioport_re Line 186  static uint32_t platform_fixed_ioport_re
 {  {
     PCIXenPlatformState *s = opaque;      PCIXenPlatformState *s = opaque;
   
     switch (addr - XEN_PLATFORM_IOPORT) {      switch (addr) {
     case 0:      case 0:
         if (s->drivers_blacklisted) {          if (s->drivers_blacklisted) {
             /* The drivers will recognise this magic number and refuse              /* The drivers will recognise this magic number and refuse
Line 161  static uint32_t platform_fixed_ioport_re Line 205  static uint32_t platform_fixed_ioport_re
 {  {
     PCIXenPlatformState *s = opaque;      PCIXenPlatformState *s = opaque;
   
     switch (addr - XEN_PLATFORM_IOPORT) {      switch (addr) {
     case 0:      case 0:
         /* Platform flags */          /* Platform flags */
         return s->flags;          return s->flags;
Line 177  static void platform_fixed_ioport_reset( Line 221  static void platform_fixed_ioport_reset(
 {  {
     PCIXenPlatformState *s = opaque;      PCIXenPlatformState *s = opaque;
   
     platform_fixed_ioport_writeb(s, XEN_PLATFORM_IOPORT, 0);      platform_fixed_ioport_writeb(s, 0, 0);
 }  }
   
   const MemoryRegionPortio xen_platform_ioport[] = {
       { 0, 16, 4, .write = platform_fixed_ioport_writel, },
       { 0, 16, 2, .write = platform_fixed_ioport_writew, },
       { 0, 16, 1, .write = platform_fixed_ioport_writeb, },
       { 0, 16, 2, .read = platform_fixed_ioport_readw, },
       { 0, 16, 1, .read = platform_fixed_ioport_readb, },
       PORTIO_END_OF_LIST()
   };
   
   static const MemoryRegionOps platform_fixed_io_ops = {
       .old_portio = xen_platform_ioport,
       .endianness = DEVICE_NATIVE_ENDIAN,
   };
   
 static void platform_fixed_ioport_init(PCIXenPlatformState* s)  static void platform_fixed_ioport_init(PCIXenPlatformState* s)
 {  {
     register_ioport_write(XEN_PLATFORM_IOPORT, 16, 4, platform_fixed_ioport_writel, s);      memory_region_init_io(&s->fixed_io, &platform_fixed_io_ops, s,
     register_ioport_write(XEN_PLATFORM_IOPORT, 16, 2, platform_fixed_ioport_writew, s);                            "xen-fixed", 16);
     register_ioport_write(XEN_PLATFORM_IOPORT, 16, 1, platform_fixed_ioport_writeb, s);      memory_region_add_subregion(get_system_io(), XEN_PLATFORM_IOPORT,
     register_ioport_read(XEN_PLATFORM_IOPORT, 16, 2, platform_fixed_ioport_readw, s);                                  &s->fixed_io);
     register_ioport_read(XEN_PLATFORM_IOPORT, 16, 1, platform_fixed_ioport_readb, s);  
 }  }
   
 /* Xen Platform PCI Device */  /* Xen Platform PCI Device */
   
 static uint32_t xen_platform_ioport_readb(void *opaque, uint32_t addr)  static uint32_t xen_platform_ioport_readb(void *opaque, uint32_t addr)
 {  {
     addr &= 0xff;  
   
     if (addr == 0) {      if (addr == 0) {
         return platform_fixed_ioport_readb(opaque, XEN_PLATFORM_IOPORT);          return platform_fixed_ioport_readb(opaque, 0);
     } else {      } else {
         return ~0u;          return ~0u;
     }      }
Line 206  static void xen_platform_ioport_writeb(v Line 261  static void xen_platform_ioport_writeb(v
 {  {
     PCIXenPlatformState *s = opaque;      PCIXenPlatformState *s = opaque;
   
     addr &= 0xff;  
     val  &= 0xff;  
   
     switch (addr) {      switch (addr) {
     case 0: /* Platform flags */      case 0: /* Platform flags */
         platform_fixed_ioport_writeb(opaque, XEN_PLATFORM_IOPORT, val);          platform_fixed_ioport_writeb(opaque, 0, val);
         break;          break;
     case 8:      case 8:
         log_writeb(s, val);          log_writeb(s, val);
Line 221  static void xen_platform_ioport_writeb(v Line 273  static void xen_platform_ioport_writeb(v
     }      }
 }  }
   
 static void platform_ioport_map(PCIDevice *pci_dev, int region_num, pcibus_t addr, pcibus_t size, int type)  static MemoryRegionPortio xen_pci_portio[] = {
 {      { 0, 0x100, 1, .read = xen_platform_ioport_readb, },
     PCIXenPlatformState *d = DO_UPCAST(PCIXenPlatformState, pci_dev, pci_dev);      { 0, 0x100, 1, .write = xen_platform_ioport_writeb, },
       PORTIO_END_OF_LIST()
   };
   
   static const MemoryRegionOps xen_pci_io_ops = {
       .old_portio = xen_pci_portio,
   };
   
     register_ioport_write(addr, size, 1, xen_platform_ioport_writeb, d);  static void platform_ioport_bar_setup(PCIXenPlatformState *d)
     register_ioport_read(addr, size, 1, xen_platform_ioport_readb, d);  {
       memory_region_init_io(&d->bar, &xen_pci_io_ops, d, "xen-pci", 0x100);
 }  }
   
 static uint32_t platform_mmio_read(ReadWriteHandler *handler, pcibus_t addr, int len)  static uint64_t platform_mmio_read(void *opaque, target_phys_addr_t addr,
                                      unsigned size)
 {  {
     DPRINTF("Warning: attempted read from physical address "      DPRINTF("Warning: attempted read from physical address "
             "0x" TARGET_FMT_plx " in xen platform mmio space\n", addr);              "0x" TARGET_FMT_plx " in xen platform mmio space\n", addr);
Line 237  static uint32_t platform_mmio_read(ReadW Line 297  static uint32_t platform_mmio_read(ReadW
     return 0;      return 0;
 }  }
   
 static void platform_mmio_write(ReadWriteHandler *handler, pcibus_t addr,  static void platform_mmio_write(void *opaque, target_phys_addr_t addr,
                                 uint32_t val, int len)                                  uint64_t val, unsigned size)
 {  {
     DPRINTF("Warning: attempted write of 0x%x to physical "      DPRINTF("Warning: attempted write of 0x%"PRIx64" to physical "
             "address 0x" TARGET_FMT_plx " in xen platform mmio space\n",              "address 0x" TARGET_FMT_plx " in xen platform mmio space\n",
             val, addr);              val, addr);
 }  }
   
 static ReadWriteHandler platform_mmio_handler = {  static const MemoryRegionOps platform_mmio_handler = {
     .read = &platform_mmio_read,      .read = &platform_mmio_read,
     .write = &platform_mmio_write,      .write = &platform_mmio_write,
       .endianness = DEVICE_NATIVE_ENDIAN,
 };  };
   
 static void platform_mmio_map(PCIDevice *d, int region_num,  static void platform_mmio_setup(PCIXenPlatformState *d)
                               pcibus_t addr, pcibus_t size, int type)  
 {  {
     int mmio_io_addr;      memory_region_init_io(&d->mmio_bar, &platform_mmio_handler, d,
                             "xen-mmio", 0x1000000);
     mmio_io_addr = cpu_register_io_memory_simple(&platform_mmio_handler,  
                                                  DEVICE_NATIVE_ENDIAN);  
   
     cpu_register_physical_memory(addr, size, mmio_io_addr);  
 }  }
   
 static int xen_platform_post_load(void *opaque, int version_id)  static int xen_platform_post_load(void *opaque, int version_id)
 {  {
     PCIXenPlatformState *s = opaque;      PCIXenPlatformState *s = opaque;
   
     platform_fixed_ioport_writeb(s, XEN_PLATFORM_IOPORT, s->flags);      platform_fixed_ioport_writeb(s, 0, s->flags);
   
     return 0;      return 0;
 }  }
Line 296  static int xen_platform_initfn(PCIDevice Line 352  static int xen_platform_initfn(PCIDevice
   
     pci_conf[PCI_INTERRUPT_PIN] = 1;      pci_conf[PCI_INTERRUPT_PIN] = 1;
   
     pci_register_bar(&d->pci_dev, 0, 0x100,      platform_ioport_bar_setup(d);
             PCI_BASE_ADDRESS_SPACE_IO, platform_ioport_map);      pci_register_bar(&d->pci_dev, 0, PCI_BASE_ADDRESS_SPACE_IO, &d->bar);
   
     /* reserve 16MB mmio address for share memory*/      /* reserve 16MB mmio address for share memory*/
     pci_register_bar(&d->pci_dev, 1, 0x1000000,      platform_mmio_setup(d);
             PCI_BASE_ADDRESS_MEM_PREFETCH, platform_mmio_map);      pci_register_bar(&d->pci_dev, 1, PCI_BASE_ADDRESS_MEM_PREFETCH,
                        &d->mmio_bar);
   
     platform_fixed_ioport_init(d);      platform_fixed_ioport_init(d);
   

Removed from v.1.1.1.1  
changed lines
  Added in v.1.1.1.2


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