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1.1 root 1: /*
2: * QEMU Xilinx OPB Interrupt Controller.
3: *
4: * Copyright (c) 2009 Edgar E. Iglesias.
5: *
6: * Permission is hereby granted, free of charge, to any person obtaining a copy
7: * of this software and associated documentation files (the "Software"), to deal
8: * in the Software without restriction, including without limitation the rights
9: * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10: * copies of the Software, and to permit persons to whom the Software is
11: * furnished to do so, subject to the following conditions:
12: *
13: * The above copyright notice and this permission notice shall be included in
14: * all copies or substantial portions of the Software.
15: *
16: * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17: * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18: * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19: * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20: * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21: * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22: * THE SOFTWARE.
23: */
24:
25: #include "sysbus.h"
26: #include "hw.h"
27:
28: #define D(x)
29:
30: #define R_ISR 0
31: #define R_IPR 1
32: #define R_IER 2
33: #define R_IAR 3
34: #define R_SIE 4
35: #define R_CIE 5
36: #define R_IVR 6
37: #define R_MER 7
38: #define R_MAX 8
39:
40: struct xlx_pic
41: {
42: SysBusDevice busdev;
1.1.1.4 root 43: MemoryRegion mmio;
1.1 root 44: qemu_irq parent_irq;
45:
46: /* Configuration reg chosen at synthesis-time. QEMU populates
47: the bits at board-setup. */
48: uint32_t c_kind_of_intr;
49:
50: /* Runtime control registers. */
51: uint32_t regs[R_MAX];
52: };
53:
54: static void update_irq(struct xlx_pic *p)
55: {
56: uint32_t i;
57: /* Update the pending register. */
58: p->regs[R_IPR] = p->regs[R_ISR] & p->regs[R_IER];
59:
60: /* Update the vector register. */
61: for (i = 0; i < 32; i++) {
62: if (p->regs[R_IPR] & (1 << i))
63: break;
64: }
65: if (i == 32)
66: i = ~0;
67:
68: p->regs[R_IVR] = i;
69: if ((p->regs[R_MER] & 1) && p->regs[R_IPR]) {
70: qemu_irq_raise(p->parent_irq);
71: } else {
72: qemu_irq_lower(p->parent_irq);
73: }
74: }
75:
1.1.1.4 root 76: static uint64_t
77: pic_read(void *opaque, target_phys_addr_t addr, unsigned int size)
1.1 root 78: {
79: struct xlx_pic *p = opaque;
80: uint32_t r = 0;
81:
82: addr >>= 2;
83: switch (addr)
84: {
85: default:
86: if (addr < ARRAY_SIZE(p->regs))
87: r = p->regs[addr];
88: break;
89:
90: }
91: D(printf("%s %x=%x\n", __func__, addr * 4, r));
92: return r;
93: }
94:
95: static void
1.1.1.4 root 96: pic_write(void *opaque, target_phys_addr_t addr,
97: uint64_t val64, unsigned int size)
1.1 root 98: {
99: struct xlx_pic *p = opaque;
1.1.1.4 root 100: uint32_t value = val64;
1.1 root 101:
102: addr >>= 2;
103: D(qemu_log("%s addr=%x val=%x\n", __func__, addr * 4, value));
104: switch (addr)
105: {
106: case R_IAR:
107: p->regs[R_ISR] &= ~value; /* ACK. */
108: break;
109: case R_SIE:
110: p->regs[R_IER] |= value; /* Atomic set ie. */
111: break;
112: case R_CIE:
113: p->regs[R_IER] &= ~value; /* Atomic clear ie. */
114: break;
115: default:
116: if (addr < ARRAY_SIZE(p->regs))
117: p->regs[addr] = value;
118: break;
119: }
120: update_irq(p);
121: }
122:
1.1.1.4 root 123: static const MemoryRegionOps pic_ops = {
124: .read = pic_read,
125: .write = pic_write,
126: .endianness = DEVICE_NATIVE_ENDIAN,
127: .valid = {
128: .min_access_size = 4,
129: .max_access_size = 4
130: }
1.1 root 131: };
132:
133: static void irq_handler(void *opaque, int irq, int level)
134: {
135: struct xlx_pic *p = opaque;
136:
137: if (!(p->regs[R_MER] & 2)) {
138: qemu_irq_lower(p->parent_irq);
139: return;
140: }
141:
142: /* Update source flops. Don't clear unless level triggered.
143: Edge triggered interrupts only go away when explicitely acked to
144: the interrupt controller. */
145: if (!(p->c_kind_of_intr & (1 << irq)) || level) {
146: p->regs[R_ISR] &= ~(1 << irq);
147: p->regs[R_ISR] |= (level << irq);
148: }
149: update_irq(p);
150: }
151:
1.1.1.2 root 152: static int xilinx_intc_init(SysBusDevice *dev)
1.1 root 153: {
154: struct xlx_pic *p = FROM_SYSBUS(typeof (*p), dev);
155:
156: qdev_init_gpio_in(&dev->qdev, irq_handler, 32);
157: sysbus_init_irq(dev, &p->parent_irq);
158:
1.1.1.4 root 159: memory_region_init_io(&p->mmio, &pic_ops, p, "xilinx-pic", R_MAX * 4);
1.1.1.5 ! root 160: sysbus_init_mmio(dev, &p->mmio);
1.1.1.2 root 161: return 0;
1.1 root 162: }
163:
1.1.1.5 ! root 164: static Property xilinx_intc_properties[] = {
! 165: DEFINE_PROP_UINT32("kind-of-intr", struct xlx_pic, c_kind_of_intr, 0),
! 166: DEFINE_PROP_END_OF_LIST(),
1.1 root 167: };
168:
1.1.1.5 ! root 169: static void xilinx_intc_class_init(ObjectClass *klass, void *data)
1.1 root 170: {
1.1.1.5 ! root 171: DeviceClass *dc = DEVICE_CLASS(klass);
! 172: SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
! 173:
! 174: k->init = xilinx_intc_init;
! 175: dc->props = xilinx_intc_properties;
! 176: }
! 177:
! 178: static TypeInfo xilinx_intc_info = {
! 179: .name = "xilinx,intc",
! 180: .parent = TYPE_SYS_BUS_DEVICE,
! 181: .instance_size = sizeof(struct xlx_pic),
! 182: .class_init = xilinx_intc_class_init,
! 183: };
! 184:
! 185: static void xilinx_intc_register_types(void)
! 186: {
! 187: type_register_static(&xilinx_intc_info);
1.1 root 188: }
189:
1.1.1.5 ! root 190: type_init(xilinx_intc_register_types)
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