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1.1 root 1: /*
2: * x3130_downstream.c
3: * TI X3130 pci express downstream port switch
4: *
5: * Copyright (c) 2010 Isaku Yamahata <yamahata at valinux co jp>
6: * VA Linux Systems Japan K.K.
7: *
8: * This program is free software; you can redistribute it and/or modify
9: * it under the terms of the GNU General Public License as published by
10: * the Free Software Foundation; either version 2 of the License, or
11: * (at your option) any later version.
12: *
13: * This program is distributed in the hope that it will be useful,
14: * but WITHOUT ANY WARRANTY; without even the implied warranty of
15: * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16: * GNU General Public License for more details.
17: *
18: * You should have received a copy of the GNU General Public License along
19: * with this program; if not, see <http://www.gnu.org/licenses/>.
20: */
21:
22: #include "pci_ids.h"
23: #include "msi.h"
24: #include "pcie.h"
25: #include "xio3130_downstream.h"
26:
27: #define PCI_DEVICE_ID_TI_XIO3130D 0x8233 /* downstream port */
28: #define XIO3130_REVISION 0x1
29: #define XIO3130_MSI_OFFSET 0x70
30: #define XIO3130_MSI_SUPPORTED_FLAGS PCI_MSI_FLAGS_64BIT
31: #define XIO3130_MSI_NR_VECTOR 1
32: #define XIO3130_SSVID_OFFSET 0x80
33: #define XIO3130_SSVID_SVID 0
34: #define XIO3130_SSVID_SSID 0
35: #define XIO3130_EXP_OFFSET 0x90
36: #define XIO3130_AER_OFFSET 0x100
37:
38: static void xio3130_downstream_write_config(PCIDevice *d, uint32_t address,
39: uint32_t val, int len)
40: {
41: pci_bridge_write_config(d, address, val, len);
42: pcie_cap_flr_write_config(d, address, val, len);
43: pcie_cap_slot_write_config(d, address, val, len);
44: msi_write_config(d, address, val, len);
45: pcie_aer_write_config(d, address, val, len);
46: }
47:
48: static void xio3130_downstream_reset(DeviceState *qdev)
49: {
1.1.1.3 ! root 50: PCIDevice *d = PCI_DEVICE(qdev);
1.1 root 51: msi_reset(d);
52: pcie_cap_deverr_reset(d);
53: pcie_cap_slot_reset(d);
54: pcie_cap_ari_reset(d);
55: pci_bridge_reset(qdev);
56: }
57:
58: static int xio3130_downstream_initfn(PCIDevice *d)
59: {
60: PCIBridge* br = DO_UPCAST(PCIBridge, dev, d);
61: PCIEPort *p = DO_UPCAST(PCIEPort, br, br);
62: PCIESlot *s = DO_UPCAST(PCIESlot, port, p);
63: int rc;
64: int tmp;
65:
66: rc = pci_bridge_initfn(d);
67: if (rc < 0) {
68: return rc;
69: }
70:
71: pcie_port_init_reg(d);
72:
73: rc = msi_init(d, XIO3130_MSI_OFFSET, XIO3130_MSI_NR_VECTOR,
74: XIO3130_MSI_SUPPORTED_FLAGS & PCI_MSI_FLAGS_64BIT,
75: XIO3130_MSI_SUPPORTED_FLAGS & PCI_MSI_FLAGS_MASKBIT);
76: if (rc < 0) {
77: goto err_bridge;
78: }
79: rc = pci_bridge_ssvid_init(d, XIO3130_SSVID_OFFSET,
80: XIO3130_SSVID_SVID, XIO3130_SSVID_SSID);
81: if (rc < 0) {
82: goto err_bridge;
83: }
84: rc = pcie_cap_init(d, XIO3130_EXP_OFFSET, PCI_EXP_TYPE_DOWNSTREAM,
85: p->port);
86: if (rc < 0) {
87: goto err_msi;
88: }
89: pcie_cap_flr_init(d);
90: pcie_cap_deverr_init(d);
91: pcie_cap_slot_init(d, s->slot);
92: pcie_chassis_create(s->chassis);
93: rc = pcie_chassis_add_slot(s);
94: if (rc < 0) {
95: goto err_pcie_cap;
96: }
97: pcie_cap_ari_init(d);
98: rc = pcie_aer_init(d, XIO3130_AER_OFFSET);
99: if (rc < 0) {
100: goto err;
101: }
102:
103: return 0;
104:
105: err:
106: pcie_chassis_del_slot(s);
107: err_pcie_cap:
108: pcie_cap_exit(d);
109: err_msi:
110: msi_uninit(d);
111: err_bridge:
112: tmp = pci_bridge_exitfn(d);
113: assert(!tmp);
114: return rc;
115: }
116:
117: static int xio3130_downstream_exitfn(PCIDevice *d)
118: {
119: PCIBridge* br = DO_UPCAST(PCIBridge, dev, d);
120: PCIEPort *p = DO_UPCAST(PCIEPort, br, br);
121: PCIESlot *s = DO_UPCAST(PCIESlot, port, p);
122:
123: pcie_aer_exit(d);
124: pcie_chassis_del_slot(s);
125: pcie_cap_exit(d);
126: msi_uninit(d);
127: return pci_bridge_exitfn(d);
128: }
129:
130: PCIESlot *xio3130_downstream_init(PCIBus *bus, int devfn, bool multifunction,
131: const char *bus_name, pci_map_irq_fn map_irq,
132: uint8_t port, uint8_t chassis,
133: uint16_t slot)
134: {
135: PCIDevice *d;
136: PCIBridge *br;
137: DeviceState *qdev;
138:
139: d = pci_create_multifunction(bus, devfn, multifunction,
140: "xio3130-downstream");
141: if (!d) {
142: return NULL;
143: }
144: br = DO_UPCAST(PCIBridge, dev, d);
145:
146: qdev = &br->dev.qdev;
147: pci_bridge_map_irq(br, bus_name, map_irq);
148: qdev_prop_set_uint8(qdev, "port", port);
149: qdev_prop_set_uint8(qdev, "chassis", chassis);
150: qdev_prop_set_uint16(qdev, "slot", slot);
151: qdev_init_nofail(qdev);
152:
153: return DO_UPCAST(PCIESlot, port, DO_UPCAST(PCIEPort, br, br));
154: }
155:
156: static const VMStateDescription vmstate_xio3130_downstream = {
157: .name = "xio3130-express-downstream-port",
158: .version_id = 1,
159: .minimum_version_id = 1,
160: .minimum_version_id_old = 1,
161: .post_load = pcie_cap_slot_post_load,
162: .fields = (VMStateField[]) {
163: VMSTATE_PCIE_DEVICE(port.br.dev, PCIESlot),
164: VMSTATE_STRUCT(port.br.dev.exp.aer_log, PCIESlot, 0,
165: vmstate_pcie_aer_log, PCIEAERLog),
166: VMSTATE_END_OF_LIST()
167: }
168: };
169:
1.1.1.3 ! root 170: static Property xio3130_downstream_properties[] = {
! 171: DEFINE_PROP_UINT8("port", PCIESlot, port.port, 0),
! 172: DEFINE_PROP_UINT8("chassis", PCIESlot, chassis, 0),
! 173: DEFINE_PROP_UINT16("slot", PCIESlot, slot, 0),
! 174: DEFINE_PROP_UINT16("aer_log_max", PCIESlot,
! 175: port.br.dev.exp.aer_log.log_max,
! 176: PCIE_AER_LOG_MAX_DEFAULT),
! 177: DEFINE_PROP_END_OF_LIST(),
! 178: };
! 179:
! 180: static void xio3130_downstream_class_init(ObjectClass *klass, void *data)
! 181: {
! 182: DeviceClass *dc = DEVICE_CLASS(klass);
! 183: PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
! 184:
! 185: k->is_express = 1;
! 186: k->is_bridge = 1;
! 187: k->config_write = xio3130_downstream_write_config;
! 188: k->init = xio3130_downstream_initfn;
! 189: k->exit = xio3130_downstream_exitfn;
! 190: k->vendor_id = PCI_VENDOR_ID_TI;
! 191: k->device_id = PCI_DEVICE_ID_TI_XIO3130D;
! 192: k->revision = XIO3130_REVISION;
! 193: dc->desc = "TI X3130 Downstream Port of PCI Express Switch";
! 194: dc->reset = xio3130_downstream_reset;
! 195: dc->vmsd = &vmstate_xio3130_downstream;
! 196: dc->props = xio3130_downstream_properties;
! 197: }
! 198:
! 199: static TypeInfo xio3130_downstream_info = {
! 200: .name = "xio3130-downstream",
! 201: .parent = TYPE_PCI_DEVICE,
! 202: .instance_size = sizeof(PCIESlot),
! 203: .class_init = xio3130_downstream_class_init,
1.1 root 204: };
205:
1.1.1.3 ! root 206: static void xio3130_downstream_register_types(void)
1.1 root 207: {
1.1.1.3 ! root 208: type_register_static(&xio3130_downstream_info);
1.1 root 209: }
210:
1.1.1.3 ! root 211: type_init(xio3130_downstream_register_types)
1.1 root 212:
213: /*
214: * Local variables:
215: * c-indent-level: 4
216: * c-basic-offset: 4
217: * tab-width: 8
218: * indent-tab-mode: nil
219: * End:
220: */
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