![[BACK]](/cvsweb/icons/back.gif){kind=icon}
Return to m68k-dis.c CVS log ![[TXT]](/cvsweb/icons/text.gif){kind=icon}
![[DIR]](/cvsweb/icons/dir.gif){kind=icon}
Up to [Qemu by Fabrice Bellard] / qemu|
Return to m68k-dis.c CVS log | Up to [Qemu by Fabrice Bellard] / qemu |
1.1 root 1: /* This file is composed of several different files from the upstream
2: sourceware.org CVS. Original file boundaries marked with **** */
3:
4: #include <string.h>
5: #include <math.h>
6: #include <stdio.h>
7:
8: #include "dis-asm.h"
9:
1.1.1.3 root 10: /* **** floatformat.h from sourceware.org CVS 2005-08-14. */
1.1 root 11: /* IEEE floating point support declarations, for GDB, the GNU Debugger.
12: Copyright 1991, 1994, 1995, 1997, 2000, 2003 Free Software Foundation, Inc.
13:
14: This file is part of GDB.
15:
16: This program is free software; you can redistribute it and/or modify
17: it under the terms of the GNU General Public License as published by
18: the Free Software Foundation; either version 2 of the License, or
19: (at your option) any later version.
20:
21: This program is distributed in the hope that it will be useful,
22: but WITHOUT ANY WARRANTY; without even the implied warranty of
23: MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
24: GNU General Public License for more details.
25:
26: You should have received a copy of the GNU General Public License
1.1.1.4 ! root 27: along with this program; if not, see <http://www.gnu.org/licenses/>. */
1.1 root 28:
29: #if !defined (FLOATFORMAT_H)
30: #define FLOATFORMAT_H 1
31:
32: /*#include "ansidecl.h" */
33:
34: /* A floatformat consists of a sign bit, an exponent and a mantissa. Once the
35: bytes are concatenated according to the byteorder flag, then each of those
36: fields is contiguous. We number the bits with 0 being the most significant
37: (i.e. BITS_BIG_ENDIAN type numbering), and specify which bits each field
38: contains with the *_start and *_len fields. */
39:
40: /* What is the order of the bytes. */
41:
42: enum floatformat_byteorders {
43:
44: /* Standard little endian byte order.
45: EX: 1.2345678e10 => 00 00 80 c5 e0 fe 06 42 */
46:
47: floatformat_little,
48:
49: /* Standard big endian byte order.
50: EX: 1.2345678e10 => 42 06 fe e0 c5 80 00 00 */
51:
52: floatformat_big,
53:
54: /* Little endian byte order but big endian word order.
55: EX: 1.2345678e10 => e0 fe 06 42 00 00 80 c5 */
56:
57: floatformat_littlebyte_bigword
58:
59: };
60:
61: enum floatformat_intbit { floatformat_intbit_yes, floatformat_intbit_no };
62:
63: struct floatformat
64: {
65: enum floatformat_byteorders byteorder;
66: unsigned int totalsize; /* Total size of number in bits */
67:
68: /* Sign bit is always one bit long. 1 means negative, 0 means positive. */
69: unsigned int sign_start;
70:
71: unsigned int exp_start;
72: unsigned int exp_len;
73: /* Bias added to a "true" exponent to form the biased exponent. It
74: is intentionally signed as, otherwize, -exp_bias can turn into a
75: very large number (e.g., given the exp_bias of 0x3fff and a 64
76: bit long, the equation (long)(1 - exp_bias) evaluates to
77: 4294950914) instead of -16382). */
78: int exp_bias;
79: /* Exponent value which indicates NaN. This is the actual value stored in
80: the float, not adjusted by the exp_bias. This usually consists of all
81: one bits. */
82: unsigned int exp_nan;
83:
84: unsigned int man_start;
85: unsigned int man_len;
86:
87: /* Is the integer bit explicit or implicit? */
88: enum floatformat_intbit intbit;
89:
90: /* Internal name for debugging. */
91: const char *name;
92:
93: /* Validator method. */
94: int (*is_valid) (const struct floatformat *fmt, const char *from);
95: };
96:
97: /* floatformats for IEEE single and double, big and little endian. */
98:
99: extern const struct floatformat floatformat_ieee_single_big;
100: extern const struct floatformat floatformat_ieee_single_little;
101: extern const struct floatformat floatformat_ieee_double_big;
102: extern const struct floatformat floatformat_ieee_double_little;
103:
104: /* floatformat for ARM IEEE double, little endian bytes and big endian words */
105:
106: extern const struct floatformat floatformat_ieee_double_littlebyte_bigword;
107:
108: /* floatformats for various extendeds. */
109:
110: extern const struct floatformat floatformat_i387_ext;
111: extern const struct floatformat floatformat_m68881_ext;
112: extern const struct floatformat floatformat_i960_ext;
113: extern const struct floatformat floatformat_m88110_ext;
114: extern const struct floatformat floatformat_m88110_harris_ext;
115: extern const struct floatformat floatformat_arm_ext_big;
116: extern const struct floatformat floatformat_arm_ext_littlebyte_bigword;
117: /* IA-64 Floating Point register spilt into memory. */
118: extern const struct floatformat floatformat_ia64_spill_big;
119: extern const struct floatformat floatformat_ia64_spill_little;
120: extern const struct floatformat floatformat_ia64_quad_big;
121: extern const struct floatformat floatformat_ia64_quad_little;
122:
123: /* Convert from FMT to a double.
124: FROM is the address of the extended float.
125: Store the double in *TO. */
126:
127: extern void
128: floatformat_to_double (const struct floatformat *, const char *, double *);
129:
130: /* The converse: convert the double *FROM to FMT
131: and store where TO points. */
132:
133: extern void
134: floatformat_from_double (const struct floatformat *, const double *, char *);
135:
136: /* Return non-zero iff the data at FROM is a valid number in format FMT. */
137:
138: extern int
139: floatformat_is_valid (const struct floatformat *fmt, const char *from);
140:
141: #endif /* defined (FLOATFORMAT_H) */
142: /* **** End of floatformat.h */
143: /* **** m68k-dis.h from sourceware.org CVS 2005-08-14. */
144: /* Opcode table header for m680[01234]0/m6888[12]/m68851.
145: Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1999, 2001,
146: 2003, 2004 Free Software Foundation, Inc.
147:
148: This file is part of GDB, GAS, and the GNU binutils.
149:
150: GDB, GAS, and the GNU binutils are free software; you can redistribute
151: them and/or modify them under the terms of the GNU General Public
152: License as published by the Free Software Foundation; either version
153: 1, or (at your option) any later version.
154:
155: GDB, GAS, and the GNU binutils are distributed in the hope that they
156: will be useful, but WITHOUT ANY WARRANTY; without even the implied
157: warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See
158: the GNU General Public License for more details.
159:
160: You should have received a copy of the GNU General Public License
1.1.1.4 ! root 161: along with this file; see the file COPYING. If not,
! 162: see <http://www.gnu.org/licenses/>. */
1.1 root 163:
164: /* These are used as bit flags for the arch field in the m68k_opcode
165: structure. */
166: #define _m68k_undef 0
167: #define m68000 0x001
168: #define m68008 m68000 /* Synonym for -m68000. otherwise unused. */
169: #define m68010 0x002
170: #define m68020 0x004
171: #define m68030 0x008
172: #define m68ec030 m68030 /* Similar enough to -m68030 to ignore differences;
173: gas will deal with the few differences. */
174: #define m68040 0x010
175: /* There is no 68050. */
176: #define m68060 0x020
177: #define m68881 0x040
178: #define m68882 m68881 /* Synonym for -m68881. otherwise unused. */
179: #define m68851 0x080
180: #define cpu32 0x100 /* e.g., 68332 */
181:
182: #define mcfmac 0x200 /* ColdFire MAC. */
183: #define mcfemac 0x400 /* ColdFire EMAC. */
184: #define cfloat 0x800 /* ColdFire FPU. */
185: #define mcfhwdiv 0x1000 /* ColdFire hardware divide. */
186:
187: #define mcfisa_a 0x2000 /* ColdFire ISA_A. */
188: #define mcfisa_aa 0x4000 /* ColdFire ISA_A+. */
189: #define mcfisa_b 0x8000 /* ColdFire ISA_B. */
190: #define mcfusp 0x10000 /* ColdFire USP instructions. */
191:
192: #define mcf5200 0x20000
193: #define mcf5206e 0x40000
194: #define mcf521x 0x80000
195: #define mcf5249 0x100000
196: #define mcf528x 0x200000
197: #define mcf5307 0x400000
198: #define mcf5407 0x800000
199: #define mcf5470 0x1000000
200: #define mcf5480 0x2000000
201:
202: /* Handy aliases. */
203: #define m68040up (m68040 | m68060)
204: #define m68030up (m68030 | m68040up)
205: #define m68020up (m68020 | m68030up)
206: #define m68010up (m68010 | cpu32 | m68020up)
207: #define m68000up (m68000 | m68010up)
208:
209: #define mfloat (m68881 | m68882 | m68040 | m68060)
210: #define mmmu (m68851 | m68030 | m68040 | m68060)
211:
212: /* The structure used to hold information for an opcode. */
213:
214: struct m68k_opcode
215: {
216: /* The opcode name. */
217: const char *name;
218: /* The pseudo-size of the instruction(in bytes). Used to determine
219: number of bytes necessary to disassemble the instruction. */
220: unsigned int size;
221: /* The opcode itself. */
222: unsigned long opcode;
223: /* The mask used by the disassembler. */
224: unsigned long match;
225: /* The arguments. */
226: const char *args;
227: /* The architectures which support this opcode. */
228: unsigned int arch;
229: };
230:
231: /* The structure used to hold information for an opcode alias. */
232:
233: struct m68k_opcode_alias
234: {
235: /* The alias name. */
236: const char *alias;
237: /* The instruction for which this is an alias. */
238: const char *primary;
239: };
240:
241: /* We store four bytes of opcode for all opcodes because that is the
242: most any of them need. The actual length of an instruction is
243: always at least 2 bytes, and is as much longer as necessary to hold
244: the operands it has.
245:
246: The match field is a mask saying which bits must match particular
247: opcode in order for an instruction to be an instance of that
248: opcode.
249:
250: The args field is a string containing two characters for each
251: operand of the instruction. The first specifies the kind of
252: operand; the second, the place it is stored. */
253:
254: /* Kinds of operands:
255: Characters used: AaBbCcDdEeFfGgHIiJkLlMmnOopQqRrSsTtU VvWwXxYyZz01234|*~%;@!&$?/<>#^+-
256:
257: D data register only. Stored as 3 bits.
258: A address register only. Stored as 3 bits.
259: a address register indirect only. Stored as 3 bits.
260: R either kind of register. Stored as 4 bits.
261: r either kind of register indirect only. Stored as 4 bits.
262: At the moment, used only for cas2 instruction.
263: F floating point coprocessor register only. Stored as 3 bits.
264: O an offset (or width): immediate data 0-31 or data register.
265: Stored as 6 bits in special format for BF... insns.
266: + autoincrement only. Stored as 3 bits (number of the address register).
267: - autodecrement only. Stored as 3 bits (number of the address register).
268: Q quick immediate data. Stored as 3 bits.
269: This matches an immediate operand only when value is in range 1 .. 8.
270: M moveq immediate data. Stored as 8 bits.
271: This matches an immediate operand only when value is in range -128..127
272: T trap vector immediate data. Stored as 4 bits.
273:
274: k K-factor for fmove.p instruction. Stored as a 7-bit constant or
275: a three bit register offset, depending on the field type.
276:
277: # immediate data. Stored in special places (b, w or l)
278: which say how many bits to store.
279: ^ immediate data for floating point instructions. Special places
280: are offset by 2 bytes from '#'...
281: B pc-relative address, converted to an offset
282: that is treated as immediate data.
283: d displacement and register. Stores the register as 3 bits
284: and stores the displacement in the entire second word.
285:
286: C the CCR. No need to store it; this is just for filtering validity.
287: S the SR. No need to store, just as with CCR.
288: U the USP. No need to store, just as with CCR.
289: E the MAC ACC. No need to store, just as with CCR.
290: e the EMAC ACC[0123].
291: G the MAC/EMAC MACSR. No need to store, just as with CCR.
292: g the EMAC ACCEXT{01,23}.
293: H the MASK. No need to store, just as with CCR.
294: i the MAC/EMAC scale factor.
295:
296: I Coprocessor ID. Not printed if 1. The Coprocessor ID is always
297: extracted from the 'd' field of word one, which means that an extended
298: coprocessor opcode can be skipped using the 'i' place, if needed.
299:
300: s System Control register for the floating point coprocessor.
301:
302: J Misc register for movec instruction, stored in 'j' format.
303: Possible values:
304: 0x000 SFC Source Function Code reg [60, 40, 30, 20, 10]
305: 0x001 DFC Data Function Code reg [60, 40, 30, 20, 10]
306: 0x002 CACR Cache Control Register [60, 40, 30, 20, mcf]
307: 0x003 TC MMU Translation Control [60, 40]
308: 0x004 ITT0 Instruction Transparent
309: Translation reg 0 [60, 40]
310: 0x005 ITT1 Instruction Transparent
311: Translation reg 1 [60, 40]
312: 0x006 DTT0 Data Transparent
313: Translation reg 0 [60, 40]
314: 0x007 DTT1 Data Transparent
315: Translation reg 1 [60, 40]
316: 0x008 BUSCR Bus Control Register [60]
317: 0x800 USP User Stack Pointer [60, 40, 30, 20, 10]
318: 0x801 VBR Vector Base reg [60, 40, 30, 20, 10, mcf]
319: 0x802 CAAR Cache Address Register [ 30, 20]
320: 0x803 MSP Master Stack Pointer [ 40, 30, 20]
321: 0x804 ISP Interrupt Stack Pointer [ 40, 30, 20]
322: 0x805 MMUSR MMU Status reg [ 40]
323: 0x806 URP User Root Pointer [60, 40]
324: 0x807 SRP Supervisor Root Pointer [60, 40]
325: 0x808 PCR Processor Configuration reg [60]
326: 0xC00 ROMBAR ROM Base Address Register [520X]
327: 0xC04 RAMBAR0 RAM Base Address Register 0 [520X]
328: 0xC05 RAMBAR1 RAM Base Address Register 0 [520X]
329: 0xC0F MBAR0 RAM Base Address Register 0 [520X]
330: 0xC04 FLASHBAR FLASH Base Address Register [mcf528x]
331: 0xC05 RAMBAR Static RAM Base Address Register [mcf528x]
332:
333: L Register list of the type d0-d7/a0-a7 etc.
334: (New! Improved! Can also hold fp0-fp7, as well!)
335: The assembler tries to see if the registers match the insn by
336: looking at where the insn wants them stored.
337:
338: l Register list like L, but with all the bits reversed.
339: Used for going the other way. . .
340:
341: c cache identifier which may be "nc" for no cache, "ic"
342: for instruction cache, "dc" for data cache, or "bc"
343: for both caches. Used in cinv and cpush. Always
344: stored in position "d".
345:
346: u Any register, with ``upper'' or ``lower'' specification. Used
347: in the mac instructions with size word.
348:
349: The remainder are all stored as 6 bits using an address mode and a
350: register number; they differ in which addressing modes they match.
351:
352: * all (modes 0-6,7.0-4)
353: ~ alterable memory (modes 2-6,7.0,7.1)
354: (not 0,1,7.2-4)
355: % alterable (modes 0-6,7.0,7.1)
356: (not 7.2-4)
357: ; data (modes 0,2-6,7.0-4)
358: (not 1)
359: @ data, but not immediate (modes 0,2-6,7.0-3)
360: (not 1,7.4)
361: ! control (modes 2,5,6,7.0-3)
362: (not 0,1,3,4,7.4)
363: & alterable control (modes 2,5,6,7.0,7.1)
364: (not 0,1,3,4,7.2-4)
365: $ alterable data (modes 0,2-6,7.0,7.1)
366: (not 1,7.2-4)
367: ? alterable control, or data register (modes 0,2,5,6,7.0,7.1)
368: (not 1,3,4,7.2-4)
369: / control, or data register (modes 0,2,5,6,7.0-3)
370: (not 1,3,4,7.4)
371: > *save operands (modes 2,4,5,6,7.0,7.1)
372: (not 0,1,3,7.2-4)
373: < *restore operands (modes 2,3,5,6,7.0-3)
374: (not 0,1,4,7.4)
375:
376: coldfire move operands:
377: m (modes 0-4)
378: n (modes 5,7.2)
379: o (modes 6,7.0,7.1,7.3,7.4)
380: p (modes 0-5)
381:
382: coldfire bset/bclr/btst/mulsl/mulul operands:
383: q (modes 0,2-5)
384: v (modes 0,2-5,7.0,7.1)
385: b (modes 0,2-5,7.2)
386: w (modes 2-5,7.2)
387: y (modes 2,5)
388: z (modes 2,5,7.2)
389: x mov3q immediate operand.
390: 4 (modes 2,3,4,5)
391: */
392:
393: /* For the 68851: */
394: /* I didn't use much imagination in choosing the
395: following codes, so many of them aren't very
396: mnemonic. -rab
397:
398: 0 32 bit pmmu register
399: Possible values:
400: 000 TC Translation Control Register (68030, 68851)
401:
402: 1 16 bit pmmu register
403: 111 AC Access Control (68851)
404:
405: 2 8 bit pmmu register
406: 100 CAL Current Access Level (68851)
407: 101 VAL Validate Access Level (68851)
408: 110 SCC Stack Change Control (68851)
409:
410: 3 68030-only pmmu registers (32 bit)
411: 010 TT0 Transparent Translation reg 0
412: (aka Access Control reg 0 -- AC0 -- on 68ec030)
413: 011 TT1 Transparent Translation reg 1
414: (aka Access Control reg 1 -- AC1 -- on 68ec030)
415:
416: W wide pmmu registers
417: Possible values:
418: 001 DRP Dma Root Pointer (68851)
419: 010 SRP Supervisor Root Pointer (68030, 68851)
420: 011 CRP Cpu Root Pointer (68030, 68851)
421:
422: f function code register (68030, 68851)
423: 0 SFC
424: 1 DFC
425:
426: V VAL register only (68851)
427:
428: X BADx, BACx (16 bit)
429: 100 BAD Breakpoint Acknowledge Data (68851)
430: 101 BAC Breakpoint Acknowledge Control (68851)
431:
432: Y PSR (68851) (MMUSR on 68030) (ACUSR on 68ec030)
433: Z PCSR (68851)
434:
435: | memory (modes 2-6, 7.*)
436:
437: t address test level (68030 only)
438: Stored as 3 bits, range 0-7.
439: Also used for breakpoint instruction now.
440:
441: */
442:
443: /* Places to put an operand, for non-general operands:
444: Characters used: BbCcDdFfGgHhIijkLlMmNnostWw123456789/
445:
446: s source, low bits of first word.
447: d dest, shifted 9 in first word
448: 1 second word, shifted 12
449: 2 second word, shifted 6
450: 3 second word, shifted 0
451: 4 third word, shifted 12
452: 5 third word, shifted 6
453: 6 third word, shifted 0
454: 7 second word, shifted 7
455: 8 second word, shifted 10
456: 9 second word, shifted 5
457: D store in both place 1 and place 3; for divul and divsl.
458: B first word, low byte, for branch displacements
459: W second word (entire), for branch displacements
460: L second and third words (entire), for branch displacements
461: (also overloaded for move16)
462: b second word, low byte
463: w second word (entire) [variable word/long branch offset for dbra]
464: W second word (entire) (must be signed 16 bit value)
465: l second and third word (entire)
466: g variable branch offset for bra and similar instructions.
467: The place to store depends on the magnitude of offset.
468: t store in both place 7 and place 8; for floating point operations
469: c branch offset for cpBcc operations.
470: The place to store is word two if bit six of word one is zero,
471: and words two and three if bit six of word one is one.
472: i Increment by two, to skip over coprocessor extended operands. Only
473: works with the 'I' format.
474: k Dynamic K-factor field. Bits 6-4 of word 2, used as a register number.
475: Also used for dynamic fmovem instruction.
476: C floating point coprocessor constant - 7 bits. Also used for static
477: K-factors...
478: j Movec register #, stored in 12 low bits of second word.
479: m For M[S]ACx; 4 bits split with MSB shifted 6 bits in first word
480: and remaining 3 bits of register shifted 9 bits in first word.
481: Indicate upper/lower in 1 bit shifted 7 bits in second word.
482: Use with `R' or `u' format.
483: n `m' withouth upper/lower indication. (For M[S]ACx; 4 bits split
484: with MSB shifted 6 bits in first word and remaining 3 bits of
485: register shifted 9 bits in first word. No upper/lower
486: indication is done.) Use with `R' or `u' format.
487: o For M[S]ACw; 4 bits shifted 12 in second word (like `1').
488: Indicate upper/lower in 1 bit shifted 7 bits in second word.
489: Use with `R' or `u' format.
490: M For M[S]ACw; 4 bits in low bits of first word. Indicate
491: upper/lower in 1 bit shifted 6 bits in second word. Use with
492: `R' or `u' format.
493: N For M[S]ACw; 4 bits in low bits of second word. Indicate
494: upper/lower in 1 bit shifted 6 bits in second word. Use with
495: `R' or `u' format.
496: h shift indicator (scale factor), 1 bit shifted 10 in second word
497:
498: Places to put operand, for general operands:
499: d destination, shifted 6 bits in first word
500: b source, at low bit of first word, and immediate uses one byte
501: w source, at low bit of first word, and immediate uses two bytes
502: l source, at low bit of first word, and immediate uses four bytes
503: s source, at low bit of first word.
504: Used sometimes in contexts where immediate is not allowed anyway.
505: f single precision float, low bit of 1st word, immediate uses 4 bytes
506: F double precision float, low bit of 1st word, immediate uses 8 bytes
507: x extended precision float, low bit of 1st word, immediate uses 12 bytes
508: p packed float, low bit of 1st word, immediate uses 12 bytes
509: G EMAC accumulator, load (bit 4 2nd word, !bit8 first word)
510: H EMAC accumulator, non load (bit 4 2nd word, bit 8 first word)
511: F EMAC ACCx
512: f EMAC ACCy
513: I MAC/EMAC scale factor
514: / Like 's', but set 2nd word, bit 5 if trailing_ampersand set
515: ] first word, bit 10
516: */
517:
518: extern const struct m68k_opcode m68k_opcodes[];
519: extern const struct m68k_opcode_alias m68k_opcode_aliases[];
520:
521: extern const int m68k_numopcodes, m68k_numaliases;
522:
523: /* **** End of m68k-opcode.h */
524: /* **** m68k-dis.c from sourceware.org CVS 2005-08-14. */
525: /* Print Motorola 68k instructions.
526: Copyright 1986, 1987, 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997,
527: 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005
528: Free Software Foundation, Inc.
529:
530: This file is free software; you can redistribute it and/or modify
531: it under the terms of the GNU General Public License as published by
532: the Free Software Foundation; either version 2 of the License, or
533: (at your option) any later version.
534:
535: This program is distributed in the hope that it will be useful,
536: but WITHOUT ANY WARRANTY; without even the implied warranty of
537: MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
538: GNU General Public License for more details.
539:
540: You should have received a copy of the GNU General Public License
1.1.1.4 ! root 541: along with this program; if not, see <http://www.gnu.org/licenses/>. */
1.1 root 542:
543: /* Local function prototypes. */
544:
1.1.1.3 root 545: static const char * const fpcr_names[] =
1.1 root 546: {
547: "", "%fpiar", "%fpsr", "%fpiar/%fpsr", "%fpcr",
548: "%fpiar/%fpcr", "%fpsr/%fpcr", "%fpiar/%fpsr/%fpcr"
549: };
550:
1.1.1.3 root 551: static const char *const reg_names[] =
1.1 root 552: {
553: "%d0", "%d1", "%d2", "%d3", "%d4", "%d5", "%d6", "%d7",
554: "%a0", "%a1", "%a2", "%a3", "%a4", "%a5", "%fp", "%sp",
555: "%ps", "%pc"
556: };
557:
558: /* Name of register halves for MAC/EMAC.
1.1.1.2 root 559: Separate from reg_names since 'spu', 'fpl' look weird. */
1.1.1.3 root 560: static const char *const reg_half_names[] =
1.1 root 561: {
562: "%d0", "%d1", "%d2", "%d3", "%d4", "%d5", "%d6", "%d7",
563: "%a0", "%a1", "%a2", "%a3", "%a4", "%a5", "%a6", "%a7",
564: "%ps", "%pc"
565: };
566:
567: /* Sign-extend an (unsigned char). */
568: #if __STDC__ == 1
569: #define COERCE_SIGNED_CHAR(ch) ((signed char) (ch))
570: #else
571: #define COERCE_SIGNED_CHAR(ch) ((int) (((ch) ^ 0x80) & 0xFF) - 128)
572: #endif
573:
574: /* Get a 1 byte signed integer. */
575: #define NEXTBYTE(p) (p += 2, FETCH_DATA (info, p), COERCE_SIGNED_CHAR(p[-1]))
576:
577: /* Get a 2 byte signed integer. */
578: #define COERCE16(x) ((int) (((x) ^ 0x8000) - 0x8000))
579: #define NEXTWORD(p) \
580: (p += 2, FETCH_DATA (info, p), \
581: COERCE16 ((p[-2] << 8) + p[-1]))
582:
583: /* Get a 4 byte signed integer. */
584: #define COERCE32(x) ((bfd_signed_vma) ((x) ^ 0x80000000) - 0x80000000)
585: #define NEXTLONG(p) \
586: (p += 4, FETCH_DATA (info, p), \
587: (COERCE32 ((((((p[-4] << 8) + p[-3]) << 8) + p[-2]) << 8) + p[-1])))
588:
589: /* Get a 4 byte unsigned integer. */
590: #define NEXTULONG(p) \
591: (p += 4, FETCH_DATA (info, p), \
592: (unsigned int) ((((((p[-4] << 8) + p[-3]) << 8) + p[-2]) << 8) + p[-1]))
593:
594: /* Get a single precision float. */
595: #define NEXTSINGLE(val, p) \
596: (p += 4, FETCH_DATA (info, p), \
597: floatformat_to_double (&floatformat_ieee_single_big, (char *) p - 4, &val))
598:
599: /* Get a double precision float. */
600: #define NEXTDOUBLE(val, p) \
601: (p += 8, FETCH_DATA (info, p), \
602: floatformat_to_double (&floatformat_ieee_double_big, (char *) p - 8, &val))
603:
604: /* Get an extended precision float. */
605: #define NEXTEXTEND(val, p) \
606: (p += 12, FETCH_DATA (info, p), \
607: floatformat_to_double (&floatformat_m68881_ext, (char *) p - 12, &val))
608:
609: /* Need a function to convert from packed to double
610: precision. Actually, it's easier to print a
611: packed number than a double anyway, so maybe
612: there should be a special case to handle this... */
613: #define NEXTPACKED(p) \
614: (p += 12, FETCH_DATA (info, p), 0.0)
615:
616: /* Maximum length of an instruction. */
617: #define MAXLEN 22
618:
619: #include <setjmp.h>
620:
621: struct private
622: {
623: /* Points to first byte not fetched. */
624: bfd_byte *max_fetched;
625: bfd_byte the_buffer[MAXLEN];
626: bfd_vma insn_start;
627: jmp_buf bailout;
628: };
629:
630: /* Make sure that bytes from INFO->PRIVATE_DATA->BUFFER (inclusive)
631: to ADDR (exclusive) are valid. Returns 1 for success, longjmps
632: on error. */
633: #define FETCH_DATA(info, addr) \
634: ((addr) <= ((struct private *) (info->private_data))->max_fetched \
635: ? 1 : fetch_data ((info), (addr)))
636:
637: static int
638: fetch_data (struct disassemble_info *info, bfd_byte *addr)
639: {
640: int status;
641: struct private *priv = (struct private *)info->private_data;
642: bfd_vma start = priv->insn_start + (priv->max_fetched - priv->the_buffer);
643:
644: status = (*info->read_memory_func) (start,
645: priv->max_fetched,
646: addr - priv->max_fetched,
647: info);
648: if (status != 0)
649: {
650: (*info->memory_error_func) (status, start, info);
651: longjmp (priv->bailout, 1);
652: }
653: else
654: priv->max_fetched = addr;
655: return 1;
656: }
657:
658: /* This function is used to print to the bit-bucket. */
659: static int
660: dummy_printer (FILE *file ATTRIBUTE_UNUSED,
661: const char *format ATTRIBUTE_UNUSED,
662: ...)
663: {
664: return 0;
665: }
666:
667: static void
668: dummy_print_address (bfd_vma vma ATTRIBUTE_UNUSED,
669: struct disassemble_info *info ATTRIBUTE_UNUSED)
670: {
671: }
672:
673: /* Fetch BITS bits from a position in the instruction specified by CODE.
674: CODE is a "place to put an argument", or 'x' for a destination
675: that is a general address (mode and register).
676: BUFFER contains the instruction. */
677:
678: static int
679: fetch_arg (unsigned char *buffer,
680: int code,
681: int bits,
682: disassemble_info *info)
683: {
684: int val = 0;
685:
686: switch (code)
687: {
688: case '/': /* MAC/EMAC mask bit. */
689: val = buffer[3] >> 5;
690: break;
691:
692: case 'G': /* EMAC ACC load. */
693: val = ((buffer[3] >> 3) & 0x2) | ((~buffer[1] >> 7) & 0x1);
694: break;
695:
696: case 'H': /* EMAC ACC !load. */
697: val = ((buffer[3] >> 3) & 0x2) | ((buffer[1] >> 7) & 0x1);
698: break;
699:
700: case ']': /* EMAC ACCEXT bit. */
701: val = buffer[0] >> 2;
702: break;
703:
704: case 'I': /* MAC/EMAC scale factor. */
705: val = buffer[2] >> 1;
706: break;
707:
708: case 'F': /* EMAC ACCx. */
709: val = buffer[0] >> 1;
710: break;
711:
712: case 'f':
713: val = buffer[1];
714: break;
715:
716: case 's':
717: val = buffer[1];
718: break;
719:
720: case 'd': /* Destination, for register or quick. */
721: val = (buffer[0] << 8) + buffer[1];
722: val >>= 9;
723: break;
724:
725: case 'x': /* Destination, for general arg. */
726: val = (buffer[0] << 8) + buffer[1];
727: val >>= 6;
728: break;
729:
730: case 'k':
731: FETCH_DATA (info, buffer + 3);
732: val = (buffer[3] >> 4);
733: break;
734:
735: case 'C':
736: FETCH_DATA (info, buffer + 3);
737: val = buffer[3];
738: break;
739:
740: case '1':
741: FETCH_DATA (info, buffer + 3);
742: val = (buffer[2] << 8) + buffer[3];
743: val >>= 12;
744: break;
745:
746: case '2':
747: FETCH_DATA (info, buffer + 3);
748: val = (buffer[2] << 8) + buffer[3];
749: val >>= 6;
750: break;
751:
752: case '3':
753: case 'j':
754: FETCH_DATA (info, buffer + 3);
755: val = (buffer[2] << 8) + buffer[3];
756: break;
757:
758: case '4':
759: FETCH_DATA (info, buffer + 5);
760: val = (buffer[4] << 8) + buffer[5];
761: val >>= 12;
762: break;
763:
764: case '5':
765: FETCH_DATA (info, buffer + 5);
766: val = (buffer[4] << 8) + buffer[5];
767: val >>= 6;
768: break;
769:
770: case '6':
771: FETCH_DATA (info, buffer + 5);
772: val = (buffer[4] << 8) + buffer[5];
773: break;
774:
775: case '7':
776: FETCH_DATA (info, buffer + 3);
777: val = (buffer[2] << 8) + buffer[3];
778: val >>= 7;
779: break;
780:
781: case '8':
782: FETCH_DATA (info, buffer + 3);
783: val = (buffer[2] << 8) + buffer[3];
784: val >>= 10;
785: break;
786:
787: case '9':
788: FETCH_DATA (info, buffer + 3);
789: val = (buffer[2] << 8) + buffer[3];
790: val >>= 5;
791: break;
792:
793: case 'e':
794: val = (buffer[1] >> 6);
795: break;
796:
797: case 'm':
798: val = (buffer[1] & 0x40 ? 0x8 : 0)
799: | ((buffer[0] >> 1) & 0x7)
800: | (buffer[3] & 0x80 ? 0x10 : 0);
801: break;
802:
803: case 'n':
804: val = (buffer[1] & 0x40 ? 0x8 : 0) | ((buffer[0] >> 1) & 0x7);
805: break;
806:
807: case 'o':
808: val = (buffer[2] >> 4) | (buffer[3] & 0x80 ? 0x10 : 0);
809: break;
810:
811: case 'M':
812: val = (buffer[1] & 0xf) | (buffer[3] & 0x40 ? 0x10 : 0);
813: break;
814:
815: case 'N':
816: val = (buffer[3] & 0xf) | (buffer[3] & 0x40 ? 0x10 : 0);
817: break;
818:
819: case 'h':
820: val = buffer[2] >> 2;
821: break;
822:
823: default:
824: abort ();
825: }
826:
827: switch (bits)
828: {
829: case 1:
830: return val & 1;
831: case 2:
832: return val & 3;
833: case 3:
834: return val & 7;
835: case 4:
836: return val & 017;
837: case 5:
838: return val & 037;
839: case 6:
840: return val & 077;
841: case 7:
842: return val & 0177;
843: case 8:
844: return val & 0377;
845: case 12:
846: return val & 07777;
847: default:
848: abort ();
849: }
850: }
851:
852: /* Check if an EA is valid for a particular code. This is required
853: for the EMAC instructions since the type of source address determines
854: if it is a EMAC-load instruciton if the EA is mode 2-5, otherwise it
855: is a non-load EMAC instruction and the bits mean register Ry.
856: A similar case exists for the movem instructions where the register
857: mask is interpreted differently for different EAs. */
858:
859: static bfd_boolean
860: m68k_valid_ea (char code, int val)
861: {
862: int mode, mask;
863: #define M(n0,n1,n2,n3,n4,n5,n6,n70,n71,n72,n73,n74) \
864: (n0 | n1 << 1 | n2 << 2 | n3 << 3 | n4 << 4 | n5 << 5 | n6 << 6 \
865: | n70 << 7 | n71 << 8 | n72 << 9 | n73 << 10 | n74 << 11)
866:
867: switch (code)
868: {
869: case '*':
870: mask = M (1,1,1,1,1,1,1,1,1,1,1,1);
871: break;
872: case '~':
873: mask = M (0,0,1,1,1,1,1,1,1,0,0,0);
874: break;
875: case '%':
876: mask = M (1,1,1,1,1,1,1,1,1,0,0,0);
877: break;
878: case ';':
879: mask = M (1,0,1,1,1,1,1,1,1,1,1,1);
880: break;
881: case '@':
882: mask = M (1,0,1,1,1,1,1,1,1,1,1,0);
883: break;
884: case '!':
885: mask = M (0,0,1,0,0,1,1,1,1,1,1,0);
886: break;
887: case '&':
888: mask = M (0,0,1,0,0,1,1,1,1,0,0,0);
889: break;
890: case '$':
891: mask = M (1,0,1,1,1,1,1,1,1,0,0,0);
892: break;
893: case '?':
894: mask = M (1,0,1,0,0,1,1,1,1,0,0,0);
895: break;
896: case '/':
897: mask = M (1,0,1,0,0,1,1,1,1,1,1,0);
898: break;
899: case '|':
900: mask = M (0,0,1,0,0,1,1,1,1,1,1,0);
901: break;
902: case '>':
903: mask = M (0,0,1,0,1,1,1,1,1,0,0,0);
904: break;
905: case '<':
906: mask = M (0,0,1,1,0,1,1,1,1,1,1,0);
907: break;
908: case 'm':
909: mask = M (1,1,1,1,1,0,0,0,0,0,0,0);
910: break;
911: case 'n':
912: mask = M (0,0,0,0,0,1,0,0,0,1,0,0);
913: break;
914: case 'o':
915: mask = M (0,0,0,0,0,0,1,1,1,0,1,1);
916: break;
917: case 'p':
918: mask = M (1,1,1,1,1,1,0,0,0,0,0,0);
919: break;
920: case 'q':
921: mask = M (1,0,1,1,1,1,0,0,0,0,0,0);
922: break;
923: case 'v':
924: mask = M (1,0,1,1,1,1,0,1,1,0,0,0);
925: break;
926: case 'b':
927: mask = M (1,0,1,1,1,1,0,0,0,1,0,0);
928: break;
929: case 'w':
930: mask = M (0,0,1,1,1,1,0,0,0,1,0,0);
931: break;
932: case 'y':
933: mask = M (0,0,1,0,0,1,0,0,0,0,0,0);
934: break;
935: case 'z':
936: mask = M (0,0,1,0,0,1,0,0,0,1,0,0);
937: break;
938: case '4':
939: mask = M (0,0,1,1,1,1,0,0,0,0,0,0);
940: break;
941: default:
942: abort ();
943: }
944: #undef M
945:
946: mode = (val >> 3) & 7;
947: if (mode == 7)
948: mode += val & 7;
949: return (mask & (1 << mode)) != 0;
950: }
951:
952: /* Print a base register REGNO and displacement DISP, on INFO->STREAM.
953: REGNO = -1 for pc, -2 for none (suppressed). */
954:
955: static void
956: print_base (int regno, bfd_vma disp, disassemble_info *info)
957: {
958: if (regno == -1)
959: {
960: (*info->fprintf_func) (info->stream, "%%pc@(");
961: (*info->print_address_func) (disp, info);
962: }
963: else
964: {
965: char buf[50];
966:
967: if (regno == -2)
968: (*info->fprintf_func) (info->stream, "@(");
969: else if (regno == -3)
970: (*info->fprintf_func) (info->stream, "%%zpc@(");
971: else
972: (*info->fprintf_func) (info->stream, "%s@(", reg_names[regno]);
973:
974: sprintf_vma (buf, disp);
975: (*info->fprintf_func) (info->stream, "%s", buf);
976: }
977: }
978:
979: /* Print an indexed argument. The base register is BASEREG (-1 for pc).
980: P points to extension word, in buffer.
981: ADDR is the nominal core address of that extension word. */
982:
983: static unsigned char *
984: print_indexed (int basereg,
985: unsigned char *p,
986: bfd_vma addr,
987: disassemble_info *info)
988: {
989: int word;
1.1.1.3 root 990: static const char *const scales[] = { "", ":2", ":4", ":8" };
1.1 root 991: bfd_vma base_disp;
992: bfd_vma outer_disp;
993: char buf[40];
994: char vmabuf[50];
995:
996: word = NEXTWORD (p);
997:
998: /* Generate the text for the index register.
999: Where this will be output is not yet determined. */
1000: sprintf (buf, "%s:%c%s",
1001: reg_names[(word >> 12) & 0xf],
1002: (word & 0x800) ? 'l' : 'w',
1003: scales[(word >> 9) & 3]);
1004:
1005: /* Handle the 68000 style of indexing. */
1006:
1007: if ((word & 0x100) == 0)
1008: {
1009: base_disp = word & 0xff;
1010: if ((base_disp & 0x80) != 0)
1011: base_disp -= 0x100;
1012: if (basereg == -1)
1013: base_disp += addr;
1014: print_base (basereg, base_disp, info);
1015: (*info->fprintf_func) (info->stream, ",%s)", buf);
1016: return p;
1017: }
1018:
1019: /* Handle the generalized kind. */
1020: /* First, compute the displacement to add to the base register. */
1021: if (word & 0200)
1022: {
1023: if (basereg == -1)
1024: basereg = -3;
1025: else
1026: basereg = -2;
1027: }
1028: if (word & 0100)
1029: buf[0] = '\0';
1030: base_disp = 0;
1031: switch ((word >> 4) & 3)
1032: {
1033: case 2:
1034: base_disp = NEXTWORD (p);
1035: break;
1036: case 3:
1037: base_disp = NEXTLONG (p);
1038: }
1039: if (basereg == -1)
1040: base_disp += addr;
1041:
1042: /* Handle single-level case (not indirect). */
1043: if ((word & 7) == 0)
1044: {
1045: print_base (basereg, base_disp, info);
1046: if (buf[0] != '\0')
1047: (*info->fprintf_func) (info->stream, ",%s", buf);
1048: (*info->fprintf_func) (info->stream, ")");
1049: return p;
1050: }
1051:
1052: /* Two level. Compute displacement to add after indirection. */
1053: outer_disp = 0;
1054: switch (word & 3)
1055: {
1056: case 2:
1057: outer_disp = NEXTWORD (p);
1058: break;
1059: case 3:
1060: outer_disp = NEXTLONG (p);
1061: }
1062:
1063: print_base (basereg, base_disp, info);
1064: if ((word & 4) == 0 && buf[0] != '\0')
1065: {
1066: (*info->fprintf_func) (info->stream, ",%s", buf);
1067: buf[0] = '\0';
1068: }
1069: sprintf_vma (vmabuf, outer_disp);
1070: (*info->fprintf_func) (info->stream, ")@(%s", vmabuf);
1071: if (buf[0] != '\0')
1072: (*info->fprintf_func) (info->stream, ",%s", buf);
1073: (*info->fprintf_func) (info->stream, ")");
1074:
1075: return p;
1076: }
1077:
1078: /* Returns number of bytes "eaten" by the operand, or
1079: return -1 if an invalid operand was found, or -2 if
1080: an opcode tabe error was found.
1081: ADDR is the pc for this arg to be relative to. */
1082:
1083: static int
1084: print_insn_arg (const char *d,
1085: unsigned char *buffer,
1086: unsigned char *p0,
1087: bfd_vma addr,
1088: disassemble_info *info)
1089: {
1090: int val = 0;
1091: int place = d[1];
1092: unsigned char *p = p0;
1093: int regno;
1094: const char *regname;
1095: unsigned char *p1;
1096: double flval;
1097: int flt_p;
1098: bfd_signed_vma disp;
1099: unsigned int uval;
1100:
1101: switch (*d)
1102: {
1103: case 'c': /* Cache identifier. */
1104: {
1.1.1.3 root 1105: static const char *const cacheFieldName[] = { "nc", "dc", "ic", "bc" };
1.1 root 1106: val = fetch_arg (buffer, place, 2, info);
1107: (*info->fprintf_func) (info->stream, cacheFieldName[val]);
1108: break;
1109: }
1110:
1111: case 'a': /* Address register indirect only. Cf. case '+'. */
1112: {
1113: (*info->fprintf_func)
1114: (info->stream,
1115: "%s@",
1116: reg_names[fetch_arg (buffer, place, 3, info) + 8]);
1117: break;
1118: }
1119:
1120: case '_': /* 32-bit absolute address for move16. */
1121: {
1122: uval = NEXTULONG (p);
1123: (*info->print_address_func) (uval, info);
1124: break;
1125: }
1126:
1127: case 'C':
1128: (*info->fprintf_func) (info->stream, "%%ccr");
1129: break;
1130:
1131: case 'S':
1132: (*info->fprintf_func) (info->stream, "%%sr");
1133: break;
1134:
1135: case 'U':
1136: (*info->fprintf_func) (info->stream, "%%usp");
1137: break;
1138:
1139: case 'E':
1140: (*info->fprintf_func) (info->stream, "%%acc");
1141: break;
1142:
1143: case 'G':
1144: (*info->fprintf_func) (info->stream, "%%macsr");
1145: break;
1146:
1147: case 'H':
1148: (*info->fprintf_func) (info->stream, "%%mask");
1149: break;
1150:
1151: case 'J':
1152: {
1153: /* FIXME: There's a problem here, different m68k processors call the
1154: same address different names. This table can't get it right
1155: because it doesn't know which processor it's disassembling for. */
1.1.1.3 root 1156: static const struct { const char *name; int value; } names[]
1.1 root 1157: = {{"%sfc", 0x000}, {"%dfc", 0x001}, {"%cacr", 0x002},
1158: {"%tc", 0x003}, {"%itt0",0x004}, {"%itt1", 0x005},
1159: {"%dtt0",0x006}, {"%dtt1",0x007}, {"%buscr",0x008},
1160: {"%usp", 0x800}, {"%vbr", 0x801}, {"%caar", 0x802},
1161: {"%msp", 0x803}, {"%isp", 0x804},
1162: {"%flashbar", 0xc04}, {"%rambar", 0xc05}, /* mcf528x added these. */
1163:
1164: /* Should we be calling this psr like we do in case 'Y'? */
1165: {"%mmusr",0x805},
1166:
1167: {"%urp", 0x806}, {"%srp", 0x807}, {"%pcr", 0x808}};
1168:
1169: val = fetch_arg (buffer, place, 12, info);
1170: for (regno = sizeof names / sizeof names[0] - 1; regno >= 0; regno--)
1171: if (names[regno].value == val)
1172: {
1173: (*info->fprintf_func) (info->stream, "%s", names[regno].name);
1174: break;
1175: }
1176: if (regno < 0)
1177: (*info->fprintf_func) (info->stream, "%d", val);
1178: }
1179: break;
1180:
1181: case 'Q':
1182: val = fetch_arg (buffer, place, 3, info);
1183: /* 0 means 8, except for the bkpt instruction... */
1184: if (val == 0 && d[1] != 's')
1185: val = 8;
1186: (*info->fprintf_func) (info->stream, "#%d", val);
1187: break;
1188:
1189: case 'x':
1190: val = fetch_arg (buffer, place, 3, info);
1191: /* 0 means -1. */
1192: if (val == 0)
1193: val = -1;
1194: (*info->fprintf_func) (info->stream, "#%d", val);
1195: break;
1196:
1197: case 'M':
1198: if (place == 'h')
1199: {
1.1.1.3 root 1200: static const char *const scalefactor_name[] = { "<<", ">>" };
1.1 root 1201: val = fetch_arg (buffer, place, 1, info);
1202: (*info->fprintf_func) (info->stream, scalefactor_name[val]);
1203: }
1204: else
1205: {
1206: val = fetch_arg (buffer, place, 8, info);
1207: if (val & 0x80)
1208: val = val - 0x100;
1209: (*info->fprintf_func) (info->stream, "#%d", val);
1210: }
1211: break;
1212:
1213: case 'T':
1214: val = fetch_arg (buffer, place, 4, info);
1215: (*info->fprintf_func) (info->stream, "#%d", val);
1216: break;
1217:
1218: case 'D':
1219: (*info->fprintf_func) (info->stream, "%s",
1220: reg_names[fetch_arg (buffer, place, 3, info)]);
1221: break;
1222:
1223: case 'A':
1224: (*info->fprintf_func)
1225: (info->stream, "%s",
1226: reg_names[fetch_arg (buffer, place, 3, info) + 010]);
1227: break;
1228:
1229: case 'R':
1230: (*info->fprintf_func)
1231: (info->stream, "%s",
1232: reg_names[fetch_arg (buffer, place, 4, info)]);
1233: break;
1234:
1235: case 'r':
1236: regno = fetch_arg (buffer, place, 4, info);
1237: if (regno > 7)
1238: (*info->fprintf_func) (info->stream, "%s@", reg_names[regno]);
1239: else
1240: (*info->fprintf_func) (info->stream, "@(%s)", reg_names[regno]);
1241: break;
1242:
1243: case 'F':
1244: (*info->fprintf_func)
1245: (info->stream, "%%fp%d",
1246: fetch_arg (buffer, place, 3, info));
1247: break;
1248:
1249: case 'O':
1250: val = fetch_arg (buffer, place, 6, info);
1251: if (val & 0x20)
1252: (*info->fprintf_func) (info->stream, "%s", reg_names[val & 7]);
1253: else
1254: (*info->fprintf_func) (info->stream, "%d", val);
1255: break;
1256:
1257: case '+':
1258: (*info->fprintf_func)
1259: (info->stream, "%s@+",
1260: reg_names[fetch_arg (buffer, place, 3, info) + 8]);
1261: break;
1262:
1263: case '-':
1264: (*info->fprintf_func)
1265: (info->stream, "%s@-",
1266: reg_names[fetch_arg (buffer, place, 3, info) + 8]);
1267: break;
1268:
1269: case 'k':
1270: if (place == 'k')
1271: (*info->fprintf_func)
1272: (info->stream, "{%s}",
1273: reg_names[fetch_arg (buffer, place, 3, info)]);
1274: else if (place == 'C')
1275: {
1276: val = fetch_arg (buffer, place, 7, info);
1277: if (val > 63) /* This is a signed constant. */
1278: val -= 128;
1279: (*info->fprintf_func) (info->stream, "{#%d}", val);
1280: }
1281: else
1282: return -2;
1283: break;
1284:
1285: case '#':
1286: case '^':
1287: p1 = buffer + (*d == '#' ? 2 : 4);
1288: if (place == 's')
1289: val = fetch_arg (buffer, place, 4, info);
1290: else if (place == 'C')
1291: val = fetch_arg (buffer, place, 7, info);
1292: else if (place == '8')
1293: val = fetch_arg (buffer, place, 3, info);
1294: else if (place == '3')
1295: val = fetch_arg (buffer, place, 8, info);
1296: else if (place == 'b')
1297: val = NEXTBYTE (p1);
1298: else if (place == 'w' || place == 'W')
1299: val = NEXTWORD (p1);
1300: else if (place == 'l')
1301: val = NEXTLONG (p1);
1302: else
1303: return -2;
1304: (*info->fprintf_func) (info->stream, "#%d", val);
1305: break;
1306:
1307: case 'B':
1308: if (place == 'b')
1309: disp = NEXTBYTE (p);
1310: else if (place == 'B')
1311: disp = COERCE_SIGNED_CHAR (buffer[1]);
1312: else if (place == 'w' || place == 'W')
1313: disp = NEXTWORD (p);
1314: else if (place == 'l' || place == 'L' || place == 'C')
1315: disp = NEXTLONG (p);
1316: else if (place == 'g')
1317: {
1318: disp = NEXTBYTE (buffer);
1319: if (disp == 0)
1320: disp = NEXTWORD (p);
1321: else if (disp == -1)
1322: disp = NEXTLONG (p);
1323: }
1324: else if (place == 'c')
1325: {
1326: if (buffer[1] & 0x40) /* If bit six is one, long offset. */
1327: disp = NEXTLONG (p);
1328: else
1329: disp = NEXTWORD (p);
1330: }
1331: else
1332: return -2;
1333:
1334: (*info->print_address_func) (addr + disp, info);
1335: break;
1336:
1337: case 'd':
1338: val = NEXTWORD (p);
1339: (*info->fprintf_func)
1340: (info->stream, "%s@(%d)",
1341: reg_names[fetch_arg (buffer, place, 3, info) + 8], val);
1342: break;
1343:
1344: case 's':
1345: (*info->fprintf_func) (info->stream, "%s",
1346: fpcr_names[fetch_arg (buffer, place, 3, info)]);
1347: break;
1348:
1349: case 'e':
1350: val = fetch_arg(buffer, place, 2, info);
1351: (*info->fprintf_func) (info->stream, "%%acc%d", val);
1352: break;
1353:
1354: case 'g':
1355: val = fetch_arg(buffer, place, 1, info);
1356: (*info->fprintf_func) (info->stream, "%%accext%s", val==0 ? "01" : "23");
1357: break;
1358:
1359: case 'i':
1360: val = fetch_arg(buffer, place, 2, info);
1361: if (val == 1)
1362: (*info->fprintf_func) (info->stream, "<<");
1363: else if (val == 3)
1364: (*info->fprintf_func) (info->stream, ">>");
1365: else
1366: return -1;
1367: break;
1368:
1369: case 'I':
1370: /* Get coprocessor ID... */
1371: val = fetch_arg (buffer, 'd', 3, info);
1372:
1373: if (val != 1) /* Unusual coprocessor ID? */
1374: (*info->fprintf_func) (info->stream, "(cpid=%d) ", val);
1375: break;
1376:
1377: case '4':
1378: case '*':
1379: case '~':
1380: case '%':
1381: case ';':
1382: case '@':
1383: case '!':
1384: case '$':
1385: case '?':
1386: case '/':
1387: case '&':
1388: case '|':
1389: case '<':
1390: case '>':
1391: case 'm':
1392: case 'n':
1393: case 'o':
1394: case 'p':
1395: case 'q':
1396: case 'v':
1397: case 'b':
1398: case 'w':
1399: case 'y':
1400: case 'z':
1401: if (place == 'd')
1402: {
1403: val = fetch_arg (buffer, 'x', 6, info);
1404: val = ((val & 7) << 3) + ((val >> 3) & 7);
1405: }
1406: else
1407: val = fetch_arg (buffer, 's', 6, info);
1408:
1409: /* If the <ea> is invalid for *d, then reject this match. */
1410: if (!m68k_valid_ea (*d, val))
1411: return -1;
1412:
1413: /* Get register number assuming address register. */
1414: regno = (val & 7) + 8;
1415: regname = reg_names[regno];
1416: switch (val >> 3)
1417: {
1418: case 0:
1419: (*info->fprintf_func) (info->stream, "%s", reg_names[val]);
1420: break;
1421:
1422: case 1:
1423: (*info->fprintf_func) (info->stream, "%s", regname);
1424: break;
1425:
1426: case 2:
1427: (*info->fprintf_func) (info->stream, "%s@", regname);
1428: break;
1429:
1430: case 3:
1431: (*info->fprintf_func) (info->stream, "%s@+", regname);
1432: break;
1433:
1434: case 4:
1435: (*info->fprintf_func) (info->stream, "%s@-", regname);
1436: break;
1437:
1438: case 5:
1439: val = NEXTWORD (p);
1440: (*info->fprintf_func) (info->stream, "%s@(%d)", regname, val);
1441: break;
1442:
1443: case 6:
1444: p = print_indexed (regno, p, addr, info);
1445: break;
1446:
1447: case 7:
1448: switch (val & 7)
1449: {
1450: case 0:
1451: val = NEXTWORD (p);
1452: (*info->print_address_func) (val, info);
1453: break;
1454:
1455: case 1:
1456: uval = NEXTULONG (p);
1457: (*info->print_address_func) (uval, info);
1458: break;
1459:
1460: case 2:
1461: val = NEXTWORD (p);
1462: (*info->fprintf_func) (info->stream, "%%pc@(");
1463: (*info->print_address_func) (addr + val, info);
1464: (*info->fprintf_func) (info->stream, ")");
1465: break;
1466:
1467: case 3:
1468: p = print_indexed (-1, p, addr, info);
1469: break;
1470:
1471: case 4:
1472: flt_p = 1; /* Assume it's a float... */
1473: switch (place)
1474: {
1475: case 'b':
1476: val = NEXTBYTE (p);
1477: flt_p = 0;
1478: break;
1479:
1480: case 'w':
1481: val = NEXTWORD (p);
1482: flt_p = 0;
1483: break;
1484:
1485: case 'l':
1486: val = NEXTLONG (p);
1487: flt_p = 0;
1488: break;
1489:
1490: case 'f':
1491: NEXTSINGLE (flval, p);
1492: break;
1493:
1494: case 'F':
1495: NEXTDOUBLE (flval, p);
1496: break;
1497:
1498: case 'x':
1499: NEXTEXTEND (flval, p);
1500: break;
1501:
1502: case 'p':
1503: flval = NEXTPACKED (p);
1504: break;
1505:
1506: default:
1507: return -1;
1508: }
1509: if (flt_p) /* Print a float? */
1510: (*info->fprintf_func) (info->stream, "#%g", flval);
1511: else
1512: (*info->fprintf_func) (info->stream, "#%d", val);
1513: break;
1514:
1515: default:
1516: return -1;
1517: }
1518: }
1519:
1520: /* If place is '/', then this is the case of the mask bit for
1521: mac/emac loads. Now that the arg has been printed, grab the
1522: mask bit and if set, add a '&' to the arg. */
1523: if (place == '/')
1524: {
1525: val = fetch_arg (buffer, place, 1, info);
1526: if (val)
1527: info->fprintf_func (info->stream, "&");
1528: }
1529: break;
1530:
1531: case 'L':
1532: case 'l':
1533: if (place == 'w')
1534: {
1535: char doneany;
1536: p1 = buffer + 2;
1537: val = NEXTWORD (p1);
1538: /* Move the pointer ahead if this point is farther ahead
1539: than the last. */
1540: p = p1 > p ? p1 : p;
1541: if (val == 0)
1542: {
1543: (*info->fprintf_func) (info->stream, "#0");
1544: break;
1545: }
1546: if (*d == 'l')
1547: {
1548: int newval = 0;
1549:
1550: for (regno = 0; regno < 16; ++regno)
1551: if (val & (0x8000 >> regno))
1552: newval |= 1 << regno;
1553: val = newval;
1554: }
1555: val &= 0xffff;
1556: doneany = 0;
1557: for (regno = 0; regno < 16; ++regno)
1558: if (val & (1 << regno))
1559: {
1560: int first_regno;
1561:
1562: if (doneany)
1563: (*info->fprintf_func) (info->stream, "/");
1564: doneany = 1;
1565: (*info->fprintf_func) (info->stream, "%s", reg_names[regno]);
1566: first_regno = regno;
1567: while (val & (1 << (regno + 1)))
1568: ++regno;
1569: if (regno > first_regno)
1570: (*info->fprintf_func) (info->stream, "-%s",
1571: reg_names[regno]);
1572: }
1573: }
1574: else if (place == '3')
1575: {
1576: /* `fmovem' insn. */
1577: char doneany;
1578: val = fetch_arg (buffer, place, 8, info);
1579: if (val == 0)
1580: {
1581: (*info->fprintf_func) (info->stream, "#0");
1582: break;
1583: }
1584: if (*d == 'l')
1585: {
1586: int newval = 0;
1587:
1588: for (regno = 0; regno < 8; ++regno)
1589: if (val & (0x80 >> regno))
1590: newval |= 1 << regno;
1591: val = newval;
1592: }
1593: val &= 0xff;
1594: doneany = 0;
1595: for (regno = 0; regno < 8; ++regno)
1596: if (val & (1 << regno))
1597: {
1598: int first_regno;
1599: if (doneany)
1600: (*info->fprintf_func) (info->stream, "/");
1601: doneany = 1;
1602: (*info->fprintf_func) (info->stream, "%%fp%d", regno);
1603: first_regno = regno;
1604: while (val & (1 << (regno + 1)))
1605: ++regno;
1606: if (regno > first_regno)
1607: (*info->fprintf_func) (info->stream, "-%%fp%d", regno);
1608: }
1609: }
1610: else if (place == '8')
1611: {
1612: /* fmoveml for FP status registers. */
1613: (*info->fprintf_func) (info->stream, "%s",
1614: fpcr_names[fetch_arg (buffer, place, 3,
1615: info)]);
1616: }
1617: else
1618: return -2;
1619: break;
1620:
1621: case 'X':
1622: place = '8';
1623: case 'Y':
1624: case 'Z':
1625: case 'W':
1626: case '0':
1627: case '1':
1628: case '2':
1629: case '3':
1630: {
1631: int val = fetch_arg (buffer, place, 5, info);
1.1.1.3 root 1632: const char *name = 0;
1.1 root 1633:
1634: switch (val)
1635: {
1636: case 2: name = "%tt0"; break;
1637: case 3: name = "%tt1"; break;
1638: case 0x10: name = "%tc"; break;
1639: case 0x11: name = "%drp"; break;
1640: case 0x12: name = "%srp"; break;
1641: case 0x13: name = "%crp"; break;
1642: case 0x14: name = "%cal"; break;
1643: case 0x15: name = "%val"; break;
1644: case 0x16: name = "%scc"; break;
1645: case 0x17: name = "%ac"; break;
1646: case 0x18: name = "%psr"; break;
1647: case 0x19: name = "%pcsr"; break;
1648: case 0x1c:
1649: case 0x1d:
1650: {
1651: int break_reg = ((buffer[3] >> 2) & 7);
1652:
1653: (*info->fprintf_func)
1654: (info->stream, val == 0x1c ? "%%bad%d" : "%%bac%d",
1655: break_reg);
1656: }
1657: break;
1658: default:
1659: (*info->fprintf_func) (info->stream, "<mmu register %d>", val);
1660: }
1661: if (name)
1662: (*info->fprintf_func) (info->stream, "%s", name);
1663: }
1664: break;
1665:
1666: case 'f':
1667: {
1668: int fc = fetch_arg (buffer, place, 5, info);
1669:
1670: if (fc == 1)
1671: (*info->fprintf_func) (info->stream, "%%dfc");
1672: else if (fc == 0)
1673: (*info->fprintf_func) (info->stream, "%%sfc");
1674: else
1675: /* xgettext:c-format */
1676: (*info->fprintf_func) (info->stream, _("<function code %d>"), fc);
1677: }
1678: break;
1679:
1680: case 'V':
1681: (*info->fprintf_func) (info->stream, "%%val");
1682: break;
1683:
1684: case 't':
1685: {
1686: int level = fetch_arg (buffer, place, 3, info);
1687:
1688: (*info->fprintf_func) (info->stream, "%d", level);
1689: }
1690: break;
1691:
1692: case 'u':
1693: {
1694: short is_upper = 0;
1695: int reg = fetch_arg (buffer, place, 5, info);
1696:
1697: if (reg & 0x10)
1698: {
1699: is_upper = 1;
1700: reg &= 0xf;
1701: }
1702: (*info->fprintf_func) (info->stream, "%s%s",
1703: reg_half_names[reg],
1704: is_upper ? "u" : "l");
1705: }
1706: break;
1707:
1708: default:
1709: return -2;
1710: }
1711:
1712: return p - p0;
1713: }
1714:
1715: /* Try to match the current instruction to best and if so, return the
1716: number of bytes consumed from the instruction stream, else zero. */
1717:
1718: static int
1719: match_insn_m68k (bfd_vma memaddr,
1720: disassemble_info * info,
1721: const struct m68k_opcode * best,
1722: struct private * priv)
1723: {
1724: unsigned char *save_p;
1725: unsigned char *p;
1726: const char *d;
1727:
1728: bfd_byte *buffer = priv->the_buffer;
1729: fprintf_ftype save_printer = info->fprintf_func;
1730: void (* save_print_address) (bfd_vma, struct disassemble_info *)
1731: = info->print_address_func;
1732:
1733: /* Point at first word of argument data,
1734: and at descriptor for first argument. */
1735: p = buffer + 2;
1736:
1737: /* Figure out how long the fixed-size portion of the instruction is.
1738: The only place this is stored in the opcode table is
1739: in the arguments--look for arguments which specify fields in the 2nd
1740: or 3rd words of the instruction. */
1741: for (d = best->args; *d; d += 2)
1742: {
1743: /* I don't think it is necessary to be checking d[0] here;
1744: I suspect all this could be moved to the case statement below. */
1745: if (d[0] == '#')
1746: {
1747: if (d[1] == 'l' && p - buffer < 6)
1748: p = buffer + 6;
1749: else if (p - buffer < 4 && d[1] != 'C' && d[1] != '8')
1750: p = buffer + 4;
1751: }
1752:
1753: if ((d[0] == 'L' || d[0] == 'l') && d[1] == 'w' && p - buffer < 4)
1754: p = buffer + 4;
1755:
1756: switch (d[1])
1757: {
1758: case '1':
1759: case '2':
1760: case '3':
1761: case '7':
1762: case '8':
1763: case '9':
1764: case 'i':
1765: if (p - buffer < 4)
1766: p = buffer + 4;
1767: break;
1768: case '4':
1769: case '5':
1770: case '6':
1771: if (p - buffer < 6)
1772: p = buffer + 6;
1773: break;
1774: default:
1775: break;
1776: }
1777: }
1778:
1779: /* pflusha is an exceptions. It takes no arguments but is two words
1780: long. Recognize it by looking at the lower 16 bits of the mask. */
1781: if (p - buffer < 4 && (best->match & 0xFFFF) != 0)
1782: p = buffer + 4;
1783:
1784: /* lpstop is another exception. It takes a one word argument but is
1785: three words long. */
1786: if (p - buffer < 6
1787: && (best->match & 0xffff) == 0xffff
1788: && best->args[0] == '#'
1789: && best->args[1] == 'w')
1790: {
1791: /* Copy the one word argument into the usual location for a one
1792: word argument, to simplify printing it. We can get away with
1793: this because we know exactly what the second word is, and we
1794: aren't going to print anything based on it. */
1795: p = buffer + 6;
1796: FETCH_DATA (info, p);
1797: buffer[2] = buffer[4];
1798: buffer[3] = buffer[5];
1799: }
1800:
1801: FETCH_DATA (info, p);
1802:
1803: d = best->args;
1804:
1805: save_p = p;
1806: info->print_address_func = dummy_print_address;
1807: info->fprintf_func = (fprintf_ftype) dummy_printer;
1808:
1809: /* We scan the operands twice. The first time we don't print anything,
1810: but look for errors. */
1811: for (; *d; d += 2)
1812: {
1813: int eaten = print_insn_arg (d, buffer, p, memaddr + (p - buffer), info);
1814:
1815: if (eaten >= 0)
1816: p += eaten;
1817: else if (eaten == -1)
1818: {
1819: info->fprintf_func = save_printer;
1820: info->print_address_func = save_print_address;
1821: return 0;
1822: }
1823: else
1824: {
1825: info->fprintf_func (info->stream,
1826: /* xgettext:c-format */
1827: _("<internal error in opcode table: %s %s>\n"),
1828: best->name, best->args);
1829: info->fprintf_func = save_printer;
1830: info->print_address_func = save_print_address;
1831: return 2;
1832: }
1833: }
1834:
1835: p = save_p;
1836: info->fprintf_func = save_printer;
1837: info->print_address_func = save_print_address;
1838:
1839: d = best->args;
1840:
1841: info->fprintf_func (info->stream, "%s", best->name);
1842:
1843: if (*d)
1844: info->fprintf_func (info->stream, " ");
1845:
1846: while (*d)
1847: {
1848: p += print_insn_arg (d, buffer, p, memaddr + (p - buffer), info);
1849: d += 2;
1850:
1851: if (*d && *(d - 2) != 'I' && *d != 'k')
1852: info->fprintf_func (info->stream, ",");
1853: }
1854:
1855: return p - buffer;
1856: }
1857:
1858: /* Print the m68k instruction at address MEMADDR in debugged memory,
1859: on INFO->STREAM. Returns length of the instruction, in bytes. */
1860:
1861: int
1862: print_insn_m68k (bfd_vma memaddr, disassemble_info *info)
1863: {
1864: int i;
1865: const char *d;
1866: unsigned int arch_mask;
1867: struct private priv;
1868: bfd_byte *buffer = priv.the_buffer;
1869: int major_opcode;
1870: static int numopcodes[16];
1871: static const struct m68k_opcode **opcodes[16];
1872: int val;
1873:
1874: if (!opcodes[0])
1875: {
1876: /* Speed up the matching by sorting the opcode
1877: table on the upper four bits of the opcode. */
1878: const struct m68k_opcode **opc_pointer[16];
1879:
1880: /* First count how many opcodes are in each of the sixteen buckets. */
1881: for (i = 0; i < m68k_numopcodes; i++)
1882: numopcodes[(m68k_opcodes[i].opcode >> 28) & 15]++;
1883:
1884: /* Then create a sorted table of pointers
1885: that point into the unsorted table. */
1886: opc_pointer[0] = malloc (sizeof (struct m68k_opcode *)
1887: * m68k_numopcodes);
1888: opcodes[0] = opc_pointer[0];
1889:
1890: for (i = 1; i < 16; i++)
1891: {
1892: opc_pointer[i] = opc_pointer[i - 1] + numopcodes[i - 1];
1893: opcodes[i] = opc_pointer[i];
1894: }
1895:
1896: for (i = 0; i < m68k_numopcodes; i++)
1897: *opc_pointer[(m68k_opcodes[i].opcode >> 28) & 15]++ = &m68k_opcodes[i];
1898: }
1899:
1900: info->private_data = (PTR) &priv;
1901: /* Tell objdump to use two bytes per chunk
1902: and six bytes per line for displaying raw data. */
1903: info->bytes_per_chunk = 2;
1904: info->bytes_per_line = 6;
1905: info->display_endian = BFD_ENDIAN_BIG;
1906: priv.max_fetched = priv.the_buffer;
1907: priv.insn_start = memaddr;
1908:
1909: if (setjmp (priv.bailout) != 0)
1910: /* Error return. */
1911: return -1;
1912:
1913: switch (info->mach)
1914: {
1915: default:
1916: case 0:
1917: arch_mask = (unsigned int) -1;
1918: break;
1919: case bfd_mach_m68000:
1920: arch_mask = m68000|m68881|m68851;
1921: break;
1922: case bfd_mach_m68008:
1923: arch_mask = m68008|m68881|m68851;
1924: break;
1925: case bfd_mach_m68010:
1926: arch_mask = m68010|m68881|m68851;
1927: break;
1928: case bfd_mach_m68020:
1929: arch_mask = m68020|m68881|m68851;
1930: break;
1931: case bfd_mach_m68030:
1932: arch_mask = m68030|m68881|m68851;
1933: break;
1934: case bfd_mach_m68040:
1935: arch_mask = m68040|m68881|m68851;
1936: break;
1937: case bfd_mach_m68060:
1938: arch_mask = m68060|m68881|m68851;
1939: break;
1940: case bfd_mach_mcf5200:
1941: arch_mask = mcfisa_a;
1942: break;
1943: case bfd_mach_mcf521x:
1944: case bfd_mach_mcf528x:
1945: arch_mask = mcfisa_a|mcfhwdiv|mcfisa_aa|mcfusp|mcfemac;
1946: break;
1947: case bfd_mach_mcf5206e:
1948: arch_mask = mcfisa_a|mcfhwdiv|mcfmac;
1949: break;
1950: case bfd_mach_mcf5249:
1951: arch_mask = mcfisa_a|mcfhwdiv|mcfemac;
1952: break;
1953: case bfd_mach_mcf5307:
1954: arch_mask = mcfisa_a|mcfhwdiv|mcfmac;
1955: break;
1956: case bfd_mach_mcf5407:
1957: arch_mask = mcfisa_a|mcfhwdiv|mcfisa_b|mcfmac;
1958: break;
1959: case bfd_mach_mcf547x:
1960: case bfd_mach_mcf548x:
1961: case bfd_mach_mcfv4e:
1962: arch_mask = mcfisa_a|mcfhwdiv|mcfisa_b|mcfusp|cfloat|mcfemac;
1963: break;
1964: }
1965:
1966: FETCH_DATA (info, buffer + 2);
1967: major_opcode = (buffer[0] >> 4) & 15;
1968:
1969: for (i = 0; i < numopcodes[major_opcode]; i++)
1970: {
1971: const struct m68k_opcode *opc = opcodes[major_opcode][i];
1972: unsigned long opcode = opc->opcode;
1973: unsigned long match = opc->match;
1974:
1975: if (((0xff & buffer[0] & (match >> 24)) == (0xff & (opcode >> 24)))
1976: && ((0xff & buffer[1] & (match >> 16)) == (0xff & (opcode >> 16)))
1977: /* Only fetch the next two bytes if we need to. */
1978: && (((0xffff & match) == 0)
1979: ||
1980: (FETCH_DATA (info, buffer + 4)
1981: && ((0xff & buffer[2] & (match >> 8)) == (0xff & (opcode >> 8)))
1982: && ((0xff & buffer[3] & match) == (0xff & opcode)))
1983: )
1984: && (opc->arch & arch_mask) != 0)
1985: {
1986: /* Don't use for printout the variants of divul and divsl
1987: that have the same register number in two places.
1988: The more general variants will match instead. */
1989: for (d = opc->args; *d; d += 2)
1990: if (d[1] == 'D')
1991: break;
1992:
1993: /* Don't use for printout the variants of most floating
1994: point coprocessor instructions which use the same
1995: register number in two places, as above. */
1996: if (*d == '\0')
1997: for (d = opc->args; *d; d += 2)
1998: if (d[1] == 't')
1999: break;
2000:
2001: /* Don't match fmovel with more than one register;
2002: wait for fmoveml. */
2003: if (*d == '\0')
2004: {
2005: for (d = opc->args; *d; d += 2)
2006: {
2007: if (d[0] == 's' && d[1] == '8')
2008: {
2009: val = fetch_arg (buffer, d[1], 3, info);
2010: if ((val & (val - 1)) != 0)
2011: break;
2012: }
2013: }
2014: }
2015:
2016: if (*d == '\0')
2017: if ((val = match_insn_m68k (memaddr, info, opc, & priv)))
2018: return val;
2019: }
2020: }
2021:
2022: /* Handle undefined instructions. */
2023: info->fprintf_func (info->stream, "0%o", (buffer[0] << 8) + buffer[1]);
2024: return 2;
2025: }
2026: /* **** End of m68k-dis.c */
2027: /* **** m68k-opc.h from sourceware.org CVS 2005-08-14. */
2028: /* Opcode table for m680[012346]0/m6888[12]/m68851/mcf5200.
2029: Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
2030: 2000, 2001, 2003, 2004, 2005
2031: Free Software Foundation, Inc.
2032:
2033: This file is part of GDB, GAS, and the GNU binutils.
2034:
2035: GDB, GAS, and the GNU binutils are free software; you can redistribute
2036: them and/or modify them under the terms of the GNU General Public
2037: License as published by the Free Software Foundation; either version
2038: 1, or (at your option) any later version.
2039:
2040: GDB, GAS, and the GNU binutils are distributed in the hope that they
2041: will be useful, but WITHOUT ANY WARRANTY; without even the implied
2042: warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See
2043: the GNU General Public License for more details.
2044:
2045: You should have received a copy of the GNU General Public License
1.1.1.4 ! root 2046: along with this file; see the file COPYING. If not,
! 2047: see <http://www.gnu.org/licenses/>. */
1.1 root 2048:
2049: #define one(x) ((unsigned int) (x) << 16)
2050: #define two(x, y) (((unsigned int) (x) << 16) + (y))
2051:
2052: /* The assembler requires that all instances of the same mnemonic must
2053: be consecutive. If they aren't, the assembler will bomb at
2054: runtime. */
2055:
2056: const struct m68k_opcode m68k_opcodes[] =
2057: {
2058: {"abcd", 2, one(0140400), one(0170770), "DsDd", m68000up },
2059: {"abcd", 2, one(0140410), one(0170770), "-s-d", m68000up },
2060:
2061: {"addaw", 2, one(0150300), one(0170700), "*wAd", m68000up },
2062: {"addal", 2, one(0150700), one(0170700), "*lAd", m68000up | mcfisa_a },
2063:
2064: {"addib", 4, one(0003000), one(0177700), "#b$s", m68000up },
2065: {"addiw", 4, one(0003100), one(0177700), "#w$s", m68000up },
2066: {"addil", 6, one(0003200), one(0177700), "#l$s", m68000up },
2067: {"addil", 6, one(0003200), one(0177700), "#lDs", mcfisa_a },
2068:
2069: {"addqb", 2, one(0050000), one(0170700), "Qd$b", m68000up },
2070: {"addqw", 2, one(0050100), one(0170700), "Qd%w", m68000up },
2071: {"addql", 2, one(0050200), one(0170700), "Qd%l", m68000up | mcfisa_a },
2072:
2073: /* The add opcode can generate the adda, addi, and addq instructions. */
2074: {"addb", 2, one(0050000), one(0170700), "Qd$b", m68000up },
2075: {"addb", 4, one(0003000), one(0177700), "#b$s", m68000up },
2076: {"addb", 2, one(0150000), one(0170700), ";bDd", m68000up },
2077: {"addb", 2, one(0150400), one(0170700), "Dd~b", m68000up },
2078: {"addw", 2, one(0050100), one(0170700), "Qd%w", m68000up },
2079: {"addw", 2, one(0150300), one(0170700), "*wAd", m68000up },
2080: {"addw", 4, one(0003100), one(0177700), "#w$s", m68000up },
2081: {"addw", 2, one(0150100), one(0170700), "*wDd", m68000up },
2082: {"addw", 2, one(0150500), one(0170700), "Dd~w", m68000up },
2083: {"addl", 2, one(0050200), one(0170700), "Qd%l", m68000up | mcfisa_a },
2084: {"addl", 6, one(0003200), one(0177700), "#l$s", m68000up },
2085: {"addl", 6, one(0003200), one(0177700), "#lDs", mcfisa_a },
2086: {"addl", 2, one(0150700), one(0170700), "*lAd", m68000up | mcfisa_a },
2087: {"addl", 2, one(0150200), one(0170700), "*lDd", m68000up | mcfisa_a },
2088: {"addl", 2, one(0150600), one(0170700), "Dd~l", m68000up | mcfisa_a },
2089:
2090: {"addxb", 2, one(0150400), one(0170770), "DsDd", m68000up },
2091: {"addxb", 2, one(0150410), one(0170770), "-s-d", m68000up },
2092: {"addxw", 2, one(0150500), one(0170770), "DsDd", m68000up },
2093: {"addxw", 2, one(0150510), one(0170770), "-s-d", m68000up },
2094: {"addxl", 2, one(0150600), one(0170770), "DsDd", m68000up | mcfisa_a },
2095: {"addxl", 2, one(0150610), one(0170770), "-s-d", m68000up },
2096:
2097: {"andib", 4, one(0001000), one(0177700), "#b$s", m68000up },
2098: {"andib", 4, one(0001074), one(0177777), "#bCs", m68000up },
2099: {"andiw", 4, one(0001100), one(0177700), "#w$s", m68000up },
2100: {"andiw", 4, one(0001174), one(0177777), "#wSs", m68000up },
2101: {"andil", 6, one(0001200), one(0177700), "#l$s", m68000up },
2102: {"andil", 6, one(0001200), one(0177700), "#lDs", mcfisa_a },
2103: {"andi", 4, one(0001100), one(0177700), "#w$s", m68000up },
2104: {"andi", 4, one(0001074), one(0177777), "#bCs", m68000up },
2105: {"andi", 4, one(0001174), one(0177777), "#wSs", m68000up },
2106:
2107: /* The and opcode can generate the andi instruction. */
2108: {"andb", 4, one(0001000), one(0177700), "#b$s", m68000up },
2109: {"andb", 4, one(0001074), one(0177777), "#bCs", m68000up },
2110: {"andb", 2, one(0140000), one(0170700), ";bDd", m68000up },
2111: {"andb", 2, one(0140400), one(0170700), "Dd~b", m68000up },
2112: {"andw", 4, one(0001100), one(0177700), "#w$s", m68000up },
2113: {"andw", 4, one(0001174), one(0177777), "#wSs", m68000up },
2114: {"andw", 2, one(0140100), one(0170700), ";wDd", m68000up },
2115: {"andw", 2, one(0140500), one(0170700), "Dd~w", m68000up },
2116: {"andl", 6, one(0001200), one(0177700), "#l$s", m68000up },
2117: {"andl", 6, one(0001200), one(0177700), "#lDs", mcfisa_a },
2118: {"andl", 2, one(0140200), one(0170700), ";lDd", m68000up | mcfisa_a },
2119: {"andl", 2, one(0140600), one(0170700), "Dd~l", m68000up | mcfisa_a },
2120: {"and", 4, one(0001100), one(0177700), "#w$w", m68000up },
2121: {"and", 4, one(0001074), one(0177777), "#bCs", m68000up },
2122: {"and", 4, one(0001174), one(0177777), "#wSs", m68000up },
2123: {"and", 2, one(0140100), one(0170700), ";wDd", m68000up },
2124: {"and", 2, one(0140500), one(0170700), "Dd~w", m68000up },
2125:
2126: {"aslb", 2, one(0160400), one(0170770), "QdDs", m68000up },
2127: {"aslb", 2, one(0160440), one(0170770), "DdDs", m68000up },
2128: {"aslw", 2, one(0160500), one(0170770), "QdDs", m68000up },
2129: {"aslw", 2, one(0160540), one(0170770), "DdDs", m68000up },
2130: {"aslw", 2, one(0160700), one(0177700), "~s", m68000up },
2131: {"asll", 2, one(0160600), one(0170770), "QdDs", m68000up | mcfisa_a },
2132: {"asll", 2, one(0160640), one(0170770), "DdDs", m68000up | mcfisa_a },
2133:
2134: {"asrb", 2, one(0160000), one(0170770), "QdDs", m68000up },
2135: {"asrb", 2, one(0160040), one(0170770), "DdDs", m68000up },
2136: {"asrw", 2, one(0160100), one(0170770), "QdDs", m68000up },
2137: {"asrw", 2, one(0160140), one(0170770), "DdDs", m68000up },
2138: {"asrw", 2, one(0160300), one(0177700), "~s", m68000up },
2139: {"asrl", 2, one(0160200), one(0170770), "QdDs", m68000up | mcfisa_a },
2140: {"asrl", 2, one(0160240), one(0170770), "DdDs", m68000up | mcfisa_a },
2141:
2142: {"bhiw", 2, one(0061000), one(0177777), "BW", m68000up | mcfisa_a },
2143: {"blsw", 2, one(0061400), one(0177777), "BW", m68000up | mcfisa_a },
2144: {"bccw", 2, one(0062000), one(0177777), "BW", m68000up | mcfisa_a },
2145: {"bcsw", 2, one(0062400), one(0177777), "BW", m68000up | mcfisa_a },
2146: {"bnew", 2, one(0063000), one(0177777), "BW", m68000up | mcfisa_a },
2147: {"beqw", 2, one(0063400), one(0177777), "BW", m68000up | mcfisa_a },
2148: {"bvcw", 2, one(0064000), one(0177777), "BW", m68000up | mcfisa_a },
2149: {"bvsw", 2, one(0064400), one(0177777), "BW", m68000up | mcfisa_a },
2150: {"bplw", 2, one(0065000), one(0177777), "BW", m68000up | mcfisa_a },
2151: {"bmiw", 2, one(0065400), one(0177777), "BW", m68000up | mcfisa_a },
2152: {"bgew", 2, one(0066000), one(0177777), "BW", m68000up | mcfisa_a },
2153: {"bltw", 2, one(0066400), one(0177777), "BW", m68000up | mcfisa_a },
2154: {"bgtw", 2, one(0067000), one(0177777), "BW", m68000up | mcfisa_a },
2155: {"blew", 2, one(0067400), one(0177777), "BW", m68000up | mcfisa_a },
2156:
2157: {"bhil", 2, one(0061377), one(0177777), "BL", m68020up | cpu32 | mcfisa_b},
2158: {"blsl", 2, one(0061777), one(0177777), "BL", m68020up | cpu32 | mcfisa_b},
2159: {"bccl", 2, one(0062377), one(0177777), "BL", m68020up | cpu32 | mcfisa_b},
2160: {"bcsl", 2, one(0062777), one(0177777), "BL", m68020up | cpu32 | mcfisa_b},
2161: {"bnel", 2, one(0063377), one(0177777), "BL", m68020up | cpu32 | mcfisa_b},
2162: {"beql", 2, one(0063777), one(0177777), "BL", m68020up | cpu32 | mcfisa_b},
2163: {"bvcl", 2, one(0064377), one(0177777), "BL", m68020up | cpu32 | mcfisa_b},
2164: {"bvsl", 2, one(0064777), one(0177777), "BL", m68020up | cpu32 | mcfisa_b},
2165: {"bpll", 2, one(0065377), one(0177777), "BL", m68020up | cpu32 | mcfisa_b},
2166: {"bmil", 2, one(0065777), one(0177777), "BL", m68020up | cpu32 | mcfisa_b},
2167: {"bgel", 2, one(0066377), one(0177777), "BL", m68020up | cpu32 | mcfisa_b},
2168: {"bltl", 2, one(0066777), one(0177777), "BL", m68020up | cpu32 | mcfisa_b},
2169: {"bgtl", 2, one(0067377), one(0177777), "BL", m68020up | cpu32 | mcfisa_b},
2170: {"blel", 2, one(0067777), one(0177777), "BL", m68020up | cpu32 | mcfisa_b},
2171:
2172: {"bhis", 2, one(0061000), one(0177400), "BB", m68000up | mcfisa_a },
2173: {"blss", 2, one(0061400), one(0177400), "BB", m68000up | mcfisa_a },
2174: {"bccs", 2, one(0062000), one(0177400), "BB", m68000up | mcfisa_a },
2175: {"bcss", 2, one(0062400), one(0177400), "BB", m68000up | mcfisa_a },
2176: {"bnes", 2, one(0063000), one(0177400), "BB", m68000up | mcfisa_a },
2177: {"beqs", 2, one(0063400), one(0177400), "BB", m68000up | mcfisa_a },
2178: {"bvcs", 2, one(0064000), one(0177400), "BB", m68000up | mcfisa_a },
2179: {"bvss", 2, one(0064400), one(0177400), "BB", m68000up | mcfisa_a },
2180: {"bpls", 2, one(0065000), one(0177400), "BB", m68000up | mcfisa_a },
2181: {"bmis", 2, one(0065400), one(0177400), "BB", m68000up | mcfisa_a },
2182: {"bges", 2, one(0066000), one(0177400), "BB", m68000up | mcfisa_a },
2183: {"blts", 2, one(0066400), one(0177400), "BB", m68000up | mcfisa_a },
2184: {"bgts", 2, one(0067000), one(0177400), "BB", m68000up | mcfisa_a },
2185: {"bles", 2, one(0067400), one(0177400), "BB", m68000up | mcfisa_a },
2186:
2187: {"jhi", 2, one(0061000), one(0177400), "Bg", m68000up | mcfisa_a },
2188: {"jls", 2, one(0061400), one(0177400), "Bg", m68000up | mcfisa_a },
2189: {"jcc", 2, one(0062000), one(0177400), "Bg", m68000up | mcfisa_a },
2190: {"jcs", 2, one(0062400), one(0177400), "Bg", m68000up | mcfisa_a },
2191: {"jne", 2, one(0063000), one(0177400), "Bg", m68000up | mcfisa_a },
2192: {"jeq", 2, one(0063400), one(0177400), "Bg", m68000up | mcfisa_a },
2193: {"jvc", 2, one(0064000), one(0177400), "Bg", m68000up | mcfisa_a },
2194: {"jvs", 2, one(0064400), one(0177400), "Bg", m68000up | mcfisa_a },
2195: {"jpl", 2, one(0065000), one(0177400), "Bg", m68000up | mcfisa_a },
2196: {"jmi", 2, one(0065400), one(0177400), "Bg", m68000up | mcfisa_a },
2197: {"jge", 2, one(0066000), one(0177400), "Bg", m68000up | mcfisa_a },
2198: {"jlt", 2, one(0066400), one(0177400), "Bg", m68000up | mcfisa_a },
2199: {"jgt", 2, one(0067000), one(0177400), "Bg", m68000up | mcfisa_a },
2200: {"jle", 2, one(0067400), one(0177400), "Bg", m68000up | mcfisa_a },
2201:
2202: {"bchg", 2, one(0000500), one(0170700), "Dd$s", m68000up | mcfisa_a },
2203: {"bchg", 4, one(0004100), one(0177700), "#b$s", m68000up },
2204: {"bchg", 4, one(0004100), one(0177700), "#bqs", mcfisa_a },
2205:
2206: {"bclr", 2, one(0000600), one(0170700), "Dd$s", m68000up | mcfisa_a },
2207: {"bclr", 4, one(0004200), one(0177700), "#b$s", m68000up },
2208: {"bclr", 4, one(0004200), one(0177700), "#bqs", mcfisa_a },
2209:
2210: {"bfchg", 4, two(0165300, 0), two(0177700, 0170000), "?sO2O3", m68020up },
2211: {"bfclr", 4, two(0166300, 0), two(0177700, 0170000), "?sO2O3", m68020up },
2212: {"bfexts", 4, two(0165700, 0), two(0177700, 0100000), "/sO2O3D1", m68020up },
2213: {"bfextu", 4, two(0164700, 0), two(0177700, 0100000), "/sO2O3D1", m68020up },
2214: {"bfffo", 4, two(0166700, 0), two(0177700, 0100000), "/sO2O3D1", m68020up },
2215: {"bfins", 4, two(0167700, 0), two(0177700, 0100000), "D1?sO2O3", m68020up },
2216: {"bfset", 4, two(0167300, 0), two(0177700, 0170000), "?sO2O3", m68020up },
2217: {"bftst", 4, two(0164300, 0), two(0177700, 0170000), "/sO2O3", m68020up },
2218:
2219: {"bgnd", 2, one(0045372), one(0177777), "", cpu32 },
2220:
2221: {"bitrev", 2, one(0000300), one(0177770), "Ds", mcfisa_aa},
2222:
2223: {"bkpt", 2, one(0044110), one(0177770), "ts", m68010up },
2224:
2225: {"braw", 2, one(0060000), one(0177777), "BW", m68000up | mcfisa_a },
2226: {"bral", 2, one(0060377), one(0177777), "BL", m68020up | cpu32 | mcfisa_b},
2227: {"bras", 2, one(0060000), one(0177400), "BB", m68000up | mcfisa_a },
2228:
2229: {"bset", 2, one(0000700), one(0170700), "Dd$s", m68000up | mcfisa_a },
2230: {"bset", 2, one(0000700), one(0170700), "Ddvs", mcfisa_a },
2231: {"bset", 4, one(0004300), one(0177700), "#b$s", m68000up },
2232: {"bset", 4, one(0004300), one(0177700), "#bqs", mcfisa_a },
2233:
2234: {"bsrw", 2, one(0060400), one(0177777), "BW", m68000up | mcfisa_a },
2235: {"bsrl", 2, one(0060777), one(0177777), "BL", m68020up | cpu32 | mcfisa_b},
2236: {"bsrs", 2, one(0060400), one(0177400), "BB", m68000up | mcfisa_a },
2237:
2238: {"btst", 2, one(0000400), one(0170700), "Dd;b", m68000up | mcfisa_a },
2239: {"btst", 4, one(0004000), one(0177700), "#b@s", m68000up },
2240: {"btst", 4, one(0004000), one(0177700), "#bqs", mcfisa_a },
2241:
2242: {"byterev", 2, one(0001300), one(0177770), "Ds", mcfisa_aa},
2243:
2244: {"callm", 4, one(0003300), one(0177700), "#b!s", m68020 },
2245:
2246: {"cas2w", 6, two(0006374,0), two(0177777,0007070), "D3D6D2D5r1r4", m68020up },
2247: {"cas2w", 6, two(0006374,0), two(0177777,0007070), "D3D6D2D5R1R4", m68020up },
2248: {"cas2l", 6, two(0007374,0), two(0177777,0007070), "D3D6D2D5r1r4", m68020up },
2249: {"cas2l", 6, two(0007374,0), two(0177777,0007070), "D3D6D2D5R1R4", m68020up },
2250:
2251: {"casb", 4, two(0005300, 0), two(0177700, 0177070), "D3D2~s", m68020up },
2252: {"casw", 4, two(0006300, 0), two(0177700, 0177070), "D3D2~s", m68020up },
2253: {"casl", 4, two(0007300, 0), two(0177700, 0177070), "D3D2~s", m68020up },
2254:
2255: {"chk2b", 4, two(0000300,0004000), two(0177700,07777), "!sR1", m68020up | cpu32 },
2256: {"chk2w", 4, two(0001300,0004000), two(0177700,07777), "!sR1", m68020up | cpu32 },
2257: {"chk2l", 4, two(0002300,0004000), two(0177700,07777), "!sR1", m68020up | cpu32 },
2258:
2259: {"chkl", 2, one(0040400), one(0170700), ";lDd", m68000up },
2260: {"chkw", 2, one(0040600), one(0170700), ";wDd", m68000up },
2261:
2262: #define SCOPE_LINE (0x1 << 3)
2263: #define SCOPE_PAGE (0x2 << 3)
2264: #define SCOPE_ALL (0x3 << 3)
2265:
2266: {"cinva", 2, one(0xf400|SCOPE_ALL), one(0xff38), "ce", m68040up },
2267: {"cinvl", 2, one(0xf400|SCOPE_LINE), one(0xff38), "ceas", m68040up },
2268: {"cinvp", 2, one(0xf400|SCOPE_PAGE), one(0xff38), "ceas", m68040up },
2269:
2270: {"cpusha", 2, one(0xf420|SCOPE_ALL), one(0xff38), "ce", m68040up },
2271: {"cpushl", 2, one(0xf420|SCOPE_LINE), one(0xff38), "ceas", m68040up | mcfisa_a },
2272: {"cpushp", 2, one(0xf420|SCOPE_PAGE), one(0xff38), "ceas", m68040up },
2273:
2274: #undef SCOPE_LINE
2275: #undef SCOPE_PAGE
2276: #undef SCOPE_ALL
2277:
2278: {"clrb", 2, one(0041000), one(0177700), "$s", m68000up | mcfisa_a },
2279: {"clrw", 2, one(0041100), one(0177700), "$s", m68000up | mcfisa_a },
2280: {"clrl", 2, one(0041200), one(0177700), "$s", m68000up | mcfisa_a },
2281:
2282: {"cmp2b", 4, two(0000300,0), two(0177700,07777), "!sR1", m68020up | cpu32 },
2283: {"cmp2w", 4, two(0001300,0), two(0177700,07777), "!sR1", m68020up | cpu32 },
2284: {"cmp2l", 4, two(0002300,0), two(0177700,07777), "!sR1", m68020up | cpu32 },
2285:
2286: {"cmpaw", 2, one(0130300), one(0170700), "*wAd", m68000up },
2287: {"cmpal", 2, one(0130700), one(0170700), "*lAd", m68000up | mcfisa_a },
2288:
2289: {"cmpib", 4, one(0006000), one(0177700), "#b@s", m68000up },
2290: {"cmpib", 4, one(0006000), one(0177700), "#bDs", mcfisa_b },
2291: {"cmpiw", 4, one(0006100), one(0177700), "#w@s", m68000up },
2292: {"cmpiw", 4, one(0006100), one(0177700), "#wDs", mcfisa_b },
2293: {"cmpil", 6, one(0006200), one(0177700), "#l@s", m68000up },
2294: {"cmpil", 6, one(0006200), one(0177700), "#lDs", mcfisa_a },
2295:
2296: {"cmpmb", 2, one(0130410), one(0170770), "+s+d", m68000up },
2297: {"cmpmw", 2, one(0130510), one(0170770), "+s+d", m68000up },
2298: {"cmpml", 2, one(0130610), one(0170770), "+s+d", m68000up },
2299:
2300: /* The cmp opcode can generate the cmpa, cmpm, and cmpi instructions. */
2301: {"cmpb", 4, one(0006000), one(0177700), "#b@s", m68000up },
2302: {"cmpb", 4, one(0006000), one(0177700), "#bDs", mcfisa_b },
2303: {"cmpb", 2, one(0130410), one(0170770), "+s+d", m68000up },
2304: {"cmpb", 2, one(0130000), one(0170700), ";bDd", m68000up },
2305: {"cmpb", 2, one(0130000), one(0170700), "*bDd", mcfisa_b },
2306: {"cmpw", 2, one(0130300), one(0170700), "*wAd", m68000up },
2307: {"cmpw", 4, one(0006100), one(0177700), "#w@s", m68000up },
2308: {"cmpw", 4, one(0006100), one(0177700), "#wDs", mcfisa_b },
2309: {"cmpw", 2, one(0130510), one(0170770), "+s+d", m68000up },
2310: {"cmpw", 2, one(0130100), one(0170700), "*wDd", m68000up | mcfisa_b },
2311: {"cmpl", 2, one(0130700), one(0170700), "*lAd", m68000up | mcfisa_a },
2312: {"cmpl", 6, one(0006200), one(0177700), "#l@s", m68000up },
2313: {"cmpl", 6, one(0006200), one(0177700), "#lDs", mcfisa_a },
2314: {"cmpl", 2, one(0130610), one(0170770), "+s+d", m68000up },
2315: {"cmpl", 2, one(0130200), one(0170700), "*lDd", m68000up | mcfisa_a },
2316:
2317: {"dbcc", 2, one(0052310), one(0177770), "DsBw", m68000up },
2318: {"dbcs", 2, one(0052710), one(0177770), "DsBw", m68000up },
2319: {"dbeq", 2, one(0053710), one(0177770), "DsBw", m68000up },
2320: {"dbf", 2, one(0050710), one(0177770), "DsBw", m68000up },
2321: {"dbge", 2, one(0056310), one(0177770), "DsBw", m68000up },
2322: {"dbgt", 2, one(0057310), one(0177770), "DsBw", m68000up },
2323: {"dbhi", 2, one(0051310), one(0177770), "DsBw", m68000up },
2324: {"dble", 2, one(0057710), one(0177770), "DsBw", m68000up },
2325: {"dbls", 2, one(0051710), one(0177770), "DsBw", m68000up },
2326: {"dblt", 2, one(0056710), one(0177770), "DsBw", m68000up },
2327: {"dbmi", 2, one(0055710), one(0177770), "DsBw", m68000up },
2328: {"dbne", 2, one(0053310), one(0177770), "DsBw", m68000up },
2329: {"dbpl", 2, one(0055310), one(0177770), "DsBw", m68000up },
2330: {"dbt", 2, one(0050310), one(0177770), "DsBw", m68000up },
2331: {"dbvc", 2, one(0054310), one(0177770), "DsBw", m68000up },
2332: {"dbvs", 2, one(0054710), one(0177770), "DsBw", m68000up },
2333:
2334: {"divsw", 2, one(0100700), one(0170700), ";wDd", m68000up | mcfhwdiv },
2335:
2336: {"divsl", 4, two(0046100,0006000),two(0177700,0107770),";lD3D1", m68020up|cpu32 },
2337: {"divsl", 4, two(0046100,0004000),two(0177700,0107770),";lDD", m68020up|cpu32 },
2338: {"divsl", 4, two(0046100,0004000),two(0177700,0107770),"qsDD", mcfhwdiv },
2339:
2340: {"divsll", 4, two(0046100,0004000),two(0177700,0107770),";lD3D1",m68020up|cpu32 },
2341: {"divsll", 4, two(0046100,0004000),two(0177700,0107770),";lDD", m68020up|cpu32 },
2342:
2343: {"divuw", 2, one(0100300), one(0170700), ";wDd", m68000up | mcfhwdiv },
2344:
2345: {"divul", 4, two(0046100,0002000),two(0177700,0107770),";lD3D1", m68020up|cpu32 },
2346: {"divul", 4, two(0046100,0000000),two(0177700,0107770),";lDD", m68020up|cpu32 },
2347: {"divul", 4, two(0046100,0000000),two(0177700,0107770),"qsDD", mcfhwdiv },
2348:
2349: {"divull", 4, two(0046100,0000000),two(0177700,0107770),";lD3D1",m68020up|cpu32 },
2350: {"divull", 4, two(0046100,0000000),two(0177700,0107770),";lDD", m68020up|cpu32 },
2351:
2352: {"eorib", 4, one(0005000), one(0177700), "#b$s", m68000up },
2353: {"eorib", 4, one(0005074), one(0177777), "#bCs", m68000up },
2354: {"eoriw", 4, one(0005100), one(0177700), "#w$s", m68000up },
2355: {"eoriw", 4, one(0005174), one(0177777), "#wSs", m68000up },
2356: {"eoril", 6, one(0005200), one(0177700), "#l$s", m68000up },
2357: {"eoril", 6, one(0005200), one(0177700), "#lDs", mcfisa_a },
2358: {"eori", 4, one(0005074), one(0177777), "#bCs", m68000up },
2359: {"eori", 4, one(0005174), one(0177777), "#wSs", m68000up },
2360: {"eori", 4, one(0005100), one(0177700), "#w$s", m68000up },
2361:
2362: /* The eor opcode can generate the eori instruction. */
2363: {"eorb", 4, one(0005000), one(0177700), "#b$s", m68000up },
2364: {"eorb", 4, one(0005074), one(0177777), "#bCs", m68000up },
2365: {"eorb", 2, one(0130400), one(0170700), "Dd$s", m68000up },
2366: {"eorw", 4, one(0005100), one(0177700), "#w$s", m68000up },
2367: {"eorw", 4, one(0005174), one(0177777), "#wSs", m68000up },
2368: {"eorw", 2, one(0130500), one(0170700), "Dd$s", m68000up },
2369: {"eorl", 6, one(0005200), one(0177700), "#l$s", m68000up },
2370: {"eorl", 6, one(0005200), one(0177700), "#lDs", mcfisa_a },
2371: {"eorl", 2, one(0130600), one(0170700), "Dd$s", m68000up | mcfisa_a },
2372: {"eor", 4, one(0005074), one(0177777), "#bCs", m68000up },
2373: {"eor", 4, one(0005174), one(0177777), "#wSs", m68000up },
2374: {"eor", 4, one(0005100), one(0177700), "#w$s", m68000up },
2375: {"eor", 2, one(0130500), one(0170700), "Dd$s", m68000up },
1.1.1.2 root 2376:
1.1 root 2377: {"exg", 2, one(0140500), one(0170770), "DdDs", m68000up },
2378: {"exg", 2, one(0140510), one(0170770), "AdAs", m68000up },
2379: {"exg", 2, one(0140610), one(0170770), "DdAs", m68000up },
2380: {"exg", 2, one(0140610), one(0170770), "AsDd", m68000up },
2381:
2382: {"extw", 2, one(0044200), one(0177770), "Ds", m68000up|mcfisa_a },
2383: {"extl", 2, one(0044300), one(0177770), "Ds", m68000up|mcfisa_a },
2384: {"extbl", 2, one(0044700), one(0177770), "Ds", m68020up|cpu32|mcfisa_a },
2385:
2386: {"ff1", 2, one(0002300), one(0177770), "Ds", mcfisa_aa},
2387:
2388: /* float stuff starts here */
2389:
2390: {"fabsb", 4, two(0xF000, 0x5818), two(0xF1C0, 0xFC7F), "Ii;bF7", mfloat },
2391: {"fabsb", 4, two(0xF000, 0x5818), two(0xF1C0, 0xFC7F), "IibsF7", cfloat },
2392: {"fabsd", 4, two(0xF000, 0x0018), two(0xF1C0, 0xE07F), "IiF8F7", cfloat },
2393: {"fabsd", 4, two(0xF000, 0x0018), two(0xF1C0, 0xE07F), "IiFt", cfloat },
2394: {"fabsd", 4, two(0xF000, 0x5418), two(0xF1C0, 0xFC7F), "Ii;FF7", mfloat },
2395: {"fabsd", 4, two(0xF000, 0x5418), two(0xF1C0, 0xFC7F), "IiwsF7", cfloat },
2396: {"fabsl", 4, two(0xF000, 0x4018), two(0xF1C0, 0xFC7F), "Ii;lF7", mfloat },
2397: {"fabsl", 4, two(0xF000, 0x4018), two(0xF1C0, 0xFC7F), "IibsF7", cfloat },
2398: {"fabsp", 4, two(0xF000, 0x4C18), two(0xF1C0, 0xFC7F), "Ii;pF7", mfloat },
2399: {"fabss", 4, two(0xF000, 0x4418), two(0xF1C0, 0xFC7F), "Ii;fF7", cfloat },
2400: {"fabss", 4, two(0xF000, 0x4418), two(0xF1C0, 0xFC7F), "Ii;fF7", mfloat },
2401: {"fabsw", 4, two(0xF000, 0x5018), two(0xF1C0, 0xFC7F), "Ii;wF7", mfloat },
2402: {"fabsw", 4, two(0xF000, 0x5018), two(0xF1C0, 0xFC7F), "IibsF7", cfloat },
2403: {"fabsx", 4, two(0xF000, 0x0018), two(0xF1C0, 0xE07F), "IiF8F7", mfloat },
2404: {"fabsx", 4, two(0xF000, 0x4818), two(0xF1C0, 0xFC7F), "Ii;xF7", mfloat },
2405: {"fabsx", 4, two(0xF000, 0x0018), two(0xF1C0, 0xE07F), "IiFt", mfloat },
2406:
2407: {"fsabsb", 4, two(0xF000, 0x5858), two(0xF1C0, 0xFC7F), "Ii;bF7", m68040up },
2408: {"fsabsb", 4, two(0xF000, 0x5858), two(0xF1C0, 0xFC7F), "IibsF7", cfloat },
2409: {"fsabsd", 4, two(0xF000, 0x0058), two(0xF1C0, 0xE07F), "IiF8F7", cfloat },
2410: {"fsabsd", 4, two(0xF000, 0x0058), two(0xF1C0, 0xE07F), "IiFt", cfloat },
2411: {"fsabsd", 4, two(0xF000, 0x5458), two(0xF1C0, 0xFC7F), "Ii;FF7", m68040up },
2412: {"fsabsd", 4, two(0xF000, 0x5458), two(0xF1C0, 0xFC7F), "IiwsF7", cfloat },
2413: {"fsabsl", 4, two(0xF000, 0x4058), two(0xF1C0, 0xFC7F), "Ii;lF7", m68040up },
2414: {"fsabsl", 4, two(0xF000, 0x4058), two(0xF1C0, 0xFC7F), "IibsF7", cfloat },
2415: {"fsabsp", 4, two(0xF000, 0x4C58), two(0xF1C0, 0xFC7F), "Ii;pF7", m68040up },
2416: {"fsabss", 4, two(0xF000, 0x4258), two(0xF1C0, 0xFC7F), "IibsF7", cfloat },
2417: {"fsabss", 4, two(0xF000, 0x4458), two(0xF1C0, 0xFC7F), "Ii;fF7", m68040up },
2418: {"fsabsw", 4, two(0xF000, 0x5058), two(0xF1C0, 0xFC7F), "Ii;wF7", m68040up },
2419: {"fsabsw", 4, two(0xF000, 0x5058), two(0xF1C0, 0xFC7F), "IibsF7", cfloat },
2420: {"fsabsx", 4, two(0xF000, 0x0058), two(0xF1C0, 0xE07F), "IiF8F7", m68040up },
2421: {"fsabsx", 4, two(0xF000, 0x4858), two(0xF1C0, 0xFC7F), "Ii;xF7", m68040up },
2422: {"fsabsx", 4, two(0xF000, 0x0058), two(0xF1C0, 0xE07F), "IiFt", m68040up },
2423:
2424: {"fdabsb", 4, two(0xF000, 0x585C), two(0xF1C0, 0xFC7F), "IibsF7", cfloat },
2425: {"fdabsb", 4, two(0xF000, 0x585c), two(0xF1C0, 0xFC7F), "Ii;bF7", m68040up},
2426: {"fdabsd", 4, two(0xF000, 0x005C), two(0xF1C0, 0xE07F), "IiF8F7", cfloat },
2427: {"fdabsd", 4, two(0xF000, 0x005C), two(0xF1C0, 0xE07F), "IiFt", cfloat },
2428: {"fdabsd", 4, two(0xF000, 0x545C), two(0xF1C0, 0xFC7F), "IiwsF7", cfloat },
2429: {"fdabsd", 4, two(0xF000, 0x545c), two(0xF1C0, 0xFC7F), "Ii;FF7", m68040up},
2430: {"fdabsl", 4, two(0xF000, 0x405C), two(0xF1C0, 0xFC7F), "IibsF7", cfloat },
2431: {"fdabsl", 4, two(0xF000, 0x405c), two(0xF1C0, 0xFC7F), "Ii;lF7", m68040up},
2432: {"fdabsp", 4, two(0xF000, 0x4C5c), two(0xF1C0, 0xFC7F), "Ii;pF7", m68040up},
2433: {"fdabss", 4, two(0xF000, 0x425C), two(0xF1C0, 0xFC7F), "IibsF7", cfloat },
2434: {"fdabss", 4, two(0xF000, 0x445c), two(0xF1C0, 0xFC7F), "Ii;fF7", m68040up},
2435: {"fdabsw", 4, two(0xF000, 0x505C), two(0xF1C0, 0xFC7F), "IibsF7", cfloat },
2436: {"fdabsw", 4, two(0xF000, 0x505c), two(0xF1C0, 0xFC7F), "Ii;wF7", m68040up},
2437: {"fdabsx", 4, two(0xF000, 0x005c), two(0xF1C0, 0xE07F), "IiF8F7", m68040up},
2438: {"fdabsx", 4, two(0xF000, 0x485c), two(0xF1C0, 0xFC7F), "Ii;xF7", m68040up},
2439: {"fdabsx", 4, two(0xF000, 0x005c), two(0xF1C0, 0xE07F), "IiFt", m68040up},
2440:
2441: {"facosb", 4, two(0xF000, 0x581C), two(0xF1C0, 0xFC7F), "Ii;bF7", mfloat },
2442: {"facosd", 4, two(0xF000, 0x541C), two(0xF1C0, 0xFC7F), "Ii;FF7", mfloat },
2443: {"facosl", 4, two(0xF000, 0x401C), two(0xF1C0, 0xFC7F), "Ii;lF7", mfloat },
2444: {"facosp", 4, two(0xF000, 0x4C1C), two(0xF1C0, 0xFC7F), "Ii;pF7", mfloat },
2445: {"facoss", 4, two(0xF000, 0x441C), two(0xF1C0, 0xFC7F), "Ii;fF7", mfloat },
2446: {"facosw", 4, two(0xF000, 0x501C), two(0xF1C0, 0xFC7F), "Ii;wF7", mfloat },
2447: {"facosx", 4, two(0xF000, 0x001C), two(0xF1C0, 0xE07F), "IiF8F7", mfloat },
2448: {"facosx", 4, two(0xF000, 0x481C), two(0xF1C0, 0xFC7F), "Ii;xF7", mfloat },
2449: {"facosx", 4, two(0xF000, 0x001C), two(0xF1C0, 0xE07F), "IiFt", mfloat },
2450:
2451: {"faddb", 4, two(0xF000, 0x5822), two(0xF1C0, 0xFC7F), "Ii;bF7", mfloat },
2452: {"faddb", 4, two(0xF000, 0x5822), two(0xF1C0, 0xFC7F), "IibsF7", cfloat },
2453: {"faddd", 4, two(0xF000, 0x0022), two(0xF1C0, 0xE07F), "IiF8F7", cfloat },
2454: {"faddd", 4, two(0xF000, 0x5422), two(0xF1C0, 0xFC7F), "IiwsF7", cfloat },
2455: {"faddd", 4, two(0xF000, 0x5422), two(0xF1C0, 0xFC7F), "Ii;FF7", mfloat },
2456: {"faddd", 4, two(0xF000, 0x5422), two(0xF1C0, 0xFC7F), "IiwsF7", cfloat },
2457: {"faddl", 4, two(0xF000, 0x4022), two(0xF1C0, 0xFC7F), "Ii;lF7", mfloat },
2458: {"faddl", 4, two(0xF000, 0x4022), two(0xF1C0, 0xFC7F), "IibsF7", cfloat },
2459: {"faddp", 4, two(0xF000, 0x4C22), two(0xF1C0, 0xFC7F), "Ii;pF7", mfloat },
2460: {"fadds", 4, two(0xF000, 0x4422), two(0xF1C0, 0xFC7F), "Ii;fF7", mfloat },
2461: {"fadds", 4, two(0xF000, 0x4422), two(0xF1C0, 0xFC7F), "IibsF7", cfloat },
2462: {"faddw", 4, two(0xF000, 0x5022), two(0xF1C0, 0xFC7F), "Ii;wF7", mfloat },
2463: {"faddw", 4, two(0xF000, 0x5022), two(0xF1C0, 0xFC7F), "IibsF7", cfloat },
2464: {"faddx", 4, two(0xF000, 0x0022), two(0xF1C0, 0xE07F), "IiF8F7", mfloat },
2465: {"faddx", 4, two(0xF000, 0x4822), two(0xF1C0, 0xFC7F), "Ii;xF7", mfloat },
2466:
2467: {"fsaddb", 4, two(0xF000, 0x5862), two(0xF1C0, 0xFC7F), "Ii;bF7", m68040up },
2468: {"fsaddb", 4, two(0xF000, 0x5862), two(0xF1C0, 0xFC7F), "IibsF7", cfloat },
2469: {"fsaddd", 4, two(0xF000, 0x0066), two(0xF1C0, 0xE07F), "IiF8F7", cfloat },
2470: {"fsaddd", 4, two(0xF000, 0x5462), two(0xF1C0, 0xFC7F), "Ii;FF7", m68040up },
2471: {"fsaddd", 4, two(0xF000, 0x5462), two(0xF1C0, 0xFC7F), "IiwsF7", cfloat },
2472: {"fsaddl", 4, two(0xF000, 0x4062), two(0xF1C0, 0xFC7F), "Ii;lF7", m68040up },
2473: {"fsaddl", 4, two(0xF000, 0x4062), two(0xF1C0, 0xFC7F), "IibsF7", cfloat },
2474: {"fsaddp", 4, two(0xF000, 0x4C62), two(0xF1C0, 0xFC7F), "Ii;pF7", m68040up },
2475: {"fsadds", 4, two(0xF000, 0x4462), two(0xF1C0, 0xFC7F), "Ii;fF7", m68040up },
2476: {"fsadds", 4, two(0xF000, 0x4862), two(0xF1C0, 0xFC7F), "IibsF7", cfloat },
2477: {"fsaddw", 4, two(0xF000, 0x5062), two(0xF1C0, 0xFC7F), "Ii;wF7", m68040up },
2478: {"fsaddw", 4, two(0xF000, 0x5062), two(0xF1C0, 0xFC7F), "IibsF7", cfloat },
2479: {"fsaddx", 4, two(0xF000, 0x0062), two(0xF1C0, 0xE07F), "IiF8F7", m68040up },
2480: {"fsaddx", 4, two(0xF000, 0x4862), two(0xF1C0, 0xFC7F), "Ii;xF7", m68040up },
2481:
2482: {"fdaddb", 4, two(0xF000, 0x5826), two(0xF1C0, 0xFC7F), "IibsF7", cfloat },
2483: {"fdaddb", 4, two(0xF000, 0x5866), two(0xF1C0, 0xFC7F), "Ii;bF7", m68040up },
2484: {"fdaddd", 4, two(0xF000, 0x0066), two(0xF1C0, 0xE07F), "IiF8F7", cfloat },
2485: {"fdaddd", 4, two(0xF000, 0x5426), two(0xF1C0, 0xFC7F), "IibsF7", cfloat },
2486: {"fdaddd", 4, two(0xF000, 0x5466), two(0xF1C0, 0xFC7F), "Ii;FF7", m68040up },
2487: {"fdaddl", 4, two(0xF000, 0x4026), two(0xF1C0, 0xFC7F), "IiwsF7", cfloat },
2488: {"fdaddl", 4, two(0xF000, 0x4066), two(0xF1C0, 0xFC7F), "Ii;lF7", m68040up },
2489: {"fdaddp", 4, two(0xF000, 0x4C66), two(0xF1C0, 0xFC7F), "Ii;pF7", m68040up },
2490: {"fdadds", 4, two(0xF000, 0x4466), two(0xF1C0, 0xFC7F), "Ii;fF7", m68040up },
2491: {"fdadds", 4, two(0xF000, 0x4826), two(0xF1C0, 0xFC7F), "IibsF7", cfloat },
2492: {"fdaddw", 4, two(0xF000, 0x5026), two(0xF1C0, 0xFC7F), "IibsF7", cfloat },
2493: {"fdaddw", 4, two(0xF000, 0x5066), two(0xF1C0, 0xFC7F), "Ii;wF7", m68040up },
2494: {"fdaddx", 4, two(0xF000, 0x0066), two(0xF1C0, 0xE07F), "IiF8F7", m68040up },
2495: {"fdaddx", 4, two(0xF000, 0x4866), two(0xF1C0, 0xFC7F), "Ii;xF7", m68040up },
2496:
2497: {"fasinb", 4, two(0xF000, 0x580C), two(0xF1C0, 0xFC7F), "Ii;bF7", mfloat },
2498: {"fasind", 4, two(0xF000, 0x540C), two(0xF1C0, 0xFC7F), "Ii;FF7", mfloat },
2499: {"fasinl", 4, two(0xF000, 0x400C), two(0xF1C0, 0xFC7F), "Ii;lF7", mfloat },
2500: {"fasinp", 4, two(0xF000, 0x4C0C), two(0xF1C0, 0xFC7F), "Ii;pF7", mfloat },
2501: {"fasins", 4, two(0xF000, 0x440C), two(0xF1C0, 0xFC7F), "Ii;fF7", mfloat },
2502: {"fasinw", 4, two(0xF000, 0x500C), two(0xF1C0, 0xFC7F), "Ii;wF7", mfloat },
2503: {"fasinx", 4, two(0xF000, 0x000C), two(0xF1C0, 0xE07F), "IiF8F7", mfloat },
2504: {"fasinx", 4, two(0xF000, 0x480C), two(0xF1C0, 0xFC7F), "Ii;xF7", mfloat },
2505: {"fasinx", 4, two(0xF000, 0x000C), two(0xF1C0, 0xE07F), "IiFt", mfloat },
2506:
2507: {"fatanb", 4, two(0xF000, 0x580A), two(0xF1C0, 0xFC7F), "Ii;bF7", mfloat },
2508: {"fatand", 4, two(0xF000, 0x540A), two(0xF1C0, 0xFC7F), "Ii;FF7", mfloat },
2509: {"fatanl", 4, two(0xF000, 0x400A), two(0xF1C0, 0xFC7F), "Ii;lF7", mfloat },
2510: {"fatanp", 4, two(0xF000, 0x4C0A), two(0xF1C0, 0xFC7F), "Ii;pF7", mfloat },
2511: {"fatans", 4, two(0xF000, 0x440A), two(0xF1C0, 0xFC7F), "Ii;fF7", mfloat },
2512: {"fatanw", 4, two(0xF000, 0x500A), two(0xF1C0, 0xFC7F), "Ii;wF7", mfloat },
2513: {"fatanx", 4, two(0xF000, 0x000A), two(0xF1C0, 0xE07F), "IiF8F7", mfloat },
2514: {"fatanx", 4, two(0xF000, 0x480A), two(0xF1C0, 0xFC7F), "Ii;xF7", mfloat },
2515: {"fatanx", 4, two(0xF000, 0x000A), two(0xF1C0, 0xE07F), "IiFt", mfloat },
2516:
2517: {"fatanhb", 4, two(0xF000, 0x580D), two(0xF1C0, 0xFC7F), "Ii;bF7", mfloat },
2518: {"fatanhd", 4, two(0xF000, 0x540D), two(0xF1C0, 0xFC7F), "Ii;FF7", mfloat },
2519: {"fatanhl", 4, two(0xF000, 0x400D), two(0xF1C0, 0xFC7F), "Ii;lF7", mfloat },
2520: {"fatanhp", 4, two(0xF000, 0x4C0D), two(0xF1C0, 0xFC7F), "Ii;pF7", mfloat },
2521: {"fatanhs", 4, two(0xF000, 0x440D), two(0xF1C0, 0xFC7F), "Ii;fF7", mfloat },
2522: {"fatanhw", 4, two(0xF000, 0x500D), two(0xF1C0, 0xFC7F), "Ii;wF7", mfloat },
2523: {"fatanhx", 4, two(0xF000, 0x000D), two(0xF1C0, 0xE07F), "IiF8F7", mfloat },
2524: {"fatanhx", 4, two(0xF000, 0x480D), two(0xF1C0, 0xFC7F), "Ii;xF7", mfloat },
2525: {"fatanhx", 4, two(0xF000, 0x000D), two(0xF1C0, 0xE07F), "IiFt", mfloat },
2526:
2527: {"fbeq", 2, one(0xF081), one(0xF1FF), "IdBW", mfloat | cfloat },
2528: {"fbf", 2, one(0xF080), one(0xF1FF), "IdBW", mfloat | cfloat },
2529: {"fbge", 2, one(0xF093), one(0xF1FF), "IdBW", mfloat | cfloat },
2530: {"fbgl", 2, one(0xF096), one(0xF1FF), "IdBW", mfloat | cfloat },
2531: {"fbgle", 2, one(0xF097), one(0xF1FF), "IdBW", mfloat | cfloat },
2532: {"fbgt", 2, one(0xF092), one(0xF1FF), "IdBW", mfloat | cfloat },
2533: {"fble", 2, one(0xF095), one(0xF1FF), "IdBW", mfloat | cfloat },
2534: {"fblt", 2, one(0xF094), one(0xF1FF), "IdBW", mfloat | cfloat },
2535: {"fbne", 2, one(0xF08E), one(0xF1FF), "IdBW", mfloat | cfloat },
2536: {"fbnge", 2, one(0xF09C), one(0xF1FF), "IdBW", mfloat | cfloat },
2537: {"fbngl", 2, one(0xF099), one(0xF1FF), "IdBW", mfloat | cfloat },
2538: {"fbngle", 2, one(0xF098), one(0xF1FF), "IdBW", mfloat | cfloat },
2539: {"fbngt", 2, one(0xF09D), one(0xF1FF), "IdBW", mfloat | cfloat },
2540: {"fbnle", 2, one(0xF09A), one(0xF1FF), "IdBW", mfloat | cfloat },
2541: {"fbnlt", 2, one(0xF09B), one(0xF1FF), "IdBW", mfloat | cfloat },
2542: {"fboge", 2, one(0xF083), one(0xF1FF), "IdBW", mfloat | cfloat },
2543: {"fbogl", 2, one(0xF086), one(0xF1FF), "IdBW", mfloat | cfloat },
2544: {"fbogt", 2, one(0xF082), one(0xF1FF), "IdBW", mfloat | cfloat },
2545: {"fbole", 2, one(0xF085), one(0xF1FF), "IdBW", mfloat | cfloat },
2546: {"fbolt", 2, one(0xF084), one(0xF1FF), "IdBW", mfloat | cfloat },
2547: {"fbor", 2, one(0xF087), one(0xF1FF), "IdBW", mfloat | cfloat },
2548: {"fbseq", 2, one(0xF091), one(0xF1FF), "IdBW", mfloat | cfloat },
2549: {"fbsf", 2, one(0xF090), one(0xF1FF), "IdBW", mfloat | cfloat },
2550: {"fbsne", 2, one(0xF09E), one(0xF1FF), "IdBW", mfloat | cfloat },
2551: {"fbst", 2, one(0xF09F), one(0xF1FF), "IdBW", mfloat | cfloat },
2552: {"fbt", 2, one(0xF08F), one(0xF1FF), "IdBW", mfloat | cfloat },
2553: {"fbueq", 2, one(0xF089), one(0xF1FF), "IdBW", mfloat | cfloat },
2554: {"fbuge", 2, one(0xF08B), one(0xF1FF), "IdBW", mfloat | cfloat },
2555: {"fbugt", 2, one(0xF08A), one(0xF1FF), "IdBW", mfloat | cfloat },
2556: {"fbule", 2, one(0xF08D), one(0xF1FF), "IdBW", mfloat | cfloat },
2557: {"fbult", 2, one(0xF08C), one(0xF1FF), "IdBW", mfloat | cfloat },
2558: {"fbun", 2, one(0xF088), one(0xF1FF), "IdBW", mfloat | cfloat },
2559:
2560: {"fbeql", 2, one(0xF0C1), one(0xF1FF), "IdBC", mfloat | cfloat },
2561: {"fbfl", 2, one(0xF0C0), one(0xF1FF), "IdBC", mfloat | cfloat },
2562: {"fbgel", 2, one(0xF0D3), one(0xF1FF), "IdBC", mfloat | cfloat },
2563: {"fbgll", 2, one(0xF0D6), one(0xF1FF), "IdBC", mfloat | cfloat },
2564: {"fbglel", 2, one(0xF0D7), one(0xF1FF), "IdBC", mfloat | cfloat },
2565: {"fbgtl", 2, one(0xF0D2), one(0xF1FF), "IdBC", mfloat | cfloat },
2566: {"fblel", 2, one(0xF0D5), one(0xF1FF), "IdBC", mfloat | cfloat },
2567: {"fbltl", 2, one(0xF0D4), one(0xF1FF), "IdBC", mfloat | cfloat },
2568: {"fbnel", 2, one(0xF0CE), one(0xF1FF), "IdBC", mfloat | cfloat },
2569: {"fbngel", 2, one(0xF0DC), one(0xF1FF), "IdBC", mfloat | cfloat },
2570: {"fbngll", 2, one(0xF0D9), one(0xF1FF), "IdBC", mfloat | cfloat },
2571: {"fbnglel", 2, one(0xF0D8), one(0xF1FF), "IdBC", mfloat | cfloat },
2572: {"fbngtl", 2, one(0xF0DD), one(0xF1FF), "IdBC", mfloat | cfloat },
2573: {"fbnlel", 2, one(0xF0DA), one(0xF1FF), "IdBC", mfloat | cfloat },
2574: {"fbnltl", 2, one(0xF0DB), one(0xF1FF), "IdBC", mfloat | cfloat },
2575: {"fbogel", 2, one(0xF0C3), one(0xF1FF), "IdBC", mfloat | cfloat },
2576: {"fbogll", 2, one(0xF0C6), one(0xF1FF), "IdBC", mfloat | cfloat },
2577: {"fbogtl", 2, one(0xF0C2), one(0xF1FF), "IdBC", mfloat | cfloat },
2578: {"fbolel", 2, one(0xF0C5), one(0xF1FF), "IdBC", mfloat | cfloat },
2579: {"fboltl", 2, one(0xF0C4), one(0xF1FF), "IdBC", mfloat | cfloat },
2580: {"fborl", 2, one(0xF0C7), one(0xF1FF), "IdBC", mfloat | cfloat },
2581: {"fbseql", 2, one(0xF0D1), one(0xF1FF), "IdBC", mfloat | cfloat },
2582: {"fbsfl", 2, one(0xF0D0), one(0xF1FF), "IdBC", mfloat | cfloat },
2583: {"fbsnel", 2, one(0xF0DE), one(0xF1FF), "IdBC", mfloat | cfloat },
2584: {"fbstl", 2, one(0xF0DF), one(0xF1FF), "IdBC", mfloat | cfloat },
2585: {"fbtl", 2, one(0xF0CF), one(0xF1FF), "IdBC", mfloat | cfloat },
2586: {"fbueql", 2, one(0xF0C9), one(0xF1FF), "IdBC", mfloat | cfloat },
2587: {"fbugel", 2, one(0xF0CB), one(0xF1FF), "IdBC", mfloat | cfloat },
2588: {"fbugtl", 2, one(0xF0CA), one(0xF1FF), "IdBC", mfloat | cfloat },
2589: {"fbulel", 2, one(0xF0CD), one(0xF1FF), "IdBC", mfloat | cfloat },
2590: {"fbultl", 2, one(0xF0CC), one(0xF1FF), "IdBC", mfloat | cfloat },
2591: {"fbunl", 2, one(0xF0C8), one(0xF1FF), "IdBC", mfloat | cfloat },
2592:
2593: {"fjeq", 2, one(0xF081), one(0xF1BF), "IdBc", mfloat | cfloat },
2594: {"fjf", 2, one(0xF080), one(0xF1BF), "IdBc", mfloat | cfloat },
2595: {"fjge", 2, one(0xF093), one(0xF1BF), "IdBc", mfloat | cfloat },
2596: {"fjgl", 2, one(0xF096), one(0xF1BF), "IdBc", mfloat | cfloat },
2597: {"fjgle", 2, one(0xF097), one(0xF1BF), "IdBc", mfloat | cfloat },
2598: {"fjgt", 2, one(0xF092), one(0xF1BF), "IdBc", mfloat | cfloat },
2599: {"fjle", 2, one(0xF095), one(0xF1BF), "IdBc", mfloat | cfloat },
2600: {"fjlt", 2, one(0xF094), one(0xF1BF), "IdBc", mfloat | cfloat },
2601: {"fjne", 2, one(0xF08E), one(0xF1BF), "IdBc", mfloat | cfloat },
2602: {"fjnge", 2, one(0xF09C), one(0xF1BF), "IdBc", mfloat | cfloat },
2603: {"fjngl", 2, one(0xF099), one(0xF1BF), "IdBc", mfloat | cfloat },
2604: {"fjngle", 2, one(0xF098), one(0xF1BF), "IdBc", mfloat | cfloat },
2605: {"fjngt", 2, one(0xF09D), one(0xF1BF), "IdBc", mfloat | cfloat },
2606: {"fjnle", 2, one(0xF09A), one(0xF1BF), "IdBc", mfloat | cfloat },
2607: {"fjnlt", 2, one(0xF09B), one(0xF1BF), "IdBc", mfloat | cfloat },
2608: {"fjoge", 2, one(0xF083), one(0xF1BF), "IdBc", mfloat | cfloat },
2609: {"fjogl", 2, one(0xF086), one(0xF1BF), "IdBc", mfloat | cfloat },
2610: {"fjogt", 2, one(0xF082), one(0xF1BF), "IdBc", mfloat | cfloat },
2611: {"fjole", 2, one(0xF085), one(0xF1BF), "IdBc", mfloat | cfloat },
2612: {"fjolt", 2, one(0xF084), one(0xF1BF), "IdBc", mfloat | cfloat },
2613: {"fjor", 2, one(0xF087), one(0xF1BF), "IdBc", mfloat | cfloat },
2614: {"fjseq", 2, one(0xF091), one(0xF1BF), "IdBc", mfloat | cfloat },
2615: {"fjsf", 2, one(0xF090), one(0xF1BF), "IdBc", mfloat | cfloat },
2616: {"fjsne", 2, one(0xF09E), one(0xF1BF), "IdBc", mfloat | cfloat },
2617: {"fjst", 2, one(0xF09F), one(0xF1BF), "IdBc", mfloat | cfloat },
2618: {"fjt", 2, one(0xF08F), one(0xF1BF), "IdBc", mfloat | cfloat },
2619: {"fjueq", 2, one(0xF089), one(0xF1BF), "IdBc", mfloat | cfloat },
2620: {"fjuge", 2, one(0xF08B), one(0xF1BF), "IdBc", mfloat | cfloat },
2621: {"fjugt", 2, one(0xF08A), one(0xF1BF), "IdBc", mfloat | cfloat },
2622: {"fjule", 2, one(0xF08D), one(0xF1BF), "IdBc", mfloat | cfloat },
2623: {"fjult", 2, one(0xF08C), one(0xF1BF), "IdBc", mfloat | cfloat },
2624: {"fjun", 2, one(0xF088), one(0xF1BF), "IdBc", mfloat | cfloat },
2625:
2626: {"fcmpb", 4, two(0xF000, 0x5838), two(0xF1C0, 0xFC7F), "IibsF7", cfloat },
2627: {"fcmpb", 4, two(0xF000, 0x5838), two(0xF1C0, 0xFC7F), "Ii;bF7", mfloat },
2628: {"fcmpd", 4, two(0xF000, 0x5438), two(0xF1C0, 0xFC7F), "Ii;FF7", mfloat },
2629: {"fcmpd", 4, two(0xF000, 0x5438), two(0xF1C0, 0xFC7F), "IiwsF7", cfloat },
2630: {"fcmpd", 4, two(0xF000, 0x0038), two(0xF1C0, 0xE07F), "IiF8F7", cfloat },
2631: {"fcmpl", 4, two(0xF000, 0x4038), two(0xF1C0, 0xFC7F), "Ii;lF7", mfloat },
2632: {"fcmpl", 4, two(0xF000, 0x4038), two(0xF1C0, 0xFC7F), "IibsF7", cfloat },
2633: {"fcmpp", 4, two(0xF000, 0x4C38), two(0xF1C0, 0xFC7F), "Ii;pF7", mfloat },
2634: {"fcmps", 4, two(0xF000, 0x4438), two(0xF1C0, 0xFC7F), "Ii;fF7", mfloat },
2635: {"fcmps", 4, two(0xF000, 0x4438), two(0xF1C0, 0xFC7F), "IibsF7", cfloat },
2636: {"fcmpw", 4, two(0xF000, 0x5038), two(0xF1C0, 0xFC7F), "Ii;wF7", mfloat },
2637: {"fcmpw", 4, two(0xF000, 0x5038), two(0xF1C0, 0xFC7F), "IibsF7", cfloat },
2638: {"fcmpx", 4, two(0xF000, 0x0038), two(0xF1C0, 0xE07F), "IiF8F7", mfloat },
2639: {"fcmpx", 4, two(0xF000, 0x4838), two(0xF1C0, 0xFC7F), "Ii;xF7", mfloat },
2640:
2641: {"fcosb", 4, two(0xF000, 0x581D), two(0xF1C0, 0xFC7F), "Ii;bF7", mfloat },
2642: {"fcosd", 4, two(0xF000, 0x541D), two(0xF1C0, 0xFC7F), "Ii;FF7", mfloat },
2643: {"fcosl", 4, two(0xF000, 0x401D), two(0xF1C0, 0xFC7F), "Ii;lF7", mfloat },
2644: {"fcosp", 4, two(0xF000, 0x4C1D), two(0xF1C0, 0xFC7F), "Ii;pF7", mfloat },
2645: {"fcoss", 4, two(0xF000, 0x441D), two(0xF1C0, 0xFC7F), "Ii;fF7", mfloat },
2646: {"fcosw", 4, two(0xF000, 0x501D), two(0xF1C0, 0xFC7F), "Ii;wF7", mfloat },
2647: {"fcosx", 4, two(0xF000, 0x001D), two(0xF1C0, 0xE07F), "IiF8F7", mfloat },
2648: {"fcosx", 4, two(0xF000, 0x481D), two(0xF1C0, 0xFC7F), "Ii;xF7", mfloat },
2649: {"fcosx", 4, two(0xF000, 0x001D), two(0xF1C0, 0xE07F), "IiFt", mfloat },
2650:
2651: {"fcoshb", 4, two(0xF000, 0x5819), two(0xF1C0, 0xFC7F), "Ii;bF7", mfloat },
2652: {"fcoshd", 4, two(0xF000, 0x5419), two(0xF1C0, 0xFC7F), "Ii;FF7", mfloat },
2653: {"fcoshl", 4, two(0xF000, 0x4019), two(0xF1C0, 0xFC7F), "Ii;lF7", mfloat },
2654: {"fcoshp", 4, two(0xF000, 0x4C19), two(0xF1C0, 0xFC7F), "Ii;pF7", mfloat },
2655: {"fcoshs", 4, two(0xF000, 0x4419), two(0xF1C0, 0xFC7F), "Ii;fF7", mfloat },
2656: {"fcoshw", 4, two(0xF000, 0x5019), two(0xF1C0, 0xFC7F), "Ii;wF7", mfloat },
2657: {"fcoshx", 4, two(0xF000, 0x0019), two(0xF1C0, 0xE07F), "IiF8F7", mfloat },
2658: {"fcoshx", 4, two(0xF000, 0x4819), two(0xF1C0, 0xFC7F), "Ii;xF7", mfloat },
2659: {"fcoshx", 4, two(0xF000, 0x0019), two(0xF1C0, 0xE07F), "IiFt", mfloat },
2660:
2661: {"fdbeq", 4, two(0xF048, 0x0001), two(0xF1F8, 0xFFFF), "IiDsBw", mfloat },
2662: {"fdbf", 4, two(0xF048, 0x0000), two(0xF1F8, 0xFFFF), "IiDsBw", mfloat },
2663: {"fdbge", 4, two(0xF048, 0x0013), two(0xF1F8, 0xFFFF), "IiDsBw", mfloat },
2664: {"fdbgl", 4, two(0xF048, 0x0016), two(0xF1F8, 0xFFFF), "IiDsBw", mfloat },
2665: {"fdbgle", 4, two(0xF048, 0x0017), two(0xF1F8, 0xFFFF), "IiDsBw", mfloat },
2666: {"fdbgt", 4, two(0xF048, 0x0012), two(0xF1F8, 0xFFFF), "IiDsBw", mfloat },
2667: {"fdble", 4, two(0xF048, 0x0015), two(0xF1F8, 0xFFFF), "IiDsBw", mfloat },
2668: {"fdblt", 4, two(0xF048, 0x0014), two(0xF1F8, 0xFFFF), "IiDsBw", mfloat },
2669: {"fdbne", 4, two(0xF048, 0x000E), two(0xF1F8, 0xFFFF), "IiDsBw", mfloat },
2670: {"fdbnge", 4, two(0xF048, 0x001C), two(0xF1F8, 0xFFFF), "IiDsBw", mfloat },
2671: {"fdbngl", 4, two(0xF048, 0x0019), two(0xF1F8, 0xFFFF), "IiDsBw", mfloat },
2672: {"fdbngle", 4, two(0xF048, 0x0018), two(0xF1F8, 0xFFFF), "IiDsBw", mfloat },
2673: {"fdbngt", 4, two(0xF048, 0x001D), two(0xF1F8, 0xFFFF), "IiDsBw", mfloat },
2674: {"fdbnle", 4, two(0xF048, 0x001A), two(0xF1F8, 0xFFFF), "IiDsBw", mfloat },
2675: {"fdbnlt", 4, two(0xF048, 0x001B), two(0xF1F8, 0xFFFF), "IiDsBw", mfloat },
2676: {"fdboge", 4, two(0xF048, 0x0003), two(0xF1F8, 0xFFFF), "IiDsBw", mfloat },
2677: {"fdbogl", 4, two(0xF048, 0x0006), two(0xF1F8, 0xFFFF), "IiDsBw", mfloat },
2678: {"fdbogt", 4, two(0xF048, 0x0002), two(0xF1F8, 0xFFFF), "IiDsBw", mfloat },
2679: {"fdbole", 4, two(0xF048, 0x0005), two(0xF1F8, 0xFFFF), "IiDsBw", mfloat },
2680: {"fdbolt", 4, two(0xF048, 0x0004), two(0xF1F8, 0xFFFF), "IiDsBw", mfloat },
2681: {"fdbor", 4, two(0xF048, 0x0007), two(0xF1F8, 0xFFFF), "IiDsBw", mfloat },
2682: {"fdbseq", 4, two(0xF048, 0x0011), two(0xF1F8, 0xFFFF), "IiDsBw", mfloat },
2683: {"fdbsf", 4, two(0xF048, 0x0010), two(0xF1F8, 0xFFFF), "IiDsBw", mfloat },
2684: {"fdbsne", 4, two(0xF048, 0x001E), two(0xF1F8, 0xFFFF), "IiDsBw", mfloat },
2685: {"fdbst", 4, two(0xF048, 0x001F), two(0xF1F8, 0xFFFF), "IiDsBw", mfloat },
2686: {"fdbt", 4, two(0xF048, 0x000F), two(0xF1F8, 0xFFFF), "IiDsBw", mfloat },
2687: {"fdbueq", 4, two(0xF048, 0x0009), two(0xF1F8, 0xFFFF), "IiDsBw", mfloat },
2688: {"fdbuge", 4, two(0xF048, 0x000B), two(0xF1F8, 0xFFFF), "IiDsBw", mfloat },
2689: {"fdbugt", 4, two(0xF048, 0x000A), two(0xF1F8, 0xFFFF), "IiDsBw", mfloat },
2690: {"fdbule", 4, two(0xF048, 0x000D), two(0xF1F8, 0xFFFF), "IiDsBw", mfloat },
2691: {"fdbult", 4, two(0xF048, 0x000C), two(0xF1F8, 0xFFFF), "IiDsBw", mfloat },
2692: {"fdbun", 4, two(0xF048, 0x0008), two(0xF1F8, 0xFFFF), "IiDsBw", mfloat },
2693:
2694: {"fdivb", 4, two(0xF000, 0x5820), two(0xF1C0, 0xFC7F), "Ii;bF7", mfloat },
2695: {"fdivb", 4, two(0xF000, 0x5820), two(0xF1C0, 0xFC7F), "IibsF7", cfloat },
2696: {"fdivd", 4, two(0xF000, 0x0020), two(0xF1C0, 0xE07F), "IiF8F7", cfloat },
2697: {"fdivd", 4, two(0xF000, 0x5420), two(0xF1C0, 0xFC7F), "Ii;FF7", mfloat },
2698: {"fdivd", 4, two(0xF000, 0x5420), two(0xF1C0, 0xFC7F), "IiwsF7", cfloat },
2699: {"fdivl", 4, two(0xF000, 0x4020), two(0xF1C0, 0xFC7F), "Ii;lF7", mfloat },
2700: {"fdivl", 4, two(0xF000, 0x4020), two(0xF1C0, 0xFC7F), "IibsF7", cfloat },
2701: {"fdivp", 4, two(0xF000, 0x4C20), two(0xF1C0, 0xFC7F), "Ii;pF7", mfloat },
2702: {"fdivs", 4, two(0xF000, 0x4420), two(0xF1C0, 0xFC7F), "Ii;fF7", mfloat },
2703: {"fdivs", 4, two(0xF000, 0x4420), two(0xF1C0, 0xFC7F), "IibsF7", cfloat },
2704: {"fdivw", 4, two(0xF000, 0x5020), two(0xF1C0, 0xFC7F), "Ii;wF7", mfloat },
2705: {"fdivw", 4, two(0xF000, 0x5020), two(0xF1C0, 0xFC7F), "IibsF7", cfloat },
2706: {"fdivx", 4, two(0xF000, 0x0020), two(0xF1C0, 0xE07F), "IiF8F7", mfloat },
2707: {"fdivx", 4, two(0xF000, 0x4820), two(0xF1C0, 0xFC7F), "Ii;xF7", mfloat },
2708:
2709: {"fsdivb", 4, two(0xF000, 0x5860), two(0xF1C0, 0xFC7F), "Ii;bF7", m68040up },
2710: {"fsdivb", 4, two(0xF000, 0x5860), two(0xF1C0, 0xFC7F), "IibsF7", cfloat },
2711: {"fsdivd", 4, two(0xF000, 0x0060), two(0xF1C0, 0xE07F), "IiF8F7", cfloat },
2712: {"fsdivd", 4, two(0xF000, 0x5460), two(0xF1C0, 0xFC7F), "Ii;FF7", m68040up },
2713: {"fsdivd", 4, two(0xF000, 0x5460), two(0xF1C0, 0xFC7F), "IiwsF7", cfloat },
2714: {"fsdivl", 4, two(0xF000, 0x4060), two(0xF1C0, 0xFC7F), "Ii;lF7", m68040up },
2715: {"fsdivl", 4, two(0xF000, 0x4060), two(0xF1C0, 0xFC7F), "IibsF7", cfloat },
2716: {"fsdivp", 4, two(0xF000, 0x4C60), two(0xF1C0, 0xFC7F), "Ii;pF7", m68040up },
2717: {"fsdivs", 4, two(0xF000, 0x4460), two(0xF1C0, 0xFC7F), "Ii;fF7", m68040up },
2718: {"fsdivs", 4, two(0xF000, 0x4460), two(0xF1C0, 0xFC7F), "IibsF7", cfloat },
2719: {"fsdivw", 4, two(0xF000, 0x5060), two(0xF1C0, 0xFC7F), "Ii;wF7", m68040up },
2720: {"fsdivw", 4, two(0xF000, 0x5060), two(0xF1C0, 0xFC7F), "IibsF7", cfloat },
2721: {"fsdivx", 4, two(0xF000, 0x0060), two(0xF1C0, 0xE07F), "IiF8F7", m68040up },
2722: {"fsdivx", 4, two(0xF000, 0x4860), two(0xF1C0, 0xFC7F), "Ii;xF7", m68040up },
2723:
2724: {"fddivb", 4, two(0xF000, 0x5864), two(0xF1C0, 0xFC7F), "Ii;bF7", m68040up },
2725: {"fddivb", 4, two(0xF000, 0x5864), two(0xF1C0, 0xFC7F), "IibsF7", cfloat },
2726: {"fddivd", 4, two(0xF000, 0x0064), two(0xF1C0, 0xE07F), "IiF8F7", cfloat },
2727: {"fddivd", 4, two(0xF000, 0x5464), two(0xF1C0, 0xFC7F), "Ii;FF7", m68040up },
2728: {"fddivd", 4, two(0xF000, 0x5464), two(0xF1C0, 0xFC7F), "IiwsF7", cfloat },
2729: {"fddivl", 4, two(0xF000, 0x4064), two(0xF1C0, 0xFC7F), "Ii;lF7", m68040up },
2730: {"fddivl", 4, two(0xF000, 0x4064), two(0xF1C0, 0xFC7F), "IibsF7", cfloat },
2731: {"fddivp", 4, two(0xF000, 0x4C64), two(0xF1C0, 0xFC7F), "Ii;pF7", m68040up },
2732: {"fddivs", 4, two(0xF000, 0x4464), two(0xF1C0, 0xFC7F), "Ii;fF7", m68040up },
2733: {"fddivs", 4, two(0xF000, 0x4464), two(0xF1C0, 0xFC7F), "IibsF7", cfloat },
2734: {"fddivw", 4, two(0xF000, 0x5064), two(0xF1C0, 0xFC7F), "Ii;wF7", m68040up },
2735: {"fddivw", 4, two(0xF000, 0x5064), two(0xF1C0, 0xFC7F), "IibsF7", cfloat },
2736: {"fddivx", 4, two(0xF000, 0x0064), two(0xF1C0, 0xE07F), "IiF8F7", m68040up },
2737: {"fddivx", 4, two(0xF000, 0x4864), two(0xF1C0, 0xFC7F), "Ii;xF7", m68040up },
2738:
2739: {"fetoxb", 4, two(0xF000, 0x5810), two(0xF1C0, 0xFC7F), "Ii;bF7", mfloat },
2740: {"fetoxd", 4, two(0xF000, 0x5410), two(0xF1C0, 0xFC7F), "Ii;FF7", mfloat },
2741: {"fetoxl", 4, two(0xF000, 0x4010), two(0xF1C0, 0xFC7F), "Ii;lF7", mfloat },
2742: {"fetoxp", 4, two(0xF000, 0x4C10), two(0xF1C0, 0xFC7F), "Ii;pF7", mfloat },
2743: {"fetoxs", 4, two(0xF000, 0x4410), two(0xF1C0, 0xFC7F), "Ii;fF7", mfloat },
2744: {"fetoxw", 4, two(0xF000, 0x5010), two(0xF1C0, 0xFC7F), "Ii;wF7", mfloat },
2745: {"fetoxx", 4, two(0xF000, 0x0010), two(0xF1C0, 0xE07F), "IiF8F7", mfloat },
2746: {"fetoxx", 4, two(0xF000, 0x4810), two(0xF1C0, 0xFC7F), "Ii;xF7", mfloat },
2747: {"fetoxx", 4, two(0xF000, 0x0010), two(0xF1C0, 0xE07F), "IiFt", mfloat },
2748:
2749: {"fetoxm1b", 4, two(0xF000, 0x5808), two(0xF1C0, 0xFC7F), "Ii;bF7", mfloat },
2750: {"fetoxm1d", 4, two(0xF000, 0x5408), two(0xF1C0, 0xFC7F), "Ii;FF7", mfloat },
2751: {"fetoxm1l", 4, two(0xF000, 0x4008), two(0xF1C0, 0xFC7F), "Ii;lF7", mfloat },
2752: {"fetoxm1p", 4, two(0xF000, 0x4C08), two(0xF1C0, 0xFC7F), "Ii;pF7", mfloat },
2753: {"fetoxm1s", 4, two(0xF000, 0x4408), two(0xF1C0, 0xFC7F), "Ii;fF7", mfloat },
2754: {"fetoxm1w", 4, two(0xF000, 0x5008), two(0xF1C0, 0xFC7F), "Ii;wF7", mfloat },
2755: {"fetoxm1x", 4, two(0xF000, 0x0008), two(0xF1C0, 0xE07F), "IiF8F7", mfloat },
2756: {"fetoxm1x", 4, two(0xF000, 0x4808), two(0xF1C0, 0xFC7F), "Ii;xF7", mfloat },
2757: {"fetoxm1x", 4, two(0xF000, 0x0008), two(0xF1C0, 0xE07F), "IiFt", mfloat },
2758:
2759: {"fgetexpb", 4, two(0xF000, 0x581E), two(0xF1C0, 0xFC7F), "Ii;bF7", mfloat },
2760: {"fgetexpd", 4, two(0xF000, 0x541E), two(0xF1C0, 0xFC7F), "Ii;FF7", mfloat },
2761: {"fgetexpl", 4, two(0xF000, 0x401E), two(0xF1C0, 0xFC7F), "Ii;lF7", mfloat },
2762: {"fgetexpp", 4, two(0xF000, 0x4C1E), two(0xF1C0, 0xFC7F), "Ii;pF7", mfloat },
2763: {"fgetexps", 4, two(0xF000, 0x441E), two(0xF1C0, 0xFC7F), "Ii;fF7", mfloat },
2764: {"fgetexpw", 4, two(0xF000, 0x501E), two(0xF1C0, 0xFC7F), "Ii;wF7", mfloat },
2765: {"fgetexpx", 4, two(0xF000, 0x001E), two(0xF1C0, 0xE07F), "IiF8F7", mfloat },
2766: {"fgetexpx", 4, two(0xF000, 0x481E), two(0xF1C0, 0xFC7F), "Ii;xF7", mfloat },
2767: {"fgetexpx", 4, two(0xF000, 0x001E), two(0xF1C0, 0xE07F), "IiFt", mfloat },
2768:
2769: {"fgetmanb", 4, two(0xF000, 0x581F), two(0xF1C0, 0xFC7F), "Ii;bF7", mfloat },
2770: {"fgetmand", 4, two(0xF000, 0x541F), two(0xF1C0, 0xFC7F), "Ii;FF7", mfloat },
2771: {"fgetmanl", 4, two(0xF000, 0x401F), two(0xF1C0, 0xFC7F), "Ii;lF7", mfloat },
2772: {"fgetmanp", 4, two(0xF000, 0x4C1F), two(0xF1C0, 0xFC7F), "Ii;pF7", mfloat },
2773: {"fgetmans", 4, two(0xF000, 0x441F), two(0xF1C0, 0xFC7F), "Ii;fF7", mfloat },
2774: {"fgetmanw", 4, two(0xF000, 0x501F), two(0xF1C0, 0xFC7F), "Ii;wF7", mfloat },
2775: {"fgetmanx", 4, two(0xF000, 0x001F), two(0xF1C0, 0xE07F), "IiF8F7", mfloat },
2776: {"fgetmanx", 4, two(0xF000, 0x481F), two(0xF1C0, 0xFC7F), "Ii;xF7", mfloat },
2777: {"fgetmanx", 4, two(0xF000, 0x001F), two(0xF1C0, 0xE07F), "IiFt", mfloat },
2778:
2779: {"fintb", 4, two(0xF000, 0x5801), two(0xF1C0, 0xFC7F), "Ii;bF7", mfloat },
2780: {"fintb", 4, two(0xF000, 0x5801), two(0xF1C0, 0xFC7F), "IibsF7", cfloat },
2781: {"fintd", 4, two(0xF000, 0x0001), two(0xF1C0, 0xE07F), "IiF8F7", cfloat },
2782: {"fintd", 4, two(0xF000, 0x0001), two(0xF1C0, 0xE07F), "IiFt", cfloat },
2783: {"fintd", 4, two(0xF000, 0x5401), two(0xF1C0, 0xFC7F), "Ii;FF7", mfloat },
2784: {"fintd", 4, two(0xF000, 0x5401), two(0xF1C0, 0xFC7F), "IiwsF7", cfloat },
2785: {"fintl", 4, two(0xF000, 0x4001), two(0xF1C0, 0xFC7F), "Ii;lF7", mfloat },
2786: {"fintl", 4, two(0xF000, 0x4001), two(0xF1C0, 0xFC7F), "IibsF7", cfloat },
2787: {"fintp", 4, two(0xF000, 0x4C01), two(0xF1C0, 0xFC7F), "Ii;pF7", mfloat },
2788: {"fints", 4, two(0xF000, 0x4401), two(0xF1C0, 0xFC7F), "Ii;fF7", mfloat },
2789: {"fints", 4, two(0xF000, 0x4401), two(0xF1C0, 0xFC7F), "IibsF7", cfloat },
2790: {"fintw", 4, two(0xF000, 0x5001), two(0xF1C0, 0xFC7F), "Ii;wF7", mfloat },
2791: {"fintw", 4, two(0xF000, 0x5001), two(0xF1C0, 0xFC7F), "IibsF7", cfloat },
2792: {"fintx", 4, two(0xF000, 0x0001), two(0xF1C0, 0xE07F), "IiF8F7", mfloat },
2793: {"fintx", 4, two(0xF000, 0x4801), two(0xF1C0, 0xFC7F), "Ii;xF7", mfloat },
2794: {"fintx", 4, two(0xF000, 0x0001), two(0xF1C0, 0xE07F), "IiFt", mfloat },
2795:
2796: {"fintrzb", 4, two(0xF000, 0x5803), two(0xF1C0, 0xFC7F), "Ii;bF7", mfloat },
2797: {"fintrzb", 4, two(0xF000, 0x5803), two(0xF1C0, 0xFC7F), "IibsF7", cfloat },
2798: {"fintrzd", 4, two(0xF000, 0x0003), two(0xF1C0, 0xE07F), "IiF8F7", cfloat },
2799: {"fintrzd", 4, two(0xF000, 0x0003), two(0xF1C0, 0xE07F), "IiFt", cfloat },
2800: {"fintrzd", 4, two(0xF000, 0x5403), two(0xF1C0, 0xFC7F), "Ii;FF7", mfloat },
2801: {"fintrzd", 4, two(0xF000, 0x5403), two(0xF1C0, 0xFC7F), "IiwsF7", cfloat },
2802: {"fintrzl", 4, two(0xF000, 0x4003), two(0xF1C0, 0xFC7F), "Ii;lF7", mfloat },
2803: {"fintrzl", 4, two(0xF000, 0x4003), two(0xF1C0, 0xFC7F), "IibsF7", cfloat },
2804: {"fintrzp", 4, two(0xF000, 0x4C03), two(0xF1C0, 0xFC7F), "Ii;pF7", mfloat },
2805: {"fintrzs", 4, two(0xF000, 0x4403), two(0xF1C0, 0xFC7F), "Ii;fF7", mfloat },
2806: {"fintrzs", 4, two(0xF000, 0x4403), two(0xF1C0, 0xFC7F), "IibsF7", cfloat },
2807: {"fintrzw", 4, two(0xF000, 0x5003), two(0xF1C0, 0xFC7F), "Ii;wF7", mfloat },
2808: {"fintrzw", 4, two(0xF000, 0x5003), two(0xF1C0, 0xFC7F), "IibsF7", cfloat },
2809: {"fintrzx", 4, two(0xF000, 0x0003), two(0xF1C0, 0xE07F), "IiF8F7", mfloat },
2810: {"fintrzx", 4, two(0xF000, 0x4803), two(0xF1C0, 0xFC7F), "Ii;xF7", mfloat },
2811: {"fintrzx", 4, two(0xF000, 0x0003), two(0xF1C0, 0xE07F), "IiFt", mfloat },
2812:
2813: {"flog10b", 4, two(0xF000, 0x5815), two(0xF1C0, 0xFC7F), "Ii;bF7", mfloat },
2814: {"flog10d", 4, two(0xF000, 0x5415), two(0xF1C0, 0xFC7F), "Ii;FF7", mfloat },
2815: {"flog10l", 4, two(0xF000, 0x4015), two(0xF1C0, 0xFC7F), "Ii;lF7", mfloat },
2816: {"flog10p", 4, two(0xF000, 0x4C15), two(0xF1C0, 0xFC7F), "Ii;pF7", mfloat },
2817: {"flog10s", 4, two(0xF000, 0x4415), two(0xF1C0, 0xFC7F), "Ii;fF7", mfloat },
2818: {"flog10w", 4, two(0xF000, 0x5015), two(0xF1C0, 0xFC7F), "Ii;wF7", mfloat },
2819: {"flog10x", 4, two(0xF000, 0x0015), two(0xF1C0, 0xE07F), "IiF8F7", mfloat },
2820: {"flog10x", 4, two(0xF000, 0x4815), two(0xF1C0, 0xFC7F), "Ii;xF7", mfloat },
2821: {"flog10x", 4, two(0xF000, 0x0015), two(0xF1C0, 0xE07F), "IiFt", mfloat },
2822:
2823: {"flog2b", 4, two(0xF000, 0x5816), two(0xF1C0, 0xFC7F), "Ii;bF7", mfloat },
2824: {"flog2d", 4, two(0xF000, 0x5416), two(0xF1C0, 0xFC7F), "Ii;FF7", mfloat },
2825: {"flog2l", 4, two(0xF000, 0x4016), two(0xF1C0, 0xFC7F), "Ii;lF7", mfloat },
2826: {"flog2p", 4, two(0xF000, 0x4C16), two(0xF1C0, 0xFC7F), "Ii;pF7", mfloat },
2827: {"flog2s", 4, two(0xF000, 0x4416), two(0xF1C0, 0xFC7F), "Ii;fF7", mfloat },
2828: {"flog2w", 4, two(0xF000, 0x5016), two(0xF1C0, 0xFC7F), "Ii;wF7", mfloat },
2829: {"flog2x", 4, two(0xF000, 0x0016), two(0xF1C0, 0xE07F), "IiF8F7", mfloat },
2830: {"flog2x", 4, two(0xF000, 0x4816), two(0xF1C0, 0xFC7F), "Ii;xF7", mfloat },
2831: {"flog2x", 4, two(0xF000, 0x0016), two(0xF1C0, 0xE07F), "IiFt", mfloat },
2832:
2833: {"flognb", 4, two(0xF000, 0x5814), two(0xF1C0, 0xFC7F), "Ii;bF7", mfloat },
2834: {"flognd", 4, two(0xF000, 0x5414), two(0xF1C0, 0xFC7F), "Ii;FF7", mfloat },
2835: {"flognl", 4, two(0xF000, 0x4014), two(0xF1C0, 0xFC7F), "Ii;lF7", mfloat },
2836: {"flognp", 4, two(0xF000, 0x4C14), two(0xF1C0, 0xFC7F), "Ii;pF7", mfloat },
2837: {"flogns", 4, two(0xF000, 0x4414), two(0xF1C0, 0xFC7F), "Ii;fF7", mfloat },
2838: {"flognw", 4, two(0xF000, 0x5014), two(0xF1C0, 0xFC7F), "Ii;wF7", mfloat },
2839: {"flognx", 4, two(0xF000, 0x0014), two(0xF1C0, 0xE07F), "IiF8F7", mfloat },
2840: {"flognx", 4, two(0xF000, 0x4814), two(0xF1C0, 0xFC7F), "Ii;xF7", mfloat },
2841: {"flognx", 4, two(0xF000, 0x0014), two(0xF1C0, 0xE07F), "IiFt", mfloat },
2842:
2843: {"flognp1b", 4, two(0xF000, 0x5806), two(0xF1C0, 0xFC7F), "Ii;bF7", mfloat },
2844: {"flognp1d", 4, two(0xF000, 0x5406), two(0xF1C0, 0xFC7F), "Ii;FF7", mfloat },
2845: {"flognp1l", 4, two(0xF000, 0x4006), two(0xF1C0, 0xFC7F), "Ii;lF7", mfloat },
2846: {"flognp1p", 4, two(0xF000, 0x4C06), two(0xF1C0, 0xFC7F), "Ii;pF7", mfloat },
2847: {"flognp1s", 4, two(0xF000, 0x4406), two(0xF1C0, 0xFC7F), "Ii;fF7", mfloat },
2848: {"flognp1w", 4, two(0xF000, 0x5006), two(0xF1C0, 0xFC7F), "Ii;wF7", mfloat },
2849: {"flognp1x", 4, two(0xF000, 0x0006), two(0xF1C0, 0xE07F), "IiF8F7", mfloat },
2850: {"flognp1x", 4, two(0xF000, 0x4806), two(0xF1C0, 0xFC7F), "Ii;xF7", mfloat },
2851: {"flognp1x", 4, two(0xF000, 0x0006), two(0xF1C0, 0xE07F), "IiFt", mfloat },
2852:
2853: {"fmodb", 4, two(0xF000, 0x5821), two(0xF1C0, 0xFC7F), "Ii;bF7", mfloat },
2854: {"fmodd", 4, two(0xF000, 0x5421), two(0xF1C0, 0xFC7F), "Ii;FF7", mfloat },
2855: {"fmodl", 4, two(0xF000, 0x4021), two(0xF1C0, 0xFC7F), "Ii;lF7", mfloat },
2856: {"fmodp", 4, two(0xF000, 0x4C21), two(0xF1C0, 0xFC7F), "Ii;pF7", mfloat },
2857: {"fmods", 4, two(0xF000, 0x4421), two(0xF1C0, 0xFC7F), "Ii;fF7", mfloat },
2858: {"fmodw", 4, two(0xF000, 0x5021), two(0xF1C0, 0xFC7F), "Ii;wF7", mfloat },
2859: {"fmodx", 4, two(0xF000, 0x0021), two(0xF1C0, 0xE07F), "IiF8F7", mfloat },
2860: {"fmodx", 4, two(0xF000, 0x4821), two(0xF1C0, 0xFC7F), "Ii;xF7", mfloat },
2861:
2862: {"fmoveb", 4, two(0xF000, 0x5800), two(0xF1C0, 0xFC7F), "IibsF7", cfloat },
2863: {"fmoveb", 4, two(0xF000, 0x7800), two(0xF1C0, 0xFC7F), "IiF7bs", cfloat },
2864: {"fmoveb", 4, two(0xF000, 0x5800), two(0xF1C0, 0xFC7F), "Ii;bF7", mfloat },
2865: {"fmoveb", 4, two(0xF000, 0x7800), two(0xF1C0, 0xFC7F), "IiF7$b", mfloat },
2866: {"fmoved", 4, two(0xF000, 0x5400), two(0xF1C0, 0xFC7F), "Ii;FF7", mfloat },
2867: {"fmoved", 4, two(0xF000, 0x7400), two(0xF1C0, 0xFC7F), "IiF7~F", mfloat },
2868: {"fmoved", 4, two(0xF000, 0x0000), two(0xF1C0, 0xE07F), "IiF8F7", cfloat },
2869: {"fmoved", 4, two(0xF000, 0x5400), two(0xF1C0, 0xFC7F), "IiwsF7", cfloat },
2870: {"fmoved", 4, two(0xF000, 0x7400), two(0xF1C0, 0xFC7F), "IiF7ws", cfloat },
2871: {"fmovel", 4, two(0xF000, 0x4000), two(0xF1C0, 0xFC7F), "Ii;lF7", mfloat },
2872: {"fmovel", 4, two(0xF000, 0x6000), two(0xF1C0, 0xFC7F), "IiF7$l", mfloat },
2873: /* FIXME: the next two variants should not permit moving an address
2874: register to anything but the floating point instruction register. */
2875: {"fmovel", 4, two(0xF000, 0xA000), two(0xF1C0, 0xE3FF), "Iis8%s", mfloat },
2876: {"fmovel", 4, two(0xF000, 0x8000), two(0xF1C0, 0xE3FF), "Ii*ls8", mfloat },
2877: {"fmovel", 4, two(0xF000, 0x4000), two(0xF1C0, 0xFC7F), "IibsF7", cfloat },
2878: {"fmovel", 4, two(0xF000, 0x6000), two(0xF1C0, 0xFC7F), "IiF7bs", cfloat },
2879: /* Move the FP control registers. */
2880: {"fmovel", 4, two(0xF000, 0xA000), two(0xF1C0, 0xE3FF), "Iis8ps", cfloat },
2881: {"fmovel", 4, two(0xF000, 0x8000), two(0xF1C0, 0xE3FF), "Iibss8", cfloat },
2882: {"fmovep", 4, two(0xF000, 0x4C00), two(0xF1C0, 0xFC7F), "Ii;pF7", mfloat },
2883: {"fmovep", 4, two(0xF000, 0x6C00), two(0xF1C0, 0xFC00), "IiF7~pkC", mfloat },
2884: {"fmovep", 4, two(0xF000, 0x7C00), two(0xF1C0, 0xFC0F), "IiF7~pDk", mfloat },
2885: {"fmoves", 4, two(0xF000, 0x4400), two(0xF1C0, 0xFC7F), "Ii;fF7", mfloat },
2886: {"fmoves", 4, two(0xF000, 0x6400), two(0xF1C0, 0xFC7F), "IiF7$f", mfloat },
2887: {"fmoves", 4, two(0xF000, 0x4400), two(0xF1C0, 0xFC7F), "IibsF7", cfloat },
2888: {"fmoves", 4, two(0xF000, 0x6400), two(0xF1C0, 0xFC7F), "IiF7qs", cfloat },
2889: {"fmovew", 4, two(0xF000, 0x5000), two(0xF1C0, 0xFC7F), "Ii;wF7", mfloat },
2890: {"fmovew", 4, two(0xF000, 0x7000), two(0xF1C0, 0xFC7F), "IiF7$w", mfloat },
2891: {"fmovew", 4, two(0xF000, 0x5000), two(0xF1C0, 0xFC7F), "IibsF7", cfloat },
2892: {"fmovew", 4, two(0xF000, 0x7000), two(0xF1C0, 0xFC7F), "IiF7qs", cfloat },
2893: {"fmovex", 4, two(0xF000, 0x0000), two(0xF1FF, 0xE07F), "IiF8F7", mfloat },
2894: {"fmovex", 4, two(0xF000, 0x4800), two(0xF1C0, 0xFC7F), "Ii;xF7", mfloat },
2895: {"fmovex", 4, two(0xF000, 0x6800), two(0xF1C0, 0xFC7F), "IiF7~x", mfloat },
2896:
2897: {"fsmoveb", 4, two(0xF000, 0x5840), two(0xF1C0, 0xFC7F), "Ii;bF7", m68040up },
2898: {"fsmoveb", 4, two(0xF000, 0x5840), two(0xF1C0, 0xFC7F), "IibsF7", cfloat },
2899: {"fsmoveb", 4, two(0xF000, 0x7840), two(0xF1C0, 0xFC7F), "IiF7qs", cfloat },
2900: {"fsmoved", 4, two(0xF000, 0x0040), two(0xF1C0, 0xE07F), "IiF8F7", cfloat },
2901: {"fsmoved", 4, two(0xF000, 0x5440), two(0xF1C0, 0xFC7F), "Ii;FF7", m68040up },
2902: {"fsmoved", 4, two(0xF000, 0x5440), two(0xF1C0, 0xFC7F), "IiwsF7", cfloat },
2903: {"fsmoved", 4, two(0xF000, 0x7440), two(0xF1C0, 0xFC7F), "IiF7ws", cfloat },
2904: {"fsmovel", 4, two(0xF000, 0x4040), two(0xF1C0, 0xFC7F), "Ii;lF7", m68040up },
2905: {"fsmovel", 4, two(0xF000, 0x4040), two(0xF1C0, 0xFC7F), "IibsF7", cfloat },
2906: {"fsmovel", 4, two(0xF000, 0x6040), two(0xF1C0, 0xFC7F), "IiF7qs", cfloat },
2907: {"fsmoves", 4, two(0xF000, 0x4440), two(0xF1C0, 0xFC7F), "Ii;fF7", m68040up },
2908: {"fsmoves", 4, two(0xF000, 0x4440), two(0xF1C0, 0xFC7F), "IibsF7", cfloat },
2909: {"fsmoves", 4, two(0xF000, 0x6440), two(0xF1C0, 0xFC7F), "IiF7qs", cfloat },
2910: {"fsmovew", 4, two(0xF000, 0x5040), two(0xF1C0, 0xFC7F), "Ii;wF7", m68040up },
2911: {"fsmovew", 4, two(0xF000, 0x5040), two(0xF1C0, 0xFC7F), "IibsF7", cfloat },
2912: {"fsmovew", 4, two(0xF000, 0x7040), two(0xF1C0, 0xFC7F), "IiF7qs", cfloat },
2913: {"fsmovex", 4, two(0xF000, 0x0040), two(0xF1C0, 0xE07F), "IiF8F7", m68040up },
2914: {"fsmovex", 4, two(0xF000, 0x4840), two(0xF1C0, 0xFC7F), "Ii;xF7", m68040up },
2915: {"fsmovep", 4, two(0xF000, 0x4C40), two(0xF1C0, 0xFC7F), "Ii;pF7", m68040up },
2916:
2917: {"fdmoveb", 4, two(0xF000, 0x5844), two(0xF1C0, 0xFC7F), "Ii;bF7", m68040up },
2918: {"fdmoveb", 4, two(0xF000, 0x5844), two(0xF1C0, 0xFC7F), "IibsF7", cfloat },
2919: {"fdmoveb", 4, two(0xF000, 0x7844), two(0xF1C0, 0xFC7F), "IiF7qs", cfloat },
2920: {"fdmoved", 4, two(0xF000, 0x0044), two(0xF1C0, 0xE07F), "IiF8F7", cfloat },
2921: {"fdmoved", 4, two(0xF000, 0x5444), two(0xF1C0, 0xFC7F), "Ii;FF7", m68040up },
2922: {"fdmoved", 4, two(0xF000, 0x5444), two(0xF1C0, 0xFC7F), "IiwsF7", cfloat },
2923: {"fdmoved", 4, two(0xF000, 0x7444), two(0xF1C0, 0xFC7F), "IiF7qs", cfloat },
2924: {"fdmovel", 4, two(0xF000, 0x4044), two(0xF1C0, 0xFC7F), "Ii;lF7", m68040up },
2925: {"fdmovel", 4, two(0xF000, 0x4044), two(0xF1C0, 0xFC7F), "IibsF7", cfloat },
2926: {"fdmovel", 4, two(0xF000, 0x6044), two(0xF1C0, 0xFC7F), "IiF7qs", cfloat },
2927: {"fdmoves", 4, two(0xF000, 0x4444), two(0xF1C0, 0xFC7F), "Ii;fF7", m68040up },
2928: {"fdmoves", 4, two(0xF000, 0x4444), two(0xF1C0, 0xFC7F), "IibsF7", cfloat },
2929: {"fdmoves", 4, two(0xF000, 0x6444), two(0xF1C0, 0xFC7F), "IiF7qs", cfloat },
2930: {"fdmovew", 4, two(0xF000, 0x5044), two(0xF1C0, 0xFC7F), "Ii;wF7", m68040up },
2931: {"fdmovew", 4, two(0xF000, 0x5044), two(0xF1C0, 0xFC7F), "IibsF7", cfloat },
2932: {"fdmovew", 4, two(0xF000, 0x7044), two(0xF1C0, 0xFC7F), "IiF7qs", cfloat },
2933: {"fdmovex", 4, two(0xF000, 0x0044), two(0xF1C0, 0xE07F), "IiF8F7", m68040up },
2934: {"fdmovex", 4, two(0xF000, 0x4844), two(0xF1C0, 0xFC7F), "Ii;xF7", m68040up },
2935: {"fdmovep", 4, two(0xF000, 0x4C44), two(0xF1C0, 0xFC7F), "Ii;pF7", m68040up },
2936:
2937: {"fmovecrx", 4, two(0xF000, 0x5C00), two(0xF1FF, 0xFC00), "Ii#CF7", mfloat },
2938:
2939: {"fmovemd", 4, two(0xF000, 0xD000), two(0xFFC0, 0xFF00), "Iizsl3", cfloat },
2940: {"fmovemd", 4, two(0xF000, 0xD000), two(0xFFC0, 0xFF00), "Iizs#3", cfloat },
2941: {"fmovemd", 4, two(0xF000, 0xF000), two(0xFFC0, 0xFF00), "Ii#3ys", cfloat },
2942: {"fmovemd", 4, two(0xF000, 0xF000), two(0xFFC0, 0xFF00), "Iil3ys", cfloat },
2943:
2944: {"fmovemx", 4, two(0xF000, 0xF800), two(0xF1C0, 0xFF8F), "IiDk&s", mfloat },
2945: {"fmovemx", 4, two(0xF020, 0xE800), two(0xF1F8, 0xFF8F), "IiDk-s", mfloat },
2946: {"fmovemx", 4, two(0xF000, 0xD800), two(0xF1C0, 0xFF8F), "Ii&sDk", mfloat },
2947: {"fmovemx", 4, two(0xF018, 0xD800), two(0xF1F8, 0xFF8F), "Ii+sDk", mfloat },
2948: {"fmovemx", 4, two(0xF000, 0xF000), two(0xF1C0, 0xFF00), "Idl3&s", mfloat },
2949: {"fmovemx", 4, two(0xF000, 0xF000), two(0xF1C0, 0xFF00), "Id#3&s", mfloat },
2950: {"fmovemx", 4, two(0xF000, 0xD000), two(0xF1C0, 0xFF00), "Id&sl3", mfloat },
2951: {"fmovemx", 4, two(0xF000, 0xD000), two(0xF1C0, 0xFF00), "Id&s#3", mfloat },
2952: {"fmovemx", 4, two(0xF020, 0xE000), two(0xF1F8, 0xFF00), "IdL3-s", mfloat },
2953: {"fmovemx", 4, two(0xF020, 0xE000), two(0xF1F8, 0xFF00), "Id#3-s", mfloat },
2954: {"fmovemx", 4, two(0xF018, 0xD000), two(0xF1F8, 0xFF00), "Id+sl3", mfloat },
2955: {"fmovemx", 4, two(0xF018, 0xD000), two(0xF1F8, 0xFF00), "Id+s#3", mfloat },
2956:
2957: {"fmoveml", 4, two(0xF000, 0xA000), two(0xF1C0, 0xE3FF), "Iis8%s", mfloat },
2958: {"fmoveml", 4, two(0xF000, 0xA000), two(0xF1C0, 0xE3FF), "IiL8~s", mfloat },
2959: /* FIXME: In the next instruction, we should only permit %dn if the
2960: target is a single register. We should only permit %an if the
2961: target is a single %fpiar. */
2962: {"fmoveml", 4, two(0xF000, 0x8000), two(0xF1C0, 0xE3FF), "Ii*lL8", mfloat },
2963:
2964: {"fmovem", 4, two(0xF000, 0xD000), two(0xFFC0, 0xFF00), "IizsL3", cfloat },
2965: {"fmovem", 4, two(0xF000, 0xD000), two(0xFFC0, 0xFF00), "Iizs#3", cfloat },
2966: {"fmovem", 4, two(0xF000, 0xF000), two(0xFFC0, 0xFF00), "Ii#3ys", cfloat },
2967: {"fmovem", 4, two(0xF000, 0xF000), two(0xFFC0, 0xFF00), "IiL3ys", cfloat },
2968:
2969: {"fmovem", 4, two(0xF020, 0xE000), two(0xF1F8, 0xFF00), "IdL3-s", mfloat },
2970: {"fmovem", 4, two(0xF000, 0xF000), two(0xF1C0, 0xFF00), "Idl3&s", mfloat },
2971: {"fmovem", 4, two(0xF018, 0xD000), two(0xF1F8, 0xFF00), "Id+sl3", mfloat },
2972: {"fmovem", 4, two(0xF000, 0xD000), two(0xF1C0, 0xFF00), "Id&sl3", mfloat },
2973: {"fmovem", 4, two(0xF020, 0xE000), two(0xF1F8, 0xFF00), "Id#3-s", mfloat },
2974: {"fmovem", 4, two(0xF020, 0xE800), two(0xF1F8, 0xFF8F), "IiDk-s", mfloat },
2975: {"fmovem", 4, two(0xF000, 0xF000), two(0xF1C0, 0xFF00), "Id#3&s", mfloat },
2976: {"fmovem", 4, two(0xF000, 0xF800), two(0xF1C0, 0xFF8F), "IiDk&s", mfloat },
2977: {"fmovem", 4, two(0xF018, 0xD000), two(0xF1F8, 0xFF00), "Id+s#3", mfloat },
2978: {"fmovem", 4, two(0xF018, 0xD800), two(0xF1F8, 0xFF8F), "Ii+sDk", mfloat },
2979: {"fmovem", 4, two(0xF000, 0xD000), two(0xF1C0, 0xFF00), "Id&s#3", mfloat },
2980: {"fmovem", 4, two(0xF000, 0xD800), two(0xF1C0, 0xFF8F), "Ii&sDk", mfloat },
2981: {"fmovem", 4, two(0xF000, 0xA000), two(0xF1C0, 0xE3FF), "Iis8%s", mfloat },
2982: {"fmovem", 4, two(0xF000, 0x8000), two(0xF1C0, 0xE3FF), "Ii*ss8", mfloat },
2983: {"fmovem", 4, two(0xF000, 0xA000), two(0xF1C0, 0xE3FF), "IiL8~s", mfloat },
2984: {"fmovem", 4, two(0xF000, 0x8000), two(0xF2C0, 0xE3FF), "Ii*sL8", mfloat },
2985:
2986: {"fmulb", 4, two(0xF000, 0x5823), two(0xF1C0, 0xFC7F), "Ii;bF7", mfloat },
2987: {"fmulb", 4, two(0xF000, 0x5823), two(0xF1C0, 0xFC7F), "IibsF7", cfloat },
2988: {"fmuld", 4, two(0xF000, 0x0023), two(0xF1C0, 0xE07F), "IiF8F7", cfloat },
2989: {"fmuld", 4, two(0xF000, 0x5423), two(0xF1C0, 0xFC7F), "Ii;FF7", mfloat },
2990: {"fmuld", 4, two(0xF000, 0x5423), two(0xF1C0, 0xFC7F), "IiwsF7", cfloat },
2991: {"fmull", 4, two(0xF000, 0x4023), two(0xF1C0, 0xFC7F), "Ii;lF7", mfloat },
2992: {"fmull", 4, two(0xF000, 0x4023), two(0xF1C0, 0xFC7F), "IibsF7", cfloat },
2993: {"fmulp", 4, two(0xF000, 0x4C23), two(0xF1C0, 0xFC7F), "Ii;pF7", mfloat },
2994: {"fmuls", 4, two(0xF000, 0x4423), two(0xF1C0, 0xFC7F), "Ii;fF7", mfloat },
2995: {"fmuls", 4, two(0xF000, 0x4423), two(0xF1C0, 0xFC7F), "IibsF7", cfloat },
2996: {"fmulw", 4, two(0xF000, 0x5023), two(0xF1C0, 0xFC7F), "Ii;wF7", mfloat },
2997: {"fmulw", 4, two(0xF000, 0x5023), two(0xF1C0, 0xFC7F), "IibsF7", cfloat },
2998: {"fmulx", 4, two(0xF000, 0x0023), two(0xF1C0, 0xE07F), "IiF8F7", mfloat },
2999: {"fmulx", 4, two(0xF000, 0x4823), two(0xF1C0, 0xFC7F), "Ii;xF7", mfloat },
3000:
3001: {"fsmulb", 4, two(0xF000, 0x5863), two(0xF1C0, 0xFC7F), "Ii;bF7", m68040up },
3002: {"fsmulb", 4, two(0xF000, 0x5863), two(0xF1C0, 0xFC7F), "IibsF7", cfloat },
3003: {"fsmuld", 4, two(0xF000, 0x0063), two(0xF1C0, 0xE07F), "IiF8F7", cfloat },
3004: {"fsmuld", 4, two(0xF000, 0x5463), two(0xF1C0, 0xFC7F), "Ii;FF7", m68040up },
3005: {"fsmuld", 4, two(0xF000, 0x5463), two(0xF1C0, 0xFC7F), "IiwsF7", cfloat },
3006: {"fsmull", 4, two(0xF000, 0x4063), two(0xF1C0, 0xFC7F), "Ii;lF7", m68040up },
3007: {"fsmull", 4, two(0xF000, 0x4063), two(0xF1C0, 0xFC7F), "IibsF7", cfloat },
3008: {"fsmulp", 4, two(0xF000, 0x4C63), two(0xF1C0, 0xFC7F), "Ii;pF7", m68040up },
3009: {"fsmuls", 4, two(0xF000, 0x4463), two(0xF1C0, 0xFC7F), "Ii;fF7", m68040up },
3010: {"fsmuls", 4, two(0xF000, 0x4463), two(0xF1C0, 0xFC7F), "IibsF7", cfloat },
3011: {"fsmulw", 4, two(0xF000, 0x5063), two(0xF1C0, 0xFC7F), "Ii;wF7", m68040up },
3012: {"fsmulw", 4, two(0xF000, 0x5063), two(0xF1C0, 0xFC7F), "IibsF7", cfloat },
3013: {"fsmulx", 4, two(0xF000, 0x0063), two(0xF1C0, 0xE07F), "IiF8F7", m68040up },
3014: {"fsmulx", 4, two(0xF000, 0x4863), two(0xF1C0, 0xFC7F), "Ii;xF7", m68040up },
3015:
3016: {"fdmulb", 4, two(0xF000, 0x5867), two(0xF1C0, 0xFC7F), "Ii;bF7", m68040up },
3017: {"fdmulb", 4, two(0xF000, 0x5867), two(0xF1C0, 0xFC7F), "IibsF7", cfloat },
3018: {"fdmuld", 4, two(0xF000, 0x0067), two(0xF1C0, 0xE07F), "IiF8F7", cfloat },
3019: {"fdmuld", 4, two(0xF000, 0x5467), two(0xF1C0, 0xFC7F), "Ii;FF7", m68040up },
3020: {"fdmuld", 4, two(0xF000, 0x5467), two(0xF1C0, 0xFC7F), "IiwsF7", cfloat },
3021: {"fdmull", 4, two(0xF000, 0x4067), two(0xF1C0, 0xFC7F), "Ii;lF7", m68040up },
3022: {"fdmull", 4, two(0xF000, 0x4067), two(0xF1C0, 0xFC7F), "IibsF7", cfloat },
3023: {"fdmulp", 4, two(0xF000, 0x4C67), two(0xF1C0, 0xFC7F), "Ii;pF7", m68040up },
3024: {"fdmuls", 4, two(0xF000, 0x4467), two(0xF1C0, 0xFC7F), "Ii;fF7", m68040up },
3025: {"fdmuls", 4, two(0xF000, 0x4467), two(0xF1C0, 0xFC7F), "IibsF7", cfloat },
3026: {"fdmulw", 4, two(0xF000, 0x5067), two(0xF1C0, 0xFC7F), "Ii;wF7", m68040up },
3027: {"fdmulw", 4, two(0xF000, 0x5067), two(0xF1C0, 0xFC7F), "IibsF7", cfloat },
3028: {"fdmulx", 4, two(0xF000, 0x0067), two(0xF1C0, 0xE07F), "IiF8F7", m68040up },
3029: {"fdmulx", 4, two(0xF000, 0x4867), two(0xF1C0, 0xFC7F), "Ii;xF7", m68040up },
3030:
3031: {"fnegb", 4, two(0xF000, 0x581A), two(0xF1C0, 0xFC7F), "Ii;bF7", mfloat },
3032: {"fnegb", 4, two(0xF000, 0x581A), two(0xF1C0, 0xFC7F), "IibsF7", cfloat },
3033: {"fnegd", 4, two(0xF000, 0x001A), two(0xF1C0, 0xE07F), "IiF8F7", cfloat },
3034: {"fnegd", 4, two(0xF000, 0x001A), two(0xF1C0, 0xE07F), "IiFt", cfloat },
3035: {"fnegd", 4, two(0xF000, 0x541A), two(0xF1C0, 0xFC7F), "Ii;FF7", mfloat },
3036: {"fnegd", 4, two(0xF000, 0x541A), two(0xF1C0, 0xFC7F), "IiwsF7", cfloat },
3037: {"fnegl", 4, two(0xF000, 0x401A), two(0xF1C0, 0xFC7F), "Ii;lF7", mfloat },
3038: {"fnegl", 4, two(0xF000, 0x401A), two(0xF1C0, 0xFC7F), "IibsF7", cfloat },
3039: {"fnegp", 4, two(0xF000, 0x4C1A), two(0xF1C0, 0xFC7F), "Ii;pF7", mfloat },
3040: {"fnegs", 4, two(0xF000, 0x441A), two(0xF1C0, 0xFC7F), "Ii;fF7", mfloat },
3041: {"fnegs", 4, two(0xF000, 0x441A), two(0xF1C0, 0xFC7F), "IibsF7", cfloat },
3042: {"fnegw", 4, two(0xF000, 0x501A), two(0xF1C0, 0xFC7F), "Ii;wF7", mfloat },
3043: {"fnegw", 4, two(0xF000, 0x501A), two(0xF1C0, 0xFC7F), "IibsF7", cfloat },
3044: {"fnegx", 4, two(0xF000, 0x001A), two(0xF1C0, 0xE07F), "IiF8F7", mfloat },
3045: {"fnegx", 4, two(0xF000, 0x481A), two(0xF1C0, 0xFC7F), "Ii;xF7", mfloat },
3046: {"fnegx", 4, two(0xF000, 0x001A), two(0xF1C0, 0xE07F), "IiFt", mfloat },
3047:
3048: {"fsnegb", 4, two(0xF000, 0x585A), two(0xF1C0, 0xFC7F), "Ii;bF7", m68040up },
3049: {"fsnegb", 4, two(0xF000, 0x585A), two(0xF1C0, 0xFC7F), "IibsF7", cfloat },
3050: {"fsnegd", 4, two(0xF000, 0x005A), two(0xF1C0, 0xE07F), "IiF8F7", cfloat },
3051: {"fsnegd", 4, two(0xF000, 0x005A), two(0xF1C0, 0xE07F), "IiFt", cfloat },
3052: {"fsnegd", 4, two(0xF000, 0x545A), two(0xF1C0, 0xFC7F), "Ii;FF7", m68040up },
3053: {"fsnegd", 4, two(0xF000, 0x545A), two(0xF1C0, 0xFC7F), "IiwsF7", cfloat },
3054: {"fsnegl", 4, two(0xF000, 0x405A), two(0xF1C0, 0xFC7F), "Ii;lF7", m68040up },
3055: {"fsnegl", 4, two(0xF000, 0x405A), two(0xF1C0, 0xFC7F), "IibsF7", cfloat },
3056: {"fsnegp", 4, two(0xF000, 0x4C5A), two(0xF1C0, 0xFC7F), "Ii;pF7", m68040up },
3057: {"fsnegs", 4, two(0xF000, 0x445A), two(0xF1C0, 0xFC7F), "Ii;fF7", m68040up },
3058: {"fsnegs", 4, two(0xF000, 0x445A), two(0xF1C0, 0xFC7F), "IibsF7", cfloat },
3059: {"fsnegw", 4, two(0xF000, 0x505A), two(0xF1C0, 0xFC7F), "Ii;wF7", m68040up },
3060: {"fsnegw", 4, two(0xF000, 0x505A), two(0xF1C0, 0xFC7F), "IibsF7", cfloat },
3061: {"fsnegx", 4, two(0xF000, 0x005A), two(0xF1C0, 0xE07F), "IiF8F7", m68040up },
3062: {"fsnegx", 4, two(0xF000, 0x485A), two(0xF1C0, 0xFC7F), "Ii;xF7", m68040up },
3063: {"fsnegx", 4, two(0xF000, 0x005A), two(0xF1C0, 0xE07F), "IiFt", m68040up },
3064:
3065: {"fdnegb", 4, two(0xF000, 0x585E), two(0xF1C0, 0xFC7F), "Ii;bF7", m68040up },
3066: {"fdnegb", 4, two(0xF000, 0x585E), two(0xF1C0, 0xFC7F), "IibsF7", cfloat },
3067: {"fdnegd", 4, two(0xF000, 0x005E), two(0xF1C0, 0xE07F), "IiF8F7", cfloat },
3068: {"fdnegd", 4, two(0xF000, 0x005E), two(0xF1C0, 0xE07F), "IiFt", cfloat },
3069: {"fdnegd", 4, two(0xF000, 0x545E), two(0xF1C0, 0xFC7F), "Ii;FF7", m68040up },
3070: {"fdnegd", 4, two(0xF000, 0x545E), two(0xF1C0, 0xFC7F), "IiwsF7", cfloat },
3071: {"fdnegl", 4, two(0xF000, 0x405E), two(0xF1C0, 0xFC7F), "Ii;lF7", m68040up },
3072: {"fdnegl", 4, two(0xF000, 0x405E), two(0xF1C0, 0xFC7F), "IibsF7", cfloat },
3073: {"fdnegp", 4, two(0xF000, 0x4C5E), two(0xF1C0, 0xFC7F), "Ii;pF7", m68040up },
3074: {"fdnegs", 4, two(0xF000, 0x445E), two(0xF1C0, 0xFC7F), "Ii;fF7", m68040up },
3075: {"fdnegs", 4, two(0xF000, 0x445E), two(0xF1C0, 0xFC7F), "IibsF7", cfloat },
3076: {"fdnegw", 4, two(0xF000, 0x505E), two(0xF1C0, 0xFC7F), "Ii;wF7", m68040up },
3077: {"fdnegw", 4, two(0xF000, 0x505E), two(0xF1C0, 0xFC7F), "IibsF7", cfloat },
3078: {"fdnegx", 4, two(0xF000, 0x005E), two(0xF1C0, 0xE07F), "IiF8F7", m68040up },
3079: {"fdnegx", 4, two(0xF000, 0x485E), two(0xF1C0, 0xFC7F), "Ii;xF7", m68040up },
3080: {"fdnegx", 4, two(0xF000, 0x005E), two(0xF1C0, 0xE07F), "IiFt", m68040up },
3081:
3082: {"fnop", 4, two(0xF280, 0x0000), two(0xFFFF, 0xFFFF), "Ii", mfloat | cfloat },
3083:
3084: {"fremb", 4, two(0xF000, 0x5825), two(0xF1C0, 0xFC7F), "Ii;bF7", mfloat },
3085: {"fremd", 4, two(0xF000, 0x5425), two(0xF1C0, 0xFC7F), "Ii;FF7", mfloat },
3086: {"freml", 4, two(0xF000, 0x4025), two(0xF1C0, 0xFC7F), "Ii;lF7", mfloat },
3087: {"fremp", 4, two(0xF000, 0x4C25), two(0xF1C0, 0xFC7F), "Ii;pF7", mfloat },
3088: {"frems", 4, two(0xF000, 0x4425), two(0xF1C0, 0xFC7F), "Ii;fF7", mfloat },
3089: {"fremw", 4, two(0xF000, 0x5025), two(0xF1C0, 0xFC7F), "Ii;wF7", mfloat },
3090: {"fremx", 4, two(0xF000, 0x0025), two(0xF1C0, 0xE07F), "IiF8F7", mfloat },
3091: {"fremx", 4, two(0xF000, 0x4825), two(0xF1C0, 0xFC7F), "Ii;xF7", mfloat },
3092:
3093: {"frestore", 2, one(0xF140), one(0xF1C0), "Id<s", mfloat },
3094: {"frestore", 2, one(0xF140), one(0xF1C0), "Idys", cfloat },
3095:
3096: {"fsave", 2, one(0xF100), one(0xF1C0), "Id>s", mfloat },
3097: {"fsave", 2, one(0xF100), one(0xF1C0), "Idzs", cfloat },
3098:
3099: {"fscaleb", 4, two(0xF000, 0x5826), two(0xF1C0, 0xFC7F), "Ii;bF7", mfloat },
3100: {"fscaled", 4, two(0xF000, 0x5426), two(0xF1C0, 0xFC7F), "Ii;FF7", mfloat },
3101: {"fscalel", 4, two(0xF000, 0x4026), two(0xF1C0, 0xFC7F), "Ii;lF7", mfloat },
3102: {"fscalep", 4, two(0xF000, 0x4C26), two(0xF1C0, 0xFC7F), "Ii;pF7", mfloat },
3103: {"fscales", 4, two(0xF000, 0x4426), two(0xF1C0, 0xFC7F), "Ii;fF7", mfloat },
3104: {"fscalew", 4, two(0xF000, 0x5026), two(0xF1C0, 0xFC7F), "Ii;wF7", mfloat },
3105: {"fscalex", 4, two(0xF000, 0x0026), two(0xF1C0, 0xE07F), "IiF8F7", mfloat },
3106: {"fscalex", 4, two(0xF000, 0x4826), two(0xF1C0, 0xFC7F), "Ii;xF7", mfloat },
3107:
3108: /* $ is necessary to prevent the assembler from using PC-relative.
3109: If @ were used, "label: fseq label" could produce "ftrapeq", 2,
3110: because "label" became "pc@label". */
3111: {"fseq", 4, two(0xF040, 0x0001), two(0xF1C0, 0xFFFF), "Ii$s", mfloat },
3112: {"fsf", 4, two(0xF040, 0x0000), two(0xF1C0, 0xFFFF), "Ii$s", mfloat },
3113: {"fsge", 4, two(0xF040, 0x0013), two(0xF1C0, 0xFFFF), "Ii$s", mfloat },
3114: {"fsgl", 4, two(0xF040, 0x0016), two(0xF1C0, 0xFFFF), "Ii$s", mfloat },
3115: {"fsgle", 4, two(0xF040, 0x0017), two(0xF1C0, 0xFFFF), "Ii$s", mfloat },
3116: {"fsgt", 4, two(0xF040, 0x0012), two(0xF1C0, 0xFFFF), "Ii$s", mfloat },
3117: {"fsle", 4, two(0xF040, 0x0015), two(0xF1C0, 0xFFFF), "Ii$s", mfloat },
3118: {"fslt", 4, two(0xF040, 0x0014), two(0xF1C0, 0xFFFF), "Ii$s", mfloat },
3119: {"fsne", 4, two(0xF040, 0x000E), two(0xF1C0, 0xFFFF), "Ii$s", mfloat },
3120: {"fsnge", 4, two(0xF040, 0x001C), two(0xF1C0, 0xFFFF), "Ii$s", mfloat },
3121: {"fsngl", 4, two(0xF040, 0x0019), two(0xF1C0, 0xFFFF), "Ii$s", mfloat },
3122: {"fsngle", 4, two(0xF040, 0x0018), two(0xF1C0, 0xFFFF), "Ii$s", mfloat },
3123: {"fsngt", 4, two(0xF040, 0x001D), two(0xF1C0, 0xFFFF), "Ii$s", mfloat },
3124: {"fsnle", 4, two(0xF040, 0x001A), two(0xF1C0, 0xFFFF), "Ii$s", mfloat },
3125: {"fsnlt", 4, two(0xF040, 0x001B), two(0xF1C0, 0xFFFF), "Ii$s", mfloat },
3126: {"fsoge", 4, two(0xF040, 0x0003), two(0xF1C0, 0xFFFF), "Ii$s", mfloat },
3127: {"fsogl", 4, two(0xF040, 0x0006), two(0xF1C0, 0xFFFF), "Ii$s", mfloat },
3128: {"fsogt", 4, two(0xF040, 0x0002), two(0xF1C0, 0xFFFF), "Ii$s", mfloat },
3129: {"fsole", 4, two(0xF040, 0x0005), two(0xF1C0, 0xFFFF), "Ii$s", mfloat },
3130: {"fsolt", 4, two(0xF040, 0x0004), two(0xF1C0, 0xFFFF), "Ii$s", mfloat },
3131: {"fsor", 4, two(0xF040, 0x0007), two(0xF1C0, 0xFFFF), "Ii$s", mfloat },
3132: {"fsseq", 4, two(0xF040, 0x0011), two(0xF1C0, 0xFFFF), "Ii$s", mfloat },
3133: {"fssf", 4, two(0xF040, 0x0010), two(0xF1C0, 0xFFFF), "Ii$s", mfloat },
3134: {"fssne", 4, two(0xF040, 0x001E), two(0xF1C0, 0xFFFF), "Ii$s", mfloat },
3135: {"fsst", 4, two(0xF040, 0x001F), two(0xF1C0, 0xFFFF), "Ii$s", mfloat },
3136: {"fst", 4, two(0xF040, 0x000F), two(0xF1C0, 0xFFFF), "Ii$s", mfloat },
3137: {"fsueq", 4, two(0xF040, 0x0009), two(0xF1C0, 0xFFFF), "Ii$s", mfloat },
3138: {"fsuge", 4, two(0xF040, 0x000B), two(0xF1C0, 0xFFFF), "Ii$s", mfloat },
3139: {"fsugt", 4, two(0xF040, 0x000A), two(0xF1C0, 0xFFFF), "Ii$s", mfloat },
3140: {"fsule", 4, two(0xF040, 0x000D), two(0xF1C0, 0xFFFF), "Ii$s", mfloat },
3141: {"fsult", 4, two(0xF040, 0x000C), two(0xF1C0, 0xFFFF), "Ii$s", mfloat },
3142: {"fsun", 4, two(0xF040, 0x0008), two(0xF1C0, 0xFFFF), "Ii$s", mfloat },
3143:
3144: {"fsgldivb", 4, two(0xF000, 0x5824), two(0xF1C0, 0xFC7F), "Ii;bF7", mfloat },
3145: {"fsgldivd", 4, two(0xF000, 0x5424), two(0xF1C0, 0xFC7F), "Ii;FF7", mfloat },
3146: {"fsgldivl", 4, two(0xF000, 0x4024), two(0xF1C0, 0xFC7F), "Ii;lF7", mfloat },
3147: {"fsgldivp", 4, two(0xF000, 0x4C24), two(0xF1C0, 0xFC7F), "Ii;pF7", mfloat },
3148: {"fsgldivs", 4, two(0xF000, 0x4424), two(0xF1C0, 0xFC7F), "Ii;fF7", mfloat },
3149: {"fsgldivw", 4, two(0xF000, 0x5024), two(0xF1C0, 0xFC7F), "Ii;wF7", mfloat },
3150: {"fsgldivx", 4, two(0xF000, 0x0024), two(0xF1C0, 0xE07F), "IiF8F7", mfloat },
3151: {"fsgldivx", 4, two(0xF000, 0x4824), two(0xF1C0, 0xFC7F), "Ii;xF7", mfloat },
3152: {"fsgldivx", 4, two(0xF000, 0x0024), two(0xF1C0, 0xE07F), "IiFt", mfloat },
3153:
3154: {"fsglmulb", 4, two(0xF000, 0x5827), two(0xF1C0, 0xFC7F), "Ii;bF7", mfloat },
3155: {"fsglmuld", 4, two(0xF000, 0x5427), two(0xF1C0, 0xFC7F), "Ii;FF7", mfloat },
3156: {"fsglmull", 4, two(0xF000, 0x4027), two(0xF1C0, 0xFC7F), "Ii;lF7", mfloat },
3157: {"fsglmulp", 4, two(0xF000, 0x4C27), two(0xF1C0, 0xFC7F), "Ii;pF7", mfloat },
3158: {"fsglmuls", 4, two(0xF000, 0x4427), two(0xF1C0, 0xFC7F), "Ii;fF7", mfloat },
3159: {"fsglmulw", 4, two(0xF000, 0x5027), two(0xF1C0, 0xFC7F), "Ii;wF7", mfloat },
3160: {"fsglmulx", 4, two(0xF000, 0x0027), two(0xF1C0, 0xE07F), "IiF8F7", mfloat },
3161: {"fsglmulx", 4, two(0xF000, 0x4827), two(0xF1C0, 0xFC7F), "Ii;xF7", mfloat },
3162: {"fsglmulx", 4, two(0xF000, 0x0027), two(0xF1C0, 0xE07F), "IiFt", mfloat },
3163:
3164: {"fsinb", 4, two(0xF000, 0x580E), two(0xF1C0, 0xFC7F), "Ii;bF7", mfloat },
3165: {"fsind", 4, two(0xF000, 0x540E), two(0xF1C0, 0xFC7F), "Ii;FF7", mfloat },
3166: {"fsinl", 4, two(0xF000, 0x400E), two(0xF1C0, 0xFC7F), "Ii;lF7", mfloat },
3167: {"fsinp", 4, two(0xF000, 0x4C0E), two(0xF1C0, 0xFC7F), "Ii;pF7", mfloat },
3168: {"fsins", 4, two(0xF000, 0x440E), two(0xF1C0, 0xFC7F), "Ii;fF7", mfloat },
3169: {"fsinw", 4, two(0xF000, 0x500E), two(0xF1C0, 0xFC7F), "Ii;wF7", mfloat },
3170: {"fsinx", 4, two(0xF000, 0x000E), two(0xF1C0, 0xE07F), "IiF8F7", mfloat },
3171: {"fsinx", 4, two(0xF000, 0x480E), two(0xF1C0, 0xFC7F), "Ii;xF7", mfloat },
3172: {"fsinx", 4, two(0xF000, 0x000E), two(0xF1C0, 0xE07F), "IiFt", mfloat },
3173:
3174: {"fsincosb", 4, two(0xF000, 0x5830), two(0xF1C0, 0xFC78), "Ii;bF3F7", mfloat },
3175: {"fsincosd", 4, two(0xF000, 0x5430), two(0xF1C0, 0xFC78), "Ii;FF3F7", mfloat },
3176: {"fsincosl", 4, two(0xF000, 0x4030), two(0xF1C0, 0xFC78), "Ii;lF3F7", mfloat },
3177: {"fsincosp", 4, two(0xF000, 0x4C30), two(0xF1C0, 0xFC78), "Ii;pF3F7", mfloat },
3178: {"fsincoss", 4, two(0xF000, 0x4430), two(0xF1C0, 0xFC78), "Ii;fF3F7", mfloat },
3179: {"fsincosw", 4, two(0xF000, 0x5030), two(0xF1C0, 0xFC78), "Ii;wF3F7", mfloat },
3180: {"fsincosx", 4, two(0xF000, 0x0030), two(0xF1C0, 0xE078), "IiF8F3F7", mfloat },
3181: {"fsincosx", 4, two(0xF000, 0x4830), two(0xF1C0, 0xFC78), "Ii;xF3F7", mfloat },
3182:
3183: {"fsinhb", 4, two(0xF000, 0x5802), two(0xF1C0, 0xFC7F), "Ii;bF7", mfloat },
3184: {"fsinhd", 4, two(0xF000, 0x5402), two(0xF1C0, 0xFC7F), "Ii;FF7", mfloat },
3185: {"fsinhl", 4, two(0xF000, 0x4002), two(0xF1C0, 0xFC7F), "Ii;lF7", mfloat },
3186: {"fsinhp", 4, two(0xF000, 0x4C02), two(0xF1C0, 0xFC7F), "Ii;pF7", mfloat },
3187: {"fsinhs", 4, two(0xF000, 0x4402), two(0xF1C0, 0xFC7F), "Ii;fF7", mfloat },
3188: {"fsinhw", 4, two(0xF000, 0x5002), two(0xF1C0, 0xFC7F), "Ii;wF7", mfloat },
3189: {"fsinhx", 4, two(0xF000, 0x0002), two(0xF1C0, 0xE07F), "IiF8F7", mfloat },
3190: {"fsinhx", 4, two(0xF000, 0x4802), two(0xF1C0, 0xFC7F), "Ii;xF7", mfloat },
3191: {"fsinhx", 4, two(0xF000, 0x0002), two(0xF1C0, 0xE07F), "IiFt", mfloat },
3192:
3193: {"fsqrtb", 4, two(0xF000, 0x5804), two(0xF1C0, 0xFC7F), "Ii;bF7", mfloat },
3194: {"fsqrtb", 4, two(0xF000, 0x5804), two(0xF1C0, 0xFC7F), "IibsF7", cfloat },
3195: {"fsqrtd", 4, two(0xF000, 0x0004), two(0xF1C0, 0xE07F), "IiF8F7", cfloat },
3196: {"fsqrtd", 4, two(0xF000, 0x0004), two(0xF1C0, 0xE07F), "IiFt", cfloat },
3197: {"fsqrtd", 4, two(0xF000, 0x5404), two(0xF1C0, 0xFC7F), "Ii;FF7", mfloat },
3198: {"fsqrtd", 4, two(0xF000, 0x5404), two(0xF1C0, 0xFC7F), "IiwsF7", cfloat },
3199: {"fsqrtl", 4, two(0xF000, 0x4004), two(0xF1C0, 0xFC7F), "Ii;lF7", mfloat },
3200: {"fsqrtl", 4, two(0xF000, 0x4004), two(0xF1C0, 0xFC7F), "IibsF7", cfloat },
3201: {"fsqrtp", 4, two(0xF000, 0x4C04), two(0xF1C0, 0xFC7F), "Ii;pF7", mfloat },
3202: {"fsqrts", 4, two(0xF000, 0x4404), two(0xF1C0, 0xFC7F), "Ii;fF7", mfloat },
3203: {"fsqrts", 4, two(0xF000, 0x4404), two(0xF1C0, 0xFC7F), "IibsF7", cfloat },
3204: {"fsqrtw", 4, two(0xF000, 0x5004), two(0xF1C0, 0xFC7F), "Ii;wF7", mfloat },
3205: {"fsqrtw", 4, two(0xF000, 0x5004), two(0xF1C0, 0xFC7F), "IibsF7", cfloat },
3206: {"fsqrtx", 4, two(0xF000, 0x0004), two(0xF1C0, 0xE07F), "IiF8F7", mfloat },
3207: {"fsqrtx", 4, two(0xF000, 0x4804), two(0xF1C0, 0xFC7F), "Ii;xF7", mfloat },
3208: {"fsqrtx", 4, two(0xF000, 0x0004), two(0xF1C0, 0xE07F), "IiFt", mfloat },
3209:
3210: {"fssqrtb", 4, two(0xF000, 0x5841), two(0xF1C0, 0xFC7F), "Ii;bF7", m68040up },
3211: {"fssqrtb", 4, two(0xF000, 0x5841), two(0xF1C0, 0xFC7F), "IibsF7", cfloat },
3212: {"fssqrtd", 4, two(0xF000, 0x0041), two(0xF1C0, 0xE07F), "IiF8F7", cfloat },
3213: {"fssqrtd", 4, two(0xF000, 0x0041), two(0xF1C0, 0xE07F), "IiFt", cfloat },
3214: {"fssqrtd", 4, two(0xF000, 0x5441), two(0xF1C0, 0xFC7F), "Ii;FF7", m68040up },
3215: {"fssqrtd", 4, two(0xF000, 0x5441), two(0xF1C0, 0xFC7F), "IiwsF7", cfloat },
3216: {"fssqrtl", 4, two(0xF000, 0x4041), two(0xF1C0, 0xFC7F), "Ii;lF7", m68040up },
3217: {"fssqrtl", 4, two(0xF000, 0x4041), two(0xF1C0, 0xFC7F), "IibsF7", cfloat },
3218: {"fssqrtp", 4, two(0xF000, 0x4C41), two(0xF1C0, 0xFC7F), "Ii;pF7", m68040up },
3219: {"fssqrts", 4, two(0xF000, 0x4441), two(0xF1C0, 0xFC7F), "Ii;fF7", m68040up },
3220: {"fssqrts", 4, two(0xF000, 0x4441), two(0xF1C0, 0xFC7F), "IibsF7", cfloat },
3221: {"fssqrtw", 4, two(0xF000, 0x5041), two(0xF1C0, 0xFC7F), "Ii;wF7", m68040up },
3222: {"fssqrtw", 4, two(0xF000, 0x5041), two(0xF1C0, 0xFC7F), "IibsF7", cfloat },
3223: {"fssqrtx", 4, two(0xF000, 0x0041), two(0xF1C0, 0xE07F), "IiF8F7", m68040up },
3224: {"fssqrtx", 4, two(0xF000, 0x4841), two(0xF1C0, 0xFC7F), "Ii;xF7", m68040up },
3225: {"fssqrtx", 4, two(0xF000, 0x0041), two(0xF1C0, 0xE07F), "IiFt", m68040up },
3226:
3227: {"fdsqrtb", 4, two(0xF000, 0x5845), two(0xF1C0, 0xFC7F), "Ii;bF7", m68040up },
3228: {"fdsqrtb", 4, two(0xF000, 0x5845), two(0xF1C0, 0xFC7F), "IibsF7", cfloat },
3229: {"fdsqrtd", 4, two(0xF000, 0x0045), two(0xF1C0, 0xE07F), "IiF8F7", cfloat },
3230: {"fdsqrtd", 4, two(0xF000, 0x0045), two(0xF1C0, 0xE07F), "IiFt", cfloat },
3231: {"fdsqrtd", 4, two(0xF000, 0x5445), two(0xF1C0, 0xFC7F), "Ii;FF7", m68040up },
3232: {"fdsqrtl", 4, two(0xF000, 0x4045), two(0xF1C0, 0xFC7F), "Ii;lF7", m68040up },
3233: {"fdsqrtl", 4, two(0xF000, 0x4045), two(0xF1C0, 0xFC7F), "IibsF7", cfloat },
3234: {"fdsqrtp", 4, two(0xF000, 0x4C45), two(0xF1C0, 0xFC7F), "Ii;pF7", m68040up },
3235: {"fdsqrts", 4, two(0xF000, 0x4445), two(0xF1C0, 0xFC7F), "Ii;fF7", m68040up },
3236: {"fdsqrts", 4, two(0xF000, 0x4445), two(0xF1C0, 0xFC7F), "IibsF7", cfloat },
3237: {"fdsqrtw", 4, two(0xF000, 0x5045), two(0xF1C0, 0xFC7F), "Ii;wF7", m68040up },
3238: {"fdsqrtw", 4, two(0xF000, 0x5045), two(0xF1C0, 0xFC7F), "IibsF7", cfloat },
3239: {"fdsqrtx", 4, two(0xF000, 0x0045), two(0xF1C0, 0xE07F), "IiF8F7", m68040up },
3240: {"fdsqrtx", 4, two(0xF000, 0x4845), two(0xF1C0, 0xFC7F), "Ii;xF7", m68040up },
3241: {"fdsqrtx", 4, two(0xF000, 0x0045), two(0xF1C0, 0xE07F), "IiFt", m68040up },
3242:
3243: {"fsubb", 4, two(0xF000, 0x5828), two(0xF1C0, 0xFC7F), "Ii;bF7", mfloat },
3244: {"fsubb", 4, two(0xF000, 0x5828), two(0xF1C0, 0xFC7F), "IibsF7", cfloat },
3245: {"fsubd", 4, two(0xF000, 0x0028), two(0xF1C0, 0xE07F), "IiF8F7", cfloat },
3246: {"fsubd", 4, two(0xF000, 0x5428), two(0xF1C0, 0xFC7F), "Ii;FF7", mfloat },
3247: {"fsubd", 4, two(0xF000, 0x5428), two(0xF1C0, 0xFC7F), "IiwsF7", cfloat },
3248: {"fsubl", 4, two(0xF000, 0x4028), two(0xF1C0, 0xFC7F), "Ii;lF7", mfloat },
3249: {"fsubl", 4, two(0xF000, 0x4028), two(0xF1C0, 0xFC7F), "IibsF7", cfloat },
3250: {"fsubp", 4, two(0xF000, 0x4C28), two(0xF1C0, 0xFC7F), "Ii;pF7", mfloat },
3251: {"fsubs", 4, two(0xF000, 0x4428), two(0xF1C0, 0xFC7F), "Ii;fF7", mfloat },
3252: {"fsubs", 4, two(0xF000, 0x4428), two(0xF1C0, 0xFC7F), "IibsF7", cfloat },
3253: {"fsubw", 4, two(0xF000, 0x5028), two(0xF1C0, 0xFC7F), "Ii;wF7", mfloat },
3254: {"fsubw", 4, two(0xF000, 0x5028), two(0xF1C0, 0xFC7F), "IibsF7", cfloat },
3255: {"fsubx", 4, two(0xF000, 0x0028), two(0xF1C0, 0xE07F), "IiF8F7", mfloat },
3256: {"fsubx", 4, two(0xF000, 0x4828), two(0xF1C0, 0xFC7F), "Ii;xF7", mfloat },
3257: {"fsubx", 4, two(0xF000, 0x0028), two(0xF1C0, 0xE07F), "IiFt", mfloat },
3258:
3259: {"fssubb", 4, two(0xF000, 0x5828), two(0xF1C0, 0xFC7F), "IibsF7", cfloat },
3260: {"fssubb", 4, two(0xF000, 0x5868), two(0xF1C0, 0xFC7F), "Ii;bF7", m68040up },
3261: {"fssubd", 4, two(0xF000, 0x0068), two(0xF1C0, 0xE07F), "IiF8F7", cfloat },
3262: {"fssubd", 4, two(0xF000, 0x5468), two(0xF1C0, 0xFC7F), "Ii;FF7", m68040up },
3263: {"fssubd", 4, two(0xF000, 0x5468), two(0xF1C0, 0xFC7F), "IiwsF7", cfloat },
3264: {"fssubl", 4, two(0xF000, 0x4068), two(0xF1C0, 0xFC7F), "Ii;lF7", m68040up },
3265: {"fssubl", 4, two(0xF000, 0x4068), two(0xF1C0, 0xFC7F), "IibsF7", cfloat },
3266: {"fssubp", 4, two(0xF000, 0x4C68), two(0xF1C0, 0xFC7F), "Ii;pF7", m68040up },
3267: {"fssubs", 4, two(0xF000, 0x4468), two(0xF1C0, 0xFC7F), "Ii;fF7", m68040up },
3268: {"fssubs", 4, two(0xF000, 0x4468), two(0xF1C0, 0xFC7F), "IibsF7", cfloat },
3269: {"fssubw", 4, two(0xF000, 0x5068), two(0xF1C0, 0xFC7F), "Ii;wF7", m68040up },
3270: {"fssubw", 4, two(0xF000, 0x5068), two(0xF1C0, 0xFC7F), "IibsF7", cfloat },
3271: {"fssubx", 4, two(0xF000, 0x0068), two(0xF1C0, 0xE07F), "IiF8F7", m68040up },
3272: {"fssubx", 4, two(0xF000, 0x4868), two(0xF1C0, 0xFC7F), "Ii;xF7", m68040up },
3273: {"fssubx", 4, two(0xF000, 0x0068), two(0xF1C0, 0xE07F), "IiFt", m68040up },
3274:
3275: {"fdsubb", 4, two(0xF000, 0x586A), two(0xF1C0, 0xFC7F), "IibsF7", cfloat },
3276: {"fdsubb", 4, two(0xF000, 0x586c), two(0xF1C0, 0xFC7F), "Ii;bF7", m68040up },
3277: {"fdsubd", 4, two(0xF000, 0x006A), two(0xF1C0, 0xE07F), "IiF8F7", cfloat },
3278: {"fdsubd", 4, two(0xF000, 0x546A), two(0xF1C0, 0xFC7F), "IiwsF7", cfloat },
3279: {"fdsubd", 4, two(0xF000, 0x546c), two(0xF1C0, 0xFC7F), "Ii;FF7", m68040up },
3280: {"fdsubl", 4, two(0xF000, 0x406A), two(0xF1C0, 0xFC7F), "IibsF7", cfloat },
3281: {"fdsubl", 4, two(0xF000, 0x406c), two(0xF1C0, 0xFC7F), "Ii;lF7", m68040up },
3282: {"fdsubp", 4, two(0xF000, 0x4C6c), two(0xF1C0, 0xFC7F), "Ii;pF7", m68040up },
3283: {"fdsubs", 4, two(0xF000, 0x446A), two(0xF1C0, 0xFC7F), "IibsF7", cfloat },
3284: {"fdsubs", 4, two(0xF000, 0x446c), two(0xF1C0, 0xFC7F), "Ii;fF7", m68040up },
3285: {"fdsubw", 4, two(0xF000, 0x506A), two(0xF1C0, 0xFC7F), "IibsF7", cfloat },
3286: {"fdsubw", 4, two(0xF000, 0x506c), two(0xF1C0, 0xFC7F), "Ii;wF7", m68040up },
3287: {"fdsubx", 4, two(0xF000, 0x006c), two(0xF1C0, 0xE07F), "IiF8F7", m68040up },
3288: {"fdsubx", 4, two(0xF000, 0x486c), two(0xF1C0, 0xFC7F), "Ii;xF7", m68040up },
3289: {"fdsubx", 4, two(0xF000, 0x006c), two(0xF1C0, 0xE07F), "IiFt", m68040up },
3290:
3291: {"ftanb", 4, two(0xF000, 0x580F), two(0xF1C0, 0xFC7F), "Ii;bF7", mfloat },
3292: {"ftand", 4, two(0xF000, 0x540F), two(0xF1C0, 0xFC7F), "Ii;FF7", mfloat },
3293: {"ftanl", 4, two(0xF000, 0x400F), two(0xF1C0, 0xFC7F), "Ii;lF7", mfloat },
3294: {"ftanp", 4, two(0xF000, 0x4C0F), two(0xF1C0, 0xFC7F), "Ii;pF7", mfloat },
3295: {"ftans", 4, two(0xF000, 0x440F), two(0xF1C0, 0xFC7F), "Ii;fF7", mfloat },
3296: {"ftanw", 4, two(0xF000, 0x500F), two(0xF1C0, 0xFC7F), "Ii;wF7", mfloat },
3297: {"ftanx", 4, two(0xF000, 0x000F), two(0xF1C0, 0xE07F), "IiF8F7", mfloat },
3298: {"ftanx", 4, two(0xF000, 0x480F), two(0xF1C0, 0xFC7F), "Ii;xF7", mfloat },
3299: {"ftanx", 4, two(0xF000, 0x000F), two(0xF1C0, 0xE07F), "IiFt", mfloat },
3300:
3301: {"ftanhb", 4, two(0xF000, 0x5809), two(0xF1C0, 0xFC7F), "Ii;bF7", mfloat },
3302: {"ftanhd", 4, two(0xF000, 0x5409), two(0xF1C0, 0xFC7F), "Ii;FF7", mfloat },
3303: {"ftanhl", 4, two(0xF000, 0x4009), two(0xF1C0, 0xFC7F), "Ii;lF7", mfloat },
3304: {"ftanhp", 4, two(0xF000, 0x4C09), two(0xF1C0, 0xFC7F), "Ii;pF7", mfloat },
3305: {"ftanhs", 4, two(0xF000, 0x4409), two(0xF1C0, 0xFC7F), "Ii;fF7", mfloat },
3306: {"ftanhw", 4, two(0xF000, 0x5009), two(0xF1C0, 0xFC7F), "Ii;wF7", mfloat },
3307: {"ftanhx", 4, two(0xF000, 0x0009), two(0xF1C0, 0xE07F), "IiF8F7", mfloat },
3308: {"ftanhx", 4, two(0xF000, 0x4809), two(0xF1C0, 0xFC7F), "Ii;xF7", mfloat },
3309: {"ftanhx", 4, two(0xF000, 0x0009), two(0xF1C0, 0xE07F), "IiFt", mfloat },
3310:
3311: {"ftentoxb", 4, two(0xF000, 0x5812), two(0xF1C0, 0xFC7F), "Ii;bF7", mfloat },
3312: {"ftentoxd", 4, two(0xF000, 0x5412), two(0xF1C0, 0xFC7F), "Ii;FF7", mfloat },
3313: {"ftentoxl", 4, two(0xF000, 0x4012), two(0xF1C0, 0xFC7F), "Ii;lF7", mfloat },
3314: {"ftentoxp", 4, two(0xF000, 0x4C12), two(0xF1C0, 0xFC7F), "Ii;pF7", mfloat },
3315: {"ftentoxs", 4, two(0xF000, 0x4412), two(0xF1C0, 0xFC7F), "Ii;fF7", mfloat },
3316: {"ftentoxw", 4, two(0xF000, 0x5012), two(0xF1C0, 0xFC7F), "Ii;wF7", mfloat },
3317: {"ftentoxx", 4, two(0xF000, 0x0012), two(0xF1C0, 0xE07F), "IiF8F7", mfloat },
3318: {"ftentoxx", 4, two(0xF000, 0x4812), two(0xF1C0, 0xFC7F), "Ii;xF7", mfloat },
3319: {"ftentoxx", 4, two(0xF000, 0x0012), two(0xF1C0, 0xE07F), "IiFt", mfloat },
3320:
3321: {"ftrapeq", 4, two(0xF07C, 0x0001), two(0xF1FF, 0xFFFF), "Ii", mfloat },
3322: {"ftrapf", 4, two(0xF07C, 0x0000), two(0xF1FF, 0xFFFF), "Ii", mfloat },
3323: {"ftrapge", 4, two(0xF07C, 0x0013), two(0xF1FF, 0xFFFF), "Ii", mfloat },
3324: {"ftrapgl", 4, two(0xF07C, 0x0016), two(0xF1FF, 0xFFFF), "Ii", mfloat },
3325: {"ftrapgle", 4, two(0xF07C, 0x0017), two(0xF1FF, 0xFFFF), "Ii", mfloat },
3326: {"ftrapgt", 4, two(0xF07C, 0x0012), two(0xF1FF, 0xFFFF), "Ii", mfloat },
3327: {"ftraple", 4, two(0xF07C, 0x0015), two(0xF1FF, 0xFFFF), "Ii", mfloat },
3328: {"ftraplt", 4, two(0xF07C, 0x0014), two(0xF1FF, 0xFFFF), "Ii", mfloat },
3329: {"ftrapne", 4, two(0xF07C, 0x000E), two(0xF1FF, 0xFFFF), "Ii", mfloat },
3330: {"ftrapnge", 4, two(0xF07C, 0x001C), two(0xF1FF, 0xFFFF), "Ii", mfloat },
3331: {"ftrapngl", 4, two(0xF07C, 0x0019), two(0xF1FF, 0xFFFF), "Ii", mfloat },
3332: {"ftrapngle", 4,two(0xF07C, 0x0018), two(0xF1FF, 0xFFFF), "Ii", mfloat },
3333: {"ftrapngt", 4, two(0xF07C, 0x001D), two(0xF1FF, 0xFFFF), "Ii", mfloat },
3334: {"ftrapnle", 4, two(0xF07C, 0x001A), two(0xF1FF, 0xFFFF), "Ii", mfloat },
3335: {"ftrapnlt", 4, two(0xF07C, 0x001B), two(0xF1FF, 0xFFFF), "Ii", mfloat },
3336: {"ftrapoge", 4, two(0xF07C, 0x0003), two(0xF1FF, 0xFFFF), "Ii", mfloat },
3337: {"ftrapogl", 4, two(0xF07C, 0x0006), two(0xF1FF, 0xFFFF), "Ii", mfloat },
3338: {"ftrapogt", 4, two(0xF07C, 0x0002), two(0xF1FF, 0xFFFF), "Ii", mfloat },
3339: {"ftrapole", 4, two(0xF07C, 0x0005), two(0xF1FF, 0xFFFF), "Ii", mfloat },
3340: {"ftrapolt", 4, two(0xF07C, 0x0004), two(0xF1FF, 0xFFFF), "Ii", mfloat },
3341: {"ftrapor", 4, two(0xF07C, 0x0007), two(0xF1FF, 0xFFFF), "Ii", mfloat },
3342: {"ftrapseq", 4, two(0xF07C, 0x0011), two(0xF1FF, 0xFFFF), "Ii", mfloat },
3343: {"ftrapsf", 4, two(0xF07C, 0x0010), two(0xF1FF, 0xFFFF), "Ii", mfloat },
3344: {"ftrapsne", 4, two(0xF07C, 0x001E), two(0xF1FF, 0xFFFF), "Ii", mfloat },
3345: {"ftrapst", 4, two(0xF07C, 0x001F), two(0xF1FF, 0xFFFF), "Ii", mfloat },
3346: {"ftrapt", 4, two(0xF07C, 0x000F), two(0xF1FF, 0xFFFF), "Ii", mfloat },
3347: {"ftrapueq", 4, two(0xF07C, 0x0009), two(0xF1FF, 0xFFFF), "Ii", mfloat },
3348: {"ftrapuge", 4, two(0xF07C, 0x000B), two(0xF1FF, 0xFFFF), "Ii", mfloat },
3349: {"ftrapugt", 4, two(0xF07C, 0x000A), two(0xF1FF, 0xFFFF), "Ii", mfloat },
3350: {"ftrapule", 4, two(0xF07C, 0x000D), two(0xF1FF, 0xFFFF), "Ii", mfloat },
3351: {"ftrapult", 4, two(0xF07C, 0x000C), two(0xF1FF, 0xFFFF), "Ii", mfloat },
3352: {"ftrapun", 4, two(0xF07C, 0x0008), two(0xF1FF, 0xFFFF), "Ii", mfloat },
3353:
3354: {"ftrapeqw", 4, two(0xF07A, 0x0001), two(0xF1FF, 0xFFFF), "Ii^w", mfloat },
3355: {"ftrapfw", 4, two(0xF07A, 0x0000), two(0xF1FF, 0xFFFF), "Ii^w", mfloat },
3356: {"ftrapgew", 4, two(0xF07A, 0x0013), two(0xF1FF, 0xFFFF), "Ii^w", mfloat },
3357: {"ftrapglw", 4, two(0xF07A, 0x0016), two(0xF1FF, 0xFFFF), "Ii^w", mfloat },
3358: {"ftrapglew", 4,two(0xF07A, 0x0017), two(0xF1FF, 0xFFFF), "Ii^w", mfloat },
3359: {"ftrapgtw", 4, two(0xF07A, 0x0012), two(0xF1FF, 0xFFFF), "Ii^w", mfloat },
3360: {"ftraplew", 4, two(0xF07A, 0x0015), two(0xF1FF, 0xFFFF), "Ii^w", mfloat },
3361: {"ftrapltw", 4, two(0xF07A, 0x0014), two(0xF1FF, 0xFFFF), "Ii^w", mfloat },
3362: {"ftrapnew", 4, two(0xF07A, 0x000E), two(0xF1FF, 0xFFFF), "Ii^w", mfloat },
3363: {"ftrapngew", 4,two(0xF07A, 0x001C), two(0xF1FF, 0xFFFF), "Ii^w", mfloat },
3364: {"ftrapnglw", 4,two(0xF07A, 0x0019), two(0xF1FF, 0xFFFF), "Ii^w", mfloat },
3365: {"ftrapnglew", 4,two(0xF07A, 0x0018), two(0xF1FF, 0xFFFF), "Ii^w", mfloat },
3366: {"ftrapngtw", 4,two(0xF07A, 0x001D), two(0xF1FF, 0xFFFF), "Ii^w", mfloat },
3367: {"ftrapnlew", 4,two(0xF07A, 0x001A), two(0xF1FF, 0xFFFF), "Ii^w", mfloat },
3368: {"ftrapnltw", 4,two(0xF07A, 0x001B), two(0xF1FF, 0xFFFF), "Ii^w", mfloat },
3369: {"ftrapogew", 4,two(0xF07A, 0x0003), two(0xF1FF, 0xFFFF), "Ii^w", mfloat },
3370: {"ftrapoglw", 4,two(0xF07A, 0x0006), two(0xF1FF, 0xFFFF), "Ii^w", mfloat },
3371: {"ftrapogtw", 4,two(0xF07A, 0x0002), two(0xF1FF, 0xFFFF), "Ii^w", mfloat },
3372: {"ftrapolew", 4,two(0xF07A, 0x0005), two(0xF1FF, 0xFFFF), "Ii^w", mfloat },
3373: {"ftrapoltw", 4,two(0xF07A, 0x0004), two(0xF1FF, 0xFFFF), "Ii^w", mfloat },
3374: {"ftraporw", 4, two(0xF07A, 0x0007), two(0xF1FF, 0xFFFF), "Ii^w", mfloat },
3375: {"ftrapseqw", 4,two(0xF07A, 0x0011), two(0xF1FF, 0xFFFF), "Ii^w", mfloat },
3376: {"ftrapsfw", 4, two(0xF07A, 0x0010), two(0xF1FF, 0xFFFF), "Ii^w", mfloat },
3377: {"ftrapsnew", 4,two(0xF07A, 0x001E), two(0xF1FF, 0xFFFF), "Ii^w", mfloat },
3378: {"ftrapstw", 4, two(0xF07A, 0x001F), two(0xF1FF, 0xFFFF), "Ii^w", mfloat },
3379: {"ftraptw", 4, two(0xF07A, 0x000F), two(0xF1FF, 0xFFFF), "Ii^w", mfloat },
3380: {"ftrapueqw", 4,two(0xF07A, 0x0009), two(0xF1FF, 0xFFFF), "Ii^w", mfloat },
3381: {"ftrapugew", 4,two(0xF07A, 0x000B), two(0xF1FF, 0xFFFF), "Ii^w", mfloat },
3382: {"ftrapugtw", 4,two(0xF07A, 0x000A), two(0xF1FF, 0xFFFF), "Ii^w", mfloat },
3383: {"ftrapulew", 4,two(0xF07A, 0x000D), two(0xF1FF, 0xFFFF), "Ii^w", mfloat },
3384: {"ftrapultw", 4,two(0xF07A, 0x000C), two(0xF1FF, 0xFFFF), "Ii^w", mfloat },
3385: {"ftrapunw", 4, two(0xF07A, 0x0008), two(0xF1FF, 0xFFFF), "Ii^w", mfloat },
3386:
3387: {"ftrapeql", 4, two(0xF07B, 0x0001), two(0xF1FF, 0xFFFF), "Ii^l", mfloat },
3388: {"ftrapfl", 4, two(0xF07B, 0x0000), two(0xF1FF, 0xFFFF), "Ii^l", mfloat },
3389: {"ftrapgel", 4, two(0xF07B, 0x0013), two(0xF1FF, 0xFFFF), "Ii^l", mfloat },
3390: {"ftrapgll", 4, two(0xF07B, 0x0016), two(0xF1FF, 0xFFFF), "Ii^l", mfloat },
3391: {"ftrapglel", 4,two(0xF07B, 0x0017), two(0xF1FF, 0xFFFF), "Ii^l", mfloat },
3392: {"ftrapgtl", 4, two(0xF07B, 0x0012), two(0xF1FF, 0xFFFF), "Ii^l", mfloat },
3393: {"ftraplel", 4, two(0xF07B, 0x0015), two(0xF1FF, 0xFFFF), "Ii^l", mfloat },
3394: {"ftrapltl", 4, two(0xF07B, 0x0014), two(0xF1FF, 0xFFFF), "Ii^l", mfloat },
3395: {"ftrapnel", 4, two(0xF07B, 0x000E), two(0xF1FF, 0xFFFF), "Ii^l", mfloat },
3396: {"ftrapngel", 4,two(0xF07B, 0x001C), two(0xF1FF, 0xFFFF), "Ii^l", mfloat },
3397: {"ftrapngll", 4,two(0xF07B, 0x0019), two(0xF1FF, 0xFFFF), "Ii^l", mfloat },
3398: {"ftrapnglel", 4,two(0xF07B, 0x0018), two(0xF1FF, 0xFFFF), "Ii^l", mfloat },
3399: {"ftrapngtl", 4,two(0xF07B, 0x001D), two(0xF1FF, 0xFFFF), "Ii^l", mfloat },
3400: {"ftrapnlel", 4,two(0xF07B, 0x001A), two(0xF1FF, 0xFFFF), "Ii^l", mfloat },
3401: {"ftrapnltl", 4,two(0xF07B, 0x001B), two(0xF1FF, 0xFFFF), "Ii^l", mfloat },
3402: {"ftrapogel", 4,two(0xF07B, 0x0003), two(0xF1FF, 0xFFFF), "Ii^l", mfloat },
3403: {"ftrapogll", 4,two(0xF07B, 0x0006), two(0xF1FF, 0xFFFF), "Ii^l", mfloat },
3404: {"ftrapogtl", 4,two(0xF07B, 0x0002), two(0xF1FF, 0xFFFF), "Ii^l", mfloat },
3405: {"ftrapolel", 4,two(0xF07B, 0x0005), two(0xF1FF, 0xFFFF), "Ii^l", mfloat },
3406: {"ftrapoltl", 4,two(0xF07B, 0x0004), two(0xF1FF, 0xFFFF), "Ii^l", mfloat },
3407: {"ftraporl", 4, two(0xF07B, 0x0007), two(0xF1FF, 0xFFFF), "Ii^l", mfloat },
3408: {"ftrapseql", 4,two(0xF07B, 0x0011), two(0xF1FF, 0xFFFF), "Ii^l", mfloat },
3409: {"ftrapsfl", 4, two(0xF07B, 0x0010), two(0xF1FF, 0xFFFF), "Ii^l", mfloat },
3410: {"ftrapsnel", 4,two(0xF07B, 0x001E), two(0xF1FF, 0xFFFF), "Ii^l", mfloat },
3411: {"ftrapstl", 4, two(0xF07B, 0x001F), two(0xF1FF, 0xFFFF), "Ii^l", mfloat },
3412: {"ftraptl", 4, two(0xF07B, 0x000F), two(0xF1FF, 0xFFFF), "Ii^l", mfloat },
3413: {"ftrapueql", 4,two(0xF07B, 0x0009), two(0xF1FF, 0xFFFF), "Ii^l", mfloat },
3414: {"ftrapugel", 4,two(0xF07B, 0x000B), two(0xF1FF, 0xFFFF), "Ii^l", mfloat },
3415: {"ftrapugtl", 4,two(0xF07B, 0x000A), two(0xF1FF, 0xFFFF), "Ii^l", mfloat },
3416: {"ftrapulel", 4,two(0xF07B, 0x000D), two(0xF1FF, 0xFFFF), "Ii^l", mfloat },
3417: {"ftrapultl", 4,two(0xF07B, 0x000C), two(0xF1FF, 0xFFFF), "Ii^l", mfloat },
3418: {"ftrapunl", 4, two(0xF07B, 0x0008), two(0xF1FF, 0xFFFF), "Ii^l", mfloat },
3419:
3420: {"ftstb", 4, two(0xF000, 0x583A), two(0xF1C0, 0xFC7F), "Ii;b", mfloat },
3421: {"ftstb", 4, two(0xF000, 0x583A), two(0xF1C0, 0xFC7F), "Iibs", cfloat },
3422: {"ftstd", 4, two(0xF000, 0x003A), two(0xF1C0, 0xE07F), "IiF8", cfloat },
3423: {"ftstd", 4, two(0xF000, 0x543A), two(0xF1C0, 0xFC7F), "Ii;F", mfloat },
3424: {"ftstd", 4, two(0xF000, 0x543A), two(0xF1C0, 0xFC7F), "Iibs", cfloat },
3425: {"ftstl", 4, two(0xF000, 0x403A), two(0xF1C0, 0xFC7F), "Ii;l", mfloat },
3426: {"ftstl", 4, two(0xF000, 0x403A), two(0xF1C0, 0xFC7F), "Iibs", cfloat },
3427: {"ftstp", 4, two(0xF000, 0x4C3A), two(0xF1C0, 0xFC7F), "Ii;p", mfloat },
3428: {"ftsts", 4, two(0xF000, 0x443A), two(0xF1C0, 0xFC7F), "Ii;f", mfloat },
3429: {"ftsts", 4, two(0xF000, 0x443A), two(0xF1C0, 0xFC7F), "Iibs", cfloat },
3430: {"ftstw", 4, two(0xF000, 0x503A), two(0xF1C0, 0xFC7F), "Ii;w", mfloat },
3431: {"ftstw", 4, two(0xF000, 0x503A), two(0xF1C0, 0xFC7F), "Iibs", cfloat },
3432: {"ftstx", 4, two(0xF000, 0x003A), two(0xF1C0, 0xE07F), "IiF8", mfloat },
3433: {"ftstx", 4, two(0xF000, 0x483A), two(0xF1C0, 0xFC7F), "Ii;x", mfloat },
3434:
3435: {"ftwotoxb", 4, two(0xF000, 0x5811), two(0xF1C0, 0xFC7F), "Ii;bF7", mfloat },
3436: {"ftwotoxd", 4, two(0xF000, 0x5411), two(0xF1C0, 0xFC7F), "Ii;FF7", mfloat },
3437: {"ftwotoxl", 4, two(0xF000, 0x4011), two(0xF1C0, 0xFC7F), "Ii;lF7", mfloat },
3438: {"ftwotoxp", 4, two(0xF000, 0x4C11), two(0xF1C0, 0xFC7F), "Ii;pF7", mfloat },
3439: {"ftwotoxs", 4, two(0xF000, 0x4411), two(0xF1C0, 0xFC7F), "Ii;fF7", mfloat },
3440: {"ftwotoxw", 4, two(0xF000, 0x5011), two(0xF1C0, 0xFC7F), "Ii;wF7", mfloat },
3441: {"ftwotoxx", 4, two(0xF000, 0x0011), two(0xF1C0, 0xE07F), "IiF8F7", mfloat },
3442: {"ftwotoxx", 4, two(0xF000, 0x4811), two(0xF1C0, 0xFC7F), "Ii;xF7", mfloat },
3443: {"ftwotoxx", 4, two(0xF000, 0x0011), two(0xF1C0, 0xE07F), "IiFt", mfloat },
3444:
3445: {"halt", 2, one(0045310), one(0177777), "", m68060 | mcfisa_a },
3446:
3447: {"illegal", 2, one(0045374), one(0177777), "", m68000up | mcfisa_a },
3448: {"intouch", 2, one(0xf428), one(0xfff8), "As", mcfisa_b },
3449:
3450: {"jmp", 2, one(0047300), one(0177700), "!s", m68000up | mcfisa_a },
3451:
3452: {"jra", 2, one(0060000), one(0177400), "Bg", m68000up | mcfisa_a },
3453: {"jra", 2, one(0047300), one(0177700), "!s", m68000up | mcfisa_a },
3454:
3455: {"jsr", 2, one(0047200), one(0177700), "!s", m68000up | mcfisa_a },
3456:
3457: {"jbsr", 2, one(0060400), one(0177400), "Bg", m68000up | mcfisa_a },
3458: {"jbsr", 2, one(0047200), one(0177700), "!s", m68000up | mcfisa_a },
3459:
3460: {"lea", 2, one(0040700), one(0170700), "!sAd", m68000up | mcfisa_a },
3461:
3462: {"lpstop", 6, two(0174000,0000700),two(0177777,0177777),"#w", cpu32|m68060 },
3463:
3464: {"linkw", 4, one(0047120), one(0177770), "As#w", m68000up | mcfisa_a },
3465: {"linkl", 6, one(0044010), one(0177770), "As#l", m68020up | cpu32 },
3466: {"link", 4, one(0047120), one(0177770), "As#W", m68000up | mcfisa_a },
3467: {"link", 6, one(0044010), one(0177770), "As#l", m68020up | cpu32 },
3468:
3469: {"lslb", 2, one(0160410), one(0170770), "QdDs", m68000up },
3470: {"lslb", 2, one(0160450), one(0170770), "DdDs", m68000up },
3471: {"lslw", 2, one(0160510), one(0170770), "QdDs", m68000up },
3472: {"lslw", 2, one(0160550), one(0170770), "DdDs", m68000up },
3473: {"lslw", 2, one(0161700), one(0177700), "~s", m68000up },
3474: {"lsll", 2, one(0160610), one(0170770), "QdDs", m68000up | mcfisa_a },
3475: {"lsll", 2, one(0160650), one(0170770), "DdDs", m68000up | mcfisa_a },
3476:
3477: {"lsrb", 2, one(0160010), one(0170770), "QdDs", m68000up },
3478: {"lsrb", 2, one(0160050), one(0170770), "DdDs", m68000up },
3479: {"lsrw", 2, one(0160110), one(0170770), "QdDs", m68000up },
3480: {"lsrw", 2, one(0160150), one(0170770), "DdDs", m68000up },
3481: {"lsrw", 2, one(0161300), one(0177700), "~s", m68000up },
3482: {"lsrl", 2, one(0160210), one(0170770), "QdDs", m68000up | mcfisa_a },
3483: {"lsrl", 2, one(0160250), one(0170770), "DdDs", m68000up | mcfisa_a },
3484:
3485: {"macw", 4, two(0xa080, 0x0000), two(0xf180, 0x0910), "uNuoiI4/Rn", mcfmac },
3486: {"macw", 4, two(0xa080, 0x0200), two(0xf180, 0x0910), "uNuoMh4/Rn", mcfmac },
3487: {"macw", 4, two(0xa080, 0x0000), two(0xf180, 0x0f10), "uNuo4/Rn", mcfmac },
3488: {"macw", 4, two(0xa000, 0x0000), two(0xf1b0, 0x0900), "uMumiI", mcfmac },
3489: {"macw", 4, two(0xa000, 0x0200), two(0xf1b0, 0x0900), "uMumMh", mcfmac },
3490: {"macw", 4, two(0xa000, 0x0000), two(0xf1b0, 0x0f00), "uMum", mcfmac },
3491:
3492: {"macw", 4, two(0xa000, 0x0000), two(0xf100, 0x0900), "uNuoiI4/RneG", mcfemac },/* Ry,Rx,SF,<ea>,accX. */
3493: {"macw", 4, two(0xa000, 0x0200), two(0xf100, 0x0900), "uNuoMh4/RneG", mcfemac },/* Ry,Rx,+1/-1,<ea>,accX. */
3494: {"macw", 4, two(0xa000, 0x0000), two(0xf100, 0x0f00), "uNuo4/RneG", mcfemac },/* Ry,Rx,<ea>,accX. */
3495: {"macw", 4, two(0xa000, 0x0000), two(0xf130, 0x0900), "uMumiIeH", mcfemac },/* Ry,Rx,SF,accX. */
3496: {"macw", 4, two(0xa000, 0x0200), two(0xf130, 0x0900), "uMumMheH", mcfemac },/* Ry,Rx,+1/-1,accX. */
3497: {"macw", 4, two(0xa000, 0x0000), two(0xf130, 0x0f00), "uMumeH", mcfemac }, /* Ry,Rx,accX. */
3498:
3499: {"macl", 4, two(0xa080, 0x0800), two(0xf180, 0x0910), "RNRoiI4/Rn", mcfmac },
3500: {"macl", 4, two(0xa080, 0x0a00), two(0xf180, 0x0910), "RNRoMh4/Rn", mcfmac },
3501: {"macl", 4, two(0xa080, 0x0800), two(0xf180, 0x0f10), "RNRo4/Rn", mcfmac },
3502: {"macl", 4, two(0xa000, 0x0800), two(0xf1b0, 0x0b00), "RMRmiI", mcfmac },
3503: {"macl", 4, two(0xa000, 0x0a00), two(0xf1b0, 0x0b00), "RMRmMh", mcfmac },
3504: {"macl", 4, two(0xa000, 0x0800), two(0xf1b0, 0x0800), "RMRm", mcfmac },
3505:
3506: {"macl", 4, two(0xa000, 0x0800), two(0xf100, 0x0900), "R3R1iI4/RneG", mcfemac },
3507: {"macl", 4, two(0xa000, 0x0a00), two(0xf100, 0x0900), "R3R1Mh4/RneG", mcfemac },
3508: {"macl", 4, two(0xa000, 0x0800), two(0xf100, 0x0f00), "R3R14/RneG", mcfemac },
3509: {"macl", 4, two(0xa000, 0x0800), two(0xf130, 0x0900), "RMRmiIeH", mcfemac },
3510: {"macl", 4, two(0xa000, 0x0a00), two(0xf130, 0x0900), "RMRmMheH", mcfemac },
3511: {"macl", 4, two(0xa000, 0x0800), two(0xf130, 0x0f00), "RMRmeH", mcfemac },
3512:
3513: /* NOTE: The mcf5200 family programmer's reference manual does not
3514: indicate the byte form of the movea instruction is invalid (as it
3515: is on 68000 family cpus). However, experiments on the 5202 yeild
3516: unexpected results. The value is copied, but it is not sign extended
3517: (as is done with movea.w) and the top three bytes in the address
3518: register are not disturbed. I don't know if this is the intended
3519: behavior --- it could be a hole in instruction decoding (Motorola
3520: decided not to trap all invalid instructions for performance reasons)
3521: --- but I suspect that it is not.
3522:
3523: I reported this to Motorola ISD Technical Communications Support,
3524: which replied that other coldfire assemblers reject movea.b. For
3525: this reason I've decided to not allow moveab.
3526:
3527: [email protected] - 97/01/24. */
3528:
3529: {"moveal", 2, one(0020100), one(0170700), "*lAd", m68000up | mcfisa_a },
3530: {"moveaw", 2, one(0030100), one(0170700), "*wAd", m68000up | mcfisa_a },
3531:
3532: {"movclrl", 2, one(0xA1C0), one(0xf9f0), "eFRs", mcfemac },
3533:
3534: {"movec", 4, one(0047173), one(0177777), "R1Jj", m68010up | mcfisa_a },
3535: {"movec", 4, one(0047173), one(0177777), "R1#j", m68010up | mcfisa_a },
3536: {"movec", 4, one(0047172), one(0177777), "JjR1", m68010up },
3537: {"movec", 4, one(0047172), one(0177777), "#jR1", m68010up },
3538:
3539: {"movemw", 4, one(0044200), one(0177700), "Lw&s", m68000up },
3540: {"movemw", 4, one(0044240), one(0177770), "lw-s", m68000up },
3541: {"movemw", 4, one(0044200), one(0177700), "#w>s", m68000up },
3542: {"movemw", 4, one(0046200), one(0177700), "<sLw", m68000up },
3543: {"movemw", 4, one(0046200), one(0177700), "<s#w", m68000up },
3544: {"moveml", 4, one(0044300), one(0177700), "Lw&s", m68000up },
3545: {"moveml", 4, one(0044340), one(0177770), "lw-s", m68000up },
3546: {"moveml", 4, one(0044300), one(0177700), "#w>s", m68000up },
3547: {"moveml", 4, one(0046300), one(0177700), "<sLw", m68000up },
3548: {"moveml", 4, one(0046300), one(0177700), "<s#w", m68000up },
3549: /* FIXME: need specifier for mode 2 and 5 to simplify below insn patterns. */
3550: {"moveml", 4, one(0044320), one(0177770), "Lwas", mcfisa_a },
3551: {"moveml", 4, one(0044320), one(0177770), "#was", mcfisa_a },
3552: {"moveml", 4, one(0044350), one(0177770), "Lwds", mcfisa_a },
3553: {"moveml", 4, one(0044350), one(0177770), "#wds", mcfisa_a },
3554: {"moveml", 4, one(0046320), one(0177770), "asLw", mcfisa_a },
3555: {"moveml", 4, one(0046320), one(0177770), "as#w", mcfisa_a },
3556: {"moveml", 4, one(0046350), one(0177770), "dsLw", mcfisa_a },
3557: {"moveml", 4, one(0046350), one(0177770), "ds#w", mcfisa_a },
3558:
3559: {"movepw", 2, one(0000410), one(0170770), "dsDd", m68000up },
3560: {"movepw", 2, one(0000610), one(0170770), "Ddds", m68000up },
3561: {"movepl", 2, one(0000510), one(0170770), "dsDd", m68000up },
3562: {"movepl", 2, one(0000710), one(0170770), "Ddds", m68000up },
3563:
3564: {"moveq", 2, one(0070000), one(0170400), "MsDd", m68000up | mcfisa_a },
3565: {"moveq", 2, one(0070000), one(0170400), "#BDd", m68000up | mcfisa_a },
3566:
3567: /* The move opcode can generate the movea and moveq instructions. */
3568: {"moveb", 2, one(0010000), one(0170000), ";b$d", m68000up },
3569: {"moveb", 2, one(0010000), one(0170070), "Ds$d", mcfisa_a },
3570: {"moveb", 2, one(0010020), one(0170070), "as$d", mcfisa_a },
3571: {"moveb", 2, one(0010030), one(0170070), "+s$d", mcfisa_a },
3572: {"moveb", 2, one(0010040), one(0170070), "-s$d", mcfisa_a },
3573: {"moveb", 2, one(0010000), one(0170000), "nsqd", mcfisa_a },
3574: {"moveb", 2, one(0010000), one(0170700), "obDd", mcfisa_a },
3575: {"moveb", 2, one(0010200), one(0170700), "obad", mcfisa_a },
3576: {"moveb", 2, one(0010300), one(0170700), "ob+d", mcfisa_a },
3577: {"moveb", 2, one(0010400), one(0170700), "ob-d", mcfisa_a },
3578: {"moveb", 2, one(0010000), one(0170000), "obnd", mcfisa_b },
3579:
3580: {"movew", 2, one(0030000), one(0170000), "*w%d", m68000up },
3581: {"movew", 2, one(0030000), one(0170000), "ms%d", mcfisa_a },
3582: {"movew", 2, one(0030000), one(0170000), "nspd", mcfisa_a },
3583: {"movew", 2, one(0030000), one(0170000), "owmd", mcfisa_a },
3584: {"movew", 2, one(0030000), one(0170000), "ownd", mcfisa_b },
3585: {"movew", 2, one(0040300), one(0177700), "Ss$s", m68000up },
3586: {"movew", 2, one(0040300), one(0177770), "SsDs", mcfisa_a },
3587: {"movew", 2, one(0041300), one(0177700), "Cs$s", m68010up },
3588: {"movew", 2, one(0041300), one(0177770), "CsDs", mcfisa_a },
3589: {"movew", 2, one(0042300), one(0177700), ";wCd", m68000up },
3590: {"movew", 2, one(0042300), one(0177700), "DsCd", mcfisa_a },
3591: {"movew", 4, one(0042374), one(0177777), "#wCd", mcfisa_a },
3592: {"movew", 2, one(0043300), one(0177700), ";wSd", m68000up },
3593: {"movew", 2, one(0043300), one(0177700), "DsSd", mcfisa_a },
3594: {"movew", 4, one(0043374), one(0177777), "#wSd", mcfisa_a },
3595:
3596: {"movel", 2, one(0070000), one(0170400), "MsDd", m68000up | mcfisa_a },
3597: {"movel", 2, one(0020000), one(0170000), "*l%d", m68000up },
3598: {"movel", 2, one(0020000), one(0170000), "ms%d", mcfisa_a },
3599: {"movel", 2, one(0020000), one(0170000), "nspd", mcfisa_a },
3600: {"movel", 2, one(0020000), one(0170000), "olmd", mcfisa_a },
3601: {"movel", 2, one(0020000), one(0170000), "olnd", mcfisa_b },
3602: {"movel", 2, one(0047140), one(0177770), "AsUd", m68000up | mcfusp },
3603: {"movel", 2, one(0047150), one(0177770), "UdAs", m68000up | mcfusp },
3604: {"movel", 2, one(0120600), one(0177760), "EsRs", mcfmac },
3605: {"movel", 2, one(0120400), one(0177760), "RsEs", mcfmac },
3606: {"movel", 6, one(0120474), one(0177777), "#lEs", mcfmac },
3607: {"movel", 2, one(0124600), one(0177760), "GsRs", mcfmac },
3608: {"movel", 2, one(0124400), one(0177760), "RsGs", mcfmac },
3609: {"movel", 6, one(0124474), one(0177777), "#lGs", mcfmac },
3610: {"movel", 2, one(0126600), one(0177760), "HsRs", mcfmac },
3611: {"movel", 2, one(0126400), one(0177760), "RsHs", mcfmac },
3612: {"movel", 6, one(0126474), one(0177777), "#lHs", mcfmac },
3613: {"movel", 2, one(0124700), one(0177777), "GsCs", mcfmac },
3614:
3615: {"movel", 2, one(0xa180), one(0xf9f0), "eFRs", mcfemac }, /* ACCx,Rx. */
3616: {"movel", 2, one(0xab80), one(0xfbf0), "g]Rs", mcfemac }, /* ACCEXTx,Rx. */
3617: {"movel", 2, one(0xa980), one(0xfff0), "G-Rs", mcfemac }, /* macsr,Rx. */
3618: {"movel", 2, one(0xad80), one(0xfff0), "H-Rs", mcfemac }, /* mask,Rx. */
3619: {"movel", 2, one(0xa110), one(0xf9fc), "efeF", mcfemac }, /* ACCy,ACCx. */
3620: {"movel", 2, one(0xa9c0), one(0xffff), "G-C-", mcfemac }, /* macsr,ccr. */
3621: {"movel", 2, one(0xa100), one(0xf9f0), "RseF", mcfemac }, /* Rx,ACCx. */
3622: {"movel", 6, one(0xa13c), one(0xf9ff), "#leF", mcfemac }, /* #,ACCx. */
3623: {"movel", 2, one(0xab00), one(0xfbc0), "Rsg]", mcfemac }, /* Rx,ACCEXTx. */
3624: {"movel", 6, one(0xab3c), one(0xfbff), "#lg]", mcfemac }, /* #,ACCEXTx. */
3625: {"movel", 2, one(0xa900), one(0xffc0), "RsG-", mcfemac }, /* Rx,macsr. */
3626: {"movel", 6, one(0xa93c), one(0xffff), "#lG-", mcfemac }, /* #,macsr. */
3627: {"movel", 2, one(0xad00), one(0xffc0), "RsH-", mcfemac }, /* Rx,mask. */
3628: {"movel", 6, one(0xad3c), one(0xffff), "#lH-", mcfemac }, /* #,mask. */
3629:
3630: {"move", 2, one(0030000), one(0170000), "*w%d", m68000up },
3631: {"move", 2, one(0030000), one(0170000), "ms%d", mcfisa_a },
3632: {"move", 2, one(0030000), one(0170000), "nspd", mcfisa_a },
3633: {"move", 2, one(0030000), one(0170000), "owmd", mcfisa_a },
3634: {"move", 2, one(0030000), one(0170000), "ownd", mcfisa_b },
3635: {"move", 2, one(0040300), one(0177700), "Ss$s", m68000up },
3636: {"move", 2, one(0040300), one(0177770), "SsDs", mcfisa_a },
3637: {"move", 2, one(0041300), one(0177700), "Cs$s", m68010up },
3638: {"move", 2, one(0041300), one(0177770), "CsDs", mcfisa_a },
3639: {"move", 2, one(0042300), one(0177700), ";wCd", m68000up },
3640: {"move", 2, one(0042300), one(0177700), "DsCd", mcfisa_a },
3641: {"move", 4, one(0042374), one(0177777), "#wCd", mcfisa_a },
3642: {"move", 2, one(0043300), one(0177700), ";wSd", m68000up },
3643: {"move", 2, one(0043300), one(0177700), "DsSd", mcfisa_a },
3644: {"move", 4, one(0043374), one(0177777), "#wSd", mcfisa_a },
3645:
3646: {"move", 2, one(0047140), one(0177770), "AsUd", m68000up },
3647: {"move", 2, one(0047150), one(0177770), "UdAs", m68000up },
3648:
3649: {"mov3ql", 2, one(0120500), one(0170700), "xd%s", mcfisa_b },
3650: {"mvsb", 2, one(0070400), one(0170700), "*bDd", mcfisa_b },
3651: {"mvsw", 2, one(0070500), one(0170700), "*wDd", mcfisa_b },
3652: {"mvzb", 2, one(0070600), one(0170700), "*bDd", mcfisa_b },
3653: {"mvzw", 2, one(0070700), one(0170700), "*wDd", mcfisa_b },
3654:
3655: {"movesb", 4, two(0007000, 0), two(0177700, 07777), "~sR1", m68010up },
3656: {"movesb", 4, two(0007000, 04000), two(0177700, 07777), "R1~s", m68010up },
3657: {"movesw", 4, two(0007100, 0), two(0177700, 07777), "~sR1", m68010up },
3658: {"movesw", 4, two(0007100, 04000), two(0177700, 07777), "R1~s", m68010up },
3659: {"movesl", 4, two(0007200, 0), two(0177700, 07777), "~sR1", m68010up },
3660: {"movesl", 4, two(0007200, 04000), two(0177700, 07777), "R1~s", m68010up },
3661:
3662: {"move16", 4, two(0xf620, 0x8000), two(0xfff8, 0x8fff), "+s+1", m68040up },
3663: {"move16", 2, one(0xf600), one(0xfff8), "+s_L", m68040up },
3664: {"move16", 2, one(0xf608), one(0xfff8), "_L+s", m68040up },
3665: {"move16", 2, one(0xf610), one(0xfff8), "as_L", m68040up },
3666: {"move16", 2, one(0xf618), one(0xfff8), "_Las", m68040up },
3667:
3668: {"msacw", 4, two(0xa080, 0x0100), two(0xf180, 0x0910), "uNuoiI4/Rn", mcfmac },
3669: {"msacw", 4, two(0xa080, 0x0300), two(0xf180, 0x0910), "uNuoMh4/Rn", mcfmac },
3670: {"msacw", 4, two(0xa080, 0x0100), two(0xf180, 0x0f10), "uNuo4/Rn", mcfmac },
3671: {"msacw", 4, two(0xa000, 0x0100), two(0xf1b0, 0x0900), "uMumiI", mcfmac },
3672: {"msacw", 4, two(0xa000, 0x0300), two(0xf1b0, 0x0900), "uMumMh", mcfmac },
3673: {"msacw", 4, two(0xa000, 0x0100), two(0xf1b0, 0x0f00), "uMum", mcfmac },
3674:
3675: {"msacw", 4, two(0xa000, 0x0100), two(0xf100, 0x0900), "uMumiI4/RneG", mcfemac },/* Ry,Rx,SF,<ea>,accX. */
3676: {"msacw", 4, two(0xa000, 0x0300), two(0xf100, 0x0900), "uMumMh4/RneG", mcfemac },/* Ry,Rx,+1/-1,<ea>,accX. */
3677: {"msacw", 4, two(0xa000, 0x0100), two(0xf100, 0x0f00), "uMum4/RneG", mcfemac },/* Ry,Rx,<ea>,accX. */
3678: {"msacw", 4, two(0xa000, 0x0100), two(0xf130, 0x0900), "uMumiIeH", mcfemac },/* Ry,Rx,SF,accX. */
3679: {"msacw", 4, two(0xa000, 0x0300), two(0xf130, 0x0900), "uMumMheH", mcfemac },/* Ry,Rx,+1/-1,accX. */
3680: {"msacw", 4, two(0xa000, 0x0100), two(0xf130, 0x0f00), "uMumeH", mcfemac }, /* Ry,Rx,accX. */
3681:
3682: {"msacl", 4, two(0xa080, 0x0900), two(0xf180, 0x0910), "RNRoiI4/Rn", mcfmac },
3683: {"msacl", 4, two(0xa080, 0x0b00), two(0xf180, 0x0910), "RNRoMh4/Rn", mcfmac },
3684: {"msacl", 4, two(0xa080, 0x0900), two(0xf180, 0x0f10), "RNRo4/Rn", mcfmac },
3685: {"msacl", 4, two(0xa000, 0x0900), two(0xf1b0, 0x0b00), "RMRmiI", mcfmac },
3686: {"msacl", 4, two(0xa000, 0x0b00), two(0xf1b0, 0x0b00), "RMRmMh", mcfmac },
3687: {"msacl", 4, two(0xa000, 0x0900), two(0xf1b0, 0x0800), "RMRm", mcfmac },
3688:
3689: {"msacl", 4, two(0xa000, 0x0900), two(0xf100, 0x0900), "R3R1iI4/RneG", mcfemac },
3690: {"msacl", 4, two(0xa000, 0x0b00), two(0xf100, 0x0900), "R3R1Mh4/RneG", mcfemac },
3691: {"msacl", 4, two(0xa000, 0x0900), two(0xf100, 0x0f00), "R3R14/RneG", mcfemac },
3692: {"msacl", 4, two(0xa000, 0x0900), two(0xf130, 0x0900), "RMRmiIeH", mcfemac },
3693: {"msacl", 4, two(0xa000, 0x0b00), two(0xf130, 0x0900), "RMRmMheH", mcfemac },
3694: {"msacl", 4, two(0xa000, 0x0900), two(0xf130, 0x0f00), "RMRmeH", mcfemac },
3695:
3696: {"mulsw", 2, one(0140700), one(0170700), ";wDd", m68000up|mcfisa_a },
3697: {"mulsl", 4, two(0046000,004000), two(0177700,0107770), ";lD1", m68020up|cpu32 },
3698: {"mulsl", 4, two(0046000,004000), two(0177700,0107770), "qsD1", mcfisa_a },
3699: {"mulsl", 4, two(0046000,006000), two(0177700,0107770), ";lD3D1",m68020up|cpu32 },
3700:
3701: {"muluw", 2, one(0140300), one(0170700), ";wDd", m68000up|mcfisa_a },
3702: {"mulul", 4, two(0046000,000000), two(0177700,0107770), ";lD1", m68020up|cpu32 },
3703: {"mulul", 4, two(0046000,000000), two(0177700,0107770), "qsD1", mcfisa_a },
3704: {"mulul", 4, two(0046000,002000), two(0177700,0107770), ";lD3D1",m68020up|cpu32 },
3705:
3706: {"nbcd", 2, one(0044000), one(0177700), "$s", m68000up },
3707:
3708: {"negb", 2, one(0042000), one(0177700), "$s", m68000up },
3709: {"negw", 2, one(0042100), one(0177700), "$s", m68000up },
3710: {"negl", 2, one(0042200), one(0177700), "$s", m68000up },
3711: {"negl", 2, one(0042200), one(0177700), "Ds", mcfisa_a},
3712:
3713: {"negxb", 2, one(0040000), one(0177700), "$s", m68000up },
3714: {"negxw", 2, one(0040100), one(0177700), "$s", m68000up },
3715: {"negxl", 2, one(0040200), one(0177700), "$s", m68000up },
3716: {"negxl", 2, one(0040200), one(0177700), "Ds", mcfisa_a},
3717:
3718: {"nop", 2, one(0047161), one(0177777), "", m68000up | mcfisa_a},
3719:
3720: {"notb", 2, one(0043000), one(0177700), "$s", m68000up },
3721: {"notw", 2, one(0043100), one(0177700), "$s", m68000up },
3722: {"notl", 2, one(0043200), one(0177700), "$s", m68000up },
3723: {"notl", 2, one(0043200), one(0177700), "Ds", mcfisa_a},
3724:
3725: {"orib", 4, one(0000000), one(0177700), "#b$s", m68000up },
3726: {"orib", 4, one(0000074), one(0177777), "#bCs", m68000up },
3727: {"oriw", 4, one(0000100), one(0177700), "#w$s", m68000up },
3728: {"oriw", 4, one(0000174), one(0177777), "#wSs", m68000up },
3729: {"oril", 6, one(0000200), one(0177700), "#l$s", m68000up },
3730: {"oril", 6, one(0000200), one(0177700), "#lDs", mcfisa_a },
3731: {"ori", 4, one(0000074), one(0177777), "#bCs", m68000up },
3732: {"ori", 4, one(0000100), one(0177700), "#w$s", m68000up },
3733: {"ori", 4, one(0000174), one(0177777), "#wSs", m68000up },
3734:
3735: /* The or opcode can generate the ori instruction. */
3736: {"orb", 4, one(0000000), one(0177700), "#b$s", m68000up },
3737: {"orb", 4, one(0000074), one(0177777), "#bCs", m68000up },
3738: {"orb", 2, one(0100000), one(0170700), ";bDd", m68000up },
3739: {"orb", 2, one(0100400), one(0170700), "Dd~s", m68000up },
3740: {"orw", 4, one(0000100), one(0177700), "#w$s", m68000up },
3741: {"orw", 4, one(0000174), one(0177777), "#wSs", m68000up },
3742: {"orw", 2, one(0100100), one(0170700), ";wDd", m68000up },
3743: {"orw", 2, one(0100500), one(0170700), "Dd~s", m68000up },
3744: {"orl", 6, one(0000200), one(0177700), "#l$s", m68000up },
3745: {"orl", 6, one(0000200), one(0177700), "#lDs", mcfisa_a },
3746: {"orl", 2, one(0100200), one(0170700), ";lDd", m68000up | mcfisa_a },
3747: {"orl", 2, one(0100600), one(0170700), "Dd~s", m68000up | mcfisa_a },
3748: {"or", 4, one(0000074), one(0177777), "#bCs", m68000up },
3749: {"or", 4, one(0000100), one(0177700), "#w$s", m68000up },
3750: {"or", 4, one(0000174), one(0177777), "#wSs", m68000up },
3751: {"or", 2, one(0100100), one(0170700), ";wDd", m68000up },
3752: {"or", 2, one(0100500), one(0170700), "Dd~s", m68000up },
3753:
3754: {"pack", 4, one(0100500), one(0170770), "DsDd#w", m68020up },
3755: {"pack", 4, one(0100510), one(0170770), "-s-d#w", m68020up },
3756:
3757: {"pbac", 2, one(0xf087), one(0xffbf), "Bc", m68851 },
3758: {"pbacw", 2, one(0xf087), one(0xffff), "BW", m68851 },
3759: {"pbas", 2, one(0xf086), one(0xffbf), "Bc", m68851 },
3760: {"pbasw", 2, one(0xf086), one(0xffff), "BW", m68851 },
3761: {"pbbc", 2, one(0xf081), one(0xffbf), "Bc", m68851 },
3762: {"pbbcw", 2, one(0xf081), one(0xffff), "BW", m68851 },
3763: {"pbbs", 2, one(0xf080), one(0xffbf), "Bc", m68851 },
3764: {"pbbsw", 2, one(0xf080), one(0xffff), "BW", m68851 },
3765: {"pbcc", 2, one(0xf08f), one(0xffbf), "Bc", m68851 },
3766: {"pbccw", 2, one(0xf08f), one(0xffff), "BW", m68851 },
3767: {"pbcs", 2, one(0xf08e), one(0xffbf), "Bc", m68851 },
3768: {"pbcsw", 2, one(0xf08e), one(0xffff), "BW", m68851 },
3769: {"pbgc", 2, one(0xf08d), one(0xffbf), "Bc", m68851 },
3770: {"pbgcw", 2, one(0xf08d), one(0xffff), "BW", m68851 },
3771: {"pbgs", 2, one(0xf08c), one(0xffbf), "Bc", m68851 },
3772: {"pbgsw", 2, one(0xf08c), one(0xffff), "BW", m68851 },
3773: {"pbic", 2, one(0xf08b), one(0xffbf), "Bc", m68851 },
3774: {"pbicw", 2, one(0xf08b), one(0xffff), "BW", m68851 },
3775: {"pbis", 2, one(0xf08a), one(0xffbf), "Bc", m68851 },
3776: {"pbisw", 2, one(0xf08a), one(0xffff), "BW", m68851 },
3777: {"pblc", 2, one(0xf083), one(0xffbf), "Bc", m68851 },
3778: {"pblcw", 2, one(0xf083), one(0xffff), "BW", m68851 },
3779: {"pbls", 2, one(0xf082), one(0xffbf), "Bc", m68851 },
3780: {"pblsw", 2, one(0xf082), one(0xffff), "BW", m68851 },
3781: {"pbsc", 2, one(0xf085), one(0xffbf), "Bc", m68851 },
3782: {"pbscw", 2, one(0xf085), one(0xffff), "BW", m68851 },
3783: {"pbss", 2, one(0xf084), one(0xffbf), "Bc", m68851 },
3784: {"pbssw", 2, one(0xf084), one(0xffff), "BW", m68851 },
3785: {"pbwc", 2, one(0xf089), one(0xffbf), "Bc", m68851 },
3786: {"pbwcw", 2, one(0xf089), one(0xffff), "BW", m68851 },
3787: {"pbws", 2, one(0xf088), one(0xffbf), "Bc", m68851 },
3788: {"pbwsw", 2, one(0xf088), one(0xffff), "BW", m68851 },
3789:
3790: {"pdbac", 4, two(0xf048, 0x0007), two(0xfff8, 0xffff), "DsBw", m68851 },
3791: {"pdbas", 4, two(0xf048, 0x0006), two(0xfff8, 0xffff), "DsBw", m68851 },
3792: {"pdbbc", 4, two(0xf048, 0x0001), two(0xfff8, 0xffff), "DsBw", m68851 },
3793: {"pdbbs", 4, two(0xf048, 0x0000), two(0xfff8, 0xffff), "DsBw", m68851 },
3794: {"pdbcc", 4, two(0xf048, 0x000f), two(0xfff8, 0xffff), "DsBw", m68851 },
3795: {"pdbcs", 4, two(0xf048, 0x000e), two(0xfff8, 0xffff), "DsBw", m68851 },
3796: {"pdbgc", 4, two(0xf048, 0x000d), two(0xfff8, 0xffff), "DsBw", m68851 },
3797: {"pdbgs", 4, two(0xf048, 0x000c), two(0xfff8, 0xffff), "DsBw", m68851 },
3798: {"pdbic", 4, two(0xf048, 0x000b), two(0xfff8, 0xffff), "DsBw", m68851 },
3799: {"pdbis", 4, two(0xf048, 0x000a), two(0xfff8, 0xffff), "DsBw", m68851 },
3800: {"pdblc", 4, two(0xf048, 0x0003), two(0xfff8, 0xffff), "DsBw", m68851 },
3801: {"pdbls", 4, two(0xf048, 0x0002), two(0xfff8, 0xffff), "DsBw", m68851 },
3802: {"pdbsc", 4, two(0xf048, 0x0005), two(0xfff8, 0xffff), "DsBw", m68851 },
3803: {"pdbss", 4, two(0xf048, 0x0004), two(0xfff8, 0xffff), "DsBw", m68851 },
3804: {"pdbwc", 4, two(0xf048, 0x0009), two(0xfff8, 0xffff), "DsBw", m68851 },
3805: {"pdbws", 4, two(0xf048, 0x0008), two(0xfff8, 0xffff), "DsBw", m68851 },
3806:
3807: {"pea", 2, one(0044100), one(0177700), "!s", m68000up|mcfisa_a },
3808:
3809: {"pflusha", 2, one(0xf518), one(0xfff8), "", m68040up },
3810: {"pflusha", 4, two(0xf000,0x2400), two(0xffff,0xffff), "", m68030 | m68851 },
3811:
3812: {"pflush", 4, two(0xf000,0x3010), two(0xffc0,0xfe10), "T3T9", m68030|m68851 },
3813: {"pflush", 4, two(0xf000,0x3810), two(0xffc0,0xfe10), "T3T9&s", m68030|m68851 },
3814: {"pflush", 4, two(0xf000,0x3008), two(0xffc0,0xfe18), "D3T9", m68030|m68851 },
3815: {"pflush", 4, two(0xf000,0x3808), two(0xffc0,0xfe18), "D3T9&s", m68030|m68851 },
3816: {"pflush", 4, two(0xf000,0x3000), two(0xffc0,0xfe1e), "f3T9", m68030|m68851 },
3817: {"pflush", 4, two(0xf000,0x3800), two(0xffc0,0xfe1e), "f3T9&s", m68030|m68851 },
3818: {"pflush", 2, one(0xf508), one(0xfff8), "as", m68040up },
3819: {"pflush", 2, one(0xf508), one(0xfff8), "As", m68040up },
3820:
3821: {"pflushan", 2, one(0xf510), one(0xfff8), "", m68040up },
3822: {"pflushn", 2, one(0xf500), one(0xfff8), "as", m68040up },
3823: {"pflushn", 2, one(0xf500), one(0xfff8), "As", m68040up },
3824:
3825: {"pflushr", 4, two(0xf000, 0xa000), two(0xffc0, 0xffff), "|s", m68851 },
3826:
3827: {"pflushs", 4, two(0xf000, 0x3410), two(0xfff8, 0xfe10), "T3T9", m68851 },
3828: {"pflushs", 4, two(0xf000, 0x3c10), two(0xfff8, 0xfe10), "T3T9&s", m68851 },
3829: {"pflushs", 4, two(0xf000, 0x3408), two(0xfff8, 0xfe18), "D3T9", m68851 },
3830: {"pflushs", 4, two(0xf000, 0x3c08), two(0xfff8, 0xfe18), "D3T9&s", m68851 },
3831: {"pflushs", 4, two(0xf000, 0x3400), two(0xfff8, 0xfe1e), "f3T9", m68851 },
3832: {"pflushs", 4, two(0xf000, 0x3c00), two(0xfff8, 0xfe1e), "f3T9&s", m68851 },
3833:
3834: {"ploadr", 4, two(0xf000,0x2210), two(0xffc0,0xfff0), "T3&s", m68030|m68851 },
3835: {"ploadr", 4, two(0xf000,0x2208), two(0xffc0,0xfff8), "D3&s", m68030|m68851 },
3836: {"ploadr", 4, two(0xf000,0x2200), two(0xffc0,0xfffe), "f3&s", m68030|m68851 },
3837: {"ploadw", 4, two(0xf000,0x2010), two(0xffc0,0xfff0), "T3&s", m68030|m68851 },
3838: {"ploadw", 4, two(0xf000,0x2008), two(0xffc0,0xfff8), "D3&s", m68030|m68851 },
3839: {"ploadw", 4, two(0xf000,0x2000), two(0xffc0,0xfffe), "f3&s", m68030|m68851 },
3840:
3841: {"plpar", 2, one(0xf5c8), one(0xfff8), "as", m68060 },
3842: {"plpaw", 2, one(0xf588), one(0xfff8), "as", m68060 },
3843:
3844: {"pmove", 4, two(0xf000,0x4000), two(0xffc0,0xffff), "*l08", m68030|m68851 },
3845: {"pmove", 4, two(0xf000,0x5c00), two(0xffc0,0xffff), "*w18", m68851 },
3846: {"pmove", 4, two(0xf000,0x4000), two(0xffc0,0xe3ff), "*b28", m68851 },
3847: {"pmove", 4, two(0xf000,0x4200), two(0xffc0,0xffff), "08%s", m68030|m68851 },
3848: {"pmove", 4, two(0xf000,0x5e00), two(0xffc0,0xffff), "18%s", m68851 },
3849: {"pmove", 4, two(0xf000,0x4200), two(0xffc0,0xe3ff), "28%s", m68851 },
3850: {"pmove", 4, two(0xf000,0x4000), two(0xffc0,0xe3ff), "|sW8", m68030|m68851 },
3851: {"pmove", 4, two(0xf000,0x4200), two(0xffc0,0xe3ff), "W8~s", m68030|m68851 },
3852: {"pmove", 4, two(0xf000,0x6200), two(0xffc0,0xe3e3), "*wX3", m68851 },
3853: {"pmove", 4, two(0xf000,0x6000), two(0xffc0,0xe3e3), "X3%s", m68851 },
3854: {"pmove", 4, two(0xf000,0x6000), two(0xffc0,0xffff), "*wY8", m68030|m68851 },
3855: {"pmove", 4, two(0xf000,0x6200), two(0xffc0,0xffff), "Y8%s", m68030|m68851 },
3856: {"pmove", 4, two(0xf000,0x6600), two(0xffc0,0xffff), "Z8%s", m68851 },
3857: {"pmove", 4, two(0xf000,0x0800), two(0xffc0,0xfbff), "*l38", m68030 },
3858: {"pmove", 4, two(0xf000,0x0a00), two(0xffc0,0xfbff), "38%s", m68030 },
3859:
3860: {"pmovefd", 4, two(0xf000, 0x4100), two(0xffc0, 0xe3ff), "*l08", m68030 },
3861: {"pmovefd", 4, two(0xf000, 0x4100), two(0xffc0, 0xe3ff), "|sW8", m68030 },
3862: {"pmovefd", 4, two(0xf000, 0x0900), two(0xffc0, 0xfbff), "*l38", m68030 },
3863:
3864: {"prestore", 2, one(0xf140), one(0xffc0), "<s", m68851 },
3865:
3866: {"psave", 2, one(0xf100), one(0xffc0), ">s", m68851 },
3867:
3868: {"psac", 4, two(0xf040, 0x0007), two(0xffc0, 0xffff), "$s", m68851 },
3869: {"psas", 4, two(0xf040, 0x0006), two(0xffc0, 0xffff), "$s", m68851 },
3870: {"psbc", 4, two(0xf040, 0x0001), two(0xffc0, 0xffff), "$s", m68851 },
3871: {"psbs", 4, two(0xf040, 0x0000), two(0xffc0, 0xffff), "$s", m68851 },
3872: {"pscc", 4, two(0xf040, 0x000f), two(0xffc0, 0xffff), "$s", m68851 },
3873: {"pscs", 4, two(0xf040, 0x000e), two(0xffc0, 0xffff), "$s", m68851 },
3874: {"psgc", 4, two(0xf040, 0x000d), two(0xffc0, 0xffff), "$s", m68851 },
3875: {"psgs", 4, two(0xf040, 0x000c), two(0xffc0, 0xffff), "$s", m68851 },
3876: {"psic", 4, two(0xf040, 0x000b), two(0xffc0, 0xffff), "$s", m68851 },
3877: {"psis", 4, two(0xf040, 0x000a), two(0xffc0, 0xffff), "$s", m68851 },
3878: {"pslc", 4, two(0xf040, 0x0003), two(0xffc0, 0xffff), "$s", m68851 },
3879: {"psls", 4, two(0xf040, 0x0002), two(0xffc0, 0xffff), "$s", m68851 },
3880: {"pssc", 4, two(0xf040, 0x0005), two(0xffc0, 0xffff), "$s", m68851 },
3881: {"psss", 4, two(0xf040, 0x0004), two(0xffc0, 0xffff), "$s", m68851 },
3882: {"pswc", 4, two(0xf040, 0x0009), two(0xffc0, 0xffff), "$s", m68851 },
3883: {"psws", 4, two(0xf040, 0x0008), two(0xffc0, 0xffff), "$s", m68851 },
3884:
3885: {"ptestr", 4, two(0xf000,0x8210), two(0xffc0, 0xe3f0), "T3&st8", m68030|m68851 },
3886: {"ptestr", 4, two(0xf000,0x8310), two(0xffc0,0xe310), "T3&st8A9", m68030|m68851 },
3887: {"ptestr", 4, two(0xf000,0x8208), two(0xffc0,0xe3f8), "D3&st8", m68030|m68851 },
3888: {"ptestr", 4, two(0xf000,0x8308), two(0xffc0,0xe318), "D3&st8A9", m68030|m68851 },
3889: {"ptestr", 4, two(0xf000,0x8200), two(0xffc0,0xe3fe), "f3&st8", m68030|m68851 },
3890: {"ptestr", 4, two(0xf000,0x8300), two(0xffc0,0xe31e), "f3&st8A9", m68030|m68851 },
3891: {"ptestr", 2, one(0xf568), one(0xfff8), "as", m68040 },
3892:
3893: {"ptestw", 4, two(0xf000,0x8010), two(0xffc0,0xe3f0), "T3&st8", m68030|m68851 },
3894: {"ptestw", 4, two(0xf000,0x8110), two(0xffc0,0xe310), "T3&st8A9", m68030|m68851 },
3895: {"ptestw", 4, two(0xf000,0x8008), two(0xffc0,0xe3f8), "D3&st8", m68030|m68851 },
3896: {"ptestw", 4, two(0xf000,0x8108), two(0xffc0,0xe318), "D3&st8A9", m68030|m68851 },
3897: {"ptestw", 4, two(0xf000,0x8000), two(0xffc0,0xe3fe), "f3&st8", m68030|m68851 },
3898: {"ptestw", 4, two(0xf000,0x8100), two(0xffc0,0xe31e), "f3&st8A9", m68030|m68851 },
3899: {"ptestw", 2, one(0xf548), one(0xfff8), "as", m68040 },
3900:
3901: {"ptrapacw", 6, two(0xf07a, 0x0007), two(0xffff, 0xffff), "#w", m68851 },
3902: {"ptrapacl", 6, two(0xf07b, 0x0007), two(0xffff, 0xffff), "#l", m68851 },
3903: {"ptrapac", 4, two(0xf07c, 0x0007), two(0xffff, 0xffff), "", m68851 },
3904:
3905: {"ptrapasw", 6, two(0xf07a, 0x0006), two(0xffff, 0xffff), "#w", m68851 },
3906: {"ptrapasl", 6, two(0xf07b, 0x0006), two(0xffff, 0xffff), "#l", m68851 },
3907: {"ptrapas", 4, two(0xf07c, 0x0006), two(0xffff, 0xffff), "", m68851 },
3908:
3909: {"ptrapbcw", 6, two(0xf07a, 0x0001), two(0xffff, 0xffff), "#w", m68851 },
3910: {"ptrapbcl", 6, two(0xf07b, 0x0001), two(0xffff, 0xffff), "#l", m68851 },
3911: {"ptrapbc", 4, two(0xf07c, 0x0001), two(0xffff, 0xffff), "", m68851 },
3912:
3913: {"ptrapbsw", 6, two(0xf07a, 0x0000), two(0xffff, 0xffff), "#w", m68851 },
3914: {"ptrapbsl", 6, two(0xf07b, 0x0000), two(0xffff, 0xffff), "#l", m68851 },
3915: {"ptrapbs", 4, two(0xf07c, 0x0000), two(0xffff, 0xffff), "", m68851 },
3916:
3917: {"ptrapccw", 6, two(0xf07a, 0x000f), two(0xffff, 0xffff), "#w", m68851 },
3918: {"ptrapccl", 6, two(0xf07b, 0x000f), two(0xffff, 0xffff), "#l", m68851 },
3919: {"ptrapcc", 4, two(0xf07c, 0x000f), two(0xffff, 0xffff), "", m68851 },
3920:
3921: {"ptrapcsw", 6, two(0xf07a, 0x000e), two(0xffff, 0xffff), "#w", m68851 },
3922: {"ptrapcsl", 6, two(0xf07b, 0x000e), two(0xffff, 0xffff), "#l", m68851 },
3923: {"ptrapcs", 4, two(0xf07c, 0x000e), two(0xffff, 0xffff), "", m68851 },
3924:
3925: {"ptrapgcw", 6, two(0xf07a, 0x000d), two(0xffff, 0xffff), "#w", m68851 },
3926: {"ptrapgcl", 6, two(0xf07b, 0x000d), two(0xffff, 0xffff), "#l", m68851 },
3927: {"ptrapgc", 4, two(0xf07c, 0x000d), two(0xffff, 0xffff), "", m68851 },
3928:
3929: {"ptrapgsw", 6, two(0xf07a, 0x000c), two(0xffff, 0xffff), "#w", m68851 },
3930: {"ptrapgsl", 6, two(0xf07b, 0x000c), two(0xffff, 0xffff), "#l", m68851 },
3931: {"ptrapgs", 4, two(0xf07c, 0x000c), two(0xffff, 0xffff), "", m68851 },
3932:
3933: {"ptrapicw", 6, two(0xf07a, 0x000b), two(0xffff, 0xffff), "#w", m68851 },
3934: {"ptrapicl", 6, two(0xf07b, 0x000b), two(0xffff, 0xffff), "#l", m68851 },
3935: {"ptrapic", 4, two(0xf07c, 0x000b), two(0xffff, 0xffff), "", m68851 },
3936:
3937: {"ptrapisw", 6, two(0xf07a, 0x000a), two(0xffff, 0xffff), "#w", m68851 },
3938: {"ptrapisl", 6, two(0xf07b, 0x000a), two(0xffff, 0xffff), "#l", m68851 },
3939: {"ptrapis", 4, two(0xf07c, 0x000a), two(0xffff, 0xffff), "", m68851 },
3940:
3941: {"ptraplcw", 6, two(0xf07a, 0x0003), two(0xffff, 0xffff), "#w", m68851 },
3942: {"ptraplcl", 6, two(0xf07b, 0x0003), two(0xffff, 0xffff), "#l", m68851 },
3943: {"ptraplc", 4, two(0xf07c, 0x0003), two(0xffff, 0xffff), "", m68851 },
3944:
3945: {"ptraplsw", 6, two(0xf07a, 0x0002), two(0xffff, 0xffff), "#w", m68851 },
3946: {"ptraplsl", 6, two(0xf07b, 0x0002), two(0xffff, 0xffff), "#l", m68851 },
3947: {"ptrapls", 4, two(0xf07c, 0x0002), two(0xffff, 0xffff), "", m68851 },
3948:
3949: {"ptrapscw", 6, two(0xf07a, 0x0005), two(0xffff, 0xffff), "#w", m68851 },
3950: {"ptrapscl", 6, two(0xf07b, 0x0005), two(0xffff, 0xffff), "#l", m68851 },
3951: {"ptrapsc", 4, two(0xf07c, 0x0005), two(0xffff, 0xffff), "", m68851 },
3952:
3953: {"ptrapssw", 6, two(0xf07a, 0x0004), two(0xffff, 0xffff), "#w", m68851 },
3954: {"ptrapssl", 6, two(0xf07b, 0x0004), two(0xffff, 0xffff), "#l", m68851 },
3955: {"ptrapss", 4, two(0xf07c, 0x0004), two(0xffff, 0xffff), "", m68851 },
3956:
3957: {"ptrapwcw", 6, two(0xf07a, 0x0009), two(0xffff, 0xffff), "#w", m68851 },
3958: {"ptrapwcl", 6, two(0xf07b, 0x0009), two(0xffff, 0xffff), "#l", m68851 },
3959: {"ptrapwc", 4, two(0xf07c, 0x0009), two(0xffff, 0xffff), "", m68851 },
3960:
3961: {"ptrapwsw", 6, two(0xf07a, 0x0008), two(0xffff, 0xffff), "#w", m68851 },
3962: {"ptrapwsl", 6, two(0xf07b, 0x0008), two(0xffff, 0xffff), "#l", m68851 },
3963: {"ptrapws", 4, two(0xf07c, 0x0008), two(0xffff, 0xffff), "", m68851 },
3964:
3965: {"pulse", 2, one(0045314), one(0177777), "", m68060 | mcfisa_a },
3966:
3967: {"pvalid", 4, two(0xf000, 0x2800), two(0xffc0, 0xffff), "Vs&s", m68851 },
3968: {"pvalid", 4, two(0xf000, 0x2c00), two(0xffc0, 0xfff8), "A3&s", m68851 },
3969:
3970: /* FIXME: don't allow Dw==Dx. */
3971: {"remsl", 4, two(0x4c40, 0x0800), two(0xffc0, 0x8ff8), "qsD3D1", mcfhwdiv },
3972: {"remul", 4, two(0x4c40, 0x0000), two(0xffc0, 0x8ff8), "qsD3D1", mcfhwdiv },
3973:
3974: {"reset", 2, one(0047160), one(0177777), "", m68000up },
3975:
3976: {"rolb", 2, one(0160430), one(0170770), "QdDs", m68000up },
3977: {"rolb", 2, one(0160470), one(0170770), "DdDs", m68000up },
3978: {"rolw", 2, one(0160530), one(0170770), "QdDs", m68000up },
3979: {"rolw", 2, one(0160570), one(0170770), "DdDs", m68000up },
3980: {"rolw", 2, one(0163700), one(0177700), "~s", m68000up },
3981: {"roll", 2, one(0160630), one(0170770), "QdDs", m68000up },
3982: {"roll", 2, one(0160670), one(0170770), "DdDs", m68000up },
3983:
3984: {"rorb", 2, one(0160030), one(0170770), "QdDs", m68000up },
3985: {"rorb", 2, one(0160070), one(0170770), "DdDs", m68000up },
3986: {"rorw", 2, one(0160130), one(0170770), "QdDs", m68000up },
3987: {"rorw", 2, one(0160170), one(0170770), "DdDs", m68000up },
3988: {"rorw", 2, one(0163300), one(0177700), "~s", m68000up },
3989: {"rorl", 2, one(0160230), one(0170770), "QdDs", m68000up },
3990: {"rorl", 2, one(0160270), one(0170770), "DdDs", m68000up },
3991:
3992: {"roxlb", 2, one(0160420), one(0170770), "QdDs", m68000up },
3993: {"roxlb", 2, one(0160460), one(0170770), "DdDs", m68000up },
3994: {"roxlw", 2, one(0160520), one(0170770), "QdDs", m68000up },
3995: {"roxlw", 2, one(0160560), one(0170770), "DdDs", m68000up },
3996: {"roxlw", 2, one(0162700), one(0177700), "~s", m68000up },
3997: {"roxll", 2, one(0160620), one(0170770), "QdDs", m68000up },
3998: {"roxll", 2, one(0160660), one(0170770), "DdDs", m68000up },
3999:
4000: {"roxrb", 2, one(0160020), one(0170770), "QdDs", m68000up },
4001: {"roxrb", 2, one(0160060), one(0170770), "DdDs", m68000up },
4002: {"roxrw", 2, one(0160120), one(0170770), "QdDs", m68000up },
4003: {"roxrw", 2, one(0160160), one(0170770), "DdDs", m68000up },
4004: {"roxrw", 2, one(0162300), one(0177700), "~s", m68000up },
4005: {"roxrl", 2, one(0160220), one(0170770), "QdDs", m68000up },
4006: {"roxrl", 2, one(0160260), one(0170770), "DdDs", m68000up },
4007:
4008: {"rtd", 4, one(0047164), one(0177777), "#w", m68010up },
1.1.1.2 root 4009:
1.1 root 4010: {"rte", 2, one(0047163), one(0177777), "", m68000up | mcfisa_a },
1.1.1.2 root 4011:
1.1 root 4012: {"rtm", 2, one(0003300), one(0177760), "Rs", m68020 },
1.1.1.2 root 4013:
1.1 root 4014: {"rtr", 2, one(0047167), one(0177777), "", m68000up },
1.1.1.2 root 4015:
1.1 root 4016: {"rts", 2, one(0047165), one(0177777), "", m68000up | mcfisa_a },
4017:
4018: {"satsl", 2, one(0046200), one(0177770), "Ds", mcfisa_b },
4019:
4020: {"sbcd", 2, one(0100400), one(0170770), "DsDd", m68000up },
4021: {"sbcd", 2, one(0100410), one(0170770), "-s-d", m68000up },
4022:
4023: {"scc", 2, one(0052300), one(0177700), "$s", m68000up },
4024: {"scc", 2, one(0052300), one(0177700), "Ds", mcfisa_a },
4025: {"scs", 2, one(0052700), one(0177700), "$s", m68000up },
4026: {"scs", 2, one(0052700), one(0177700), "Ds", mcfisa_a },
4027: {"seq", 2, one(0053700), one(0177700), "$s", m68000up },
4028: {"seq", 2, one(0053700), one(0177700), "Ds", mcfisa_a },
4029: {"sf", 2, one(0050700), one(0177700), "$s", m68000up },
4030: {"sf", 2, one(0050700), one(0177700), "Ds", mcfisa_a },
4031: {"sge", 2, one(0056300), one(0177700), "$s", m68000up },
4032: {"sge", 2, one(0056300), one(0177700), "Ds", mcfisa_a },
4033: {"sgt", 2, one(0057300), one(0177700), "$s", m68000up },
4034: {"sgt", 2, one(0057300), one(0177700), "Ds", mcfisa_a },
4035: {"shi", 2, one(0051300), one(0177700), "$s", m68000up },
4036: {"shi", 2, one(0051300), one(0177700), "Ds", mcfisa_a },
4037: {"sle", 2, one(0057700), one(0177700), "$s", m68000up },
4038: {"sle", 2, one(0057700), one(0177700), "Ds", mcfisa_a },
4039: {"sls", 2, one(0051700), one(0177700), "$s", m68000up },
4040: {"sls", 2, one(0051700), one(0177700), "Ds", mcfisa_a },
4041: {"slt", 2, one(0056700), one(0177700), "$s", m68000up },
4042: {"slt", 2, one(0056700), one(0177700), "Ds", mcfisa_a },
4043: {"smi", 2, one(0055700), one(0177700), "$s", m68000up },
4044: {"smi", 2, one(0055700), one(0177700), "Ds", mcfisa_a },
4045: {"sne", 2, one(0053300), one(0177700), "$s", m68000up },
4046: {"sne", 2, one(0053300), one(0177700), "Ds", mcfisa_a },
4047: {"spl", 2, one(0055300), one(0177700), "$s", m68000up },
4048: {"spl", 2, one(0055300), one(0177700), "Ds", mcfisa_a },
4049: {"st", 2, one(0050300), one(0177700), "$s", m68000up },
4050: {"st", 2, one(0050300), one(0177700), "Ds", mcfisa_a },
4051: {"svc", 2, one(0054300), one(0177700), "$s", m68000up },
4052: {"svc", 2, one(0054300), one(0177700), "Ds", mcfisa_a },
4053: {"svs", 2, one(0054700), one(0177700), "$s", m68000up },
4054: {"svs", 2, one(0054700), one(0177700), "Ds", mcfisa_a },
4055:
4056: {"stop", 4, one(0047162), one(0177777), "#w", m68000up | mcfisa_a },
4057:
4058: {"strldsr", 4, two(0040347,0043374), two(0177777,0177777), "#w", mcfisa_aa},
4059:
4060: {"subal", 2, one(0110700), one(0170700), "*lAd", m68000up | mcfisa_a },
4061: {"subaw", 2, one(0110300), one(0170700), "*wAd", m68000up },
4062:
4063: {"subib", 4, one(0002000), one(0177700), "#b$s", m68000up },
4064: {"subiw", 4, one(0002100), one(0177700), "#w$s", m68000up },
4065: {"subil", 6, one(0002200), one(0177700), "#l$s", m68000up },
4066: {"subil", 6, one(0002200), one(0177700), "#lDs", mcfisa_a },
4067:
4068: {"subqb", 2, one(0050400), one(0170700), "Qd%s", m68000up },
4069: {"subqw", 2, one(0050500), one(0170700), "Qd%s", m68000up },
4070: {"subql", 2, one(0050600), one(0170700), "Qd%s", m68000up | mcfisa_a },
4071:
4072: /* The sub opcode can generate the suba, subi, and subq instructions. */
4073: {"subb", 2, one(0050400), one(0170700), "Qd%s", m68000up },
4074: {"subb", 4, one(0002000), one(0177700), "#b$s", m68000up },
4075: {"subb", 2, one(0110000), one(0170700), ";bDd", m68000up },
4076: {"subb", 2, one(0110400), one(0170700), "Dd~s", m68000up },
4077: {"subw", 2, one(0050500), one(0170700), "Qd%s", m68000up },
4078: {"subw", 4, one(0002100), one(0177700), "#w$s", m68000up },
4079: {"subw", 2, one(0110300), one(0170700), "*wAd", m68000up },
4080: {"subw", 2, one(0110100), one(0170700), "*wDd", m68000up },
4081: {"subw", 2, one(0110500), one(0170700), "Dd~s", m68000up },
4082: {"subl", 2, one(0050600), one(0170700), "Qd%s", m68000up | mcfisa_a },
4083: {"subl", 6, one(0002200), one(0177700), "#l$s", m68000up },
4084: {"subl", 6, one(0002200), one(0177700), "#lDs", mcfisa_a },
4085: {"subl", 2, one(0110700), one(0170700), "*lAd", m68000up | mcfisa_a },
4086: {"subl", 2, one(0110200), one(0170700), "*lDd", m68000up | mcfisa_a },
4087: {"subl", 2, one(0110600), one(0170700), "Dd~s", m68000up | mcfisa_a },
4088:
4089: {"subxb", 2, one(0110400), one(0170770), "DsDd", m68000up },
4090: {"subxb", 2, one(0110410), one(0170770), "-s-d", m68000up },
4091: {"subxw", 2, one(0110500), one(0170770), "DsDd", m68000up },
4092: {"subxw", 2, one(0110510), one(0170770), "-s-d", m68000up },
4093: {"subxl", 2, one(0110600), one(0170770), "DsDd", m68000up | mcfisa_a },
4094: {"subxl", 2, one(0110610), one(0170770), "-s-d", m68000up },
4095:
4096: {"swap", 2, one(0044100), one(0177770), "Ds", m68000up | mcfisa_a },
4097:
4098: /* swbeg and swbegl are magic constants used on sysV68. The compiler
4099: generates them before a switch table. They tell the debugger and
4100: disassembler that a switch table follows. The parameter is the
4101: number of elements in the table. swbeg means that the entries in
4102: the table are word (2 byte) sized, and swbegl means that the
4103: entries in the table are longword (4 byte) sized. */
4104: {"swbeg", 4, one(0045374), one(0177777), "#w", m68000up | mcfisa_a },
4105: {"swbegl", 6, one(0045375), one(0177777), "#l", m68000up | mcfisa_a },
4106:
4107: {"tas", 2, one(0045300), one(0177700), "$s", m68000up | mcfisa_b},
4108:
4109: #define TBL1(name,insn_size,signed,round,size) \
4110: {name, insn_size, two(0174000, (signed<<11)|(!round<<10)|(size<<6)|0000400), \
4111: two(0177700,0107777), "!sD1", cpu32 }, \
4112: {name, insn_size, two(0174000, (signed<<11)|(!round<<10)|(size<<6)), \
4113: two(0177770,0107770), "DsD3D1", cpu32 }
4114: #define TBL(name1, name2, name3, s, r) \
4115: TBL1(name1, 4, s, r, 0), TBL1(name2, 4, s, r, 1), TBL1(name3, 4, s, r, 2)
4116: TBL("tblsb", "tblsw", "tblsl", 2, 1),
4117: TBL("tblsnb", "tblsnw", "tblsnl", 2, 0),
4118: TBL("tblub", "tbluw", "tblul", 0, 1),
4119: TBL("tblunb", "tblunw", "tblunl", 0, 0),
4120:
4121: {"trap", 2, one(0047100), one(0177760), "Ts", m68000up | mcfisa_a },
4122:
4123: {"trapcc", 2, one(0052374), one(0177777), "", m68020up | cpu32 },
4124: {"trapcs", 2, one(0052774), one(0177777), "", m68020up | cpu32 },
4125: {"trapeq", 2, one(0053774), one(0177777), "", m68020up | cpu32 },
4126: {"trapf", 2, one(0050774), one(0177777), "", m68020up | cpu32 | mcfisa_a },
4127: {"trapge", 2, one(0056374), one(0177777), "", m68020up | cpu32 },
4128: {"trapgt", 2, one(0057374), one(0177777), "", m68020up | cpu32 },
4129: {"traphi", 2, one(0051374), one(0177777), "", m68020up | cpu32 },
4130: {"traple", 2, one(0057774), one(0177777), "", m68020up | cpu32 },
4131: {"trapls", 2, one(0051774), one(0177777), "", m68020up | cpu32 },
4132: {"traplt", 2, one(0056774), one(0177777), "", m68020up | cpu32 },
4133: {"trapmi", 2, one(0055774), one(0177777), "", m68020up | cpu32 },
4134: {"trapne", 2, one(0053374), one(0177777), "", m68020up | cpu32 },
4135: {"trappl", 2, one(0055374), one(0177777), "", m68020up | cpu32 },
4136: {"trapt", 2, one(0050374), one(0177777), "", m68020up | cpu32 },
4137: {"trapvc", 2, one(0054374), one(0177777), "", m68020up | cpu32 },
4138: {"trapvs", 2, one(0054774), one(0177777), "", m68020up | cpu32 },
4139:
4140: {"trapccw", 4, one(0052372), one(0177777), "#w", m68020up|cpu32 },
4141: {"trapcsw", 4, one(0052772), one(0177777), "#w", m68020up|cpu32 },
4142: {"trapeqw", 4, one(0053772), one(0177777), "#w", m68020up|cpu32 },
4143: {"trapfw", 4, one(0050772), one(0177777), "#w", m68020up|cpu32|mcfisa_a},
4144: {"trapgew", 4, one(0056372), one(0177777), "#w", m68020up|cpu32 },
4145: {"trapgtw", 4, one(0057372), one(0177777), "#w", m68020up|cpu32 },
4146: {"traphiw", 4, one(0051372), one(0177777), "#w", m68020up|cpu32 },
4147: {"traplew", 4, one(0057772), one(0177777), "#w", m68020up|cpu32 },
4148: {"traplsw", 4, one(0051772), one(0177777), "#w", m68020up|cpu32 },
4149: {"trapltw", 4, one(0056772), one(0177777), "#w", m68020up|cpu32 },
4150: {"trapmiw", 4, one(0055772), one(0177777), "#w", m68020up|cpu32 },
4151: {"trapnew", 4, one(0053372), one(0177777), "#w", m68020up|cpu32 },
4152: {"trapplw", 4, one(0055372), one(0177777), "#w", m68020up|cpu32 },
4153: {"traptw", 4, one(0050372), one(0177777), "#w", m68020up|cpu32 },
4154: {"trapvcw", 4, one(0054372), one(0177777), "#w", m68020up|cpu32 },
4155: {"trapvsw", 4, one(0054772), one(0177777), "#w", m68020up|cpu32 },
4156:
4157: {"trapccl", 6, one(0052373), one(0177777), "#l", m68020up|cpu32 },
4158: {"trapcsl", 6, one(0052773), one(0177777), "#l", m68020up|cpu32 },
4159: {"trapeql", 6, one(0053773), one(0177777), "#l", m68020up|cpu32 },
4160: {"trapfl", 6, one(0050773), one(0177777), "#l", m68020up|cpu32|mcfisa_a},
4161: {"trapgel", 6, one(0056373), one(0177777), "#l", m68020up|cpu32 },
4162: {"trapgtl", 6, one(0057373), one(0177777), "#l", m68020up|cpu32 },
4163: {"traphil", 6, one(0051373), one(0177777), "#l", m68020up|cpu32 },
4164: {"traplel", 6, one(0057773), one(0177777), "#l", m68020up|cpu32 },
4165: {"traplsl", 6, one(0051773), one(0177777), "#l", m68020up|cpu32 },
4166: {"trapltl", 6, one(0056773), one(0177777), "#l", m68020up|cpu32 },
4167: {"trapmil", 6, one(0055773), one(0177777), "#l", m68020up|cpu32 },
4168: {"trapnel", 6, one(0053373), one(0177777), "#l", m68020up|cpu32 },
4169: {"trappll", 6, one(0055373), one(0177777), "#l", m68020up|cpu32 },
4170: {"traptl", 6, one(0050373), one(0177777), "#l", m68020up|cpu32 },
4171: {"trapvcl", 6, one(0054373), one(0177777), "#l", m68020up|cpu32 },
4172: {"trapvsl", 6, one(0054773), one(0177777), "#l", m68020up|cpu32 },
4173:
4174: {"trapv", 2, one(0047166), one(0177777), "", m68000up },
4175:
4176: {"tstb", 2, one(0045000), one(0177700), ";b", m68020up|cpu32|mcfisa_a },
4177: {"tstb", 2, one(0045000), one(0177700), "$b", m68000up },
4178: {"tstw", 2, one(0045100), one(0177700), "*w", m68020up|cpu32|mcfisa_a },
4179: {"tstw", 2, one(0045100), one(0177700), "$w", m68000up },
4180: {"tstl", 2, one(0045200), one(0177700), "*l", m68020up|cpu32|mcfisa_a },
4181: {"tstl", 2, one(0045200), one(0177700), "$l", m68000up },
4182:
4183: {"unlk", 2, one(0047130), one(0177770), "As", m68000up | mcfisa_a },
4184:
4185: {"unpk", 4, one(0100600), one(0170770), "DsDd#w", m68020up },
4186: {"unpk", 4, one(0100610), one(0170770), "-s-d#w", m68020up },
4187:
4188: {"wddatab", 2, one(0175400), one(0177700), "~s", mcfisa_a },
4189: {"wddataw", 2, one(0175500), one(0177700), "~s", mcfisa_a },
4190: {"wddatal", 2, one(0175600), one(0177700), "~s", mcfisa_a },
4191:
4192: {"wdebug", 4, two(0175720, 03), two(0177770, 0xffff), "as", mcfisa_a },
4193: {"wdebug", 4, two(0175750, 03), two(0177770, 0xffff), "ds", mcfisa_a },
4194: };
4195:
4196: const int m68k_numopcodes = sizeof m68k_opcodes / sizeof m68k_opcodes[0];
4197:
4198: /* These aliases used to be in the above table, each one duplicating
4199: all of the entries for its primary exactly. This table was
4200: constructed by mechanical processing of the opcode table, with a
4201: small number of tweaks done by hand. There are probably a lot more
4202: aliases above that could be moved down here, except for very minor
4203: differences. */
4204:
4205: const struct m68k_opcode_alias m68k_opcode_aliases[] =
4206: {
4207: { "add", "addw", },
4208: { "adda", "addaw", },
4209: { "addi", "addiw", },
4210: { "addq", "addqw", },
4211: { "addx", "addxw", },
4212: { "asl", "aslw", },
4213: { "asr", "asrw", },
4214: { "bhi", "bhiw", },
4215: { "bls", "blsw", },
4216: { "bcc", "bccw", },
4217: { "bcs", "bcsw", },
4218: { "bne", "bnew", },
4219: { "beq", "beqw", },
4220: { "bvc", "bvcw", },
4221: { "bvs", "bvsw", },
4222: { "bpl", "bplw", },
4223: { "bmi", "bmiw", },
4224: { "bge", "bgew", },
4225: { "blt", "bltw", },
4226: { "bgt", "bgtw", },
4227: { "ble", "blew", },
4228: { "bra", "braw", },
4229: { "bsr", "bsrw", },
4230: { "bhib", "bhis", },
4231: { "blsb", "blss", },
4232: { "bccb", "bccs", },
4233: { "bcsb", "bcss", },
4234: { "bneb", "bnes", },
4235: { "beqb", "beqs", },
4236: { "bvcb", "bvcs", },
4237: { "bvsb", "bvss", },
4238: { "bplb", "bpls", },
4239: { "bmib", "bmis", },
4240: { "bgeb", "bges", },
4241: { "bltb", "blts", },
4242: { "bgtb", "bgts", },
4243: { "bleb", "bles", },
4244: { "brab", "bras", },
4245: { "bsrb", "bsrs", },
4246: { "bhs", "bccw" },
4247: { "bhss", "bccs" },
4248: { "bhsb", "bccs" },
4249: { "bhsw", "bccw" },
4250: { "bhsl", "bccl" },
4251: { "blo", "bcsw" },
4252: { "blos", "bcss" },
4253: { "blob", "bcss" },
4254: { "blow", "bcsw" },
4255: { "blol", "bcsl" },
4256: { "br", "braw", },
4257: { "brs", "bras", },
4258: { "brb", "bras", },
4259: { "brw", "braw", },
4260: { "brl", "bral", },
4261: { "jfnlt", "bcc", }, /* Apparently a sun alias. */
4262: { "jfngt", "ble", }, /* Apparently a sun alias. */
4263: { "jfeq", "beqs", }, /* Apparently a sun alias. */
4264: { "bchgb", "bchg", },
4265: { "bchgl", "bchg", },
4266: { "bclrb", "bclr", },
4267: { "bclrl", "bclr", },
4268: { "bsetb", "bset", },
4269: { "bsetl", "bset", },
4270: { "btstb", "btst", },
4271: { "btstl", "btst", },
4272: { "cas2", "cas2w", },
4273: { "cas", "casw", },
4274: { "chk2", "chk2w", },
4275: { "chk", "chkw", },
4276: { "clr", "clrw", },
4277: { "cmp2", "cmp2w", },
4278: { "cmpa", "cmpaw", },
4279: { "cmpi", "cmpiw", },
4280: { "cmpm", "cmpmw", },
4281: { "cmp", "cmpw", },
4282: { "dbccw", "dbcc", },
4283: { "dbcsw", "dbcs", },
4284: { "dbeqw", "dbeq", },
4285: { "dbfw", "dbf", },
4286: { "dbgew", "dbge", },
4287: { "dbgtw", "dbgt", },
4288: { "dbhiw", "dbhi", },
4289: { "dblew", "dble", },
4290: { "dblsw", "dbls", },
4291: { "dbltw", "dblt", },
4292: { "dbmiw", "dbmi", },
4293: { "dbnew", "dbne", },
4294: { "dbplw", "dbpl", },
4295: { "dbtw", "dbt", },
4296: { "dbvcw", "dbvc", },
4297: { "dbvsw", "dbvs", },
4298: { "dbhs", "dbcc", },
4299: { "dbhsw", "dbcc", },
4300: { "dbra", "dbf", },
4301: { "dbraw", "dbf", },
4302: { "tdivsl", "divsl", },
4303: { "divs", "divsw", },
4304: { "divu", "divuw", },
4305: { "ext", "extw", },
4306: { "extbw", "extw", },
4307: { "extwl", "extl", },
4308: { "fbneq", "fbne", },
4309: { "fbsneq", "fbsne", },
4310: { "fdbneq", "fdbne", },
4311: { "fdbsneq", "fdbsne", },
4312: { "fmovecr", "fmovecrx", },
4313: { "fmovm", "fmovem", },
4314: { "fsneq", "fsne", },
4315: { "fssneq", "fssne", },
4316: { "ftrapneq", "ftrapne", },
4317: { "ftrapsneq", "ftrapsne", },
4318: { "fjneq", "fjne", },
4319: { "fjsneq", "fjsne", },
4320: { "jmpl", "jmp", },
4321: { "jmps", "jmp", },
4322: { "jsrl", "jsr", },
4323: { "jsrs", "jsr", },
4324: { "leal", "lea", },
4325: { "lsl", "lslw", },
4326: { "lsr", "lsrw", },
4327: { "mac", "macw" },
4328: { "movea", "moveaw", },
4329: { "movem", "movemw", },
4330: { "movml", "moveml", },
4331: { "movmw", "movemw", },
4332: { "movm", "movemw", },
4333: { "movep", "movepw", },
4334: { "movpw", "movepw", },
4335: { "moves", "movesw" },
4336: { "muls", "mulsw", },
4337: { "mulu", "muluw", },
4338: { "msac", "msacw" },
4339: { "nbcdb", "nbcd" },
4340: { "neg", "negw", },
4341: { "negx", "negxw", },
4342: { "not", "notw", },
4343: { "peal", "pea", },
4344: { "rol", "rolw", },
4345: { "ror", "rorw", },
4346: { "roxl", "roxlw", },
4347: { "roxr", "roxrw", },
4348: { "sats", "satsl", },
4349: { "sbcdb", "sbcd", },
4350: { "sccb", "scc", },
4351: { "scsb", "scs", },
4352: { "seqb", "seq", },
4353: { "sfb", "sf", },
4354: { "sgeb", "sge", },
4355: { "sgtb", "sgt", },
4356: { "shib", "shi", },
4357: { "sleb", "sle", },
4358: { "slsb", "sls", },
4359: { "sltb", "slt", },
4360: { "smib", "smi", },
4361: { "sneb", "sne", },
4362: { "splb", "spl", },
4363: { "stb", "st", },
4364: { "svcb", "svc", },
4365: { "svsb", "svs", },
4366: { "sfge", "sge", },
4367: { "sfgt", "sgt", },
4368: { "sfle", "sle", },
4369: { "sflt", "slt", },
4370: { "sfneq", "sne", },
4371: { "suba", "subaw", },
4372: { "subi", "subiw", },
4373: { "subq", "subqw", },
4374: { "sub", "subw", },
4375: { "subx", "subxw", },
4376: { "swapw", "swap", },
4377: { "tasb", "tas", },
4378: { "tpcc", "trapcc", },
4379: { "tcc", "trapcc", },
4380: { "tst", "tstw", },
4381: { "jbra", "jra", },
4382: { "jbhi", "jhi", },
4383: { "jbls", "jls", },
4384: { "jbcc", "jcc", },
4385: { "jbcs", "jcs", },
4386: { "jbne", "jne", },
4387: { "jbeq", "jeq", },
4388: { "jbvc", "jvc", },
4389: { "jbvs", "jvs", },
4390: { "jbpl", "jpl", },
4391: { "jbmi", "jmi", },
4392: { "jbge", "jge", },
4393: { "jblt", "jlt", },
4394: { "jbgt", "jgt", },
4395: { "jble", "jle", },
4396: { "movql", "moveq", },
4397: { "moveql", "moveq", },
4398: { "movl", "movel", },
4399: { "movq", "moveq", },
4400: { "moval", "moveal", },
4401: { "movaw", "moveaw", },
4402: { "movb", "moveb", },
4403: { "movc", "movec", },
4404: { "movecl", "movec", },
4405: { "movpl", "movepl", },
4406: { "movw", "movew", },
4407: { "movsb", "movesb", },
4408: { "movsl", "movesl", },
4409: { "movsw", "movesw", },
4410: { "mov3q", "mov3ql", },
4411:
4412: { "tdivul", "divul", }, /* For m68k-svr4. */
4413: { "fmovb", "fmoveb", },
4414: { "fsmovb", "fsmoveb", },
4415: { "fdmovb", "fdmoveb", },
4416: { "fmovd", "fmoved", },
4417: { "fsmovd", "fsmoved", },
4418: { "fmovl", "fmovel", },
4419: { "fsmovl", "fsmovel", },
4420: { "fdmovl", "fdmovel", },
4421: { "fmovp", "fmovep", },
4422: { "fsmovp", "fsmovep", },
4423: { "fdmovp", "fdmovep", },
4424: { "fmovs", "fmoves", },
4425: { "fsmovs", "fsmoves", },
4426: { "fdmovs", "fdmoves", },
4427: { "fmovw", "fmovew", },
4428: { "fsmovw", "fsmovew", },
4429: { "fdmovw", "fdmovew", },
4430: { "fmovx", "fmovex", },
4431: { "fsmovx", "fsmovex", },
4432: { "fdmovx", "fdmovex", },
4433: { "fmovcr", "fmovecr", },
4434: { "fmovcrx", "fmovecrx", },
4435: { "ftestb", "ftstb", },
4436: { "ftestd", "ftstd", },
4437: { "ftestl", "ftstl", },
4438: { "ftestp", "ftstp", },
4439: { "ftests", "ftsts", },
4440: { "ftestw", "ftstw", },
4441: { "ftestx", "ftstx", },
4442:
4443: { "bitrevl", "bitrev", },
4444: { "byterevl", "byterev", },
4445: { "ff1l", "ff1", },
4446:
4447: };
4448:
4449: const int m68k_numaliases =
4450: sizeof m68k_opcode_aliases / sizeof m68k_opcode_aliases[0];
4451: /* **** End of m68k-opc.c */
4452: /* **** floatformat.c from sourceware.org CVS 2005-08-14. */
4453: /* IEEE floating point support routines, for GDB, the GNU Debugger.
4454: Copyright (C) 1991, 1994, 1999, 2000, 2003 Free Software Foundation, Inc.
4455:
4456: This file is part of GDB.
4457:
4458: This program is free software; you can redistribute it and/or modify
4459: it under the terms of the GNU General Public License as published by
4460: the Free Software Foundation; either version 2 of the License, or
4461: (at your option) any later version.
4462:
4463: This program is distributed in the hope that it will be useful,
4464: but WITHOUT ANY WARRANTY; without even the implied warranty of
4465: MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
4466: GNU General Public License for more details.
4467:
4468: You should have received a copy of the GNU General Public License
1.1.1.4 ! root 4469: along with this program; if not, see <http://www.gnu.org/licenses/>. */
1.1 root 4470:
4471: /* This is needed to pick up the NAN macro on some systems. */
4472: //#define _GNU_SOURCE
4473:
4474: #ifndef INFINITY
4475: #ifdef HUGE_VAL
4476: #define INFINITY HUGE_VAL
4477: #else
4478: #define INFINITY (1.0 / 0.0)
4479: #endif
4480: #endif
4481:
4482: #ifndef NAN
4483: #define NAN (0.0 / 0.0)
4484: #endif
4485:
4486: static unsigned long get_field (const unsigned char *,
4487: enum floatformat_byteorders,
4488: unsigned int,
4489: unsigned int,
4490: unsigned int);
4491: static int floatformat_always_valid (const struct floatformat *fmt,
4492: const char *from);
4493:
4494: static int
4495: floatformat_always_valid (const struct floatformat *fmt ATTRIBUTE_UNUSED,
4496: const char *from ATTRIBUTE_UNUSED)
4497: {
4498: return 1;
4499: }
4500:
4501: /* The odds that CHAR_BIT will be anything but 8 are low enough that I'm not
4502: going to bother with trying to muck around with whether it is defined in
4503: a system header, what we do if not, etc. */
4504: #define FLOATFORMAT_CHAR_BIT 8
4505:
4506: /* floatformats for IEEE single and double, big and little endian. */
4507: const struct floatformat floatformat_ieee_single_big =
4508: {
4509: floatformat_big, 32, 0, 1, 8, 127, 255, 9, 23,
4510: floatformat_intbit_no,
4511: "floatformat_ieee_single_big",
4512: floatformat_always_valid
4513: };
4514: const struct floatformat floatformat_ieee_single_little =
4515: {
4516: floatformat_little, 32, 0, 1, 8, 127, 255, 9, 23,
4517: floatformat_intbit_no,
4518: "floatformat_ieee_single_little",
4519: floatformat_always_valid
4520: };
4521: const struct floatformat floatformat_ieee_double_big =
4522: {
4523: floatformat_big, 64, 0, 1, 11, 1023, 2047, 12, 52,
4524: floatformat_intbit_no,
4525: "floatformat_ieee_double_big",
4526: floatformat_always_valid
4527: };
4528: const struct floatformat floatformat_ieee_double_little =
4529: {
4530: floatformat_little, 64, 0, 1, 11, 1023, 2047, 12, 52,
4531: floatformat_intbit_no,
4532: "floatformat_ieee_double_little",
4533: floatformat_always_valid
4534: };
4535:
4536: /* floatformat for IEEE double, little endian byte order, with big endian word
4537: ordering, as on the ARM. */
4538:
4539: const struct floatformat floatformat_ieee_double_littlebyte_bigword =
4540: {
4541: floatformat_littlebyte_bigword, 64, 0, 1, 11, 1023, 2047, 12, 52,
4542: floatformat_intbit_no,
4543: "floatformat_ieee_double_littlebyte_bigword",
4544: floatformat_always_valid
4545: };
4546:
4547: static int floatformat_i387_ext_is_valid (const struct floatformat *fmt, const char *from);
4548:
4549: static int
4550: floatformat_i387_ext_is_valid (const struct floatformat *fmt, const char *from)
4551: {
4552: /* In the i387 double-extended format, if the exponent is all ones,
4553: then the integer bit must be set. If the exponent is neither 0
4554: nor ~0, the intbit must also be set. Only if the exponent is
4555: zero can it be zero, and then it must be zero. */
4556: unsigned long exponent, int_bit;
4557: const unsigned char *ufrom = (const unsigned char *) from;
1.1.1.2 root 4558:
1.1 root 4559: exponent = get_field (ufrom, fmt->byteorder, fmt->totalsize,
4560: fmt->exp_start, fmt->exp_len);
4561: int_bit = get_field (ufrom, fmt->byteorder, fmt->totalsize,
4562: fmt->man_start, 1);
1.1.1.2 root 4563:
1.1 root 4564: if ((exponent == 0) != (int_bit == 0))
4565: return 0;
4566: else
4567: return 1;
4568: }
4569:
4570: const struct floatformat floatformat_i387_ext =
4571: {
4572: floatformat_little, 80, 0, 1, 15, 0x3fff, 0x7fff, 16, 64,
4573: floatformat_intbit_yes,
4574: "floatformat_i387_ext",
4575: floatformat_i387_ext_is_valid
4576: };
4577: const struct floatformat floatformat_m68881_ext =
4578: {
4579: /* Note that the bits from 16 to 31 are unused. */
4580: floatformat_big, 96, 0, 1, 15, 0x3fff, 0x7fff, 32, 64,
4581: floatformat_intbit_yes,
4582: "floatformat_m68881_ext",
4583: floatformat_always_valid
4584: };
4585: const struct floatformat floatformat_i960_ext =
4586: {
4587: /* Note that the bits from 0 to 15 are unused. */
4588: floatformat_little, 96, 16, 17, 15, 0x3fff, 0x7fff, 32, 64,
4589: floatformat_intbit_yes,
4590: "floatformat_i960_ext",
4591: floatformat_always_valid
4592: };
4593: const struct floatformat floatformat_m88110_ext =
4594: {
4595: floatformat_big, 80, 0, 1, 15, 0x3fff, 0x7fff, 16, 64,
4596: floatformat_intbit_yes,
4597: "floatformat_m88110_ext",
4598: floatformat_always_valid
4599: };
4600: const struct floatformat floatformat_m88110_harris_ext =
4601: {
4602: /* Harris uses raw format 128 bytes long, but the number is just an ieee
4603: double, and the last 64 bits are wasted. */
4604: floatformat_big,128, 0, 1, 11, 0x3ff, 0x7ff, 12, 52,
4605: floatformat_intbit_no,
4606: "floatformat_m88110_ext_harris",
4607: floatformat_always_valid
4608: };
4609: const struct floatformat floatformat_arm_ext_big =
4610: {
4611: /* Bits 1 to 16 are unused. */
4612: floatformat_big, 96, 0, 17, 15, 0x3fff, 0x7fff, 32, 64,
4613: floatformat_intbit_yes,
4614: "floatformat_arm_ext_big",
4615: floatformat_always_valid
4616: };
4617: const struct floatformat floatformat_arm_ext_littlebyte_bigword =
4618: {
4619: /* Bits 1 to 16 are unused. */
4620: floatformat_littlebyte_bigword, 96, 0, 17, 15, 0x3fff, 0x7fff, 32, 64,
4621: floatformat_intbit_yes,
4622: "floatformat_arm_ext_littlebyte_bigword",
4623: floatformat_always_valid
4624: };
4625: const struct floatformat floatformat_ia64_spill_big =
4626: {
4627: floatformat_big, 128, 0, 1, 17, 65535, 0x1ffff, 18, 64,
4628: floatformat_intbit_yes,
4629: "floatformat_ia64_spill_big",
4630: floatformat_always_valid
4631: };
4632: const struct floatformat floatformat_ia64_spill_little =
4633: {
4634: floatformat_little, 128, 0, 1, 17, 65535, 0x1ffff, 18, 64,
4635: floatformat_intbit_yes,
4636: "floatformat_ia64_spill_little",
4637: floatformat_always_valid
4638: };
4639: const struct floatformat floatformat_ia64_quad_big =
4640: {
4641: floatformat_big, 128, 0, 1, 15, 16383, 0x7fff, 16, 112,
4642: floatformat_intbit_no,
4643: "floatformat_ia64_quad_big",
4644: floatformat_always_valid
4645: };
4646: const struct floatformat floatformat_ia64_quad_little =
4647: {
4648: floatformat_little, 128, 0, 1, 15, 16383, 0x7fff, 16, 112,
4649: floatformat_intbit_no,
4650: "floatformat_ia64_quad_little",
4651: floatformat_always_valid
4652: };
4653:
4654: /* Extract a field which starts at START and is LEN bits long. DATA and
4655: TOTAL_LEN are the thing we are extracting it from, in byteorder ORDER. */
4656: static unsigned long
4657: get_field (const unsigned char *data, enum floatformat_byteorders order,
4658: unsigned int total_len, unsigned int start, unsigned int len)
4659: {
4660: unsigned long result;
4661: unsigned int cur_byte;
4662: int cur_bitshift;
4663:
4664: /* Start at the least significant part of the field. */
4665: cur_byte = (start + len) / FLOATFORMAT_CHAR_BIT;
4666: if (order == floatformat_little)
4667: cur_byte = (total_len / FLOATFORMAT_CHAR_BIT) - cur_byte - 1;
4668: cur_bitshift =
4669: ((start + len) % FLOATFORMAT_CHAR_BIT) - FLOATFORMAT_CHAR_BIT;
4670: result = *(data + cur_byte) >> (-cur_bitshift);
4671: cur_bitshift += FLOATFORMAT_CHAR_BIT;
4672: if (order == floatformat_little)
4673: ++cur_byte;
4674: else
4675: --cur_byte;
4676:
4677: /* Move towards the most significant part of the field. */
4678: while ((unsigned int) cur_bitshift < len)
4679: {
4680: if (len - cur_bitshift < FLOATFORMAT_CHAR_BIT)
4681: /* This is the last byte; zero out the bits which are not part of
4682: this field. */
4683: result |=
4684: (*(data + cur_byte) & ((1 << (len - cur_bitshift)) - 1))
4685: << cur_bitshift;
4686: else
4687: result |= *(data + cur_byte) << cur_bitshift;
4688: cur_bitshift += FLOATFORMAT_CHAR_BIT;
4689: if (order == floatformat_little)
4690: ++cur_byte;
4691: else
4692: --cur_byte;
4693: }
4694: return result;
4695: }
1.1.1.2 root 4696:
1.1 root 4697: #ifndef min
4698: #define min(a, b) ((a) < (b) ? (a) : (b))
4699: #endif
4700:
4701: /* Convert from FMT to a double.
4702: FROM is the address of the extended float.
4703: Store the double in *TO. */
4704:
4705: void
4706: floatformat_to_double (const struct floatformat *fmt,
4707: const char *from, double *to)
4708: {
4709: const unsigned char *ufrom = (const unsigned char *)from;
4710: double dto;
4711: long exponent;
4712: unsigned long mant;
4713: unsigned int mant_bits, mant_off;
4714: int mant_bits_left;
4715: int special_exponent; /* It's a NaN, denorm or zero */
4716:
4717: exponent = get_field (ufrom, fmt->byteorder, fmt->totalsize,
4718: fmt->exp_start, fmt->exp_len);
4719:
4720: /* If the exponent indicates a NaN, we don't have information to
4721: decide what to do. So we handle it like IEEE, except that we
4722: don't try to preserve the type of NaN. FIXME. */
4723: if ((unsigned long) exponent == fmt->exp_nan)
4724: {
4725: int nan;
4726:
4727: mant_off = fmt->man_start;
4728: mant_bits_left = fmt->man_len;
4729: nan = 0;
4730: while (mant_bits_left > 0)
4731: {
4732: mant_bits = min (mant_bits_left, 32);
4733:
4734: if (get_field (ufrom, fmt->byteorder, fmt->totalsize,
4735: mant_off, mant_bits) != 0)
4736: {
4737: /* This is a NaN. */
4738: nan = 1;
4739: break;
4740: }
4741:
4742: mant_off += mant_bits;
4743: mant_bits_left -= mant_bits;
4744: }
4745:
4746: /* On certain systems (such as GNU/Linux), the use of the
4747: INFINITY macro below may generate a warning that can not be
4748: silenced due to a bug in GCC (PR preprocessor/11931). The
4749: preprocessor fails to recognise the __extension__ keyword in
4750: conjunction with the GNU/C99 extension for hexadecimal
4751: floating point constants and will issue a warning when
4752: compiling with -pedantic. */
4753: if (nan)
4754: dto = NAN;
4755: else
4756: dto = INFINITY;
4757:
4758: if (get_field (ufrom, fmt->byteorder, fmt->totalsize, fmt->sign_start, 1))
4759: dto = -dto;
4760:
4761: *to = dto;
4762:
4763: return;
4764: }
4765:
4766: mant_bits_left = fmt->man_len;
4767: mant_off = fmt->man_start;
4768: dto = 0.0;
4769:
4770: special_exponent = exponent == 0 || (unsigned long) exponent == fmt->exp_nan;
4771:
4772: /* Don't bias zero's, denorms or NaNs. */
4773: if (!special_exponent)
4774: exponent -= fmt->exp_bias;
4775:
4776: /* Build the result algebraically. Might go infinite, underflow, etc;
4777: who cares. */
4778:
4779: /* If this format uses a hidden bit, explicitly add it in now. Otherwise,
4780: increment the exponent by one to account for the integer bit. */
4781:
4782: if (!special_exponent)
4783: {
4784: if (fmt->intbit == floatformat_intbit_no)
4785: dto = ldexp (1.0, exponent);
4786: else
4787: exponent++;
4788: }
4789:
4790: while (mant_bits_left > 0)
4791: {
4792: mant_bits = min (mant_bits_left, 32);
4793:
4794: mant = get_field (ufrom, fmt->byteorder, fmt->totalsize,
4795: mant_off, mant_bits);
4796:
4797: /* Handle denormalized numbers. FIXME: What should we do for
4798: non-IEEE formats? */
4799: if (exponent == 0 && mant != 0)
4800: dto += ldexp ((double)mant,
4801: (- fmt->exp_bias
4802: - mant_bits
4803: - (mant_off - fmt->man_start)
4804: + 1));
4805: else
4806: dto += ldexp ((double)mant, exponent - mant_bits);
4807: if (exponent != 0)
4808: exponent -= mant_bits;
4809: mant_off += mant_bits;
4810: mant_bits_left -= mant_bits;
4811: }
4812:
4813: /* Negate it if negative. */
4814: if (get_field (ufrom, fmt->byteorder, fmt->totalsize, fmt->sign_start, 1))
4815: dto = -dto;
4816: *to = dto;
4817: }
4818:
4819: static void put_field (unsigned char *, enum floatformat_byteorders,
4820: unsigned int,
4821: unsigned int,
4822: unsigned int,
4823: unsigned long);
4824:
4825: /* Set a field which starts at START and is LEN bits long. DATA and
4826: TOTAL_LEN are the thing we are extracting it from, in byteorder ORDER. */
4827: static void
4828: put_field (unsigned char *data, enum floatformat_byteorders order,
4829: unsigned int total_len, unsigned int start, unsigned int len,
4830: unsigned long stuff_to_put)
4831: {
4832: unsigned int cur_byte;
4833: int cur_bitshift;
4834:
4835: /* Start at the least significant part of the field. */
4836: cur_byte = (start + len) / FLOATFORMAT_CHAR_BIT;
4837: if (order == floatformat_little)
4838: cur_byte = (total_len / FLOATFORMAT_CHAR_BIT) - cur_byte - 1;
4839: cur_bitshift =
4840: ((start + len) % FLOATFORMAT_CHAR_BIT) - FLOATFORMAT_CHAR_BIT;
4841: *(data + cur_byte) &=
4842: ~(((1 << ((start + len) % FLOATFORMAT_CHAR_BIT)) - 1) << (-cur_bitshift));
4843: *(data + cur_byte) |=
4844: (stuff_to_put & ((1 << FLOATFORMAT_CHAR_BIT) - 1)) << (-cur_bitshift);
4845: cur_bitshift += FLOATFORMAT_CHAR_BIT;
4846: if (order == floatformat_little)
4847: ++cur_byte;
4848: else
4849: --cur_byte;
4850:
4851: /* Move towards the most significant part of the field. */
4852: while ((unsigned int) cur_bitshift < len)
4853: {
4854: if (len - cur_bitshift < FLOATFORMAT_CHAR_BIT)
4855: {
4856: /* This is the last byte. */
4857: *(data + cur_byte) &=
4858: ~((1 << (len - cur_bitshift)) - 1);
4859: *(data + cur_byte) |= (stuff_to_put >> cur_bitshift);
4860: }
4861: else
4862: *(data + cur_byte) = ((stuff_to_put >> cur_bitshift)
4863: & ((1 << FLOATFORMAT_CHAR_BIT) - 1));
4864: cur_bitshift += FLOATFORMAT_CHAR_BIT;
4865: if (order == floatformat_little)
4866: ++cur_byte;
4867: else
4868: --cur_byte;
4869: }
4870: }
4871:
4872: /* The converse: convert the double *FROM to an extended float
4873: and store where TO points. Neither FROM nor TO have any alignment
4874: restrictions. */
4875:
4876: void
4877: floatformat_from_double (const struct floatformat *fmt,
4878: const double *from, char *to)
4879: {
4880: double dfrom;
4881: int exponent;
4882: double mant;
4883: unsigned int mant_bits, mant_off;
4884: int mant_bits_left;
4885: unsigned char *uto = (unsigned char *)to;
4886:
4887: dfrom = *from;
4888: memset (uto, 0, fmt->totalsize / FLOATFORMAT_CHAR_BIT);
4889:
4890: /* If negative, set the sign bit. */
4891: if (dfrom < 0)
4892: {
4893: put_field (uto, fmt->byteorder, fmt->totalsize, fmt->sign_start, 1, 1);
4894: dfrom = -dfrom;
4895: }
4896:
4897: if (dfrom == 0)
4898: {
4899: /* 0.0. */
4900: return;
4901: }
4902:
4903: if (dfrom != dfrom)
4904: {
4905: /* NaN. */
4906: put_field (uto, fmt->byteorder, fmt->totalsize, fmt->exp_start,
4907: fmt->exp_len, fmt->exp_nan);
4908: /* Be sure it's not infinity, but NaN value is irrelevant. */
4909: put_field (uto, fmt->byteorder, fmt->totalsize, fmt->man_start,
4910: 32, 1);
4911: return;
4912: }
4913:
4914: if (dfrom + dfrom == dfrom)
4915: {
4916: /* This can only happen for an infinite value (or zero, which we
4917: already handled above). */
4918: put_field (uto, fmt->byteorder, fmt->totalsize, fmt->exp_start,
4919: fmt->exp_len, fmt->exp_nan);
4920: return;
4921: }
4922:
4923: mant = frexp (dfrom, &exponent);
4924: if (exponent + fmt->exp_bias - 1 > 0)
4925: put_field (uto, fmt->byteorder, fmt->totalsize, fmt->exp_start,
4926: fmt->exp_len, exponent + fmt->exp_bias - 1);
4927: else
4928: {
4929: /* Handle a denormalized number. FIXME: What should we do for
4930: non-IEEE formats? */
4931: put_field (uto, fmt->byteorder, fmt->totalsize, fmt->exp_start,
4932: fmt->exp_len, 0);
4933: mant = ldexp (mant, exponent + fmt->exp_bias - 1);
4934: }
4935:
4936: mant_bits_left = fmt->man_len;
4937: mant_off = fmt->man_start;
4938: while (mant_bits_left > 0)
4939: {
4940: unsigned long mant_long;
4941: mant_bits = mant_bits_left < 32 ? mant_bits_left : 32;
4942:
4943: mant *= 4294967296.0;
4944: mant_long = (unsigned long)mant;
4945: mant -= mant_long;
4946:
4947: /* If the integer bit is implicit, and we are not creating a
4948: denormalized number, then we need to discard it. */
4949: if ((unsigned int) mant_bits_left == fmt->man_len
4950: && fmt->intbit == floatformat_intbit_no
4951: && exponent + fmt->exp_bias - 1 > 0)
4952: {
4953: mant_long &= 0x7fffffff;
4954: mant_bits -= 1;
4955: }
4956: else if (mant_bits < 32)
4957: {
4958: /* The bits we want are in the most significant MANT_BITS bits of
4959: mant_long. Move them to the least significant. */
4960: mant_long >>= 32 - mant_bits;
4961: }
4962:
4963: put_field (uto, fmt->byteorder, fmt->totalsize,
4964: mant_off, mant_bits, mant_long);
4965: mant_off += mant_bits;
4966: mant_bits_left -= mant_bits;
4967: }
4968: }
4969:
4970: /* Return non-zero iff the data at FROM is a valid number in format FMT. */
4971:
4972: int
4973: floatformat_is_valid (const struct floatformat *fmt, const char *from)
4974: {
4975: return fmt->is_valid (fmt, from);
4976: }
4977:
4978:
4979: #ifdef IEEE_DEBUG
4980:
4981: /* This is to be run on a host which uses IEEE floating point. */
4982:
4983: void
4984: ieee_test (double n)
4985: {
4986: double result;
4987:
4988: floatformat_to_double (&floatformat_ieee_double_little, (char *) &n,
4989: &result);
4990: if ((n != result && (! isnan (n) || ! isnan (result)))
4991: || (n < 0 && result >= 0)
4992: || (n >= 0 && result < 0))
4993: printf ("Differ(to): %.20g -> %.20g\n", n, result);
4994:
4995: floatformat_from_double (&floatformat_ieee_double_little, &n,
4996: (char *) &result);
4997: if ((n != result && (! isnan (n) || ! isnan (result)))
4998: || (n < 0 && result >= 0)
4999: || (n >= 0 && result < 0))
5000: printf ("Differ(from): %.20g -> %.20g\n", n, result);
5001:
5002: #if 0
5003: {
5004: char exten[16];
5005:
5006: floatformat_from_double (&floatformat_m68881_ext, &n, exten);
5007: floatformat_to_double (&floatformat_m68881_ext, exten, &result);
5008: if (n != result)
5009: printf ("Differ(to+from): %.20g -> %.20g\n", n, result);
5010: }
5011: #endif
5012:
5013: #if IEEE_DEBUG > 1
5014: /* This is to be run on a host which uses 68881 format. */
5015: {
5016: long double ex = *(long double *)exten;
5017: if (ex != n)
5018: printf ("Differ(from vs. extended): %.20g\n", n);
5019: }
5020: #endif
5021: }
5022:
5023: int
5024: main (void)
5025: {
5026: ieee_test (0.0);
5027: ieee_test (0.5);
5028: ieee_test (256.0);
5029: ieee_test (0.12345);
5030: ieee_test (234235.78907234);
5031: ieee_test (-512.0);
5032: ieee_test (-0.004321);
5033: ieee_test (1.2E-70);
5034: ieee_test (1.2E-316);
5035: ieee_test (4.9406564584124654E-324);
5036: ieee_test (- 4.9406564584124654E-324);
5037: ieee_test (- 0.0);
5038: ieee_test (- INFINITY);
5039: ieee_test (- NAN);
5040: ieee_test (INFINITY);
5041: ieee_test (NAN);
5042: return 0;
5043: }
5044: #endif
5045: /* **** End of floatformat.c */
This archive runs on limited infrastructure. Preserving old code on modern bandwidth. Automated agents are requested to crawl responsibly.