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1.1 root 1: /* This file is composed of several different files from the upstream
2: sourceware.org CVS. Original file boundaries marked with **** */
3:
4: #include <string.h>
5: #include <math.h>
6: #include <stdio.h>
7:
8: #include "dis-asm.h"
9:
1.1.1.3 root 10: /* **** floatformat.h from sourceware.org CVS 2005-08-14. */
1.1 root 11: /* IEEE floating point support declarations, for GDB, the GNU Debugger.
12: Copyright 1991, 1994, 1995, 1997, 2000, 2003 Free Software Foundation, Inc.
13:
14: This file is part of GDB.
15:
16: This program is free software; you can redistribute it and/or modify
17: it under the terms of the GNU General Public License as published by
18: the Free Software Foundation; either version 2 of the License, or
19: (at your option) any later version.
20:
21: This program is distributed in the hope that it will be useful,
22: but WITHOUT ANY WARRANTY; without even the implied warranty of
23: MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
24: GNU General Public License for more details.
25:
26: You should have received a copy of the GNU General Public License
1.1.1.4 root 27: along with this program; if not, see <http://www.gnu.org/licenses/>. */
1.1 root 28:
29: #if !defined (FLOATFORMAT_H)
30: #define FLOATFORMAT_H 1
31:
32: /*#include "ansidecl.h" */
33:
34: /* A floatformat consists of a sign bit, an exponent and a mantissa. Once the
35: bytes are concatenated according to the byteorder flag, then each of those
36: fields is contiguous. We number the bits with 0 being the most significant
37: (i.e. BITS_BIG_ENDIAN type numbering), and specify which bits each field
38: contains with the *_start and *_len fields. */
39:
40: /* What is the order of the bytes. */
41:
42: enum floatformat_byteorders {
43:
44: /* Standard little endian byte order.
45: EX: 1.2345678e10 => 00 00 80 c5 e0 fe 06 42 */
46:
47: floatformat_little,
48:
49: /* Standard big endian byte order.
50: EX: 1.2345678e10 => 42 06 fe e0 c5 80 00 00 */
51:
52: floatformat_big,
53:
54: /* Little endian byte order but big endian word order.
55: EX: 1.2345678e10 => e0 fe 06 42 00 00 80 c5 */
56:
57: floatformat_littlebyte_bigword
58:
59: };
60:
61: enum floatformat_intbit { floatformat_intbit_yes, floatformat_intbit_no };
62:
63: struct floatformat
64: {
65: enum floatformat_byteorders byteorder;
66: unsigned int totalsize; /* Total size of number in bits */
67:
68: /* Sign bit is always one bit long. 1 means negative, 0 means positive. */
69: unsigned int sign_start;
70:
71: unsigned int exp_start;
72: unsigned int exp_len;
73: /* Bias added to a "true" exponent to form the biased exponent. It
74: is intentionally signed as, otherwize, -exp_bias can turn into a
75: very large number (e.g., given the exp_bias of 0x3fff and a 64
76: bit long, the equation (long)(1 - exp_bias) evaluates to
77: 4294950914) instead of -16382). */
78: int exp_bias;
79: /* Exponent value which indicates NaN. This is the actual value stored in
80: the float, not adjusted by the exp_bias. This usually consists of all
81: one bits. */
82: unsigned int exp_nan;
83:
84: unsigned int man_start;
85: unsigned int man_len;
86:
87: /* Is the integer bit explicit or implicit? */
88: enum floatformat_intbit intbit;
89:
90: /* Internal name for debugging. */
91: const char *name;
92:
93: /* Validator method. */
94: int (*is_valid) (const struct floatformat *fmt, const char *from);
95: };
96:
97: /* floatformats for IEEE single and double, big and little endian. */
98:
99: extern const struct floatformat floatformat_ieee_single_big;
100: extern const struct floatformat floatformat_ieee_single_little;
101: extern const struct floatformat floatformat_ieee_double_big;
102: extern const struct floatformat floatformat_ieee_double_little;
103:
104: /* floatformat for ARM IEEE double, little endian bytes and big endian words */
105:
106: extern const struct floatformat floatformat_ieee_double_littlebyte_bigword;
107:
108: /* floatformats for various extendeds. */
109:
110: extern const struct floatformat floatformat_i387_ext;
111: extern const struct floatformat floatformat_m68881_ext;
112: extern const struct floatformat floatformat_i960_ext;
113: extern const struct floatformat floatformat_m88110_ext;
114: extern const struct floatformat floatformat_m88110_harris_ext;
115: extern const struct floatformat floatformat_arm_ext_big;
116: extern const struct floatformat floatformat_arm_ext_littlebyte_bigword;
117: /* IA-64 Floating Point register spilt into memory. */
118: extern const struct floatformat floatformat_ia64_spill_big;
119: extern const struct floatformat floatformat_ia64_spill_little;
120: extern const struct floatformat floatformat_ia64_quad_big;
121: extern const struct floatformat floatformat_ia64_quad_little;
122:
123: /* Convert from FMT to a double.
124: FROM is the address of the extended float.
125: Store the double in *TO. */
126:
127: extern void
128: floatformat_to_double (const struct floatformat *, const char *, double *);
129:
130: /* The converse: convert the double *FROM to FMT
131: and store where TO points. */
132:
133: extern void
134: floatformat_from_double (const struct floatformat *, const double *, char *);
135:
136: /* Return non-zero iff the data at FROM is a valid number in format FMT. */
137:
138: extern int
139: floatformat_is_valid (const struct floatformat *fmt, const char *from);
140:
141: #endif /* defined (FLOATFORMAT_H) */
142: /* **** End of floatformat.h */
143: /* **** m68k-dis.h from sourceware.org CVS 2005-08-14. */
144: /* Opcode table header for m680[01234]0/m6888[12]/m68851.
145: Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1999, 2001,
146: 2003, 2004 Free Software Foundation, Inc.
147:
148: This file is part of GDB, GAS, and the GNU binutils.
149:
150: GDB, GAS, and the GNU binutils are free software; you can redistribute
151: them and/or modify them under the terms of the GNU General Public
152: License as published by the Free Software Foundation; either version
153: 1, or (at your option) any later version.
154:
155: GDB, GAS, and the GNU binutils are distributed in the hope that they
156: will be useful, but WITHOUT ANY WARRANTY; without even the implied
157: warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See
158: the GNU General Public License for more details.
159:
160: You should have received a copy of the GNU General Public License
1.1.1.4 root 161: along with this file; see the file COPYING. If not,
162: see <http://www.gnu.org/licenses/>. */
1.1 root 163:
164: /* These are used as bit flags for the arch field in the m68k_opcode
165: structure. */
166: #define _m68k_undef 0
167: #define m68000 0x001
168: #define m68008 m68000 /* Synonym for -m68000. otherwise unused. */
169: #define m68010 0x002
170: #define m68020 0x004
171: #define m68030 0x008
172: #define m68ec030 m68030 /* Similar enough to -m68030 to ignore differences;
173: gas will deal with the few differences. */
174: #define m68040 0x010
175: /* There is no 68050. */
176: #define m68060 0x020
177: #define m68881 0x040
178: #define m68882 m68881 /* Synonym for -m68881. otherwise unused. */
179: #define m68851 0x080
180: #define cpu32 0x100 /* e.g., 68332 */
181:
182: #define mcfmac 0x200 /* ColdFire MAC. */
183: #define mcfemac 0x400 /* ColdFire EMAC. */
184: #define cfloat 0x800 /* ColdFire FPU. */
185: #define mcfhwdiv 0x1000 /* ColdFire hardware divide. */
186:
187: #define mcfisa_a 0x2000 /* ColdFire ISA_A. */
188: #define mcfisa_aa 0x4000 /* ColdFire ISA_A+. */
189: #define mcfisa_b 0x8000 /* ColdFire ISA_B. */
190: #define mcfusp 0x10000 /* ColdFire USP instructions. */
191:
192: #define mcf5200 0x20000
193: #define mcf5206e 0x40000
194: #define mcf521x 0x80000
195: #define mcf5249 0x100000
196: #define mcf528x 0x200000
197: #define mcf5307 0x400000
198: #define mcf5407 0x800000
199: #define mcf5470 0x1000000
200: #define mcf5480 0x2000000
201:
202: /* Handy aliases. */
203: #define m68040up (m68040 | m68060)
204: #define m68030up (m68030 | m68040up)
205: #define m68020up (m68020 | m68030up)
206: #define m68010up (m68010 | cpu32 | m68020up)
207: #define m68000up (m68000 | m68010up)
208:
209: #define mfloat (m68881 | m68882 | m68040 | m68060)
210: #define mmmu (m68851 | m68030 | m68040 | m68060)
211:
212: /* The structure used to hold information for an opcode. */
213:
214: struct m68k_opcode
215: {
216: /* The opcode name. */
217: const char *name;
218: /* The pseudo-size of the instruction(in bytes). Used to determine
219: number of bytes necessary to disassemble the instruction. */
220: unsigned int size;
221: /* The opcode itself. */
222: unsigned long opcode;
223: /* The mask used by the disassembler. */
224: unsigned long match;
225: /* The arguments. */
226: const char *args;
227: /* The architectures which support this opcode. */
228: unsigned int arch;
229: };
230:
231: /* The structure used to hold information for an opcode alias. */
232:
233: struct m68k_opcode_alias
234: {
235: /* The alias name. */
236: const char *alias;
237: /* The instruction for which this is an alias. */
238: const char *primary;
239: };
240:
241: /* We store four bytes of opcode for all opcodes because that is the
242: most any of them need. The actual length of an instruction is
243: always at least 2 bytes, and is as much longer as necessary to hold
244: the operands it has.
245:
246: The match field is a mask saying which bits must match particular
247: opcode in order for an instruction to be an instance of that
248: opcode.
249:
250: The args field is a string containing two characters for each
251: operand of the instruction. The first specifies the kind of
252: operand; the second, the place it is stored. */
253:
254: /* Kinds of operands:
255: Characters used: AaBbCcDdEeFfGgHIiJkLlMmnOopQqRrSsTtU VvWwXxYyZz01234|*~%;@!&$?/<>#^+-
256:
257: D data register only. Stored as 3 bits.
258: A address register only. Stored as 3 bits.
259: a address register indirect only. Stored as 3 bits.
260: R either kind of register. Stored as 4 bits.
261: r either kind of register indirect only. Stored as 4 bits.
262: At the moment, used only for cas2 instruction.
263: F floating point coprocessor register only. Stored as 3 bits.
264: O an offset (or width): immediate data 0-31 or data register.
265: Stored as 6 bits in special format for BF... insns.
266: + autoincrement only. Stored as 3 bits (number of the address register).
267: - autodecrement only. Stored as 3 bits (number of the address register).
268: Q quick immediate data. Stored as 3 bits.
269: This matches an immediate operand only when value is in range 1 .. 8.
270: M moveq immediate data. Stored as 8 bits.
271: This matches an immediate operand only when value is in range -128..127
272: T trap vector immediate data. Stored as 4 bits.
273:
274: k K-factor for fmove.p instruction. Stored as a 7-bit constant or
275: a three bit register offset, depending on the field type.
276:
277: # immediate data. Stored in special places (b, w or l)
278: which say how many bits to store.
279: ^ immediate data for floating point instructions. Special places
280: are offset by 2 bytes from '#'...
281: B pc-relative address, converted to an offset
282: that is treated as immediate data.
283: d displacement and register. Stores the register as 3 bits
284: and stores the displacement in the entire second word.
285:
286: C the CCR. No need to store it; this is just for filtering validity.
287: S the SR. No need to store, just as with CCR.
288: U the USP. No need to store, just as with CCR.
289: E the MAC ACC. No need to store, just as with CCR.
290: e the EMAC ACC[0123].
291: G the MAC/EMAC MACSR. No need to store, just as with CCR.
292: g the EMAC ACCEXT{01,23}.
293: H the MASK. No need to store, just as with CCR.
294: i the MAC/EMAC scale factor.
295:
296: I Coprocessor ID. Not printed if 1. The Coprocessor ID is always
297: extracted from the 'd' field of word one, which means that an extended
298: coprocessor opcode can be skipped using the 'i' place, if needed.
299:
300: s System Control register for the floating point coprocessor.
301:
302: J Misc register for movec instruction, stored in 'j' format.
303: Possible values:
304: 0x000 SFC Source Function Code reg [60, 40, 30, 20, 10]
305: 0x001 DFC Data Function Code reg [60, 40, 30, 20, 10]
306: 0x002 CACR Cache Control Register [60, 40, 30, 20, mcf]
307: 0x003 TC MMU Translation Control [60, 40]
308: 0x004 ITT0 Instruction Transparent
309: Translation reg 0 [60, 40]
310: 0x005 ITT1 Instruction Transparent
311: Translation reg 1 [60, 40]
312: 0x006 DTT0 Data Transparent
313: Translation reg 0 [60, 40]
314: 0x007 DTT1 Data Transparent
315: Translation reg 1 [60, 40]
316: 0x008 BUSCR Bus Control Register [60]
317: 0x800 USP User Stack Pointer [60, 40, 30, 20, 10]
318: 0x801 VBR Vector Base reg [60, 40, 30, 20, 10, mcf]
319: 0x802 CAAR Cache Address Register [ 30, 20]
320: 0x803 MSP Master Stack Pointer [ 40, 30, 20]
321: 0x804 ISP Interrupt Stack Pointer [ 40, 30, 20]
322: 0x805 MMUSR MMU Status reg [ 40]
323: 0x806 URP User Root Pointer [60, 40]
324: 0x807 SRP Supervisor Root Pointer [60, 40]
325: 0x808 PCR Processor Configuration reg [60]
326: 0xC00 ROMBAR ROM Base Address Register [520X]
327: 0xC04 RAMBAR0 RAM Base Address Register 0 [520X]
328: 0xC05 RAMBAR1 RAM Base Address Register 0 [520X]
329: 0xC0F MBAR0 RAM Base Address Register 0 [520X]
330: 0xC04 FLASHBAR FLASH Base Address Register [mcf528x]
331: 0xC05 RAMBAR Static RAM Base Address Register [mcf528x]
332:
333: L Register list of the type d0-d7/a0-a7 etc.
334: (New! Improved! Can also hold fp0-fp7, as well!)
335: The assembler tries to see if the registers match the insn by
336: looking at where the insn wants them stored.
337:
338: l Register list like L, but with all the bits reversed.
339: Used for going the other way. . .
340:
341: c cache identifier which may be "nc" for no cache, "ic"
342: for instruction cache, "dc" for data cache, or "bc"
343: for both caches. Used in cinv and cpush. Always
344: stored in position "d".
345:
346: u Any register, with ``upper'' or ``lower'' specification. Used
347: in the mac instructions with size word.
348:
349: The remainder are all stored as 6 bits using an address mode and a
350: register number; they differ in which addressing modes they match.
351:
352: * all (modes 0-6,7.0-4)
353: ~ alterable memory (modes 2-6,7.0,7.1)
354: (not 0,1,7.2-4)
355: % alterable (modes 0-6,7.0,7.1)
356: (not 7.2-4)
357: ; data (modes 0,2-6,7.0-4)
358: (not 1)
359: @ data, but not immediate (modes 0,2-6,7.0-3)
360: (not 1,7.4)
361: ! control (modes 2,5,6,7.0-3)
362: (not 0,1,3,4,7.4)
363: & alterable control (modes 2,5,6,7.0,7.1)
364: (not 0,1,3,4,7.2-4)
365: $ alterable data (modes 0,2-6,7.0,7.1)
366: (not 1,7.2-4)
367: ? alterable control, or data register (modes 0,2,5,6,7.0,7.1)
368: (not 1,3,4,7.2-4)
369: / control, or data register (modes 0,2,5,6,7.0-3)
370: (not 1,3,4,7.4)
371: > *save operands (modes 2,4,5,6,7.0,7.1)
372: (not 0,1,3,7.2-4)
373: < *restore operands (modes 2,3,5,6,7.0-3)
374: (not 0,1,4,7.4)
375:
376: coldfire move operands:
377: m (modes 0-4)
378: n (modes 5,7.2)
379: o (modes 6,7.0,7.1,7.3,7.4)
380: p (modes 0-5)
381:
382: coldfire bset/bclr/btst/mulsl/mulul operands:
383: q (modes 0,2-5)
384: v (modes 0,2-5,7.0,7.1)
385: b (modes 0,2-5,7.2)
386: w (modes 2-5,7.2)
387: y (modes 2,5)
388: z (modes 2,5,7.2)
389: x mov3q immediate operand.
390: 4 (modes 2,3,4,5)
391: */
392:
393: /* For the 68851: */
394: /* I didn't use much imagination in choosing the
395: following codes, so many of them aren't very
396: mnemonic. -rab
397:
398: 0 32 bit pmmu register
399: Possible values:
400: 000 TC Translation Control Register (68030, 68851)
401:
402: 1 16 bit pmmu register
403: 111 AC Access Control (68851)
404:
405: 2 8 bit pmmu register
406: 100 CAL Current Access Level (68851)
407: 101 VAL Validate Access Level (68851)
408: 110 SCC Stack Change Control (68851)
409:
410: 3 68030-only pmmu registers (32 bit)
411: 010 TT0 Transparent Translation reg 0
412: (aka Access Control reg 0 -- AC0 -- on 68ec030)
413: 011 TT1 Transparent Translation reg 1
414: (aka Access Control reg 1 -- AC1 -- on 68ec030)
415:
416: W wide pmmu registers
417: Possible values:
418: 001 DRP Dma Root Pointer (68851)
419: 010 SRP Supervisor Root Pointer (68030, 68851)
420: 011 CRP Cpu Root Pointer (68030, 68851)
421:
422: f function code register (68030, 68851)
423: 0 SFC
424: 1 DFC
425:
426: V VAL register only (68851)
427:
428: X BADx, BACx (16 bit)
429: 100 BAD Breakpoint Acknowledge Data (68851)
430: 101 BAC Breakpoint Acknowledge Control (68851)
431:
432: Y PSR (68851) (MMUSR on 68030) (ACUSR on 68ec030)
433: Z PCSR (68851)
434:
435: | memory (modes 2-6, 7.*)
436:
437: t address test level (68030 only)
438: Stored as 3 bits, range 0-7.
439: Also used for breakpoint instruction now.
440:
441: */
442:
443: /* Places to put an operand, for non-general operands:
444: Characters used: BbCcDdFfGgHhIijkLlMmNnostWw123456789/
445:
446: s source, low bits of first word.
447: d dest, shifted 9 in first word
448: 1 second word, shifted 12
449: 2 second word, shifted 6
450: 3 second word, shifted 0
451: 4 third word, shifted 12
452: 5 third word, shifted 6
453: 6 third word, shifted 0
454: 7 second word, shifted 7
455: 8 second word, shifted 10
456: 9 second word, shifted 5
457: D store in both place 1 and place 3; for divul and divsl.
458: B first word, low byte, for branch displacements
459: W second word (entire), for branch displacements
460: L second and third words (entire), for branch displacements
461: (also overloaded for move16)
462: b second word, low byte
463: w second word (entire) [variable word/long branch offset for dbra]
464: W second word (entire) (must be signed 16 bit value)
465: l second and third word (entire)
466: g variable branch offset for bra and similar instructions.
467: The place to store depends on the magnitude of offset.
468: t store in both place 7 and place 8; for floating point operations
469: c branch offset for cpBcc operations.
470: The place to store is word two if bit six of word one is zero,
471: and words two and three if bit six of word one is one.
472: i Increment by two, to skip over coprocessor extended operands. Only
473: works with the 'I' format.
474: k Dynamic K-factor field. Bits 6-4 of word 2, used as a register number.
475: Also used for dynamic fmovem instruction.
476: C floating point coprocessor constant - 7 bits. Also used for static
477: K-factors...
478: j Movec register #, stored in 12 low bits of second word.
479: m For M[S]ACx; 4 bits split with MSB shifted 6 bits in first word
480: and remaining 3 bits of register shifted 9 bits in first word.
481: Indicate upper/lower in 1 bit shifted 7 bits in second word.
482: Use with `R' or `u' format.
483: n `m' withouth upper/lower indication. (For M[S]ACx; 4 bits split
484: with MSB shifted 6 bits in first word and remaining 3 bits of
485: register shifted 9 bits in first word. No upper/lower
486: indication is done.) Use with `R' or `u' format.
487: o For M[S]ACw; 4 bits shifted 12 in second word (like `1').
488: Indicate upper/lower in 1 bit shifted 7 bits in second word.
489: Use with `R' or `u' format.
490: M For M[S]ACw; 4 bits in low bits of first word. Indicate
491: upper/lower in 1 bit shifted 6 bits in second word. Use with
492: `R' or `u' format.
493: N For M[S]ACw; 4 bits in low bits of second word. Indicate
494: upper/lower in 1 bit shifted 6 bits in second word. Use with
495: `R' or `u' format.
496: h shift indicator (scale factor), 1 bit shifted 10 in second word
497:
498: Places to put operand, for general operands:
499: d destination, shifted 6 bits in first word
500: b source, at low bit of first word, and immediate uses one byte
501: w source, at low bit of first word, and immediate uses two bytes
502: l source, at low bit of first word, and immediate uses four bytes
503: s source, at low bit of first word.
504: Used sometimes in contexts where immediate is not allowed anyway.
505: f single precision float, low bit of 1st word, immediate uses 4 bytes
506: F double precision float, low bit of 1st word, immediate uses 8 bytes
507: x extended precision float, low bit of 1st word, immediate uses 12 bytes
508: p packed float, low bit of 1st word, immediate uses 12 bytes
509: G EMAC accumulator, load (bit 4 2nd word, !bit8 first word)
510: H EMAC accumulator, non load (bit 4 2nd word, bit 8 first word)
511: F EMAC ACCx
512: f EMAC ACCy
513: I MAC/EMAC scale factor
514: / Like 's', but set 2nd word, bit 5 if trailing_ampersand set
515: ] first word, bit 10
516: */
517:
518: extern const struct m68k_opcode m68k_opcodes[];
519: extern const struct m68k_opcode_alias m68k_opcode_aliases[];
520:
521: extern const int m68k_numopcodes, m68k_numaliases;
522:
523: /* **** End of m68k-opcode.h */
524: /* **** m68k-dis.c from sourceware.org CVS 2005-08-14. */
525: /* Print Motorola 68k instructions.
526: Copyright 1986, 1987, 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997,
527: 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005
528: Free Software Foundation, Inc.
529:
530: This file is free software; you can redistribute it and/or modify
531: it under the terms of the GNU General Public License as published by
532: the Free Software Foundation; either version 2 of the License, or
533: (at your option) any later version.
534:
535: This program is distributed in the hope that it will be useful,
536: but WITHOUT ANY WARRANTY; without even the implied warranty of
537: MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
538: GNU General Public License for more details.
539:
540: You should have received a copy of the GNU General Public License
1.1.1.4 root 541: along with this program; if not, see <http://www.gnu.org/licenses/>. */
1.1 root 542:
543: /* Local function prototypes. */
544:
1.1.1.3 root 545: static const char * const fpcr_names[] =
1.1 root 546: {
547: "", "%fpiar", "%fpsr", "%fpiar/%fpsr", "%fpcr",
548: "%fpiar/%fpcr", "%fpsr/%fpcr", "%fpiar/%fpsr/%fpcr"
549: };
550:
1.1.1.3 root 551: static const char *const reg_names[] =
1.1 root 552: {
553: "%d0", "%d1", "%d2", "%d3", "%d4", "%d5", "%d6", "%d7",
554: "%a0", "%a1", "%a2", "%a3", "%a4", "%a5", "%fp", "%sp",
555: "%ps", "%pc"
556: };
557:
558: /* Name of register halves for MAC/EMAC.
1.1.1.2 root 559: Separate from reg_names since 'spu', 'fpl' look weird. */
1.1.1.3 root 560: static const char *const reg_half_names[] =
1.1 root 561: {
562: "%d0", "%d1", "%d2", "%d3", "%d4", "%d5", "%d6", "%d7",
563: "%a0", "%a1", "%a2", "%a3", "%a4", "%a5", "%a6", "%a7",
564: "%ps", "%pc"
565: };
566:
567: /* Sign-extend an (unsigned char). */
568: #if __STDC__ == 1
569: #define COERCE_SIGNED_CHAR(ch) ((signed char) (ch))
570: #else
571: #define COERCE_SIGNED_CHAR(ch) ((int) (((ch) ^ 0x80) & 0xFF) - 128)
572: #endif
573:
574: /* Get a 1 byte signed integer. */
1.1.1.5 ! root 575: #define NEXTBYTE(p) (p += 2, fetch_data(info, p), COERCE_SIGNED_CHAR(p[-1]))
1.1 root 576:
577: /* Get a 2 byte signed integer. */
578: #define COERCE16(x) ((int) (((x) ^ 0x8000) - 0x8000))
579: #define NEXTWORD(p) \
1.1.1.5 ! root 580: (p += 2, fetch_data(info, p), \
1.1 root 581: COERCE16 ((p[-2] << 8) + p[-1]))
582:
583: /* Get a 4 byte signed integer. */
584: #define COERCE32(x) ((bfd_signed_vma) ((x) ^ 0x80000000) - 0x80000000)
585: #define NEXTLONG(p) \
1.1.1.5 ! root 586: (p += 4, fetch_data(info, p), \
1.1 root 587: (COERCE32 ((((((p[-4] << 8) + p[-3]) << 8) + p[-2]) << 8) + p[-1])))
588:
589: /* Get a 4 byte unsigned integer. */
590: #define NEXTULONG(p) \
1.1.1.5 ! root 591: (p += 4, fetch_data(info, p), \
1.1 root 592: (unsigned int) ((((((p[-4] << 8) + p[-3]) << 8) + p[-2]) << 8) + p[-1]))
593:
594: /* Get a single precision float. */
595: #define NEXTSINGLE(val, p) \
1.1.1.5 ! root 596: (p += 4, fetch_data(info, p), \
1.1 root 597: floatformat_to_double (&floatformat_ieee_single_big, (char *) p - 4, &val))
598:
599: /* Get a double precision float. */
600: #define NEXTDOUBLE(val, p) \
1.1.1.5 ! root 601: (p += 8, fetch_data(info, p), \
1.1 root 602: floatformat_to_double (&floatformat_ieee_double_big, (char *) p - 8, &val))
603:
604: /* Get an extended precision float. */
605: #define NEXTEXTEND(val, p) \
1.1.1.5 ! root 606: (p += 12, fetch_data(info, p), \
1.1 root 607: floatformat_to_double (&floatformat_m68881_ext, (char *) p - 12, &val))
608:
609: /* Need a function to convert from packed to double
610: precision. Actually, it's easier to print a
611: packed number than a double anyway, so maybe
612: there should be a special case to handle this... */
613: #define NEXTPACKED(p) \
1.1.1.5 ! root 614: (p += 12, fetch_data(info, p), 0.0)
1.1 root 615:
616: /* Maximum length of an instruction. */
617: #define MAXLEN 22
618:
619: #include <setjmp.h>
620:
621: struct private
622: {
623: /* Points to first byte not fetched. */
624: bfd_byte *max_fetched;
625: bfd_byte the_buffer[MAXLEN];
626: bfd_vma insn_start;
627: jmp_buf bailout;
628: };
629:
630: /* Make sure that bytes from INFO->PRIVATE_DATA->BUFFER (inclusive)
631: to ADDR (exclusive) are valid. Returns 1 for success, longjmps
632: on error. */
633: static int
1.1.1.5 ! root 634: fetch_data2(struct disassemble_info *info, bfd_byte *addr)
1.1 root 635: {
636: int status;
637: struct private *priv = (struct private *)info->private_data;
638: bfd_vma start = priv->insn_start + (priv->max_fetched - priv->the_buffer);
639:
640: status = (*info->read_memory_func) (start,
641: priv->max_fetched,
642: addr - priv->max_fetched,
643: info);
644: if (status != 0)
645: {
646: (*info->memory_error_func) (status, start, info);
647: longjmp (priv->bailout, 1);
648: }
649: else
650: priv->max_fetched = addr;
651: return 1;
652: }
1.1.1.5 ! root 653:
! 654: static int
! 655: fetch_data(struct disassemble_info *info, bfd_byte *addr)
! 656: {
! 657: if (addr <= ((struct private *) (info->private_data))->max_fetched) {
! 658: return 1;
! 659: } else {
! 660: return fetch_data2(info, addr);
! 661: }
! 662: }
! 663:
1.1 root 664: /* This function is used to print to the bit-bucket. */
665: static int
666: dummy_printer (FILE *file ATTRIBUTE_UNUSED,
667: const char *format ATTRIBUTE_UNUSED,
668: ...)
669: {
670: return 0;
671: }
672:
673: static void
674: dummy_print_address (bfd_vma vma ATTRIBUTE_UNUSED,
675: struct disassemble_info *info ATTRIBUTE_UNUSED)
676: {
677: }
678:
679: /* Fetch BITS bits from a position in the instruction specified by CODE.
680: CODE is a "place to put an argument", or 'x' for a destination
681: that is a general address (mode and register).
682: BUFFER contains the instruction. */
683:
684: static int
685: fetch_arg (unsigned char *buffer,
686: int code,
687: int bits,
688: disassemble_info *info)
689: {
690: int val = 0;
691:
692: switch (code)
693: {
694: case '/': /* MAC/EMAC mask bit. */
695: val = buffer[3] >> 5;
696: break;
697:
698: case 'G': /* EMAC ACC load. */
699: val = ((buffer[3] >> 3) & 0x2) | ((~buffer[1] >> 7) & 0x1);
700: break;
701:
702: case 'H': /* EMAC ACC !load. */
703: val = ((buffer[3] >> 3) & 0x2) | ((buffer[1] >> 7) & 0x1);
704: break;
705:
706: case ']': /* EMAC ACCEXT bit. */
707: val = buffer[0] >> 2;
708: break;
709:
710: case 'I': /* MAC/EMAC scale factor. */
711: val = buffer[2] >> 1;
712: break;
713:
714: case 'F': /* EMAC ACCx. */
715: val = buffer[0] >> 1;
716: break;
717:
718: case 'f':
719: val = buffer[1];
720: break;
721:
722: case 's':
723: val = buffer[1];
724: break;
725:
726: case 'd': /* Destination, for register or quick. */
727: val = (buffer[0] << 8) + buffer[1];
728: val >>= 9;
729: break;
730:
731: case 'x': /* Destination, for general arg. */
732: val = (buffer[0] << 8) + buffer[1];
733: val >>= 6;
734: break;
735:
736: case 'k':
1.1.1.5 ! root 737: fetch_data(info, buffer + 3);
1.1 root 738: val = (buffer[3] >> 4);
739: break;
740:
741: case 'C':
1.1.1.5 ! root 742: fetch_data(info, buffer + 3);
1.1 root 743: val = buffer[3];
744: break;
745:
746: case '1':
1.1.1.5 ! root 747: fetch_data(info, buffer + 3);
1.1 root 748: val = (buffer[2] << 8) + buffer[3];
749: val >>= 12;
750: break;
751:
752: case '2':
1.1.1.5 ! root 753: fetch_data(info, buffer + 3);
1.1 root 754: val = (buffer[2] << 8) + buffer[3];
755: val >>= 6;
756: break;
757:
758: case '3':
759: case 'j':
1.1.1.5 ! root 760: fetch_data(info, buffer + 3);
1.1 root 761: val = (buffer[2] << 8) + buffer[3];
762: break;
763:
764: case '4':
1.1.1.5 ! root 765: fetch_data(info, buffer + 5);
1.1 root 766: val = (buffer[4] << 8) + buffer[5];
767: val >>= 12;
768: break;
769:
770: case '5':
1.1.1.5 ! root 771: fetch_data(info, buffer + 5);
1.1 root 772: val = (buffer[4] << 8) + buffer[5];
773: val >>= 6;
774: break;
775:
776: case '6':
1.1.1.5 ! root 777: fetch_data(info, buffer + 5);
1.1 root 778: val = (buffer[4] << 8) + buffer[5];
779: break;
780:
781: case '7':
1.1.1.5 ! root 782: fetch_data(info, buffer + 3);
1.1 root 783: val = (buffer[2] << 8) + buffer[3];
784: val >>= 7;
785: break;
786:
787: case '8':
1.1.1.5 ! root 788: fetch_data(info, buffer + 3);
1.1 root 789: val = (buffer[2] << 8) + buffer[3];
790: val >>= 10;
791: break;
792:
793: case '9':
1.1.1.5 ! root 794: fetch_data(info, buffer + 3);
1.1 root 795: val = (buffer[2] << 8) + buffer[3];
796: val >>= 5;
797: break;
798:
799: case 'e':
800: val = (buffer[1] >> 6);
801: break;
802:
803: case 'm':
804: val = (buffer[1] & 0x40 ? 0x8 : 0)
805: | ((buffer[0] >> 1) & 0x7)
806: | (buffer[3] & 0x80 ? 0x10 : 0);
807: break;
808:
809: case 'n':
810: val = (buffer[1] & 0x40 ? 0x8 : 0) | ((buffer[0] >> 1) & 0x7);
811: break;
812:
813: case 'o':
814: val = (buffer[2] >> 4) | (buffer[3] & 0x80 ? 0x10 : 0);
815: break;
816:
817: case 'M':
818: val = (buffer[1] & 0xf) | (buffer[3] & 0x40 ? 0x10 : 0);
819: break;
820:
821: case 'N':
822: val = (buffer[3] & 0xf) | (buffer[3] & 0x40 ? 0x10 : 0);
823: break;
824:
825: case 'h':
826: val = buffer[2] >> 2;
827: break;
828:
829: default:
830: abort ();
831: }
832:
833: switch (bits)
834: {
835: case 1:
836: return val & 1;
837: case 2:
838: return val & 3;
839: case 3:
840: return val & 7;
841: case 4:
842: return val & 017;
843: case 5:
844: return val & 037;
845: case 6:
846: return val & 077;
847: case 7:
848: return val & 0177;
849: case 8:
850: return val & 0377;
851: case 12:
852: return val & 07777;
853: default:
854: abort ();
855: }
856: }
857:
858: /* Check if an EA is valid for a particular code. This is required
859: for the EMAC instructions since the type of source address determines
860: if it is a EMAC-load instruciton if the EA is mode 2-5, otherwise it
861: is a non-load EMAC instruction and the bits mean register Ry.
862: A similar case exists for the movem instructions where the register
863: mask is interpreted differently for different EAs. */
864:
865: static bfd_boolean
866: m68k_valid_ea (char code, int val)
867: {
868: int mode, mask;
869: #define M(n0,n1,n2,n3,n4,n5,n6,n70,n71,n72,n73,n74) \
870: (n0 | n1 << 1 | n2 << 2 | n3 << 3 | n4 << 4 | n5 << 5 | n6 << 6 \
871: | n70 << 7 | n71 << 8 | n72 << 9 | n73 << 10 | n74 << 11)
872:
873: switch (code)
874: {
875: case '*':
876: mask = M (1,1,1,1,1,1,1,1,1,1,1,1);
877: break;
878: case '~':
879: mask = M (0,0,1,1,1,1,1,1,1,0,0,0);
880: break;
881: case '%':
882: mask = M (1,1,1,1,1,1,1,1,1,0,0,0);
883: break;
884: case ';':
885: mask = M (1,0,1,1,1,1,1,1,1,1,1,1);
886: break;
887: case '@':
888: mask = M (1,0,1,1,1,1,1,1,1,1,1,0);
889: break;
890: case '!':
891: mask = M (0,0,1,0,0,1,1,1,1,1,1,0);
892: break;
893: case '&':
894: mask = M (0,0,1,0,0,1,1,1,1,0,0,0);
895: break;
896: case '$':
897: mask = M (1,0,1,1,1,1,1,1,1,0,0,0);
898: break;
899: case '?':
900: mask = M (1,0,1,0,0,1,1,1,1,0,0,0);
901: break;
902: case '/':
903: mask = M (1,0,1,0,0,1,1,1,1,1,1,0);
904: break;
905: case '|':
906: mask = M (0,0,1,0,0,1,1,1,1,1,1,0);
907: break;
908: case '>':
909: mask = M (0,0,1,0,1,1,1,1,1,0,0,0);
910: break;
911: case '<':
912: mask = M (0,0,1,1,0,1,1,1,1,1,1,0);
913: break;
914: case 'm':
915: mask = M (1,1,1,1,1,0,0,0,0,0,0,0);
916: break;
917: case 'n':
918: mask = M (0,0,0,0,0,1,0,0,0,1,0,0);
919: break;
920: case 'o':
921: mask = M (0,0,0,0,0,0,1,1,1,0,1,1);
922: break;
923: case 'p':
924: mask = M (1,1,1,1,1,1,0,0,0,0,0,0);
925: break;
926: case 'q':
927: mask = M (1,0,1,1,1,1,0,0,0,0,0,0);
928: break;
929: case 'v':
930: mask = M (1,0,1,1,1,1,0,1,1,0,0,0);
931: break;
932: case 'b':
933: mask = M (1,0,1,1,1,1,0,0,0,1,0,0);
934: break;
935: case 'w':
936: mask = M (0,0,1,1,1,1,0,0,0,1,0,0);
937: break;
938: case 'y':
939: mask = M (0,0,1,0,0,1,0,0,0,0,0,0);
940: break;
941: case 'z':
942: mask = M (0,0,1,0,0,1,0,0,0,1,0,0);
943: break;
944: case '4':
945: mask = M (0,0,1,1,1,1,0,0,0,0,0,0);
946: break;
947: default:
948: abort ();
949: }
950: #undef M
951:
952: mode = (val >> 3) & 7;
953: if (mode == 7)
954: mode += val & 7;
955: return (mask & (1 << mode)) != 0;
956: }
957:
958: /* Print a base register REGNO and displacement DISP, on INFO->STREAM.
959: REGNO = -1 for pc, -2 for none (suppressed). */
960:
961: static void
962: print_base (int regno, bfd_vma disp, disassemble_info *info)
963: {
964: if (regno == -1)
965: {
966: (*info->fprintf_func) (info->stream, "%%pc@(");
967: (*info->print_address_func) (disp, info);
968: }
969: else
970: {
971: char buf[50];
972:
973: if (regno == -2)
974: (*info->fprintf_func) (info->stream, "@(");
975: else if (regno == -3)
976: (*info->fprintf_func) (info->stream, "%%zpc@(");
977: else
978: (*info->fprintf_func) (info->stream, "%s@(", reg_names[regno]);
979:
980: sprintf_vma (buf, disp);
981: (*info->fprintf_func) (info->stream, "%s", buf);
982: }
983: }
984:
985: /* Print an indexed argument. The base register is BASEREG (-1 for pc).
986: P points to extension word, in buffer.
987: ADDR is the nominal core address of that extension word. */
988:
989: static unsigned char *
990: print_indexed (int basereg,
991: unsigned char *p,
992: bfd_vma addr,
993: disassemble_info *info)
994: {
995: int word;
1.1.1.3 root 996: static const char *const scales[] = { "", ":2", ":4", ":8" };
1.1 root 997: bfd_vma base_disp;
998: bfd_vma outer_disp;
999: char buf[40];
1000: char vmabuf[50];
1001:
1002: word = NEXTWORD (p);
1003:
1004: /* Generate the text for the index register.
1005: Where this will be output is not yet determined. */
1006: sprintf (buf, "%s:%c%s",
1007: reg_names[(word >> 12) & 0xf],
1008: (word & 0x800) ? 'l' : 'w',
1009: scales[(word >> 9) & 3]);
1010:
1011: /* Handle the 68000 style of indexing. */
1012:
1013: if ((word & 0x100) == 0)
1014: {
1015: base_disp = word & 0xff;
1016: if ((base_disp & 0x80) != 0)
1017: base_disp -= 0x100;
1018: if (basereg == -1)
1019: base_disp += addr;
1020: print_base (basereg, base_disp, info);
1021: (*info->fprintf_func) (info->stream, ",%s)", buf);
1022: return p;
1023: }
1024:
1025: /* Handle the generalized kind. */
1026: /* First, compute the displacement to add to the base register. */
1027: if (word & 0200)
1028: {
1029: if (basereg == -1)
1030: basereg = -3;
1031: else
1032: basereg = -2;
1033: }
1034: if (word & 0100)
1035: buf[0] = '\0';
1036: base_disp = 0;
1037: switch ((word >> 4) & 3)
1038: {
1039: case 2:
1040: base_disp = NEXTWORD (p);
1041: break;
1042: case 3:
1043: base_disp = NEXTLONG (p);
1044: }
1045: if (basereg == -1)
1046: base_disp += addr;
1047:
1048: /* Handle single-level case (not indirect). */
1049: if ((word & 7) == 0)
1050: {
1051: print_base (basereg, base_disp, info);
1052: if (buf[0] != '\0')
1053: (*info->fprintf_func) (info->stream, ",%s", buf);
1054: (*info->fprintf_func) (info->stream, ")");
1055: return p;
1056: }
1057:
1058: /* Two level. Compute displacement to add after indirection. */
1059: outer_disp = 0;
1060: switch (word & 3)
1061: {
1062: case 2:
1063: outer_disp = NEXTWORD (p);
1064: break;
1065: case 3:
1066: outer_disp = NEXTLONG (p);
1067: }
1068:
1069: print_base (basereg, base_disp, info);
1070: if ((word & 4) == 0 && buf[0] != '\0')
1071: {
1072: (*info->fprintf_func) (info->stream, ",%s", buf);
1073: buf[0] = '\0';
1074: }
1075: sprintf_vma (vmabuf, outer_disp);
1076: (*info->fprintf_func) (info->stream, ")@(%s", vmabuf);
1077: if (buf[0] != '\0')
1078: (*info->fprintf_func) (info->stream, ",%s", buf);
1079: (*info->fprintf_func) (info->stream, ")");
1080:
1081: return p;
1082: }
1083:
1084: /* Returns number of bytes "eaten" by the operand, or
1085: return -1 if an invalid operand was found, or -2 if
1086: an opcode tabe error was found.
1087: ADDR is the pc for this arg to be relative to. */
1088:
1089: static int
1090: print_insn_arg (const char *d,
1091: unsigned char *buffer,
1092: unsigned char *p0,
1093: bfd_vma addr,
1094: disassemble_info *info)
1095: {
1096: int val = 0;
1097: int place = d[1];
1098: unsigned char *p = p0;
1099: int regno;
1100: const char *regname;
1101: unsigned char *p1;
1102: double flval;
1103: int flt_p;
1104: bfd_signed_vma disp;
1105: unsigned int uval;
1106:
1107: switch (*d)
1108: {
1109: case 'c': /* Cache identifier. */
1110: {
1.1.1.3 root 1111: static const char *const cacheFieldName[] = { "nc", "dc", "ic", "bc" };
1.1 root 1112: val = fetch_arg (buffer, place, 2, info);
1.1.1.5 ! root 1113: (*info->fprintf_func) (info->stream, "%s", cacheFieldName[val]);
1.1 root 1114: break;
1115: }
1116:
1117: case 'a': /* Address register indirect only. Cf. case '+'. */
1118: {
1119: (*info->fprintf_func)
1120: (info->stream,
1121: "%s@",
1122: reg_names[fetch_arg (buffer, place, 3, info) + 8]);
1123: break;
1124: }
1125:
1126: case '_': /* 32-bit absolute address for move16. */
1127: {
1128: uval = NEXTULONG (p);
1129: (*info->print_address_func) (uval, info);
1130: break;
1131: }
1132:
1133: case 'C':
1134: (*info->fprintf_func) (info->stream, "%%ccr");
1135: break;
1136:
1137: case 'S':
1138: (*info->fprintf_func) (info->stream, "%%sr");
1139: break;
1140:
1141: case 'U':
1142: (*info->fprintf_func) (info->stream, "%%usp");
1143: break;
1144:
1145: case 'E':
1146: (*info->fprintf_func) (info->stream, "%%acc");
1147: break;
1148:
1149: case 'G':
1150: (*info->fprintf_func) (info->stream, "%%macsr");
1151: break;
1152:
1153: case 'H':
1154: (*info->fprintf_func) (info->stream, "%%mask");
1155: break;
1156:
1157: case 'J':
1158: {
1159: /* FIXME: There's a problem here, different m68k processors call the
1160: same address different names. This table can't get it right
1161: because it doesn't know which processor it's disassembling for. */
1.1.1.3 root 1162: static const struct { const char *name; int value; } names[]
1.1 root 1163: = {{"%sfc", 0x000}, {"%dfc", 0x001}, {"%cacr", 0x002},
1164: {"%tc", 0x003}, {"%itt0",0x004}, {"%itt1", 0x005},
1165: {"%dtt0",0x006}, {"%dtt1",0x007}, {"%buscr",0x008},
1166: {"%usp", 0x800}, {"%vbr", 0x801}, {"%caar", 0x802},
1167: {"%msp", 0x803}, {"%isp", 0x804},
1168: {"%flashbar", 0xc04}, {"%rambar", 0xc05}, /* mcf528x added these. */
1169:
1170: /* Should we be calling this psr like we do in case 'Y'? */
1171: {"%mmusr",0x805},
1172:
1173: {"%urp", 0x806}, {"%srp", 0x807}, {"%pcr", 0x808}};
1174:
1175: val = fetch_arg (buffer, place, 12, info);
1176: for (regno = sizeof names / sizeof names[0] - 1; regno >= 0; regno--)
1177: if (names[regno].value == val)
1178: {
1179: (*info->fprintf_func) (info->stream, "%s", names[regno].name);
1180: break;
1181: }
1182: if (regno < 0)
1183: (*info->fprintf_func) (info->stream, "%d", val);
1184: }
1185: break;
1186:
1187: case 'Q':
1188: val = fetch_arg (buffer, place, 3, info);
1189: /* 0 means 8, except for the bkpt instruction... */
1190: if (val == 0 && d[1] != 's')
1191: val = 8;
1192: (*info->fprintf_func) (info->stream, "#%d", val);
1193: break;
1194:
1195: case 'x':
1196: val = fetch_arg (buffer, place, 3, info);
1197: /* 0 means -1. */
1198: if (val == 0)
1199: val = -1;
1200: (*info->fprintf_func) (info->stream, "#%d", val);
1201: break;
1202:
1203: case 'M':
1204: if (place == 'h')
1205: {
1.1.1.3 root 1206: static const char *const scalefactor_name[] = { "<<", ">>" };
1.1 root 1207: val = fetch_arg (buffer, place, 1, info);
1.1.1.5 ! root 1208: (*info->fprintf_func) (info->stream, "%s", scalefactor_name[val]);
1.1 root 1209: }
1210: else
1211: {
1212: val = fetch_arg (buffer, place, 8, info);
1213: if (val & 0x80)
1214: val = val - 0x100;
1215: (*info->fprintf_func) (info->stream, "#%d", val);
1216: }
1217: break;
1218:
1219: case 'T':
1220: val = fetch_arg (buffer, place, 4, info);
1221: (*info->fprintf_func) (info->stream, "#%d", val);
1222: break;
1223:
1224: case 'D':
1225: (*info->fprintf_func) (info->stream, "%s",
1226: reg_names[fetch_arg (buffer, place, 3, info)]);
1227: break;
1228:
1229: case 'A':
1230: (*info->fprintf_func)
1231: (info->stream, "%s",
1232: reg_names[fetch_arg (buffer, place, 3, info) + 010]);
1233: break;
1234:
1235: case 'R':
1236: (*info->fprintf_func)
1237: (info->stream, "%s",
1238: reg_names[fetch_arg (buffer, place, 4, info)]);
1239: break;
1240:
1241: case 'r':
1242: regno = fetch_arg (buffer, place, 4, info);
1243: if (regno > 7)
1244: (*info->fprintf_func) (info->stream, "%s@", reg_names[regno]);
1245: else
1246: (*info->fprintf_func) (info->stream, "@(%s)", reg_names[regno]);
1247: break;
1248:
1249: case 'F':
1250: (*info->fprintf_func)
1251: (info->stream, "%%fp%d",
1252: fetch_arg (buffer, place, 3, info));
1253: break;
1254:
1255: case 'O':
1256: val = fetch_arg (buffer, place, 6, info);
1257: if (val & 0x20)
1258: (*info->fprintf_func) (info->stream, "%s", reg_names[val & 7]);
1259: else
1260: (*info->fprintf_func) (info->stream, "%d", val);
1261: break;
1262:
1263: case '+':
1264: (*info->fprintf_func)
1265: (info->stream, "%s@+",
1266: reg_names[fetch_arg (buffer, place, 3, info) + 8]);
1267: break;
1268:
1269: case '-':
1270: (*info->fprintf_func)
1271: (info->stream, "%s@-",
1272: reg_names[fetch_arg (buffer, place, 3, info) + 8]);
1273: break;
1274:
1275: case 'k':
1276: if (place == 'k')
1277: (*info->fprintf_func)
1278: (info->stream, "{%s}",
1279: reg_names[fetch_arg (buffer, place, 3, info)]);
1280: else if (place == 'C')
1281: {
1282: val = fetch_arg (buffer, place, 7, info);
1283: if (val > 63) /* This is a signed constant. */
1284: val -= 128;
1285: (*info->fprintf_func) (info->stream, "{#%d}", val);
1286: }
1287: else
1288: return -2;
1289: break;
1290:
1291: case '#':
1292: case '^':
1293: p1 = buffer + (*d == '#' ? 2 : 4);
1294: if (place == 's')
1295: val = fetch_arg (buffer, place, 4, info);
1296: else if (place == 'C')
1297: val = fetch_arg (buffer, place, 7, info);
1298: else if (place == '8')
1299: val = fetch_arg (buffer, place, 3, info);
1300: else if (place == '3')
1301: val = fetch_arg (buffer, place, 8, info);
1302: else if (place == 'b')
1303: val = NEXTBYTE (p1);
1304: else if (place == 'w' || place == 'W')
1305: val = NEXTWORD (p1);
1306: else if (place == 'l')
1307: val = NEXTLONG (p1);
1308: else
1309: return -2;
1310: (*info->fprintf_func) (info->stream, "#%d", val);
1311: break;
1312:
1313: case 'B':
1314: if (place == 'b')
1315: disp = NEXTBYTE (p);
1316: else if (place == 'B')
1317: disp = COERCE_SIGNED_CHAR (buffer[1]);
1318: else if (place == 'w' || place == 'W')
1319: disp = NEXTWORD (p);
1320: else if (place == 'l' || place == 'L' || place == 'C')
1321: disp = NEXTLONG (p);
1322: else if (place == 'g')
1323: {
1324: disp = NEXTBYTE (buffer);
1325: if (disp == 0)
1326: disp = NEXTWORD (p);
1327: else if (disp == -1)
1328: disp = NEXTLONG (p);
1329: }
1330: else if (place == 'c')
1331: {
1332: if (buffer[1] & 0x40) /* If bit six is one, long offset. */
1333: disp = NEXTLONG (p);
1334: else
1335: disp = NEXTWORD (p);
1336: }
1337: else
1338: return -2;
1339:
1340: (*info->print_address_func) (addr + disp, info);
1341: break;
1342:
1343: case 'd':
1344: val = NEXTWORD (p);
1345: (*info->fprintf_func)
1346: (info->stream, "%s@(%d)",
1347: reg_names[fetch_arg (buffer, place, 3, info) + 8], val);
1348: break;
1349:
1350: case 's':
1351: (*info->fprintf_func) (info->stream, "%s",
1352: fpcr_names[fetch_arg (buffer, place, 3, info)]);
1353: break;
1354:
1355: case 'e':
1356: val = fetch_arg(buffer, place, 2, info);
1357: (*info->fprintf_func) (info->stream, "%%acc%d", val);
1358: break;
1359:
1360: case 'g':
1361: val = fetch_arg(buffer, place, 1, info);
1362: (*info->fprintf_func) (info->stream, "%%accext%s", val==0 ? "01" : "23");
1363: break;
1364:
1365: case 'i':
1366: val = fetch_arg(buffer, place, 2, info);
1367: if (val == 1)
1368: (*info->fprintf_func) (info->stream, "<<");
1369: else if (val == 3)
1370: (*info->fprintf_func) (info->stream, ">>");
1371: else
1372: return -1;
1373: break;
1374:
1375: case 'I':
1376: /* Get coprocessor ID... */
1377: val = fetch_arg (buffer, 'd', 3, info);
1378:
1379: if (val != 1) /* Unusual coprocessor ID? */
1380: (*info->fprintf_func) (info->stream, "(cpid=%d) ", val);
1381: break;
1382:
1383: case '4':
1384: case '*':
1385: case '~':
1386: case '%':
1387: case ';':
1388: case '@':
1389: case '!':
1390: case '$':
1391: case '?':
1392: case '/':
1393: case '&':
1394: case '|':
1395: case '<':
1396: case '>':
1397: case 'm':
1398: case 'n':
1399: case 'o':
1400: case 'p':
1401: case 'q':
1402: case 'v':
1403: case 'b':
1404: case 'w':
1405: case 'y':
1406: case 'z':
1407: if (place == 'd')
1408: {
1409: val = fetch_arg (buffer, 'x', 6, info);
1410: val = ((val & 7) << 3) + ((val >> 3) & 7);
1411: }
1412: else
1413: val = fetch_arg (buffer, 's', 6, info);
1414:
1415: /* If the <ea> is invalid for *d, then reject this match. */
1416: if (!m68k_valid_ea (*d, val))
1417: return -1;
1418:
1419: /* Get register number assuming address register. */
1420: regno = (val & 7) + 8;
1421: regname = reg_names[regno];
1422: switch (val >> 3)
1423: {
1424: case 0:
1425: (*info->fprintf_func) (info->stream, "%s", reg_names[val]);
1426: break;
1427:
1428: case 1:
1429: (*info->fprintf_func) (info->stream, "%s", regname);
1430: break;
1431:
1432: case 2:
1433: (*info->fprintf_func) (info->stream, "%s@", regname);
1434: break;
1435:
1436: case 3:
1437: (*info->fprintf_func) (info->stream, "%s@+", regname);
1438: break;
1439:
1440: case 4:
1441: (*info->fprintf_func) (info->stream, "%s@-", regname);
1442: break;
1443:
1444: case 5:
1445: val = NEXTWORD (p);
1446: (*info->fprintf_func) (info->stream, "%s@(%d)", regname, val);
1447: break;
1448:
1449: case 6:
1450: p = print_indexed (regno, p, addr, info);
1451: break;
1452:
1453: case 7:
1454: switch (val & 7)
1455: {
1456: case 0:
1457: val = NEXTWORD (p);
1458: (*info->print_address_func) (val, info);
1459: break;
1460:
1461: case 1:
1462: uval = NEXTULONG (p);
1463: (*info->print_address_func) (uval, info);
1464: break;
1465:
1466: case 2:
1467: val = NEXTWORD (p);
1468: (*info->fprintf_func) (info->stream, "%%pc@(");
1469: (*info->print_address_func) (addr + val, info);
1470: (*info->fprintf_func) (info->stream, ")");
1471: break;
1472:
1473: case 3:
1474: p = print_indexed (-1, p, addr, info);
1475: break;
1476:
1477: case 4:
1478: flt_p = 1; /* Assume it's a float... */
1479: switch (place)
1480: {
1481: case 'b':
1482: val = NEXTBYTE (p);
1483: flt_p = 0;
1484: break;
1485:
1486: case 'w':
1487: val = NEXTWORD (p);
1488: flt_p = 0;
1489: break;
1490:
1491: case 'l':
1492: val = NEXTLONG (p);
1493: flt_p = 0;
1494: break;
1495:
1496: case 'f':
1497: NEXTSINGLE (flval, p);
1498: break;
1499:
1500: case 'F':
1501: NEXTDOUBLE (flval, p);
1502: break;
1503:
1504: case 'x':
1505: NEXTEXTEND (flval, p);
1506: break;
1507:
1508: case 'p':
1509: flval = NEXTPACKED (p);
1510: break;
1511:
1512: default:
1513: return -1;
1514: }
1515: if (flt_p) /* Print a float? */
1516: (*info->fprintf_func) (info->stream, "#%g", flval);
1517: else
1518: (*info->fprintf_func) (info->stream, "#%d", val);
1519: break;
1520:
1521: default:
1522: return -1;
1523: }
1524: }
1525:
1526: /* If place is '/', then this is the case of the mask bit for
1527: mac/emac loads. Now that the arg has been printed, grab the
1528: mask bit and if set, add a '&' to the arg. */
1529: if (place == '/')
1530: {
1531: val = fetch_arg (buffer, place, 1, info);
1532: if (val)
1533: info->fprintf_func (info->stream, "&");
1534: }
1535: break;
1536:
1537: case 'L':
1538: case 'l':
1539: if (place == 'w')
1540: {
1541: char doneany;
1542: p1 = buffer + 2;
1543: val = NEXTWORD (p1);
1544: /* Move the pointer ahead if this point is farther ahead
1545: than the last. */
1546: p = p1 > p ? p1 : p;
1547: if (val == 0)
1548: {
1549: (*info->fprintf_func) (info->stream, "#0");
1550: break;
1551: }
1552: if (*d == 'l')
1553: {
1554: int newval = 0;
1555:
1556: for (regno = 0; regno < 16; ++regno)
1557: if (val & (0x8000 >> regno))
1558: newval |= 1 << regno;
1559: val = newval;
1560: }
1561: val &= 0xffff;
1562: doneany = 0;
1563: for (regno = 0; regno < 16; ++regno)
1564: if (val & (1 << regno))
1565: {
1566: int first_regno;
1567:
1568: if (doneany)
1569: (*info->fprintf_func) (info->stream, "/");
1570: doneany = 1;
1571: (*info->fprintf_func) (info->stream, "%s", reg_names[regno]);
1572: first_regno = regno;
1573: while (val & (1 << (regno + 1)))
1574: ++regno;
1575: if (regno > first_regno)
1576: (*info->fprintf_func) (info->stream, "-%s",
1577: reg_names[regno]);
1578: }
1579: }
1580: else if (place == '3')
1581: {
1582: /* `fmovem' insn. */
1583: char doneany;
1584: val = fetch_arg (buffer, place, 8, info);
1585: if (val == 0)
1586: {
1587: (*info->fprintf_func) (info->stream, "#0");
1588: break;
1589: }
1590: if (*d == 'l')
1591: {
1592: int newval = 0;
1593:
1594: for (regno = 0; regno < 8; ++regno)
1595: if (val & (0x80 >> regno))
1596: newval |= 1 << regno;
1597: val = newval;
1598: }
1599: val &= 0xff;
1600: doneany = 0;
1601: for (regno = 0; regno < 8; ++regno)
1602: if (val & (1 << regno))
1603: {
1604: int first_regno;
1605: if (doneany)
1606: (*info->fprintf_func) (info->stream, "/");
1607: doneany = 1;
1608: (*info->fprintf_func) (info->stream, "%%fp%d", regno);
1609: first_regno = regno;
1610: while (val & (1 << (regno + 1)))
1611: ++regno;
1612: if (regno > first_regno)
1613: (*info->fprintf_func) (info->stream, "-%%fp%d", regno);
1614: }
1615: }
1616: else if (place == '8')
1617: {
1618: /* fmoveml for FP status registers. */
1619: (*info->fprintf_func) (info->stream, "%s",
1620: fpcr_names[fetch_arg (buffer, place, 3,
1621: info)]);
1622: }
1623: else
1624: return -2;
1625: break;
1626:
1627: case 'X':
1628: place = '8';
1629: case 'Y':
1630: case 'Z':
1631: case 'W':
1632: case '0':
1633: case '1':
1634: case '2':
1635: case '3':
1636: {
1637: int val = fetch_arg (buffer, place, 5, info);
1.1.1.3 root 1638: const char *name = 0;
1.1 root 1639:
1640: switch (val)
1641: {
1642: case 2: name = "%tt0"; break;
1643: case 3: name = "%tt1"; break;
1644: case 0x10: name = "%tc"; break;
1645: case 0x11: name = "%drp"; break;
1646: case 0x12: name = "%srp"; break;
1647: case 0x13: name = "%crp"; break;
1648: case 0x14: name = "%cal"; break;
1649: case 0x15: name = "%val"; break;
1650: case 0x16: name = "%scc"; break;
1651: case 0x17: name = "%ac"; break;
1652: case 0x18: name = "%psr"; break;
1653: case 0x19: name = "%pcsr"; break;
1654: case 0x1c:
1655: case 0x1d:
1656: {
1657: int break_reg = ((buffer[3] >> 2) & 7);
1658:
1659: (*info->fprintf_func)
1660: (info->stream, val == 0x1c ? "%%bad%d" : "%%bac%d",
1661: break_reg);
1662: }
1663: break;
1664: default:
1665: (*info->fprintf_func) (info->stream, "<mmu register %d>", val);
1666: }
1667: if (name)
1668: (*info->fprintf_func) (info->stream, "%s", name);
1669: }
1670: break;
1671:
1672: case 'f':
1673: {
1674: int fc = fetch_arg (buffer, place, 5, info);
1675:
1676: if (fc == 1)
1677: (*info->fprintf_func) (info->stream, "%%dfc");
1678: else if (fc == 0)
1679: (*info->fprintf_func) (info->stream, "%%sfc");
1680: else
1681: /* xgettext:c-format */
1682: (*info->fprintf_func) (info->stream, _("<function code %d>"), fc);
1683: }
1684: break;
1685:
1686: case 'V':
1687: (*info->fprintf_func) (info->stream, "%%val");
1688: break;
1689:
1690: case 't':
1691: {
1692: int level = fetch_arg (buffer, place, 3, info);
1693:
1694: (*info->fprintf_func) (info->stream, "%d", level);
1695: }
1696: break;
1697:
1698: case 'u':
1699: {
1700: short is_upper = 0;
1701: int reg = fetch_arg (buffer, place, 5, info);
1702:
1703: if (reg & 0x10)
1704: {
1705: is_upper = 1;
1706: reg &= 0xf;
1707: }
1708: (*info->fprintf_func) (info->stream, "%s%s",
1709: reg_half_names[reg],
1710: is_upper ? "u" : "l");
1711: }
1712: break;
1713:
1714: default:
1715: return -2;
1716: }
1717:
1718: return p - p0;
1719: }
1720:
1721: /* Try to match the current instruction to best and if so, return the
1722: number of bytes consumed from the instruction stream, else zero. */
1723:
1724: static int
1725: match_insn_m68k (bfd_vma memaddr,
1726: disassemble_info * info,
1727: const struct m68k_opcode * best,
1728: struct private * priv)
1729: {
1730: unsigned char *save_p;
1731: unsigned char *p;
1732: const char *d;
1733:
1734: bfd_byte *buffer = priv->the_buffer;
1735: fprintf_ftype save_printer = info->fprintf_func;
1736: void (* save_print_address) (bfd_vma, struct disassemble_info *)
1737: = info->print_address_func;
1738:
1739: /* Point at first word of argument data,
1740: and at descriptor for first argument. */
1741: p = buffer + 2;
1742:
1743: /* Figure out how long the fixed-size portion of the instruction is.
1744: The only place this is stored in the opcode table is
1745: in the arguments--look for arguments which specify fields in the 2nd
1746: or 3rd words of the instruction. */
1747: for (d = best->args; *d; d += 2)
1748: {
1749: /* I don't think it is necessary to be checking d[0] here;
1750: I suspect all this could be moved to the case statement below. */
1751: if (d[0] == '#')
1752: {
1753: if (d[1] == 'l' && p - buffer < 6)
1754: p = buffer + 6;
1755: else if (p - buffer < 4 && d[1] != 'C' && d[1] != '8')
1756: p = buffer + 4;
1757: }
1758:
1759: if ((d[0] == 'L' || d[0] == 'l') && d[1] == 'w' && p - buffer < 4)
1760: p = buffer + 4;
1761:
1762: switch (d[1])
1763: {
1764: case '1':
1765: case '2':
1766: case '3':
1767: case '7':
1768: case '8':
1769: case '9':
1770: case 'i':
1771: if (p - buffer < 4)
1772: p = buffer + 4;
1773: break;
1774: case '4':
1775: case '5':
1776: case '6':
1777: if (p - buffer < 6)
1778: p = buffer + 6;
1779: break;
1780: default:
1781: break;
1782: }
1783: }
1784:
1785: /* pflusha is an exceptions. It takes no arguments but is two words
1786: long. Recognize it by looking at the lower 16 bits of the mask. */
1787: if (p - buffer < 4 && (best->match & 0xFFFF) != 0)
1788: p = buffer + 4;
1789:
1790: /* lpstop is another exception. It takes a one word argument but is
1791: three words long. */
1792: if (p - buffer < 6
1793: && (best->match & 0xffff) == 0xffff
1794: && best->args[0] == '#'
1795: && best->args[1] == 'w')
1796: {
1797: /* Copy the one word argument into the usual location for a one
1798: word argument, to simplify printing it. We can get away with
1799: this because we know exactly what the second word is, and we
1800: aren't going to print anything based on it. */
1801: p = buffer + 6;
1.1.1.5 ! root 1802: fetch_data(info, p);
1.1 root 1803: buffer[2] = buffer[4];
1804: buffer[3] = buffer[5];
1805: }
1806:
1.1.1.5 ! root 1807: fetch_data(info, p);
1.1 root 1808:
1809: d = best->args;
1810:
1811: save_p = p;
1812: info->print_address_func = dummy_print_address;
1.1.1.5 ! root 1813: info->fprintf_func = dummy_printer;
1.1 root 1814:
1815: /* We scan the operands twice. The first time we don't print anything,
1816: but look for errors. */
1817: for (; *d; d += 2)
1818: {
1819: int eaten = print_insn_arg (d, buffer, p, memaddr + (p - buffer), info);
1820:
1821: if (eaten >= 0)
1822: p += eaten;
1823: else if (eaten == -1)
1824: {
1825: info->fprintf_func = save_printer;
1826: info->print_address_func = save_print_address;
1827: return 0;
1828: }
1829: else
1830: {
1831: info->fprintf_func (info->stream,
1832: /* xgettext:c-format */
1833: _("<internal error in opcode table: %s %s>\n"),
1834: best->name, best->args);
1835: info->fprintf_func = save_printer;
1836: info->print_address_func = save_print_address;
1837: return 2;
1838: }
1839: }
1840:
1841: p = save_p;
1842: info->fprintf_func = save_printer;
1843: info->print_address_func = save_print_address;
1844:
1845: d = best->args;
1846:
1847: info->fprintf_func (info->stream, "%s", best->name);
1848:
1849: if (*d)
1850: info->fprintf_func (info->stream, " ");
1851:
1852: while (*d)
1853: {
1854: p += print_insn_arg (d, buffer, p, memaddr + (p - buffer), info);
1855: d += 2;
1856:
1857: if (*d && *(d - 2) != 'I' && *d != 'k')
1858: info->fprintf_func (info->stream, ",");
1859: }
1860:
1861: return p - buffer;
1862: }
1863:
1864: /* Print the m68k instruction at address MEMADDR in debugged memory,
1865: on INFO->STREAM. Returns length of the instruction, in bytes. */
1866:
1867: int
1868: print_insn_m68k (bfd_vma memaddr, disassemble_info *info)
1869: {
1870: int i;
1871: const char *d;
1872: unsigned int arch_mask;
1873: struct private priv;
1874: bfd_byte *buffer = priv.the_buffer;
1875: int major_opcode;
1876: static int numopcodes[16];
1877: static const struct m68k_opcode **opcodes[16];
1878: int val;
1879:
1880: if (!opcodes[0])
1881: {
1882: /* Speed up the matching by sorting the opcode
1883: table on the upper four bits of the opcode. */
1884: const struct m68k_opcode **opc_pointer[16];
1885:
1886: /* First count how many opcodes are in each of the sixteen buckets. */
1887: for (i = 0; i < m68k_numopcodes; i++)
1888: numopcodes[(m68k_opcodes[i].opcode >> 28) & 15]++;
1889:
1890: /* Then create a sorted table of pointers
1891: that point into the unsorted table. */
1892: opc_pointer[0] = malloc (sizeof (struct m68k_opcode *)
1893: * m68k_numopcodes);
1894: opcodes[0] = opc_pointer[0];
1895:
1896: for (i = 1; i < 16; i++)
1897: {
1898: opc_pointer[i] = opc_pointer[i - 1] + numopcodes[i - 1];
1899: opcodes[i] = opc_pointer[i];
1900: }
1901:
1902: for (i = 0; i < m68k_numopcodes; i++)
1903: *opc_pointer[(m68k_opcodes[i].opcode >> 28) & 15]++ = &m68k_opcodes[i];
1904: }
1905:
1906: info->private_data = (PTR) &priv;
1907: /* Tell objdump to use two bytes per chunk
1908: and six bytes per line for displaying raw data. */
1909: info->bytes_per_chunk = 2;
1910: info->bytes_per_line = 6;
1911: info->display_endian = BFD_ENDIAN_BIG;
1912: priv.max_fetched = priv.the_buffer;
1913: priv.insn_start = memaddr;
1914:
1915: if (setjmp (priv.bailout) != 0)
1916: /* Error return. */
1917: return -1;
1918:
1919: switch (info->mach)
1920: {
1921: default:
1922: case 0:
1923: arch_mask = (unsigned int) -1;
1924: break;
1925: case bfd_mach_m68000:
1926: arch_mask = m68000|m68881|m68851;
1927: break;
1928: case bfd_mach_m68008:
1929: arch_mask = m68008|m68881|m68851;
1930: break;
1931: case bfd_mach_m68010:
1932: arch_mask = m68010|m68881|m68851;
1933: break;
1934: case bfd_mach_m68020:
1935: arch_mask = m68020|m68881|m68851;
1936: break;
1937: case bfd_mach_m68030:
1938: arch_mask = m68030|m68881|m68851;
1939: break;
1940: case bfd_mach_m68040:
1941: arch_mask = m68040|m68881|m68851;
1942: break;
1943: case bfd_mach_m68060:
1944: arch_mask = m68060|m68881|m68851;
1945: break;
1946: case bfd_mach_mcf5200:
1947: arch_mask = mcfisa_a;
1948: break;
1949: case bfd_mach_mcf521x:
1950: case bfd_mach_mcf528x:
1951: arch_mask = mcfisa_a|mcfhwdiv|mcfisa_aa|mcfusp|mcfemac;
1952: break;
1953: case bfd_mach_mcf5206e:
1954: arch_mask = mcfisa_a|mcfhwdiv|mcfmac;
1955: break;
1956: case bfd_mach_mcf5249:
1957: arch_mask = mcfisa_a|mcfhwdiv|mcfemac;
1958: break;
1959: case bfd_mach_mcf5307:
1960: arch_mask = mcfisa_a|mcfhwdiv|mcfmac;
1961: break;
1962: case bfd_mach_mcf5407:
1963: arch_mask = mcfisa_a|mcfhwdiv|mcfisa_b|mcfmac;
1964: break;
1965: case bfd_mach_mcf547x:
1966: case bfd_mach_mcf548x:
1967: case bfd_mach_mcfv4e:
1968: arch_mask = mcfisa_a|mcfhwdiv|mcfisa_b|mcfusp|cfloat|mcfemac;
1969: break;
1970: }
1971:
1.1.1.5 ! root 1972: fetch_data(info, buffer + 2);
1.1 root 1973: major_opcode = (buffer[0] >> 4) & 15;
1974:
1975: for (i = 0; i < numopcodes[major_opcode]; i++)
1976: {
1977: const struct m68k_opcode *opc = opcodes[major_opcode][i];
1978: unsigned long opcode = opc->opcode;
1979: unsigned long match = opc->match;
1980:
1981: if (((0xff & buffer[0] & (match >> 24)) == (0xff & (opcode >> 24)))
1982: && ((0xff & buffer[1] & (match >> 16)) == (0xff & (opcode >> 16)))
1983: /* Only fetch the next two bytes if we need to. */
1984: && (((0xffff & match) == 0)
1985: ||
1.1.1.5 ! root 1986: (fetch_data(info, buffer + 4)
1.1 root 1987: && ((0xff & buffer[2] & (match >> 8)) == (0xff & (opcode >> 8)))
1988: && ((0xff & buffer[3] & match) == (0xff & opcode)))
1989: )
1990: && (opc->arch & arch_mask) != 0)
1991: {
1992: /* Don't use for printout the variants of divul and divsl
1993: that have the same register number in two places.
1994: The more general variants will match instead. */
1995: for (d = opc->args; *d; d += 2)
1996: if (d[1] == 'D')
1997: break;
1998:
1999: /* Don't use for printout the variants of most floating
2000: point coprocessor instructions which use the same
2001: register number in two places, as above. */
2002: if (*d == '\0')
2003: for (d = opc->args; *d; d += 2)
2004: if (d[1] == 't')
2005: break;
2006:
2007: /* Don't match fmovel with more than one register;
2008: wait for fmoveml. */
2009: if (*d == '\0')
2010: {
2011: for (d = opc->args; *d; d += 2)
2012: {
2013: if (d[0] == 's' && d[1] == '8')
2014: {
2015: val = fetch_arg (buffer, d[1], 3, info);
2016: if ((val & (val - 1)) != 0)
2017: break;
2018: }
2019: }
2020: }
2021:
2022: if (*d == '\0')
2023: if ((val = match_insn_m68k (memaddr, info, opc, & priv)))
2024: return val;
2025: }
2026: }
2027:
2028: /* Handle undefined instructions. */
2029: info->fprintf_func (info->stream, "0%o", (buffer[0] << 8) + buffer[1]);
2030: return 2;
2031: }
2032: /* **** End of m68k-dis.c */
2033: /* **** m68k-opc.h from sourceware.org CVS 2005-08-14. */
2034: /* Opcode table for m680[012346]0/m6888[12]/m68851/mcf5200.
2035: Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
2036: 2000, 2001, 2003, 2004, 2005
2037: Free Software Foundation, Inc.
2038:
2039: This file is part of GDB, GAS, and the GNU binutils.
2040:
2041: GDB, GAS, and the GNU binutils are free software; you can redistribute
2042: them and/or modify them under the terms of the GNU General Public
2043: License as published by the Free Software Foundation; either version
2044: 1, or (at your option) any later version.
2045:
2046: GDB, GAS, and the GNU binutils are distributed in the hope that they
2047: will be useful, but WITHOUT ANY WARRANTY; without even the implied
2048: warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See
2049: the GNU General Public License for more details.
2050:
2051: You should have received a copy of the GNU General Public License
1.1.1.4 root 2052: along with this file; see the file COPYING. If not,
2053: see <http://www.gnu.org/licenses/>. */
1.1 root 2054:
2055: #define one(x) ((unsigned int) (x) << 16)
2056: #define two(x, y) (((unsigned int) (x) << 16) + (y))
2057:
2058: /* The assembler requires that all instances of the same mnemonic must
2059: be consecutive. If they aren't, the assembler will bomb at
2060: runtime. */
2061:
2062: const struct m68k_opcode m68k_opcodes[] =
2063: {
2064: {"abcd", 2, one(0140400), one(0170770), "DsDd", m68000up },
2065: {"abcd", 2, one(0140410), one(0170770), "-s-d", m68000up },
2066:
2067: {"addaw", 2, one(0150300), one(0170700), "*wAd", m68000up },
2068: {"addal", 2, one(0150700), one(0170700), "*lAd", m68000up | mcfisa_a },
2069:
2070: {"addib", 4, one(0003000), one(0177700), "#b$s", m68000up },
2071: {"addiw", 4, one(0003100), one(0177700), "#w$s", m68000up },
2072: {"addil", 6, one(0003200), one(0177700), "#l$s", m68000up },
2073: {"addil", 6, one(0003200), one(0177700), "#lDs", mcfisa_a },
2074:
2075: {"addqb", 2, one(0050000), one(0170700), "Qd$b", m68000up },
2076: {"addqw", 2, one(0050100), one(0170700), "Qd%w", m68000up },
2077: {"addql", 2, one(0050200), one(0170700), "Qd%l", m68000up | mcfisa_a },
2078:
2079: /* The add opcode can generate the adda, addi, and addq instructions. */
2080: {"addb", 2, one(0050000), one(0170700), "Qd$b", m68000up },
2081: {"addb", 4, one(0003000), one(0177700), "#b$s", m68000up },
2082: {"addb", 2, one(0150000), one(0170700), ";bDd", m68000up },
2083: {"addb", 2, one(0150400), one(0170700), "Dd~b", m68000up },
2084: {"addw", 2, one(0050100), one(0170700), "Qd%w", m68000up },
2085: {"addw", 2, one(0150300), one(0170700), "*wAd", m68000up },
2086: {"addw", 4, one(0003100), one(0177700), "#w$s", m68000up },
2087: {"addw", 2, one(0150100), one(0170700), "*wDd", m68000up },
2088: {"addw", 2, one(0150500), one(0170700), "Dd~w", m68000up },
2089: {"addl", 2, one(0050200), one(0170700), "Qd%l", m68000up | mcfisa_a },
2090: {"addl", 6, one(0003200), one(0177700), "#l$s", m68000up },
2091: {"addl", 6, one(0003200), one(0177700), "#lDs", mcfisa_a },
2092: {"addl", 2, one(0150700), one(0170700), "*lAd", m68000up | mcfisa_a },
2093: {"addl", 2, one(0150200), one(0170700), "*lDd", m68000up | mcfisa_a },
2094: {"addl", 2, one(0150600), one(0170700), "Dd~l", m68000up | mcfisa_a },
2095:
2096: {"addxb", 2, one(0150400), one(0170770), "DsDd", m68000up },
2097: {"addxb", 2, one(0150410), one(0170770), "-s-d", m68000up },
2098: {"addxw", 2, one(0150500), one(0170770), "DsDd", m68000up },
2099: {"addxw", 2, one(0150510), one(0170770), "-s-d", m68000up },
2100: {"addxl", 2, one(0150600), one(0170770), "DsDd", m68000up | mcfisa_a },
2101: {"addxl", 2, one(0150610), one(0170770), "-s-d", m68000up },
2102:
2103: {"andib", 4, one(0001000), one(0177700), "#b$s", m68000up },
2104: {"andib", 4, one(0001074), one(0177777), "#bCs", m68000up },
2105: {"andiw", 4, one(0001100), one(0177700), "#w$s", m68000up },
2106: {"andiw", 4, one(0001174), one(0177777), "#wSs", m68000up },
2107: {"andil", 6, one(0001200), one(0177700), "#l$s", m68000up },
2108: {"andil", 6, one(0001200), one(0177700), "#lDs", mcfisa_a },
2109: {"andi", 4, one(0001100), one(0177700), "#w$s", m68000up },
2110: {"andi", 4, one(0001074), one(0177777), "#bCs", m68000up },
2111: {"andi", 4, one(0001174), one(0177777), "#wSs", m68000up },
2112:
2113: /* The and opcode can generate the andi instruction. */
2114: {"andb", 4, one(0001000), one(0177700), "#b$s", m68000up },
2115: {"andb", 4, one(0001074), one(0177777), "#bCs", m68000up },
2116: {"andb", 2, one(0140000), one(0170700), ";bDd", m68000up },
2117: {"andb", 2, one(0140400), one(0170700), "Dd~b", m68000up },
2118: {"andw", 4, one(0001100), one(0177700), "#w$s", m68000up },
2119: {"andw", 4, one(0001174), one(0177777), "#wSs", m68000up },
2120: {"andw", 2, one(0140100), one(0170700), ";wDd", m68000up },
2121: {"andw", 2, one(0140500), one(0170700), "Dd~w", m68000up },
2122: {"andl", 6, one(0001200), one(0177700), "#l$s", m68000up },
2123: {"andl", 6, one(0001200), one(0177700), "#lDs", mcfisa_a },
2124: {"andl", 2, one(0140200), one(0170700), ";lDd", m68000up | mcfisa_a },
2125: {"andl", 2, one(0140600), one(0170700), "Dd~l", m68000up | mcfisa_a },
2126: {"and", 4, one(0001100), one(0177700), "#w$w", m68000up },
2127: {"and", 4, one(0001074), one(0177777), "#bCs", m68000up },
2128: {"and", 4, one(0001174), one(0177777), "#wSs", m68000up },
2129: {"and", 2, one(0140100), one(0170700), ";wDd", m68000up },
2130: {"and", 2, one(0140500), one(0170700), "Dd~w", m68000up },
2131:
2132: {"aslb", 2, one(0160400), one(0170770), "QdDs", m68000up },
2133: {"aslb", 2, one(0160440), one(0170770), "DdDs", m68000up },
2134: {"aslw", 2, one(0160500), one(0170770), "QdDs", m68000up },
2135: {"aslw", 2, one(0160540), one(0170770), "DdDs", m68000up },
2136: {"aslw", 2, one(0160700), one(0177700), "~s", m68000up },
2137: {"asll", 2, one(0160600), one(0170770), "QdDs", m68000up | mcfisa_a },
2138: {"asll", 2, one(0160640), one(0170770), "DdDs", m68000up | mcfisa_a },
2139:
2140: {"asrb", 2, one(0160000), one(0170770), "QdDs", m68000up },
2141: {"asrb", 2, one(0160040), one(0170770), "DdDs", m68000up },
2142: {"asrw", 2, one(0160100), one(0170770), "QdDs", m68000up },
2143: {"asrw", 2, one(0160140), one(0170770), "DdDs", m68000up },
2144: {"asrw", 2, one(0160300), one(0177700), "~s", m68000up },
2145: {"asrl", 2, one(0160200), one(0170770), "QdDs", m68000up | mcfisa_a },
2146: {"asrl", 2, one(0160240), one(0170770), "DdDs", m68000up | mcfisa_a },
2147:
2148: {"bhiw", 2, one(0061000), one(0177777), "BW", m68000up | mcfisa_a },
2149: {"blsw", 2, one(0061400), one(0177777), "BW", m68000up | mcfisa_a },
2150: {"bccw", 2, one(0062000), one(0177777), "BW", m68000up | mcfisa_a },
2151: {"bcsw", 2, one(0062400), one(0177777), "BW", m68000up | mcfisa_a },
2152: {"bnew", 2, one(0063000), one(0177777), "BW", m68000up | mcfisa_a },
2153: {"beqw", 2, one(0063400), one(0177777), "BW", m68000up | mcfisa_a },
2154: {"bvcw", 2, one(0064000), one(0177777), "BW", m68000up | mcfisa_a },
2155: {"bvsw", 2, one(0064400), one(0177777), "BW", m68000up | mcfisa_a },
2156: {"bplw", 2, one(0065000), one(0177777), "BW", m68000up | mcfisa_a },
2157: {"bmiw", 2, one(0065400), one(0177777), "BW", m68000up | mcfisa_a },
2158: {"bgew", 2, one(0066000), one(0177777), "BW", m68000up | mcfisa_a },
2159: {"bltw", 2, one(0066400), one(0177777), "BW", m68000up | mcfisa_a },
2160: {"bgtw", 2, one(0067000), one(0177777), "BW", m68000up | mcfisa_a },
2161: {"blew", 2, one(0067400), one(0177777), "BW", m68000up | mcfisa_a },
2162:
2163: {"bhil", 2, one(0061377), one(0177777), "BL", m68020up | cpu32 | mcfisa_b},
2164: {"blsl", 2, one(0061777), one(0177777), "BL", m68020up | cpu32 | mcfisa_b},
2165: {"bccl", 2, one(0062377), one(0177777), "BL", m68020up | cpu32 | mcfisa_b},
2166: {"bcsl", 2, one(0062777), one(0177777), "BL", m68020up | cpu32 | mcfisa_b},
2167: {"bnel", 2, one(0063377), one(0177777), "BL", m68020up | cpu32 | mcfisa_b},
2168: {"beql", 2, one(0063777), one(0177777), "BL", m68020up | cpu32 | mcfisa_b},
2169: {"bvcl", 2, one(0064377), one(0177777), "BL", m68020up | cpu32 | mcfisa_b},
2170: {"bvsl", 2, one(0064777), one(0177777), "BL", m68020up | cpu32 | mcfisa_b},
2171: {"bpll", 2, one(0065377), one(0177777), "BL", m68020up | cpu32 | mcfisa_b},
2172: {"bmil", 2, one(0065777), one(0177777), "BL", m68020up | cpu32 | mcfisa_b},
2173: {"bgel", 2, one(0066377), one(0177777), "BL", m68020up | cpu32 | mcfisa_b},
2174: {"bltl", 2, one(0066777), one(0177777), "BL", m68020up | cpu32 | mcfisa_b},
2175: {"bgtl", 2, one(0067377), one(0177777), "BL", m68020up | cpu32 | mcfisa_b},
2176: {"blel", 2, one(0067777), one(0177777), "BL", m68020up | cpu32 | mcfisa_b},
2177:
2178: {"bhis", 2, one(0061000), one(0177400), "BB", m68000up | mcfisa_a },
2179: {"blss", 2, one(0061400), one(0177400), "BB", m68000up | mcfisa_a },
2180: {"bccs", 2, one(0062000), one(0177400), "BB", m68000up | mcfisa_a },
2181: {"bcss", 2, one(0062400), one(0177400), "BB", m68000up | mcfisa_a },
2182: {"bnes", 2, one(0063000), one(0177400), "BB", m68000up | mcfisa_a },
2183: {"beqs", 2, one(0063400), one(0177400), "BB", m68000up | mcfisa_a },
2184: {"bvcs", 2, one(0064000), one(0177400), "BB", m68000up | mcfisa_a },
2185: {"bvss", 2, one(0064400), one(0177400), "BB", m68000up | mcfisa_a },
2186: {"bpls", 2, one(0065000), one(0177400), "BB", m68000up | mcfisa_a },
2187: {"bmis", 2, one(0065400), one(0177400), "BB", m68000up | mcfisa_a },
2188: {"bges", 2, one(0066000), one(0177400), "BB", m68000up | mcfisa_a },
2189: {"blts", 2, one(0066400), one(0177400), "BB", m68000up | mcfisa_a },
2190: {"bgts", 2, one(0067000), one(0177400), "BB", m68000up | mcfisa_a },
2191: {"bles", 2, one(0067400), one(0177400), "BB", m68000up | mcfisa_a },
2192:
2193: {"jhi", 2, one(0061000), one(0177400), "Bg", m68000up | mcfisa_a },
2194: {"jls", 2, one(0061400), one(0177400), "Bg", m68000up | mcfisa_a },
2195: {"jcc", 2, one(0062000), one(0177400), "Bg", m68000up | mcfisa_a },
2196: {"jcs", 2, one(0062400), one(0177400), "Bg", m68000up | mcfisa_a },
2197: {"jne", 2, one(0063000), one(0177400), "Bg", m68000up | mcfisa_a },
2198: {"jeq", 2, one(0063400), one(0177400), "Bg", m68000up | mcfisa_a },
2199: {"jvc", 2, one(0064000), one(0177400), "Bg", m68000up | mcfisa_a },
2200: {"jvs", 2, one(0064400), one(0177400), "Bg", m68000up | mcfisa_a },
2201: {"jpl", 2, one(0065000), one(0177400), "Bg", m68000up | mcfisa_a },
2202: {"jmi", 2, one(0065400), one(0177400), "Bg", m68000up | mcfisa_a },
2203: {"jge", 2, one(0066000), one(0177400), "Bg", m68000up | mcfisa_a },
2204: {"jlt", 2, one(0066400), one(0177400), "Bg", m68000up | mcfisa_a },
2205: {"jgt", 2, one(0067000), one(0177400), "Bg", m68000up | mcfisa_a },
2206: {"jle", 2, one(0067400), one(0177400), "Bg", m68000up | mcfisa_a },
2207:
2208: {"bchg", 2, one(0000500), one(0170700), "Dd$s", m68000up | mcfisa_a },
2209: {"bchg", 4, one(0004100), one(0177700), "#b$s", m68000up },
2210: {"bchg", 4, one(0004100), one(0177700), "#bqs", mcfisa_a },
2211:
2212: {"bclr", 2, one(0000600), one(0170700), "Dd$s", m68000up | mcfisa_a },
2213: {"bclr", 4, one(0004200), one(0177700), "#b$s", m68000up },
2214: {"bclr", 4, one(0004200), one(0177700), "#bqs", mcfisa_a },
2215:
2216: {"bfchg", 4, two(0165300, 0), two(0177700, 0170000), "?sO2O3", m68020up },
2217: {"bfclr", 4, two(0166300, 0), two(0177700, 0170000), "?sO2O3", m68020up },
2218: {"bfexts", 4, two(0165700, 0), two(0177700, 0100000), "/sO2O3D1", m68020up },
2219: {"bfextu", 4, two(0164700, 0), two(0177700, 0100000), "/sO2O3D1", m68020up },
2220: {"bfffo", 4, two(0166700, 0), two(0177700, 0100000), "/sO2O3D1", m68020up },
2221: {"bfins", 4, two(0167700, 0), two(0177700, 0100000), "D1?sO2O3", m68020up },
2222: {"bfset", 4, two(0167300, 0), two(0177700, 0170000), "?sO2O3", m68020up },
2223: {"bftst", 4, two(0164300, 0), two(0177700, 0170000), "/sO2O3", m68020up },
2224:
2225: {"bgnd", 2, one(0045372), one(0177777), "", cpu32 },
2226:
2227: {"bitrev", 2, one(0000300), one(0177770), "Ds", mcfisa_aa},
2228:
2229: {"bkpt", 2, one(0044110), one(0177770), "ts", m68010up },
2230:
2231: {"braw", 2, one(0060000), one(0177777), "BW", m68000up | mcfisa_a },
2232: {"bral", 2, one(0060377), one(0177777), "BL", m68020up | cpu32 | mcfisa_b},
2233: {"bras", 2, one(0060000), one(0177400), "BB", m68000up | mcfisa_a },
2234:
2235: {"bset", 2, one(0000700), one(0170700), "Dd$s", m68000up | mcfisa_a },
2236: {"bset", 2, one(0000700), one(0170700), "Ddvs", mcfisa_a },
2237: {"bset", 4, one(0004300), one(0177700), "#b$s", m68000up },
2238: {"bset", 4, one(0004300), one(0177700), "#bqs", mcfisa_a },
2239:
2240: {"bsrw", 2, one(0060400), one(0177777), "BW", m68000up | mcfisa_a },
2241: {"bsrl", 2, one(0060777), one(0177777), "BL", m68020up | cpu32 | mcfisa_b},
2242: {"bsrs", 2, one(0060400), one(0177400), "BB", m68000up | mcfisa_a },
2243:
2244: {"btst", 2, one(0000400), one(0170700), "Dd;b", m68000up | mcfisa_a },
2245: {"btst", 4, one(0004000), one(0177700), "#b@s", m68000up },
2246: {"btst", 4, one(0004000), one(0177700), "#bqs", mcfisa_a },
2247:
2248: {"byterev", 2, one(0001300), one(0177770), "Ds", mcfisa_aa},
2249:
2250: {"callm", 4, one(0003300), one(0177700), "#b!s", m68020 },
2251:
2252: {"cas2w", 6, two(0006374,0), two(0177777,0007070), "D3D6D2D5r1r4", m68020up },
2253: {"cas2w", 6, two(0006374,0), two(0177777,0007070), "D3D6D2D5R1R4", m68020up },
2254: {"cas2l", 6, two(0007374,0), two(0177777,0007070), "D3D6D2D5r1r4", m68020up },
2255: {"cas2l", 6, two(0007374,0), two(0177777,0007070), "D3D6D2D5R1R4", m68020up },
2256:
2257: {"casb", 4, two(0005300, 0), two(0177700, 0177070), "D3D2~s", m68020up },
2258: {"casw", 4, two(0006300, 0), two(0177700, 0177070), "D3D2~s", m68020up },
2259: {"casl", 4, two(0007300, 0), two(0177700, 0177070), "D3D2~s", m68020up },
2260:
2261: {"chk2b", 4, two(0000300,0004000), two(0177700,07777), "!sR1", m68020up | cpu32 },
2262: {"chk2w", 4, two(0001300,0004000), two(0177700,07777), "!sR1", m68020up | cpu32 },
2263: {"chk2l", 4, two(0002300,0004000), two(0177700,07777), "!sR1", m68020up | cpu32 },
2264:
2265: {"chkl", 2, one(0040400), one(0170700), ";lDd", m68000up },
2266: {"chkw", 2, one(0040600), one(0170700), ";wDd", m68000up },
2267:
2268: #define SCOPE_LINE (0x1 << 3)
2269: #define SCOPE_PAGE (0x2 << 3)
2270: #define SCOPE_ALL (0x3 << 3)
2271:
2272: {"cinva", 2, one(0xf400|SCOPE_ALL), one(0xff38), "ce", m68040up },
2273: {"cinvl", 2, one(0xf400|SCOPE_LINE), one(0xff38), "ceas", m68040up },
2274: {"cinvp", 2, one(0xf400|SCOPE_PAGE), one(0xff38), "ceas", m68040up },
2275:
2276: {"cpusha", 2, one(0xf420|SCOPE_ALL), one(0xff38), "ce", m68040up },
2277: {"cpushl", 2, one(0xf420|SCOPE_LINE), one(0xff38), "ceas", m68040up | mcfisa_a },
2278: {"cpushp", 2, one(0xf420|SCOPE_PAGE), one(0xff38), "ceas", m68040up },
2279:
2280: #undef SCOPE_LINE
2281: #undef SCOPE_PAGE
2282: #undef SCOPE_ALL
2283:
2284: {"clrb", 2, one(0041000), one(0177700), "$s", m68000up | mcfisa_a },
2285: {"clrw", 2, one(0041100), one(0177700), "$s", m68000up | mcfisa_a },
2286: {"clrl", 2, one(0041200), one(0177700), "$s", m68000up | mcfisa_a },
2287:
2288: {"cmp2b", 4, two(0000300,0), two(0177700,07777), "!sR1", m68020up | cpu32 },
2289: {"cmp2w", 4, two(0001300,0), two(0177700,07777), "!sR1", m68020up | cpu32 },
2290: {"cmp2l", 4, two(0002300,0), two(0177700,07777), "!sR1", m68020up | cpu32 },
2291:
2292: {"cmpaw", 2, one(0130300), one(0170700), "*wAd", m68000up },
2293: {"cmpal", 2, one(0130700), one(0170700), "*lAd", m68000up | mcfisa_a },
2294:
2295: {"cmpib", 4, one(0006000), one(0177700), "#b@s", m68000up },
2296: {"cmpib", 4, one(0006000), one(0177700), "#bDs", mcfisa_b },
2297: {"cmpiw", 4, one(0006100), one(0177700), "#w@s", m68000up },
2298: {"cmpiw", 4, one(0006100), one(0177700), "#wDs", mcfisa_b },
2299: {"cmpil", 6, one(0006200), one(0177700), "#l@s", m68000up },
2300: {"cmpil", 6, one(0006200), one(0177700), "#lDs", mcfisa_a },
2301:
2302: {"cmpmb", 2, one(0130410), one(0170770), "+s+d", m68000up },
2303: {"cmpmw", 2, one(0130510), one(0170770), "+s+d", m68000up },
2304: {"cmpml", 2, one(0130610), one(0170770), "+s+d", m68000up },
2305:
2306: /* The cmp opcode can generate the cmpa, cmpm, and cmpi instructions. */
2307: {"cmpb", 4, one(0006000), one(0177700), "#b@s", m68000up },
2308: {"cmpb", 4, one(0006000), one(0177700), "#bDs", mcfisa_b },
2309: {"cmpb", 2, one(0130410), one(0170770), "+s+d", m68000up },
2310: {"cmpb", 2, one(0130000), one(0170700), ";bDd", m68000up },
2311: {"cmpb", 2, one(0130000), one(0170700), "*bDd", mcfisa_b },
2312: {"cmpw", 2, one(0130300), one(0170700), "*wAd", m68000up },
2313: {"cmpw", 4, one(0006100), one(0177700), "#w@s", m68000up },
2314: {"cmpw", 4, one(0006100), one(0177700), "#wDs", mcfisa_b },
2315: {"cmpw", 2, one(0130510), one(0170770), "+s+d", m68000up },
2316: {"cmpw", 2, one(0130100), one(0170700), "*wDd", m68000up | mcfisa_b },
2317: {"cmpl", 2, one(0130700), one(0170700), "*lAd", m68000up | mcfisa_a },
2318: {"cmpl", 6, one(0006200), one(0177700), "#l@s", m68000up },
2319: {"cmpl", 6, one(0006200), one(0177700), "#lDs", mcfisa_a },
2320: {"cmpl", 2, one(0130610), one(0170770), "+s+d", m68000up },
2321: {"cmpl", 2, one(0130200), one(0170700), "*lDd", m68000up | mcfisa_a },
2322:
2323: {"dbcc", 2, one(0052310), one(0177770), "DsBw", m68000up },
2324: {"dbcs", 2, one(0052710), one(0177770), "DsBw", m68000up },
2325: {"dbeq", 2, one(0053710), one(0177770), "DsBw", m68000up },
2326: {"dbf", 2, one(0050710), one(0177770), "DsBw", m68000up },
2327: {"dbge", 2, one(0056310), one(0177770), "DsBw", m68000up },
2328: {"dbgt", 2, one(0057310), one(0177770), "DsBw", m68000up },
2329: {"dbhi", 2, one(0051310), one(0177770), "DsBw", m68000up },
2330: {"dble", 2, one(0057710), one(0177770), "DsBw", m68000up },
2331: {"dbls", 2, one(0051710), one(0177770), "DsBw", m68000up },
2332: {"dblt", 2, one(0056710), one(0177770), "DsBw", m68000up },
2333: {"dbmi", 2, one(0055710), one(0177770), "DsBw", m68000up },
2334: {"dbne", 2, one(0053310), one(0177770), "DsBw", m68000up },
2335: {"dbpl", 2, one(0055310), one(0177770), "DsBw", m68000up },
2336: {"dbt", 2, one(0050310), one(0177770), "DsBw", m68000up },
2337: {"dbvc", 2, one(0054310), one(0177770), "DsBw", m68000up },
2338: {"dbvs", 2, one(0054710), one(0177770), "DsBw", m68000up },
2339:
2340: {"divsw", 2, one(0100700), one(0170700), ";wDd", m68000up | mcfhwdiv },
2341:
2342: {"divsl", 4, two(0046100,0006000),two(0177700,0107770),";lD3D1", m68020up|cpu32 },
2343: {"divsl", 4, two(0046100,0004000),two(0177700,0107770),";lDD", m68020up|cpu32 },
2344: {"divsl", 4, two(0046100,0004000),two(0177700,0107770),"qsDD", mcfhwdiv },
2345:
2346: {"divsll", 4, two(0046100,0004000),two(0177700,0107770),";lD3D1",m68020up|cpu32 },
2347: {"divsll", 4, two(0046100,0004000),two(0177700,0107770),";lDD", m68020up|cpu32 },
2348:
2349: {"divuw", 2, one(0100300), one(0170700), ";wDd", m68000up | mcfhwdiv },
2350:
2351: {"divul", 4, two(0046100,0002000),two(0177700,0107770),";lD3D1", m68020up|cpu32 },
2352: {"divul", 4, two(0046100,0000000),two(0177700,0107770),";lDD", m68020up|cpu32 },
2353: {"divul", 4, two(0046100,0000000),two(0177700,0107770),"qsDD", mcfhwdiv },
2354:
2355: {"divull", 4, two(0046100,0000000),two(0177700,0107770),";lD3D1",m68020up|cpu32 },
2356: {"divull", 4, two(0046100,0000000),two(0177700,0107770),";lDD", m68020up|cpu32 },
2357:
2358: {"eorib", 4, one(0005000), one(0177700), "#b$s", m68000up },
2359: {"eorib", 4, one(0005074), one(0177777), "#bCs", m68000up },
2360: {"eoriw", 4, one(0005100), one(0177700), "#w$s", m68000up },
2361: {"eoriw", 4, one(0005174), one(0177777), "#wSs", m68000up },
2362: {"eoril", 6, one(0005200), one(0177700), "#l$s", m68000up },
2363: {"eoril", 6, one(0005200), one(0177700), "#lDs", mcfisa_a },
2364: {"eori", 4, one(0005074), one(0177777), "#bCs", m68000up },
2365: {"eori", 4, one(0005174), one(0177777), "#wSs", m68000up },
2366: {"eori", 4, one(0005100), one(0177700), "#w$s", m68000up },
2367:
2368: /* The eor opcode can generate the eori instruction. */
2369: {"eorb", 4, one(0005000), one(0177700), "#b$s", m68000up },
2370: {"eorb", 4, one(0005074), one(0177777), "#bCs", m68000up },
2371: {"eorb", 2, one(0130400), one(0170700), "Dd$s", m68000up },
2372: {"eorw", 4, one(0005100), one(0177700), "#w$s", m68000up },
2373: {"eorw", 4, one(0005174), one(0177777), "#wSs", m68000up },
2374: {"eorw", 2, one(0130500), one(0170700), "Dd$s", m68000up },
2375: {"eorl", 6, one(0005200), one(0177700), "#l$s", m68000up },
2376: {"eorl", 6, one(0005200), one(0177700), "#lDs", mcfisa_a },
2377: {"eorl", 2, one(0130600), one(0170700), "Dd$s", m68000up | mcfisa_a },
2378: {"eor", 4, one(0005074), one(0177777), "#bCs", m68000up },
2379: {"eor", 4, one(0005174), one(0177777), "#wSs", m68000up },
2380: {"eor", 4, one(0005100), one(0177700), "#w$s", m68000up },
2381: {"eor", 2, one(0130500), one(0170700), "Dd$s", m68000up },
1.1.1.2 root 2382:
1.1 root 2383: {"exg", 2, one(0140500), one(0170770), "DdDs", m68000up },
2384: {"exg", 2, one(0140510), one(0170770), "AdAs", m68000up },
2385: {"exg", 2, one(0140610), one(0170770), "DdAs", m68000up },
2386: {"exg", 2, one(0140610), one(0170770), "AsDd", m68000up },
2387:
2388: {"extw", 2, one(0044200), one(0177770), "Ds", m68000up|mcfisa_a },
2389: {"extl", 2, one(0044300), one(0177770), "Ds", m68000up|mcfisa_a },
2390: {"extbl", 2, one(0044700), one(0177770), "Ds", m68020up|cpu32|mcfisa_a },
2391:
2392: {"ff1", 2, one(0002300), one(0177770), "Ds", mcfisa_aa},
2393:
2394: /* float stuff starts here */
2395:
2396: {"fabsb", 4, two(0xF000, 0x5818), two(0xF1C0, 0xFC7F), "Ii;bF7", mfloat },
2397: {"fabsb", 4, two(0xF000, 0x5818), two(0xF1C0, 0xFC7F), "IibsF7", cfloat },
2398: {"fabsd", 4, two(0xF000, 0x0018), two(0xF1C0, 0xE07F), "IiF8F7", cfloat },
2399: {"fabsd", 4, two(0xF000, 0x0018), two(0xF1C0, 0xE07F), "IiFt", cfloat },
2400: {"fabsd", 4, two(0xF000, 0x5418), two(0xF1C0, 0xFC7F), "Ii;FF7", mfloat },
2401: {"fabsd", 4, two(0xF000, 0x5418), two(0xF1C0, 0xFC7F), "IiwsF7", cfloat },
2402: {"fabsl", 4, two(0xF000, 0x4018), two(0xF1C0, 0xFC7F), "Ii;lF7", mfloat },
2403: {"fabsl", 4, two(0xF000, 0x4018), two(0xF1C0, 0xFC7F), "IibsF7", cfloat },
2404: {"fabsp", 4, two(0xF000, 0x4C18), two(0xF1C0, 0xFC7F), "Ii;pF7", mfloat },
2405: {"fabss", 4, two(0xF000, 0x4418), two(0xF1C0, 0xFC7F), "Ii;fF7", cfloat },
2406: {"fabss", 4, two(0xF000, 0x4418), two(0xF1C0, 0xFC7F), "Ii;fF7", mfloat },
2407: {"fabsw", 4, two(0xF000, 0x5018), two(0xF1C0, 0xFC7F), "Ii;wF7", mfloat },
2408: {"fabsw", 4, two(0xF000, 0x5018), two(0xF1C0, 0xFC7F), "IibsF7", cfloat },
2409: {"fabsx", 4, two(0xF000, 0x0018), two(0xF1C0, 0xE07F), "IiF8F7", mfloat },
2410: {"fabsx", 4, two(0xF000, 0x4818), two(0xF1C0, 0xFC7F), "Ii;xF7", mfloat },
2411: {"fabsx", 4, two(0xF000, 0x0018), two(0xF1C0, 0xE07F), "IiFt", mfloat },
2412:
2413: {"fsabsb", 4, two(0xF000, 0x5858), two(0xF1C0, 0xFC7F), "Ii;bF7", m68040up },
2414: {"fsabsb", 4, two(0xF000, 0x5858), two(0xF1C0, 0xFC7F), "IibsF7", cfloat },
2415: {"fsabsd", 4, two(0xF000, 0x0058), two(0xF1C0, 0xE07F), "IiF8F7", cfloat },
2416: {"fsabsd", 4, two(0xF000, 0x0058), two(0xF1C0, 0xE07F), "IiFt", cfloat },
2417: {"fsabsd", 4, two(0xF000, 0x5458), two(0xF1C0, 0xFC7F), "Ii;FF7", m68040up },
2418: {"fsabsd", 4, two(0xF000, 0x5458), two(0xF1C0, 0xFC7F), "IiwsF7", cfloat },
2419: {"fsabsl", 4, two(0xF000, 0x4058), two(0xF1C0, 0xFC7F), "Ii;lF7", m68040up },
2420: {"fsabsl", 4, two(0xF000, 0x4058), two(0xF1C0, 0xFC7F), "IibsF7", cfloat },
2421: {"fsabsp", 4, two(0xF000, 0x4C58), two(0xF1C0, 0xFC7F), "Ii;pF7", m68040up },
2422: {"fsabss", 4, two(0xF000, 0x4258), two(0xF1C0, 0xFC7F), "IibsF7", cfloat },
2423: {"fsabss", 4, two(0xF000, 0x4458), two(0xF1C0, 0xFC7F), "Ii;fF7", m68040up },
2424: {"fsabsw", 4, two(0xF000, 0x5058), two(0xF1C0, 0xFC7F), "Ii;wF7", m68040up },
2425: {"fsabsw", 4, two(0xF000, 0x5058), two(0xF1C0, 0xFC7F), "IibsF7", cfloat },
2426: {"fsabsx", 4, two(0xF000, 0x0058), two(0xF1C0, 0xE07F), "IiF8F7", m68040up },
2427: {"fsabsx", 4, two(0xF000, 0x4858), two(0xF1C0, 0xFC7F), "Ii;xF7", m68040up },
2428: {"fsabsx", 4, two(0xF000, 0x0058), two(0xF1C0, 0xE07F), "IiFt", m68040up },
2429:
2430: {"fdabsb", 4, two(0xF000, 0x585C), two(0xF1C0, 0xFC7F), "IibsF7", cfloat },
2431: {"fdabsb", 4, two(0xF000, 0x585c), two(0xF1C0, 0xFC7F), "Ii;bF7", m68040up},
2432: {"fdabsd", 4, two(0xF000, 0x005C), two(0xF1C0, 0xE07F), "IiF8F7", cfloat },
2433: {"fdabsd", 4, two(0xF000, 0x005C), two(0xF1C0, 0xE07F), "IiFt", cfloat },
2434: {"fdabsd", 4, two(0xF000, 0x545C), two(0xF1C0, 0xFC7F), "IiwsF7", cfloat },
2435: {"fdabsd", 4, two(0xF000, 0x545c), two(0xF1C0, 0xFC7F), "Ii;FF7", m68040up},
2436: {"fdabsl", 4, two(0xF000, 0x405C), two(0xF1C0, 0xFC7F), "IibsF7", cfloat },
2437: {"fdabsl", 4, two(0xF000, 0x405c), two(0xF1C0, 0xFC7F), "Ii;lF7", m68040up},
2438: {"fdabsp", 4, two(0xF000, 0x4C5c), two(0xF1C0, 0xFC7F), "Ii;pF7", m68040up},
2439: {"fdabss", 4, two(0xF000, 0x425C), two(0xF1C0, 0xFC7F), "IibsF7", cfloat },
2440: {"fdabss", 4, two(0xF000, 0x445c), two(0xF1C0, 0xFC7F), "Ii;fF7", m68040up},
2441: {"fdabsw", 4, two(0xF000, 0x505C), two(0xF1C0, 0xFC7F), "IibsF7", cfloat },
2442: {"fdabsw", 4, two(0xF000, 0x505c), two(0xF1C0, 0xFC7F), "Ii;wF7", m68040up},
2443: {"fdabsx", 4, two(0xF000, 0x005c), two(0xF1C0, 0xE07F), "IiF8F7", m68040up},
2444: {"fdabsx", 4, two(0xF000, 0x485c), two(0xF1C0, 0xFC7F), "Ii;xF7", m68040up},
2445: {"fdabsx", 4, two(0xF000, 0x005c), two(0xF1C0, 0xE07F), "IiFt", m68040up},
2446:
2447: {"facosb", 4, two(0xF000, 0x581C), two(0xF1C0, 0xFC7F), "Ii;bF7", mfloat },
2448: {"facosd", 4, two(0xF000, 0x541C), two(0xF1C0, 0xFC7F), "Ii;FF7", mfloat },
2449: {"facosl", 4, two(0xF000, 0x401C), two(0xF1C0, 0xFC7F), "Ii;lF7", mfloat },
2450: {"facosp", 4, two(0xF000, 0x4C1C), two(0xF1C0, 0xFC7F), "Ii;pF7", mfloat },
2451: {"facoss", 4, two(0xF000, 0x441C), two(0xF1C0, 0xFC7F), "Ii;fF7", mfloat },
2452: {"facosw", 4, two(0xF000, 0x501C), two(0xF1C0, 0xFC7F), "Ii;wF7", mfloat },
2453: {"facosx", 4, two(0xF000, 0x001C), two(0xF1C0, 0xE07F), "IiF8F7", mfloat },
2454: {"facosx", 4, two(0xF000, 0x481C), two(0xF1C0, 0xFC7F), "Ii;xF7", mfloat },
2455: {"facosx", 4, two(0xF000, 0x001C), two(0xF1C0, 0xE07F), "IiFt", mfloat },
2456:
2457: {"faddb", 4, two(0xF000, 0x5822), two(0xF1C0, 0xFC7F), "Ii;bF7", mfloat },
2458: {"faddb", 4, two(0xF000, 0x5822), two(0xF1C0, 0xFC7F), "IibsF7", cfloat },
2459: {"faddd", 4, two(0xF000, 0x0022), two(0xF1C0, 0xE07F), "IiF8F7", cfloat },
2460: {"faddd", 4, two(0xF000, 0x5422), two(0xF1C0, 0xFC7F), "IiwsF7", cfloat },
2461: {"faddd", 4, two(0xF000, 0x5422), two(0xF1C0, 0xFC7F), "Ii;FF7", mfloat },
2462: {"faddd", 4, two(0xF000, 0x5422), two(0xF1C0, 0xFC7F), "IiwsF7", cfloat },
2463: {"faddl", 4, two(0xF000, 0x4022), two(0xF1C0, 0xFC7F), "Ii;lF7", mfloat },
2464: {"faddl", 4, two(0xF000, 0x4022), two(0xF1C0, 0xFC7F), "IibsF7", cfloat },
2465: {"faddp", 4, two(0xF000, 0x4C22), two(0xF1C0, 0xFC7F), "Ii;pF7", mfloat },
2466: {"fadds", 4, two(0xF000, 0x4422), two(0xF1C0, 0xFC7F), "Ii;fF7", mfloat },
2467: {"fadds", 4, two(0xF000, 0x4422), two(0xF1C0, 0xFC7F), "IibsF7", cfloat },
2468: {"faddw", 4, two(0xF000, 0x5022), two(0xF1C0, 0xFC7F), "Ii;wF7", mfloat },
2469: {"faddw", 4, two(0xF000, 0x5022), two(0xF1C0, 0xFC7F), "IibsF7", cfloat },
2470: {"faddx", 4, two(0xF000, 0x0022), two(0xF1C0, 0xE07F), "IiF8F7", mfloat },
2471: {"faddx", 4, two(0xF000, 0x4822), two(0xF1C0, 0xFC7F), "Ii;xF7", mfloat },
2472:
2473: {"fsaddb", 4, two(0xF000, 0x5862), two(0xF1C0, 0xFC7F), "Ii;bF7", m68040up },
2474: {"fsaddb", 4, two(0xF000, 0x5862), two(0xF1C0, 0xFC7F), "IibsF7", cfloat },
2475: {"fsaddd", 4, two(0xF000, 0x0066), two(0xF1C0, 0xE07F), "IiF8F7", cfloat },
2476: {"fsaddd", 4, two(0xF000, 0x5462), two(0xF1C0, 0xFC7F), "Ii;FF7", m68040up },
2477: {"fsaddd", 4, two(0xF000, 0x5462), two(0xF1C0, 0xFC7F), "IiwsF7", cfloat },
2478: {"fsaddl", 4, two(0xF000, 0x4062), two(0xF1C0, 0xFC7F), "Ii;lF7", m68040up },
2479: {"fsaddl", 4, two(0xF000, 0x4062), two(0xF1C0, 0xFC7F), "IibsF7", cfloat },
2480: {"fsaddp", 4, two(0xF000, 0x4C62), two(0xF1C0, 0xFC7F), "Ii;pF7", m68040up },
2481: {"fsadds", 4, two(0xF000, 0x4462), two(0xF1C0, 0xFC7F), "Ii;fF7", m68040up },
2482: {"fsadds", 4, two(0xF000, 0x4862), two(0xF1C0, 0xFC7F), "IibsF7", cfloat },
2483: {"fsaddw", 4, two(0xF000, 0x5062), two(0xF1C0, 0xFC7F), "Ii;wF7", m68040up },
2484: {"fsaddw", 4, two(0xF000, 0x5062), two(0xF1C0, 0xFC7F), "IibsF7", cfloat },
2485: {"fsaddx", 4, two(0xF000, 0x0062), two(0xF1C0, 0xE07F), "IiF8F7", m68040up },
2486: {"fsaddx", 4, two(0xF000, 0x4862), two(0xF1C0, 0xFC7F), "Ii;xF7", m68040up },
2487:
2488: {"fdaddb", 4, two(0xF000, 0x5826), two(0xF1C0, 0xFC7F), "IibsF7", cfloat },
2489: {"fdaddb", 4, two(0xF000, 0x5866), two(0xF1C0, 0xFC7F), "Ii;bF7", m68040up },
2490: {"fdaddd", 4, two(0xF000, 0x0066), two(0xF1C0, 0xE07F), "IiF8F7", cfloat },
2491: {"fdaddd", 4, two(0xF000, 0x5426), two(0xF1C0, 0xFC7F), "IibsF7", cfloat },
2492: {"fdaddd", 4, two(0xF000, 0x5466), two(0xF1C0, 0xFC7F), "Ii;FF7", m68040up },
2493: {"fdaddl", 4, two(0xF000, 0x4026), two(0xF1C0, 0xFC7F), "IiwsF7", cfloat },
2494: {"fdaddl", 4, two(0xF000, 0x4066), two(0xF1C0, 0xFC7F), "Ii;lF7", m68040up },
2495: {"fdaddp", 4, two(0xF000, 0x4C66), two(0xF1C0, 0xFC7F), "Ii;pF7", m68040up },
2496: {"fdadds", 4, two(0xF000, 0x4466), two(0xF1C0, 0xFC7F), "Ii;fF7", m68040up },
2497: {"fdadds", 4, two(0xF000, 0x4826), two(0xF1C0, 0xFC7F), "IibsF7", cfloat },
2498: {"fdaddw", 4, two(0xF000, 0x5026), two(0xF1C0, 0xFC7F), "IibsF7", cfloat },
2499: {"fdaddw", 4, two(0xF000, 0x5066), two(0xF1C0, 0xFC7F), "Ii;wF7", m68040up },
2500: {"fdaddx", 4, two(0xF000, 0x0066), two(0xF1C0, 0xE07F), "IiF8F7", m68040up },
2501: {"fdaddx", 4, two(0xF000, 0x4866), two(0xF1C0, 0xFC7F), "Ii;xF7", m68040up },
2502:
2503: {"fasinb", 4, two(0xF000, 0x580C), two(0xF1C0, 0xFC7F), "Ii;bF7", mfloat },
2504: {"fasind", 4, two(0xF000, 0x540C), two(0xF1C0, 0xFC7F), "Ii;FF7", mfloat },
2505: {"fasinl", 4, two(0xF000, 0x400C), two(0xF1C0, 0xFC7F), "Ii;lF7", mfloat },
2506: {"fasinp", 4, two(0xF000, 0x4C0C), two(0xF1C0, 0xFC7F), "Ii;pF7", mfloat },
2507: {"fasins", 4, two(0xF000, 0x440C), two(0xF1C0, 0xFC7F), "Ii;fF7", mfloat },
2508: {"fasinw", 4, two(0xF000, 0x500C), two(0xF1C0, 0xFC7F), "Ii;wF7", mfloat },
2509: {"fasinx", 4, two(0xF000, 0x000C), two(0xF1C0, 0xE07F), "IiF8F7", mfloat },
2510: {"fasinx", 4, two(0xF000, 0x480C), two(0xF1C0, 0xFC7F), "Ii;xF7", mfloat },
2511: {"fasinx", 4, two(0xF000, 0x000C), two(0xF1C0, 0xE07F), "IiFt", mfloat },
2512:
2513: {"fatanb", 4, two(0xF000, 0x580A), two(0xF1C0, 0xFC7F), "Ii;bF7", mfloat },
2514: {"fatand", 4, two(0xF000, 0x540A), two(0xF1C0, 0xFC7F), "Ii;FF7", mfloat },
2515: {"fatanl", 4, two(0xF000, 0x400A), two(0xF1C0, 0xFC7F), "Ii;lF7", mfloat },
2516: {"fatanp", 4, two(0xF000, 0x4C0A), two(0xF1C0, 0xFC7F), "Ii;pF7", mfloat },
2517: {"fatans", 4, two(0xF000, 0x440A), two(0xF1C0, 0xFC7F), "Ii;fF7", mfloat },
2518: {"fatanw", 4, two(0xF000, 0x500A), two(0xF1C0, 0xFC7F), "Ii;wF7", mfloat },
2519: {"fatanx", 4, two(0xF000, 0x000A), two(0xF1C0, 0xE07F), "IiF8F7", mfloat },
2520: {"fatanx", 4, two(0xF000, 0x480A), two(0xF1C0, 0xFC7F), "Ii;xF7", mfloat },
2521: {"fatanx", 4, two(0xF000, 0x000A), two(0xF1C0, 0xE07F), "IiFt", mfloat },
2522:
2523: {"fatanhb", 4, two(0xF000, 0x580D), two(0xF1C0, 0xFC7F), "Ii;bF7", mfloat },
2524: {"fatanhd", 4, two(0xF000, 0x540D), two(0xF1C0, 0xFC7F), "Ii;FF7", mfloat },
2525: {"fatanhl", 4, two(0xF000, 0x400D), two(0xF1C0, 0xFC7F), "Ii;lF7", mfloat },
2526: {"fatanhp", 4, two(0xF000, 0x4C0D), two(0xF1C0, 0xFC7F), "Ii;pF7", mfloat },
2527: {"fatanhs", 4, two(0xF000, 0x440D), two(0xF1C0, 0xFC7F), "Ii;fF7", mfloat },
2528: {"fatanhw", 4, two(0xF000, 0x500D), two(0xF1C0, 0xFC7F), "Ii;wF7", mfloat },
2529: {"fatanhx", 4, two(0xF000, 0x000D), two(0xF1C0, 0xE07F), "IiF8F7", mfloat },
2530: {"fatanhx", 4, two(0xF000, 0x480D), two(0xF1C0, 0xFC7F), "Ii;xF7", mfloat },
2531: {"fatanhx", 4, two(0xF000, 0x000D), two(0xF1C0, 0xE07F), "IiFt", mfloat },
2532:
2533: {"fbeq", 2, one(0xF081), one(0xF1FF), "IdBW", mfloat | cfloat },
2534: {"fbf", 2, one(0xF080), one(0xF1FF), "IdBW", mfloat | cfloat },
2535: {"fbge", 2, one(0xF093), one(0xF1FF), "IdBW", mfloat | cfloat },
2536: {"fbgl", 2, one(0xF096), one(0xF1FF), "IdBW", mfloat | cfloat },
2537: {"fbgle", 2, one(0xF097), one(0xF1FF), "IdBW", mfloat | cfloat },
2538: {"fbgt", 2, one(0xF092), one(0xF1FF), "IdBW", mfloat | cfloat },
2539: {"fble", 2, one(0xF095), one(0xF1FF), "IdBW", mfloat | cfloat },
2540: {"fblt", 2, one(0xF094), one(0xF1FF), "IdBW", mfloat | cfloat },
2541: {"fbne", 2, one(0xF08E), one(0xF1FF), "IdBW", mfloat | cfloat },
2542: {"fbnge", 2, one(0xF09C), one(0xF1FF), "IdBW", mfloat | cfloat },
2543: {"fbngl", 2, one(0xF099), one(0xF1FF), "IdBW", mfloat | cfloat },
2544: {"fbngle", 2, one(0xF098), one(0xF1FF), "IdBW", mfloat | cfloat },
2545: {"fbngt", 2, one(0xF09D), one(0xF1FF), "IdBW", mfloat | cfloat },
2546: {"fbnle", 2, one(0xF09A), one(0xF1FF), "IdBW", mfloat | cfloat },
2547: {"fbnlt", 2, one(0xF09B), one(0xF1FF), "IdBW", mfloat | cfloat },
2548: {"fboge", 2, one(0xF083), one(0xF1FF), "IdBW", mfloat | cfloat },
2549: {"fbogl", 2, one(0xF086), one(0xF1FF), "IdBW", mfloat | cfloat },
2550: {"fbogt", 2, one(0xF082), one(0xF1FF), "IdBW", mfloat | cfloat },
2551: {"fbole", 2, one(0xF085), one(0xF1FF), "IdBW", mfloat | cfloat },
2552: {"fbolt", 2, one(0xF084), one(0xF1FF), "IdBW", mfloat | cfloat },
2553: {"fbor", 2, one(0xF087), one(0xF1FF), "IdBW", mfloat | cfloat },
2554: {"fbseq", 2, one(0xF091), one(0xF1FF), "IdBW", mfloat | cfloat },
2555: {"fbsf", 2, one(0xF090), one(0xF1FF), "IdBW", mfloat | cfloat },
2556: {"fbsne", 2, one(0xF09E), one(0xF1FF), "IdBW", mfloat | cfloat },
2557: {"fbst", 2, one(0xF09F), one(0xF1FF), "IdBW", mfloat | cfloat },
2558: {"fbt", 2, one(0xF08F), one(0xF1FF), "IdBW", mfloat | cfloat },
2559: {"fbueq", 2, one(0xF089), one(0xF1FF), "IdBW", mfloat | cfloat },
2560: {"fbuge", 2, one(0xF08B), one(0xF1FF), "IdBW", mfloat | cfloat },
2561: {"fbugt", 2, one(0xF08A), one(0xF1FF), "IdBW", mfloat | cfloat },
2562: {"fbule", 2, one(0xF08D), one(0xF1FF), "IdBW", mfloat | cfloat },
2563: {"fbult", 2, one(0xF08C), one(0xF1FF), "IdBW", mfloat | cfloat },
2564: {"fbun", 2, one(0xF088), one(0xF1FF), "IdBW", mfloat | cfloat },
2565:
2566: {"fbeql", 2, one(0xF0C1), one(0xF1FF), "IdBC", mfloat | cfloat },
2567: {"fbfl", 2, one(0xF0C0), one(0xF1FF), "IdBC", mfloat | cfloat },
2568: {"fbgel", 2, one(0xF0D3), one(0xF1FF), "IdBC", mfloat | cfloat },
2569: {"fbgll", 2, one(0xF0D6), one(0xF1FF), "IdBC", mfloat | cfloat },
2570: {"fbglel", 2, one(0xF0D7), one(0xF1FF), "IdBC", mfloat | cfloat },
2571: {"fbgtl", 2, one(0xF0D2), one(0xF1FF), "IdBC", mfloat | cfloat },
2572: {"fblel", 2, one(0xF0D5), one(0xF1FF), "IdBC", mfloat | cfloat },
2573: {"fbltl", 2, one(0xF0D4), one(0xF1FF), "IdBC", mfloat | cfloat },
2574: {"fbnel", 2, one(0xF0CE), one(0xF1FF), "IdBC", mfloat | cfloat },
2575: {"fbngel", 2, one(0xF0DC), one(0xF1FF), "IdBC", mfloat | cfloat },
2576: {"fbngll", 2, one(0xF0D9), one(0xF1FF), "IdBC", mfloat | cfloat },
2577: {"fbnglel", 2, one(0xF0D8), one(0xF1FF), "IdBC", mfloat | cfloat },
2578: {"fbngtl", 2, one(0xF0DD), one(0xF1FF), "IdBC", mfloat | cfloat },
2579: {"fbnlel", 2, one(0xF0DA), one(0xF1FF), "IdBC", mfloat | cfloat },
2580: {"fbnltl", 2, one(0xF0DB), one(0xF1FF), "IdBC", mfloat | cfloat },
2581: {"fbogel", 2, one(0xF0C3), one(0xF1FF), "IdBC", mfloat | cfloat },
2582: {"fbogll", 2, one(0xF0C6), one(0xF1FF), "IdBC", mfloat | cfloat },
2583: {"fbogtl", 2, one(0xF0C2), one(0xF1FF), "IdBC", mfloat | cfloat },
2584: {"fbolel", 2, one(0xF0C5), one(0xF1FF), "IdBC", mfloat | cfloat },
2585: {"fboltl", 2, one(0xF0C4), one(0xF1FF), "IdBC", mfloat | cfloat },
2586: {"fborl", 2, one(0xF0C7), one(0xF1FF), "IdBC", mfloat | cfloat },
2587: {"fbseql", 2, one(0xF0D1), one(0xF1FF), "IdBC", mfloat | cfloat },
2588: {"fbsfl", 2, one(0xF0D0), one(0xF1FF), "IdBC", mfloat | cfloat },
2589: {"fbsnel", 2, one(0xF0DE), one(0xF1FF), "IdBC", mfloat | cfloat },
2590: {"fbstl", 2, one(0xF0DF), one(0xF1FF), "IdBC", mfloat | cfloat },
2591: {"fbtl", 2, one(0xF0CF), one(0xF1FF), "IdBC", mfloat | cfloat },
2592: {"fbueql", 2, one(0xF0C9), one(0xF1FF), "IdBC", mfloat | cfloat },
2593: {"fbugel", 2, one(0xF0CB), one(0xF1FF), "IdBC", mfloat | cfloat },
2594: {"fbugtl", 2, one(0xF0CA), one(0xF1FF), "IdBC", mfloat | cfloat },
2595: {"fbulel", 2, one(0xF0CD), one(0xF1FF), "IdBC", mfloat | cfloat },
2596: {"fbultl", 2, one(0xF0CC), one(0xF1FF), "IdBC", mfloat | cfloat },
2597: {"fbunl", 2, one(0xF0C8), one(0xF1FF), "IdBC", mfloat | cfloat },
2598:
2599: {"fjeq", 2, one(0xF081), one(0xF1BF), "IdBc", mfloat | cfloat },
2600: {"fjf", 2, one(0xF080), one(0xF1BF), "IdBc", mfloat | cfloat },
2601: {"fjge", 2, one(0xF093), one(0xF1BF), "IdBc", mfloat | cfloat },
2602: {"fjgl", 2, one(0xF096), one(0xF1BF), "IdBc", mfloat | cfloat },
2603: {"fjgle", 2, one(0xF097), one(0xF1BF), "IdBc", mfloat | cfloat },
2604: {"fjgt", 2, one(0xF092), one(0xF1BF), "IdBc", mfloat | cfloat },
2605: {"fjle", 2, one(0xF095), one(0xF1BF), "IdBc", mfloat | cfloat },
2606: {"fjlt", 2, one(0xF094), one(0xF1BF), "IdBc", mfloat | cfloat },
2607: {"fjne", 2, one(0xF08E), one(0xF1BF), "IdBc", mfloat | cfloat },
2608: {"fjnge", 2, one(0xF09C), one(0xF1BF), "IdBc", mfloat | cfloat },
2609: {"fjngl", 2, one(0xF099), one(0xF1BF), "IdBc", mfloat | cfloat },
2610: {"fjngle", 2, one(0xF098), one(0xF1BF), "IdBc", mfloat | cfloat },
2611: {"fjngt", 2, one(0xF09D), one(0xF1BF), "IdBc", mfloat | cfloat },
2612: {"fjnle", 2, one(0xF09A), one(0xF1BF), "IdBc", mfloat | cfloat },
2613: {"fjnlt", 2, one(0xF09B), one(0xF1BF), "IdBc", mfloat | cfloat },
2614: {"fjoge", 2, one(0xF083), one(0xF1BF), "IdBc", mfloat | cfloat },
2615: {"fjogl", 2, one(0xF086), one(0xF1BF), "IdBc", mfloat | cfloat },
2616: {"fjogt", 2, one(0xF082), one(0xF1BF), "IdBc", mfloat | cfloat },
2617: {"fjole", 2, one(0xF085), one(0xF1BF), "IdBc", mfloat | cfloat },
2618: {"fjolt", 2, one(0xF084), one(0xF1BF), "IdBc", mfloat | cfloat },
2619: {"fjor", 2, one(0xF087), one(0xF1BF), "IdBc", mfloat | cfloat },
2620: {"fjseq", 2, one(0xF091), one(0xF1BF), "IdBc", mfloat | cfloat },
2621: {"fjsf", 2, one(0xF090), one(0xF1BF), "IdBc", mfloat | cfloat },
2622: {"fjsne", 2, one(0xF09E), one(0xF1BF), "IdBc", mfloat | cfloat },
2623: {"fjst", 2, one(0xF09F), one(0xF1BF), "IdBc", mfloat | cfloat },
2624: {"fjt", 2, one(0xF08F), one(0xF1BF), "IdBc", mfloat | cfloat },
2625: {"fjueq", 2, one(0xF089), one(0xF1BF), "IdBc", mfloat | cfloat },
2626: {"fjuge", 2, one(0xF08B), one(0xF1BF), "IdBc", mfloat | cfloat },
2627: {"fjugt", 2, one(0xF08A), one(0xF1BF), "IdBc", mfloat | cfloat },
2628: {"fjule", 2, one(0xF08D), one(0xF1BF), "IdBc", mfloat | cfloat },
2629: {"fjult", 2, one(0xF08C), one(0xF1BF), "IdBc", mfloat | cfloat },
2630: {"fjun", 2, one(0xF088), one(0xF1BF), "IdBc", mfloat | cfloat },
2631:
2632: {"fcmpb", 4, two(0xF000, 0x5838), two(0xF1C0, 0xFC7F), "IibsF7", cfloat },
2633: {"fcmpb", 4, two(0xF000, 0x5838), two(0xF1C0, 0xFC7F), "Ii;bF7", mfloat },
2634: {"fcmpd", 4, two(0xF000, 0x5438), two(0xF1C0, 0xFC7F), "Ii;FF7", mfloat },
2635: {"fcmpd", 4, two(0xF000, 0x5438), two(0xF1C0, 0xFC7F), "IiwsF7", cfloat },
2636: {"fcmpd", 4, two(0xF000, 0x0038), two(0xF1C0, 0xE07F), "IiF8F7", cfloat },
2637: {"fcmpl", 4, two(0xF000, 0x4038), two(0xF1C0, 0xFC7F), "Ii;lF7", mfloat },
2638: {"fcmpl", 4, two(0xF000, 0x4038), two(0xF1C0, 0xFC7F), "IibsF7", cfloat },
2639: {"fcmpp", 4, two(0xF000, 0x4C38), two(0xF1C0, 0xFC7F), "Ii;pF7", mfloat },
2640: {"fcmps", 4, two(0xF000, 0x4438), two(0xF1C0, 0xFC7F), "Ii;fF7", mfloat },
2641: {"fcmps", 4, two(0xF000, 0x4438), two(0xF1C0, 0xFC7F), "IibsF7", cfloat },
2642: {"fcmpw", 4, two(0xF000, 0x5038), two(0xF1C0, 0xFC7F), "Ii;wF7", mfloat },
2643: {"fcmpw", 4, two(0xF000, 0x5038), two(0xF1C0, 0xFC7F), "IibsF7", cfloat },
2644: {"fcmpx", 4, two(0xF000, 0x0038), two(0xF1C0, 0xE07F), "IiF8F7", mfloat },
2645: {"fcmpx", 4, two(0xF000, 0x4838), two(0xF1C0, 0xFC7F), "Ii;xF7", mfloat },
2646:
2647: {"fcosb", 4, two(0xF000, 0x581D), two(0xF1C0, 0xFC7F), "Ii;bF7", mfloat },
2648: {"fcosd", 4, two(0xF000, 0x541D), two(0xF1C0, 0xFC7F), "Ii;FF7", mfloat },
2649: {"fcosl", 4, two(0xF000, 0x401D), two(0xF1C0, 0xFC7F), "Ii;lF7", mfloat },
2650: {"fcosp", 4, two(0xF000, 0x4C1D), two(0xF1C0, 0xFC7F), "Ii;pF7", mfloat },
2651: {"fcoss", 4, two(0xF000, 0x441D), two(0xF1C0, 0xFC7F), "Ii;fF7", mfloat },
2652: {"fcosw", 4, two(0xF000, 0x501D), two(0xF1C0, 0xFC7F), "Ii;wF7", mfloat },
2653: {"fcosx", 4, two(0xF000, 0x001D), two(0xF1C0, 0xE07F), "IiF8F7", mfloat },
2654: {"fcosx", 4, two(0xF000, 0x481D), two(0xF1C0, 0xFC7F), "Ii;xF7", mfloat },
2655: {"fcosx", 4, two(0xF000, 0x001D), two(0xF1C0, 0xE07F), "IiFt", mfloat },
2656:
2657: {"fcoshb", 4, two(0xF000, 0x5819), two(0xF1C0, 0xFC7F), "Ii;bF7", mfloat },
2658: {"fcoshd", 4, two(0xF000, 0x5419), two(0xF1C0, 0xFC7F), "Ii;FF7", mfloat },
2659: {"fcoshl", 4, two(0xF000, 0x4019), two(0xF1C0, 0xFC7F), "Ii;lF7", mfloat },
2660: {"fcoshp", 4, two(0xF000, 0x4C19), two(0xF1C0, 0xFC7F), "Ii;pF7", mfloat },
2661: {"fcoshs", 4, two(0xF000, 0x4419), two(0xF1C0, 0xFC7F), "Ii;fF7", mfloat },
2662: {"fcoshw", 4, two(0xF000, 0x5019), two(0xF1C0, 0xFC7F), "Ii;wF7", mfloat },
2663: {"fcoshx", 4, two(0xF000, 0x0019), two(0xF1C0, 0xE07F), "IiF8F7", mfloat },
2664: {"fcoshx", 4, two(0xF000, 0x4819), two(0xF1C0, 0xFC7F), "Ii;xF7", mfloat },
2665: {"fcoshx", 4, two(0xF000, 0x0019), two(0xF1C0, 0xE07F), "IiFt", mfloat },
2666:
2667: {"fdbeq", 4, two(0xF048, 0x0001), two(0xF1F8, 0xFFFF), "IiDsBw", mfloat },
2668: {"fdbf", 4, two(0xF048, 0x0000), two(0xF1F8, 0xFFFF), "IiDsBw", mfloat },
2669: {"fdbge", 4, two(0xF048, 0x0013), two(0xF1F8, 0xFFFF), "IiDsBw", mfloat },
2670: {"fdbgl", 4, two(0xF048, 0x0016), two(0xF1F8, 0xFFFF), "IiDsBw", mfloat },
2671: {"fdbgle", 4, two(0xF048, 0x0017), two(0xF1F8, 0xFFFF), "IiDsBw", mfloat },
2672: {"fdbgt", 4, two(0xF048, 0x0012), two(0xF1F8, 0xFFFF), "IiDsBw", mfloat },
2673: {"fdble", 4, two(0xF048, 0x0015), two(0xF1F8, 0xFFFF), "IiDsBw", mfloat },
2674: {"fdblt", 4, two(0xF048, 0x0014), two(0xF1F8, 0xFFFF), "IiDsBw", mfloat },
2675: {"fdbne", 4, two(0xF048, 0x000E), two(0xF1F8, 0xFFFF), "IiDsBw", mfloat },
2676: {"fdbnge", 4, two(0xF048, 0x001C), two(0xF1F8, 0xFFFF), "IiDsBw", mfloat },
2677: {"fdbngl", 4, two(0xF048, 0x0019), two(0xF1F8, 0xFFFF), "IiDsBw", mfloat },
2678: {"fdbngle", 4, two(0xF048, 0x0018), two(0xF1F8, 0xFFFF), "IiDsBw", mfloat },
2679: {"fdbngt", 4, two(0xF048, 0x001D), two(0xF1F8, 0xFFFF), "IiDsBw", mfloat },
2680: {"fdbnle", 4, two(0xF048, 0x001A), two(0xF1F8, 0xFFFF), "IiDsBw", mfloat },
2681: {"fdbnlt", 4, two(0xF048, 0x001B), two(0xF1F8, 0xFFFF), "IiDsBw", mfloat },
2682: {"fdboge", 4, two(0xF048, 0x0003), two(0xF1F8, 0xFFFF), "IiDsBw", mfloat },
2683: {"fdbogl", 4, two(0xF048, 0x0006), two(0xF1F8, 0xFFFF), "IiDsBw", mfloat },
2684: {"fdbogt", 4, two(0xF048, 0x0002), two(0xF1F8, 0xFFFF), "IiDsBw", mfloat },
2685: {"fdbole", 4, two(0xF048, 0x0005), two(0xF1F8, 0xFFFF), "IiDsBw", mfloat },
2686: {"fdbolt", 4, two(0xF048, 0x0004), two(0xF1F8, 0xFFFF), "IiDsBw", mfloat },
2687: {"fdbor", 4, two(0xF048, 0x0007), two(0xF1F8, 0xFFFF), "IiDsBw", mfloat },
2688: {"fdbseq", 4, two(0xF048, 0x0011), two(0xF1F8, 0xFFFF), "IiDsBw", mfloat },
2689: {"fdbsf", 4, two(0xF048, 0x0010), two(0xF1F8, 0xFFFF), "IiDsBw", mfloat },
2690: {"fdbsne", 4, two(0xF048, 0x001E), two(0xF1F8, 0xFFFF), "IiDsBw", mfloat },
2691: {"fdbst", 4, two(0xF048, 0x001F), two(0xF1F8, 0xFFFF), "IiDsBw", mfloat },
2692: {"fdbt", 4, two(0xF048, 0x000F), two(0xF1F8, 0xFFFF), "IiDsBw", mfloat },
2693: {"fdbueq", 4, two(0xF048, 0x0009), two(0xF1F8, 0xFFFF), "IiDsBw", mfloat },
2694: {"fdbuge", 4, two(0xF048, 0x000B), two(0xF1F8, 0xFFFF), "IiDsBw", mfloat },
2695: {"fdbugt", 4, two(0xF048, 0x000A), two(0xF1F8, 0xFFFF), "IiDsBw", mfloat },
2696: {"fdbule", 4, two(0xF048, 0x000D), two(0xF1F8, 0xFFFF), "IiDsBw", mfloat },
2697: {"fdbult", 4, two(0xF048, 0x000C), two(0xF1F8, 0xFFFF), "IiDsBw", mfloat },
2698: {"fdbun", 4, two(0xF048, 0x0008), two(0xF1F8, 0xFFFF), "IiDsBw", mfloat },
2699:
2700: {"fdivb", 4, two(0xF000, 0x5820), two(0xF1C0, 0xFC7F), "Ii;bF7", mfloat },
2701: {"fdivb", 4, two(0xF000, 0x5820), two(0xF1C0, 0xFC7F), "IibsF7", cfloat },
2702: {"fdivd", 4, two(0xF000, 0x0020), two(0xF1C0, 0xE07F), "IiF8F7", cfloat },
2703: {"fdivd", 4, two(0xF000, 0x5420), two(0xF1C0, 0xFC7F), "Ii;FF7", mfloat },
2704: {"fdivd", 4, two(0xF000, 0x5420), two(0xF1C0, 0xFC7F), "IiwsF7", cfloat },
2705: {"fdivl", 4, two(0xF000, 0x4020), two(0xF1C0, 0xFC7F), "Ii;lF7", mfloat },
2706: {"fdivl", 4, two(0xF000, 0x4020), two(0xF1C0, 0xFC7F), "IibsF7", cfloat },
2707: {"fdivp", 4, two(0xF000, 0x4C20), two(0xF1C0, 0xFC7F), "Ii;pF7", mfloat },
2708: {"fdivs", 4, two(0xF000, 0x4420), two(0xF1C0, 0xFC7F), "Ii;fF7", mfloat },
2709: {"fdivs", 4, two(0xF000, 0x4420), two(0xF1C0, 0xFC7F), "IibsF7", cfloat },
2710: {"fdivw", 4, two(0xF000, 0x5020), two(0xF1C0, 0xFC7F), "Ii;wF7", mfloat },
2711: {"fdivw", 4, two(0xF000, 0x5020), two(0xF1C0, 0xFC7F), "IibsF7", cfloat },
2712: {"fdivx", 4, two(0xF000, 0x0020), two(0xF1C0, 0xE07F), "IiF8F7", mfloat },
2713: {"fdivx", 4, two(0xF000, 0x4820), two(0xF1C0, 0xFC7F), "Ii;xF7", mfloat },
2714:
2715: {"fsdivb", 4, two(0xF000, 0x5860), two(0xF1C0, 0xFC7F), "Ii;bF7", m68040up },
2716: {"fsdivb", 4, two(0xF000, 0x5860), two(0xF1C0, 0xFC7F), "IibsF7", cfloat },
2717: {"fsdivd", 4, two(0xF000, 0x0060), two(0xF1C0, 0xE07F), "IiF8F7", cfloat },
2718: {"fsdivd", 4, two(0xF000, 0x5460), two(0xF1C0, 0xFC7F), "Ii;FF7", m68040up },
2719: {"fsdivd", 4, two(0xF000, 0x5460), two(0xF1C0, 0xFC7F), "IiwsF7", cfloat },
2720: {"fsdivl", 4, two(0xF000, 0x4060), two(0xF1C0, 0xFC7F), "Ii;lF7", m68040up },
2721: {"fsdivl", 4, two(0xF000, 0x4060), two(0xF1C0, 0xFC7F), "IibsF7", cfloat },
2722: {"fsdivp", 4, two(0xF000, 0x4C60), two(0xF1C0, 0xFC7F), "Ii;pF7", m68040up },
2723: {"fsdivs", 4, two(0xF000, 0x4460), two(0xF1C0, 0xFC7F), "Ii;fF7", m68040up },
2724: {"fsdivs", 4, two(0xF000, 0x4460), two(0xF1C0, 0xFC7F), "IibsF7", cfloat },
2725: {"fsdivw", 4, two(0xF000, 0x5060), two(0xF1C0, 0xFC7F), "Ii;wF7", m68040up },
2726: {"fsdivw", 4, two(0xF000, 0x5060), two(0xF1C0, 0xFC7F), "IibsF7", cfloat },
2727: {"fsdivx", 4, two(0xF000, 0x0060), two(0xF1C0, 0xE07F), "IiF8F7", m68040up },
2728: {"fsdivx", 4, two(0xF000, 0x4860), two(0xF1C0, 0xFC7F), "Ii;xF7", m68040up },
2729:
2730: {"fddivb", 4, two(0xF000, 0x5864), two(0xF1C0, 0xFC7F), "Ii;bF7", m68040up },
2731: {"fddivb", 4, two(0xF000, 0x5864), two(0xF1C0, 0xFC7F), "IibsF7", cfloat },
2732: {"fddivd", 4, two(0xF000, 0x0064), two(0xF1C0, 0xE07F), "IiF8F7", cfloat },
2733: {"fddivd", 4, two(0xF000, 0x5464), two(0xF1C0, 0xFC7F), "Ii;FF7", m68040up },
2734: {"fddivd", 4, two(0xF000, 0x5464), two(0xF1C0, 0xFC7F), "IiwsF7", cfloat },
2735: {"fddivl", 4, two(0xF000, 0x4064), two(0xF1C0, 0xFC7F), "Ii;lF7", m68040up },
2736: {"fddivl", 4, two(0xF000, 0x4064), two(0xF1C0, 0xFC7F), "IibsF7", cfloat },
2737: {"fddivp", 4, two(0xF000, 0x4C64), two(0xF1C0, 0xFC7F), "Ii;pF7", m68040up },
2738: {"fddivs", 4, two(0xF000, 0x4464), two(0xF1C0, 0xFC7F), "Ii;fF7", m68040up },
2739: {"fddivs", 4, two(0xF000, 0x4464), two(0xF1C0, 0xFC7F), "IibsF7", cfloat },
2740: {"fddivw", 4, two(0xF000, 0x5064), two(0xF1C0, 0xFC7F), "Ii;wF7", m68040up },
2741: {"fddivw", 4, two(0xF000, 0x5064), two(0xF1C0, 0xFC7F), "IibsF7", cfloat },
2742: {"fddivx", 4, two(0xF000, 0x0064), two(0xF1C0, 0xE07F), "IiF8F7", m68040up },
2743: {"fddivx", 4, two(0xF000, 0x4864), two(0xF1C0, 0xFC7F), "Ii;xF7", m68040up },
2744:
2745: {"fetoxb", 4, two(0xF000, 0x5810), two(0xF1C0, 0xFC7F), "Ii;bF7", mfloat },
2746: {"fetoxd", 4, two(0xF000, 0x5410), two(0xF1C0, 0xFC7F), "Ii;FF7", mfloat },
2747: {"fetoxl", 4, two(0xF000, 0x4010), two(0xF1C0, 0xFC7F), "Ii;lF7", mfloat },
2748: {"fetoxp", 4, two(0xF000, 0x4C10), two(0xF1C0, 0xFC7F), "Ii;pF7", mfloat },
2749: {"fetoxs", 4, two(0xF000, 0x4410), two(0xF1C0, 0xFC7F), "Ii;fF7", mfloat },
2750: {"fetoxw", 4, two(0xF000, 0x5010), two(0xF1C0, 0xFC7F), "Ii;wF7", mfloat },
2751: {"fetoxx", 4, two(0xF000, 0x0010), two(0xF1C0, 0xE07F), "IiF8F7", mfloat },
2752: {"fetoxx", 4, two(0xF000, 0x4810), two(0xF1C0, 0xFC7F), "Ii;xF7", mfloat },
2753: {"fetoxx", 4, two(0xF000, 0x0010), two(0xF1C0, 0xE07F), "IiFt", mfloat },
2754:
2755: {"fetoxm1b", 4, two(0xF000, 0x5808), two(0xF1C0, 0xFC7F), "Ii;bF7", mfloat },
2756: {"fetoxm1d", 4, two(0xF000, 0x5408), two(0xF1C0, 0xFC7F), "Ii;FF7", mfloat },
2757: {"fetoxm1l", 4, two(0xF000, 0x4008), two(0xF1C0, 0xFC7F), "Ii;lF7", mfloat },
2758: {"fetoxm1p", 4, two(0xF000, 0x4C08), two(0xF1C0, 0xFC7F), "Ii;pF7", mfloat },
2759: {"fetoxm1s", 4, two(0xF000, 0x4408), two(0xF1C0, 0xFC7F), "Ii;fF7", mfloat },
2760: {"fetoxm1w", 4, two(0xF000, 0x5008), two(0xF1C0, 0xFC7F), "Ii;wF7", mfloat },
2761: {"fetoxm1x", 4, two(0xF000, 0x0008), two(0xF1C0, 0xE07F), "IiF8F7", mfloat },
2762: {"fetoxm1x", 4, two(0xF000, 0x4808), two(0xF1C0, 0xFC7F), "Ii;xF7", mfloat },
2763: {"fetoxm1x", 4, two(0xF000, 0x0008), two(0xF1C0, 0xE07F), "IiFt", mfloat },
2764:
2765: {"fgetexpb", 4, two(0xF000, 0x581E), two(0xF1C0, 0xFC7F), "Ii;bF7", mfloat },
2766: {"fgetexpd", 4, two(0xF000, 0x541E), two(0xF1C0, 0xFC7F), "Ii;FF7", mfloat },
2767: {"fgetexpl", 4, two(0xF000, 0x401E), two(0xF1C0, 0xFC7F), "Ii;lF7", mfloat },
2768: {"fgetexpp", 4, two(0xF000, 0x4C1E), two(0xF1C0, 0xFC7F), "Ii;pF7", mfloat },
2769: {"fgetexps", 4, two(0xF000, 0x441E), two(0xF1C0, 0xFC7F), "Ii;fF7", mfloat },
2770: {"fgetexpw", 4, two(0xF000, 0x501E), two(0xF1C0, 0xFC7F), "Ii;wF7", mfloat },
2771: {"fgetexpx", 4, two(0xF000, 0x001E), two(0xF1C0, 0xE07F), "IiF8F7", mfloat },
2772: {"fgetexpx", 4, two(0xF000, 0x481E), two(0xF1C0, 0xFC7F), "Ii;xF7", mfloat },
2773: {"fgetexpx", 4, two(0xF000, 0x001E), two(0xF1C0, 0xE07F), "IiFt", mfloat },
2774:
2775: {"fgetmanb", 4, two(0xF000, 0x581F), two(0xF1C0, 0xFC7F), "Ii;bF7", mfloat },
2776: {"fgetmand", 4, two(0xF000, 0x541F), two(0xF1C0, 0xFC7F), "Ii;FF7", mfloat },
2777: {"fgetmanl", 4, two(0xF000, 0x401F), two(0xF1C0, 0xFC7F), "Ii;lF7", mfloat },
2778: {"fgetmanp", 4, two(0xF000, 0x4C1F), two(0xF1C0, 0xFC7F), "Ii;pF7", mfloat },
2779: {"fgetmans", 4, two(0xF000, 0x441F), two(0xF1C0, 0xFC7F), "Ii;fF7", mfloat },
2780: {"fgetmanw", 4, two(0xF000, 0x501F), two(0xF1C0, 0xFC7F), "Ii;wF7", mfloat },
2781: {"fgetmanx", 4, two(0xF000, 0x001F), two(0xF1C0, 0xE07F), "IiF8F7", mfloat },
2782: {"fgetmanx", 4, two(0xF000, 0x481F), two(0xF1C0, 0xFC7F), "Ii;xF7", mfloat },
2783: {"fgetmanx", 4, two(0xF000, 0x001F), two(0xF1C0, 0xE07F), "IiFt", mfloat },
2784:
2785: {"fintb", 4, two(0xF000, 0x5801), two(0xF1C0, 0xFC7F), "Ii;bF7", mfloat },
2786: {"fintb", 4, two(0xF000, 0x5801), two(0xF1C0, 0xFC7F), "IibsF7", cfloat },
2787: {"fintd", 4, two(0xF000, 0x0001), two(0xF1C0, 0xE07F), "IiF8F7", cfloat },
2788: {"fintd", 4, two(0xF000, 0x0001), two(0xF1C0, 0xE07F), "IiFt", cfloat },
2789: {"fintd", 4, two(0xF000, 0x5401), two(0xF1C0, 0xFC7F), "Ii;FF7", mfloat },
2790: {"fintd", 4, two(0xF000, 0x5401), two(0xF1C0, 0xFC7F), "IiwsF7", cfloat },
2791: {"fintl", 4, two(0xF000, 0x4001), two(0xF1C0, 0xFC7F), "Ii;lF7", mfloat },
2792: {"fintl", 4, two(0xF000, 0x4001), two(0xF1C0, 0xFC7F), "IibsF7", cfloat },
2793: {"fintp", 4, two(0xF000, 0x4C01), two(0xF1C0, 0xFC7F), "Ii;pF7", mfloat },
2794: {"fints", 4, two(0xF000, 0x4401), two(0xF1C0, 0xFC7F), "Ii;fF7", mfloat },
2795: {"fints", 4, two(0xF000, 0x4401), two(0xF1C0, 0xFC7F), "IibsF7", cfloat },
2796: {"fintw", 4, two(0xF000, 0x5001), two(0xF1C0, 0xFC7F), "Ii;wF7", mfloat },
2797: {"fintw", 4, two(0xF000, 0x5001), two(0xF1C0, 0xFC7F), "IibsF7", cfloat },
2798: {"fintx", 4, two(0xF000, 0x0001), two(0xF1C0, 0xE07F), "IiF8F7", mfloat },
2799: {"fintx", 4, two(0xF000, 0x4801), two(0xF1C0, 0xFC7F), "Ii;xF7", mfloat },
2800: {"fintx", 4, two(0xF000, 0x0001), two(0xF1C0, 0xE07F), "IiFt", mfloat },
2801:
2802: {"fintrzb", 4, two(0xF000, 0x5803), two(0xF1C0, 0xFC7F), "Ii;bF7", mfloat },
2803: {"fintrzb", 4, two(0xF000, 0x5803), two(0xF1C0, 0xFC7F), "IibsF7", cfloat },
2804: {"fintrzd", 4, two(0xF000, 0x0003), two(0xF1C0, 0xE07F), "IiF8F7", cfloat },
2805: {"fintrzd", 4, two(0xF000, 0x0003), two(0xF1C0, 0xE07F), "IiFt", cfloat },
2806: {"fintrzd", 4, two(0xF000, 0x5403), two(0xF1C0, 0xFC7F), "Ii;FF7", mfloat },
2807: {"fintrzd", 4, two(0xF000, 0x5403), two(0xF1C0, 0xFC7F), "IiwsF7", cfloat },
2808: {"fintrzl", 4, two(0xF000, 0x4003), two(0xF1C0, 0xFC7F), "Ii;lF7", mfloat },
2809: {"fintrzl", 4, two(0xF000, 0x4003), two(0xF1C0, 0xFC7F), "IibsF7", cfloat },
2810: {"fintrzp", 4, two(0xF000, 0x4C03), two(0xF1C0, 0xFC7F), "Ii;pF7", mfloat },
2811: {"fintrzs", 4, two(0xF000, 0x4403), two(0xF1C0, 0xFC7F), "Ii;fF7", mfloat },
2812: {"fintrzs", 4, two(0xF000, 0x4403), two(0xF1C0, 0xFC7F), "IibsF7", cfloat },
2813: {"fintrzw", 4, two(0xF000, 0x5003), two(0xF1C0, 0xFC7F), "Ii;wF7", mfloat },
2814: {"fintrzw", 4, two(0xF000, 0x5003), two(0xF1C0, 0xFC7F), "IibsF7", cfloat },
2815: {"fintrzx", 4, two(0xF000, 0x0003), two(0xF1C0, 0xE07F), "IiF8F7", mfloat },
2816: {"fintrzx", 4, two(0xF000, 0x4803), two(0xF1C0, 0xFC7F), "Ii;xF7", mfloat },
2817: {"fintrzx", 4, two(0xF000, 0x0003), two(0xF1C0, 0xE07F), "IiFt", mfloat },
2818:
2819: {"flog10b", 4, two(0xF000, 0x5815), two(0xF1C0, 0xFC7F), "Ii;bF7", mfloat },
2820: {"flog10d", 4, two(0xF000, 0x5415), two(0xF1C0, 0xFC7F), "Ii;FF7", mfloat },
2821: {"flog10l", 4, two(0xF000, 0x4015), two(0xF1C0, 0xFC7F), "Ii;lF7", mfloat },
2822: {"flog10p", 4, two(0xF000, 0x4C15), two(0xF1C0, 0xFC7F), "Ii;pF7", mfloat },
2823: {"flog10s", 4, two(0xF000, 0x4415), two(0xF1C0, 0xFC7F), "Ii;fF7", mfloat },
2824: {"flog10w", 4, two(0xF000, 0x5015), two(0xF1C0, 0xFC7F), "Ii;wF7", mfloat },
2825: {"flog10x", 4, two(0xF000, 0x0015), two(0xF1C0, 0xE07F), "IiF8F7", mfloat },
2826: {"flog10x", 4, two(0xF000, 0x4815), two(0xF1C0, 0xFC7F), "Ii;xF7", mfloat },
2827: {"flog10x", 4, two(0xF000, 0x0015), two(0xF1C0, 0xE07F), "IiFt", mfloat },
2828:
2829: {"flog2b", 4, two(0xF000, 0x5816), two(0xF1C0, 0xFC7F), "Ii;bF7", mfloat },
2830: {"flog2d", 4, two(0xF000, 0x5416), two(0xF1C0, 0xFC7F), "Ii;FF7", mfloat },
2831: {"flog2l", 4, two(0xF000, 0x4016), two(0xF1C0, 0xFC7F), "Ii;lF7", mfloat },
2832: {"flog2p", 4, two(0xF000, 0x4C16), two(0xF1C0, 0xFC7F), "Ii;pF7", mfloat },
2833: {"flog2s", 4, two(0xF000, 0x4416), two(0xF1C0, 0xFC7F), "Ii;fF7", mfloat },
2834: {"flog2w", 4, two(0xF000, 0x5016), two(0xF1C0, 0xFC7F), "Ii;wF7", mfloat },
2835: {"flog2x", 4, two(0xF000, 0x0016), two(0xF1C0, 0xE07F), "IiF8F7", mfloat },
2836: {"flog2x", 4, two(0xF000, 0x4816), two(0xF1C0, 0xFC7F), "Ii;xF7", mfloat },
2837: {"flog2x", 4, two(0xF000, 0x0016), two(0xF1C0, 0xE07F), "IiFt", mfloat },
2838:
2839: {"flognb", 4, two(0xF000, 0x5814), two(0xF1C0, 0xFC7F), "Ii;bF7", mfloat },
2840: {"flognd", 4, two(0xF000, 0x5414), two(0xF1C0, 0xFC7F), "Ii;FF7", mfloat },
2841: {"flognl", 4, two(0xF000, 0x4014), two(0xF1C0, 0xFC7F), "Ii;lF7", mfloat },
2842: {"flognp", 4, two(0xF000, 0x4C14), two(0xF1C0, 0xFC7F), "Ii;pF7", mfloat },
2843: {"flogns", 4, two(0xF000, 0x4414), two(0xF1C0, 0xFC7F), "Ii;fF7", mfloat },
2844: {"flognw", 4, two(0xF000, 0x5014), two(0xF1C0, 0xFC7F), "Ii;wF7", mfloat },
2845: {"flognx", 4, two(0xF000, 0x0014), two(0xF1C0, 0xE07F), "IiF8F7", mfloat },
2846: {"flognx", 4, two(0xF000, 0x4814), two(0xF1C0, 0xFC7F), "Ii;xF7", mfloat },
2847: {"flognx", 4, two(0xF000, 0x0014), two(0xF1C0, 0xE07F), "IiFt", mfloat },
2848:
2849: {"flognp1b", 4, two(0xF000, 0x5806), two(0xF1C0, 0xFC7F), "Ii;bF7", mfloat },
2850: {"flognp1d", 4, two(0xF000, 0x5406), two(0xF1C0, 0xFC7F), "Ii;FF7", mfloat },
2851: {"flognp1l", 4, two(0xF000, 0x4006), two(0xF1C0, 0xFC7F), "Ii;lF7", mfloat },
2852: {"flognp1p", 4, two(0xF000, 0x4C06), two(0xF1C0, 0xFC7F), "Ii;pF7", mfloat },
2853: {"flognp1s", 4, two(0xF000, 0x4406), two(0xF1C0, 0xFC7F), "Ii;fF7", mfloat },
2854: {"flognp1w", 4, two(0xF000, 0x5006), two(0xF1C0, 0xFC7F), "Ii;wF7", mfloat },
2855: {"flognp1x", 4, two(0xF000, 0x0006), two(0xF1C0, 0xE07F), "IiF8F7", mfloat },
2856: {"flognp1x", 4, two(0xF000, 0x4806), two(0xF1C0, 0xFC7F), "Ii;xF7", mfloat },
2857: {"flognp1x", 4, two(0xF000, 0x0006), two(0xF1C0, 0xE07F), "IiFt", mfloat },
2858:
2859: {"fmodb", 4, two(0xF000, 0x5821), two(0xF1C0, 0xFC7F), "Ii;bF7", mfloat },
2860: {"fmodd", 4, two(0xF000, 0x5421), two(0xF1C0, 0xFC7F), "Ii;FF7", mfloat },
2861: {"fmodl", 4, two(0xF000, 0x4021), two(0xF1C0, 0xFC7F), "Ii;lF7", mfloat },
2862: {"fmodp", 4, two(0xF000, 0x4C21), two(0xF1C0, 0xFC7F), "Ii;pF7", mfloat },
2863: {"fmods", 4, two(0xF000, 0x4421), two(0xF1C0, 0xFC7F), "Ii;fF7", mfloat },
2864: {"fmodw", 4, two(0xF000, 0x5021), two(0xF1C0, 0xFC7F), "Ii;wF7", mfloat },
2865: {"fmodx", 4, two(0xF000, 0x0021), two(0xF1C0, 0xE07F), "IiF8F7", mfloat },
2866: {"fmodx", 4, two(0xF000, 0x4821), two(0xF1C0, 0xFC7F), "Ii;xF7", mfloat },
2867:
2868: {"fmoveb", 4, two(0xF000, 0x5800), two(0xF1C0, 0xFC7F), "IibsF7", cfloat },
2869: {"fmoveb", 4, two(0xF000, 0x7800), two(0xF1C0, 0xFC7F), "IiF7bs", cfloat },
2870: {"fmoveb", 4, two(0xF000, 0x5800), two(0xF1C0, 0xFC7F), "Ii;bF7", mfloat },
2871: {"fmoveb", 4, two(0xF000, 0x7800), two(0xF1C0, 0xFC7F), "IiF7$b", mfloat },
2872: {"fmoved", 4, two(0xF000, 0x5400), two(0xF1C0, 0xFC7F), "Ii;FF7", mfloat },
2873: {"fmoved", 4, two(0xF000, 0x7400), two(0xF1C0, 0xFC7F), "IiF7~F", mfloat },
2874: {"fmoved", 4, two(0xF000, 0x0000), two(0xF1C0, 0xE07F), "IiF8F7", cfloat },
2875: {"fmoved", 4, two(0xF000, 0x5400), two(0xF1C0, 0xFC7F), "IiwsF7", cfloat },
2876: {"fmoved", 4, two(0xF000, 0x7400), two(0xF1C0, 0xFC7F), "IiF7ws", cfloat },
2877: {"fmovel", 4, two(0xF000, 0x4000), two(0xF1C0, 0xFC7F), "Ii;lF7", mfloat },
2878: {"fmovel", 4, two(0xF000, 0x6000), two(0xF1C0, 0xFC7F), "IiF7$l", mfloat },
2879: /* FIXME: the next two variants should not permit moving an address
2880: register to anything but the floating point instruction register. */
2881: {"fmovel", 4, two(0xF000, 0xA000), two(0xF1C0, 0xE3FF), "Iis8%s", mfloat },
2882: {"fmovel", 4, two(0xF000, 0x8000), two(0xF1C0, 0xE3FF), "Ii*ls8", mfloat },
2883: {"fmovel", 4, two(0xF000, 0x4000), two(0xF1C0, 0xFC7F), "IibsF7", cfloat },
2884: {"fmovel", 4, two(0xF000, 0x6000), two(0xF1C0, 0xFC7F), "IiF7bs", cfloat },
2885: /* Move the FP control registers. */
2886: {"fmovel", 4, two(0xF000, 0xA000), two(0xF1C0, 0xE3FF), "Iis8ps", cfloat },
2887: {"fmovel", 4, two(0xF000, 0x8000), two(0xF1C0, 0xE3FF), "Iibss8", cfloat },
2888: {"fmovep", 4, two(0xF000, 0x4C00), two(0xF1C0, 0xFC7F), "Ii;pF7", mfloat },
2889: {"fmovep", 4, two(0xF000, 0x6C00), two(0xF1C0, 0xFC00), "IiF7~pkC", mfloat },
2890: {"fmovep", 4, two(0xF000, 0x7C00), two(0xF1C0, 0xFC0F), "IiF7~pDk", mfloat },
2891: {"fmoves", 4, two(0xF000, 0x4400), two(0xF1C0, 0xFC7F), "Ii;fF7", mfloat },
2892: {"fmoves", 4, two(0xF000, 0x6400), two(0xF1C0, 0xFC7F), "IiF7$f", mfloat },
2893: {"fmoves", 4, two(0xF000, 0x4400), two(0xF1C0, 0xFC7F), "IibsF7", cfloat },
2894: {"fmoves", 4, two(0xF000, 0x6400), two(0xF1C0, 0xFC7F), "IiF7qs", cfloat },
2895: {"fmovew", 4, two(0xF000, 0x5000), two(0xF1C0, 0xFC7F), "Ii;wF7", mfloat },
2896: {"fmovew", 4, two(0xF000, 0x7000), two(0xF1C0, 0xFC7F), "IiF7$w", mfloat },
2897: {"fmovew", 4, two(0xF000, 0x5000), two(0xF1C0, 0xFC7F), "IibsF7", cfloat },
2898: {"fmovew", 4, two(0xF000, 0x7000), two(0xF1C0, 0xFC7F), "IiF7qs", cfloat },
2899: {"fmovex", 4, two(0xF000, 0x0000), two(0xF1FF, 0xE07F), "IiF8F7", mfloat },
2900: {"fmovex", 4, two(0xF000, 0x4800), two(0xF1C0, 0xFC7F), "Ii;xF7", mfloat },
2901: {"fmovex", 4, two(0xF000, 0x6800), two(0xF1C0, 0xFC7F), "IiF7~x", mfloat },
2902:
2903: {"fsmoveb", 4, two(0xF000, 0x5840), two(0xF1C0, 0xFC7F), "Ii;bF7", m68040up },
2904: {"fsmoveb", 4, two(0xF000, 0x5840), two(0xF1C0, 0xFC7F), "IibsF7", cfloat },
2905: {"fsmoveb", 4, two(0xF000, 0x7840), two(0xF1C0, 0xFC7F), "IiF7qs", cfloat },
2906: {"fsmoved", 4, two(0xF000, 0x0040), two(0xF1C0, 0xE07F), "IiF8F7", cfloat },
2907: {"fsmoved", 4, two(0xF000, 0x5440), two(0xF1C0, 0xFC7F), "Ii;FF7", m68040up },
2908: {"fsmoved", 4, two(0xF000, 0x5440), two(0xF1C0, 0xFC7F), "IiwsF7", cfloat },
2909: {"fsmoved", 4, two(0xF000, 0x7440), two(0xF1C0, 0xFC7F), "IiF7ws", cfloat },
2910: {"fsmovel", 4, two(0xF000, 0x4040), two(0xF1C0, 0xFC7F), "Ii;lF7", m68040up },
2911: {"fsmovel", 4, two(0xF000, 0x4040), two(0xF1C0, 0xFC7F), "IibsF7", cfloat },
2912: {"fsmovel", 4, two(0xF000, 0x6040), two(0xF1C0, 0xFC7F), "IiF7qs", cfloat },
2913: {"fsmoves", 4, two(0xF000, 0x4440), two(0xF1C0, 0xFC7F), "Ii;fF7", m68040up },
2914: {"fsmoves", 4, two(0xF000, 0x4440), two(0xF1C0, 0xFC7F), "IibsF7", cfloat },
2915: {"fsmoves", 4, two(0xF000, 0x6440), two(0xF1C0, 0xFC7F), "IiF7qs", cfloat },
2916: {"fsmovew", 4, two(0xF000, 0x5040), two(0xF1C0, 0xFC7F), "Ii;wF7", m68040up },
2917: {"fsmovew", 4, two(0xF000, 0x5040), two(0xF1C0, 0xFC7F), "IibsF7", cfloat },
2918: {"fsmovew", 4, two(0xF000, 0x7040), two(0xF1C0, 0xFC7F), "IiF7qs", cfloat },
2919: {"fsmovex", 4, two(0xF000, 0x0040), two(0xF1C0, 0xE07F), "IiF8F7", m68040up },
2920: {"fsmovex", 4, two(0xF000, 0x4840), two(0xF1C0, 0xFC7F), "Ii;xF7", m68040up },
2921: {"fsmovep", 4, two(0xF000, 0x4C40), two(0xF1C0, 0xFC7F), "Ii;pF7", m68040up },
2922:
2923: {"fdmoveb", 4, two(0xF000, 0x5844), two(0xF1C0, 0xFC7F), "Ii;bF7", m68040up },
2924: {"fdmoveb", 4, two(0xF000, 0x5844), two(0xF1C0, 0xFC7F), "IibsF7", cfloat },
2925: {"fdmoveb", 4, two(0xF000, 0x7844), two(0xF1C0, 0xFC7F), "IiF7qs", cfloat },
2926: {"fdmoved", 4, two(0xF000, 0x0044), two(0xF1C0, 0xE07F), "IiF8F7", cfloat },
2927: {"fdmoved", 4, two(0xF000, 0x5444), two(0xF1C0, 0xFC7F), "Ii;FF7", m68040up },
2928: {"fdmoved", 4, two(0xF000, 0x5444), two(0xF1C0, 0xFC7F), "IiwsF7", cfloat },
2929: {"fdmoved", 4, two(0xF000, 0x7444), two(0xF1C0, 0xFC7F), "IiF7qs", cfloat },
2930: {"fdmovel", 4, two(0xF000, 0x4044), two(0xF1C0, 0xFC7F), "Ii;lF7", m68040up },
2931: {"fdmovel", 4, two(0xF000, 0x4044), two(0xF1C0, 0xFC7F), "IibsF7", cfloat },
2932: {"fdmovel", 4, two(0xF000, 0x6044), two(0xF1C0, 0xFC7F), "IiF7qs", cfloat },
2933: {"fdmoves", 4, two(0xF000, 0x4444), two(0xF1C0, 0xFC7F), "Ii;fF7", m68040up },
2934: {"fdmoves", 4, two(0xF000, 0x4444), two(0xF1C0, 0xFC7F), "IibsF7", cfloat },
2935: {"fdmoves", 4, two(0xF000, 0x6444), two(0xF1C0, 0xFC7F), "IiF7qs", cfloat },
2936: {"fdmovew", 4, two(0xF000, 0x5044), two(0xF1C0, 0xFC7F), "Ii;wF7", m68040up },
2937: {"fdmovew", 4, two(0xF000, 0x5044), two(0xF1C0, 0xFC7F), "IibsF7", cfloat },
2938: {"fdmovew", 4, two(0xF000, 0x7044), two(0xF1C0, 0xFC7F), "IiF7qs", cfloat },
2939: {"fdmovex", 4, two(0xF000, 0x0044), two(0xF1C0, 0xE07F), "IiF8F7", m68040up },
2940: {"fdmovex", 4, two(0xF000, 0x4844), two(0xF1C0, 0xFC7F), "Ii;xF7", m68040up },
2941: {"fdmovep", 4, two(0xF000, 0x4C44), two(0xF1C0, 0xFC7F), "Ii;pF7", m68040up },
2942:
2943: {"fmovecrx", 4, two(0xF000, 0x5C00), two(0xF1FF, 0xFC00), "Ii#CF7", mfloat },
2944:
2945: {"fmovemd", 4, two(0xF000, 0xD000), two(0xFFC0, 0xFF00), "Iizsl3", cfloat },
2946: {"fmovemd", 4, two(0xF000, 0xD000), two(0xFFC0, 0xFF00), "Iizs#3", cfloat },
2947: {"fmovemd", 4, two(0xF000, 0xF000), two(0xFFC0, 0xFF00), "Ii#3ys", cfloat },
2948: {"fmovemd", 4, two(0xF000, 0xF000), two(0xFFC0, 0xFF00), "Iil3ys", cfloat },
2949:
2950: {"fmovemx", 4, two(0xF000, 0xF800), two(0xF1C0, 0xFF8F), "IiDk&s", mfloat },
2951: {"fmovemx", 4, two(0xF020, 0xE800), two(0xF1F8, 0xFF8F), "IiDk-s", mfloat },
2952: {"fmovemx", 4, two(0xF000, 0xD800), two(0xF1C0, 0xFF8F), "Ii&sDk", mfloat },
2953: {"fmovemx", 4, two(0xF018, 0xD800), two(0xF1F8, 0xFF8F), "Ii+sDk", mfloat },
2954: {"fmovemx", 4, two(0xF000, 0xF000), two(0xF1C0, 0xFF00), "Idl3&s", mfloat },
2955: {"fmovemx", 4, two(0xF000, 0xF000), two(0xF1C0, 0xFF00), "Id#3&s", mfloat },
2956: {"fmovemx", 4, two(0xF000, 0xD000), two(0xF1C0, 0xFF00), "Id&sl3", mfloat },
2957: {"fmovemx", 4, two(0xF000, 0xD000), two(0xF1C0, 0xFF00), "Id&s#3", mfloat },
2958: {"fmovemx", 4, two(0xF020, 0xE000), two(0xF1F8, 0xFF00), "IdL3-s", mfloat },
2959: {"fmovemx", 4, two(0xF020, 0xE000), two(0xF1F8, 0xFF00), "Id#3-s", mfloat },
2960: {"fmovemx", 4, two(0xF018, 0xD000), two(0xF1F8, 0xFF00), "Id+sl3", mfloat },
2961: {"fmovemx", 4, two(0xF018, 0xD000), two(0xF1F8, 0xFF00), "Id+s#3", mfloat },
2962:
2963: {"fmoveml", 4, two(0xF000, 0xA000), two(0xF1C0, 0xE3FF), "Iis8%s", mfloat },
2964: {"fmoveml", 4, two(0xF000, 0xA000), two(0xF1C0, 0xE3FF), "IiL8~s", mfloat },
2965: /* FIXME: In the next instruction, we should only permit %dn if the
2966: target is a single register. We should only permit %an if the
2967: target is a single %fpiar. */
2968: {"fmoveml", 4, two(0xF000, 0x8000), two(0xF1C0, 0xE3FF), "Ii*lL8", mfloat },
2969:
2970: {"fmovem", 4, two(0xF000, 0xD000), two(0xFFC0, 0xFF00), "IizsL3", cfloat },
2971: {"fmovem", 4, two(0xF000, 0xD000), two(0xFFC0, 0xFF00), "Iizs#3", cfloat },
2972: {"fmovem", 4, two(0xF000, 0xF000), two(0xFFC0, 0xFF00), "Ii#3ys", cfloat },
2973: {"fmovem", 4, two(0xF000, 0xF000), two(0xFFC0, 0xFF00), "IiL3ys", cfloat },
2974:
2975: {"fmovem", 4, two(0xF020, 0xE000), two(0xF1F8, 0xFF00), "IdL3-s", mfloat },
2976: {"fmovem", 4, two(0xF000, 0xF000), two(0xF1C0, 0xFF00), "Idl3&s", mfloat },
2977: {"fmovem", 4, two(0xF018, 0xD000), two(0xF1F8, 0xFF00), "Id+sl3", mfloat },
2978: {"fmovem", 4, two(0xF000, 0xD000), two(0xF1C0, 0xFF00), "Id&sl3", mfloat },
2979: {"fmovem", 4, two(0xF020, 0xE000), two(0xF1F8, 0xFF00), "Id#3-s", mfloat },
2980: {"fmovem", 4, two(0xF020, 0xE800), two(0xF1F8, 0xFF8F), "IiDk-s", mfloat },
2981: {"fmovem", 4, two(0xF000, 0xF000), two(0xF1C0, 0xFF00), "Id#3&s", mfloat },
2982: {"fmovem", 4, two(0xF000, 0xF800), two(0xF1C0, 0xFF8F), "IiDk&s", mfloat },
2983: {"fmovem", 4, two(0xF018, 0xD000), two(0xF1F8, 0xFF00), "Id+s#3", mfloat },
2984: {"fmovem", 4, two(0xF018, 0xD800), two(0xF1F8, 0xFF8F), "Ii+sDk", mfloat },
2985: {"fmovem", 4, two(0xF000, 0xD000), two(0xF1C0, 0xFF00), "Id&s#3", mfloat },
2986: {"fmovem", 4, two(0xF000, 0xD800), two(0xF1C0, 0xFF8F), "Ii&sDk", mfloat },
2987: {"fmovem", 4, two(0xF000, 0xA000), two(0xF1C0, 0xE3FF), "Iis8%s", mfloat },
2988: {"fmovem", 4, two(0xF000, 0x8000), two(0xF1C0, 0xE3FF), "Ii*ss8", mfloat },
2989: {"fmovem", 4, two(0xF000, 0xA000), two(0xF1C0, 0xE3FF), "IiL8~s", mfloat },
2990: {"fmovem", 4, two(0xF000, 0x8000), two(0xF2C0, 0xE3FF), "Ii*sL8", mfloat },
2991:
2992: {"fmulb", 4, two(0xF000, 0x5823), two(0xF1C0, 0xFC7F), "Ii;bF7", mfloat },
2993: {"fmulb", 4, two(0xF000, 0x5823), two(0xF1C0, 0xFC7F), "IibsF7", cfloat },
2994: {"fmuld", 4, two(0xF000, 0x0023), two(0xF1C0, 0xE07F), "IiF8F7", cfloat },
2995: {"fmuld", 4, two(0xF000, 0x5423), two(0xF1C0, 0xFC7F), "Ii;FF7", mfloat },
2996: {"fmuld", 4, two(0xF000, 0x5423), two(0xF1C0, 0xFC7F), "IiwsF7", cfloat },
2997: {"fmull", 4, two(0xF000, 0x4023), two(0xF1C0, 0xFC7F), "Ii;lF7", mfloat },
2998: {"fmull", 4, two(0xF000, 0x4023), two(0xF1C0, 0xFC7F), "IibsF7", cfloat },
2999: {"fmulp", 4, two(0xF000, 0x4C23), two(0xF1C0, 0xFC7F), "Ii;pF7", mfloat },
3000: {"fmuls", 4, two(0xF000, 0x4423), two(0xF1C0, 0xFC7F), "Ii;fF7", mfloat },
3001: {"fmuls", 4, two(0xF000, 0x4423), two(0xF1C0, 0xFC7F), "IibsF7", cfloat },
3002: {"fmulw", 4, two(0xF000, 0x5023), two(0xF1C0, 0xFC7F), "Ii;wF7", mfloat },
3003: {"fmulw", 4, two(0xF000, 0x5023), two(0xF1C0, 0xFC7F), "IibsF7", cfloat },
3004: {"fmulx", 4, two(0xF000, 0x0023), two(0xF1C0, 0xE07F), "IiF8F7", mfloat },
3005: {"fmulx", 4, two(0xF000, 0x4823), two(0xF1C0, 0xFC7F), "Ii;xF7", mfloat },
3006:
3007: {"fsmulb", 4, two(0xF000, 0x5863), two(0xF1C0, 0xFC7F), "Ii;bF7", m68040up },
3008: {"fsmulb", 4, two(0xF000, 0x5863), two(0xF1C0, 0xFC7F), "IibsF7", cfloat },
3009: {"fsmuld", 4, two(0xF000, 0x0063), two(0xF1C0, 0xE07F), "IiF8F7", cfloat },
3010: {"fsmuld", 4, two(0xF000, 0x5463), two(0xF1C0, 0xFC7F), "Ii;FF7", m68040up },
3011: {"fsmuld", 4, two(0xF000, 0x5463), two(0xF1C0, 0xFC7F), "IiwsF7", cfloat },
3012: {"fsmull", 4, two(0xF000, 0x4063), two(0xF1C0, 0xFC7F), "Ii;lF7", m68040up },
3013: {"fsmull", 4, two(0xF000, 0x4063), two(0xF1C0, 0xFC7F), "IibsF7", cfloat },
3014: {"fsmulp", 4, two(0xF000, 0x4C63), two(0xF1C0, 0xFC7F), "Ii;pF7", m68040up },
3015: {"fsmuls", 4, two(0xF000, 0x4463), two(0xF1C0, 0xFC7F), "Ii;fF7", m68040up },
3016: {"fsmuls", 4, two(0xF000, 0x4463), two(0xF1C0, 0xFC7F), "IibsF7", cfloat },
3017: {"fsmulw", 4, two(0xF000, 0x5063), two(0xF1C0, 0xFC7F), "Ii;wF7", m68040up },
3018: {"fsmulw", 4, two(0xF000, 0x5063), two(0xF1C0, 0xFC7F), "IibsF7", cfloat },
3019: {"fsmulx", 4, two(0xF000, 0x0063), two(0xF1C0, 0xE07F), "IiF8F7", m68040up },
3020: {"fsmulx", 4, two(0xF000, 0x4863), two(0xF1C0, 0xFC7F), "Ii;xF7", m68040up },
3021:
3022: {"fdmulb", 4, two(0xF000, 0x5867), two(0xF1C0, 0xFC7F), "Ii;bF7", m68040up },
3023: {"fdmulb", 4, two(0xF000, 0x5867), two(0xF1C0, 0xFC7F), "IibsF7", cfloat },
3024: {"fdmuld", 4, two(0xF000, 0x0067), two(0xF1C0, 0xE07F), "IiF8F7", cfloat },
3025: {"fdmuld", 4, two(0xF000, 0x5467), two(0xF1C0, 0xFC7F), "Ii;FF7", m68040up },
3026: {"fdmuld", 4, two(0xF000, 0x5467), two(0xF1C0, 0xFC7F), "IiwsF7", cfloat },
3027: {"fdmull", 4, two(0xF000, 0x4067), two(0xF1C0, 0xFC7F), "Ii;lF7", m68040up },
3028: {"fdmull", 4, two(0xF000, 0x4067), two(0xF1C0, 0xFC7F), "IibsF7", cfloat },
3029: {"fdmulp", 4, two(0xF000, 0x4C67), two(0xF1C0, 0xFC7F), "Ii;pF7", m68040up },
3030: {"fdmuls", 4, two(0xF000, 0x4467), two(0xF1C0, 0xFC7F), "Ii;fF7", m68040up },
3031: {"fdmuls", 4, two(0xF000, 0x4467), two(0xF1C0, 0xFC7F), "IibsF7", cfloat },
3032: {"fdmulw", 4, two(0xF000, 0x5067), two(0xF1C0, 0xFC7F), "Ii;wF7", m68040up },
3033: {"fdmulw", 4, two(0xF000, 0x5067), two(0xF1C0, 0xFC7F), "IibsF7", cfloat },
3034: {"fdmulx", 4, two(0xF000, 0x0067), two(0xF1C0, 0xE07F), "IiF8F7", m68040up },
3035: {"fdmulx", 4, two(0xF000, 0x4867), two(0xF1C0, 0xFC7F), "Ii;xF7", m68040up },
3036:
3037: {"fnegb", 4, two(0xF000, 0x581A), two(0xF1C0, 0xFC7F), "Ii;bF7", mfloat },
3038: {"fnegb", 4, two(0xF000, 0x581A), two(0xF1C0, 0xFC7F), "IibsF7", cfloat },
3039: {"fnegd", 4, two(0xF000, 0x001A), two(0xF1C0, 0xE07F), "IiF8F7", cfloat },
3040: {"fnegd", 4, two(0xF000, 0x001A), two(0xF1C0, 0xE07F), "IiFt", cfloat },
3041: {"fnegd", 4, two(0xF000, 0x541A), two(0xF1C0, 0xFC7F), "Ii;FF7", mfloat },
3042: {"fnegd", 4, two(0xF000, 0x541A), two(0xF1C0, 0xFC7F), "IiwsF7", cfloat },
3043: {"fnegl", 4, two(0xF000, 0x401A), two(0xF1C0, 0xFC7F), "Ii;lF7", mfloat },
3044: {"fnegl", 4, two(0xF000, 0x401A), two(0xF1C0, 0xFC7F), "IibsF7", cfloat },
3045: {"fnegp", 4, two(0xF000, 0x4C1A), two(0xF1C0, 0xFC7F), "Ii;pF7", mfloat },
3046: {"fnegs", 4, two(0xF000, 0x441A), two(0xF1C0, 0xFC7F), "Ii;fF7", mfloat },
3047: {"fnegs", 4, two(0xF000, 0x441A), two(0xF1C0, 0xFC7F), "IibsF7", cfloat },
3048: {"fnegw", 4, two(0xF000, 0x501A), two(0xF1C0, 0xFC7F), "Ii;wF7", mfloat },
3049: {"fnegw", 4, two(0xF000, 0x501A), two(0xF1C0, 0xFC7F), "IibsF7", cfloat },
3050: {"fnegx", 4, two(0xF000, 0x001A), two(0xF1C0, 0xE07F), "IiF8F7", mfloat },
3051: {"fnegx", 4, two(0xF000, 0x481A), two(0xF1C0, 0xFC7F), "Ii;xF7", mfloat },
3052: {"fnegx", 4, two(0xF000, 0x001A), two(0xF1C0, 0xE07F), "IiFt", mfloat },
3053:
3054: {"fsnegb", 4, two(0xF000, 0x585A), two(0xF1C0, 0xFC7F), "Ii;bF7", m68040up },
3055: {"fsnegb", 4, two(0xF000, 0x585A), two(0xF1C0, 0xFC7F), "IibsF7", cfloat },
3056: {"fsnegd", 4, two(0xF000, 0x005A), two(0xF1C0, 0xE07F), "IiF8F7", cfloat },
3057: {"fsnegd", 4, two(0xF000, 0x005A), two(0xF1C0, 0xE07F), "IiFt", cfloat },
3058: {"fsnegd", 4, two(0xF000, 0x545A), two(0xF1C0, 0xFC7F), "Ii;FF7", m68040up },
3059: {"fsnegd", 4, two(0xF000, 0x545A), two(0xF1C0, 0xFC7F), "IiwsF7", cfloat },
3060: {"fsnegl", 4, two(0xF000, 0x405A), two(0xF1C0, 0xFC7F), "Ii;lF7", m68040up },
3061: {"fsnegl", 4, two(0xF000, 0x405A), two(0xF1C0, 0xFC7F), "IibsF7", cfloat },
3062: {"fsnegp", 4, two(0xF000, 0x4C5A), two(0xF1C0, 0xFC7F), "Ii;pF7", m68040up },
3063: {"fsnegs", 4, two(0xF000, 0x445A), two(0xF1C0, 0xFC7F), "Ii;fF7", m68040up },
3064: {"fsnegs", 4, two(0xF000, 0x445A), two(0xF1C0, 0xFC7F), "IibsF7", cfloat },
3065: {"fsnegw", 4, two(0xF000, 0x505A), two(0xF1C0, 0xFC7F), "Ii;wF7", m68040up },
3066: {"fsnegw", 4, two(0xF000, 0x505A), two(0xF1C0, 0xFC7F), "IibsF7", cfloat },
3067: {"fsnegx", 4, two(0xF000, 0x005A), two(0xF1C0, 0xE07F), "IiF8F7", m68040up },
3068: {"fsnegx", 4, two(0xF000, 0x485A), two(0xF1C0, 0xFC7F), "Ii;xF7", m68040up },
3069: {"fsnegx", 4, two(0xF000, 0x005A), two(0xF1C0, 0xE07F), "IiFt", m68040up },
3070:
3071: {"fdnegb", 4, two(0xF000, 0x585E), two(0xF1C0, 0xFC7F), "Ii;bF7", m68040up },
3072: {"fdnegb", 4, two(0xF000, 0x585E), two(0xF1C0, 0xFC7F), "IibsF7", cfloat },
3073: {"fdnegd", 4, two(0xF000, 0x005E), two(0xF1C0, 0xE07F), "IiF8F7", cfloat },
3074: {"fdnegd", 4, two(0xF000, 0x005E), two(0xF1C0, 0xE07F), "IiFt", cfloat },
3075: {"fdnegd", 4, two(0xF000, 0x545E), two(0xF1C0, 0xFC7F), "Ii;FF7", m68040up },
3076: {"fdnegd", 4, two(0xF000, 0x545E), two(0xF1C0, 0xFC7F), "IiwsF7", cfloat },
3077: {"fdnegl", 4, two(0xF000, 0x405E), two(0xF1C0, 0xFC7F), "Ii;lF7", m68040up },
3078: {"fdnegl", 4, two(0xF000, 0x405E), two(0xF1C0, 0xFC7F), "IibsF7", cfloat },
3079: {"fdnegp", 4, two(0xF000, 0x4C5E), two(0xF1C0, 0xFC7F), "Ii;pF7", m68040up },
3080: {"fdnegs", 4, two(0xF000, 0x445E), two(0xF1C0, 0xFC7F), "Ii;fF7", m68040up },
3081: {"fdnegs", 4, two(0xF000, 0x445E), two(0xF1C0, 0xFC7F), "IibsF7", cfloat },
3082: {"fdnegw", 4, two(0xF000, 0x505E), two(0xF1C0, 0xFC7F), "Ii;wF7", m68040up },
3083: {"fdnegw", 4, two(0xF000, 0x505E), two(0xF1C0, 0xFC7F), "IibsF7", cfloat },
3084: {"fdnegx", 4, two(0xF000, 0x005E), two(0xF1C0, 0xE07F), "IiF8F7", m68040up },
3085: {"fdnegx", 4, two(0xF000, 0x485E), two(0xF1C0, 0xFC7F), "Ii;xF7", m68040up },
3086: {"fdnegx", 4, two(0xF000, 0x005E), two(0xF1C0, 0xE07F), "IiFt", m68040up },
3087:
3088: {"fnop", 4, two(0xF280, 0x0000), two(0xFFFF, 0xFFFF), "Ii", mfloat | cfloat },
3089:
3090: {"fremb", 4, two(0xF000, 0x5825), two(0xF1C0, 0xFC7F), "Ii;bF7", mfloat },
3091: {"fremd", 4, two(0xF000, 0x5425), two(0xF1C0, 0xFC7F), "Ii;FF7", mfloat },
3092: {"freml", 4, two(0xF000, 0x4025), two(0xF1C0, 0xFC7F), "Ii;lF7", mfloat },
3093: {"fremp", 4, two(0xF000, 0x4C25), two(0xF1C0, 0xFC7F), "Ii;pF7", mfloat },
3094: {"frems", 4, two(0xF000, 0x4425), two(0xF1C0, 0xFC7F), "Ii;fF7", mfloat },
3095: {"fremw", 4, two(0xF000, 0x5025), two(0xF1C0, 0xFC7F), "Ii;wF7", mfloat },
3096: {"fremx", 4, two(0xF000, 0x0025), two(0xF1C0, 0xE07F), "IiF8F7", mfloat },
3097: {"fremx", 4, two(0xF000, 0x4825), two(0xF1C0, 0xFC7F), "Ii;xF7", mfloat },
3098:
3099: {"frestore", 2, one(0xF140), one(0xF1C0), "Id<s", mfloat },
3100: {"frestore", 2, one(0xF140), one(0xF1C0), "Idys", cfloat },
3101:
3102: {"fsave", 2, one(0xF100), one(0xF1C0), "Id>s", mfloat },
3103: {"fsave", 2, one(0xF100), one(0xF1C0), "Idzs", cfloat },
3104:
3105: {"fscaleb", 4, two(0xF000, 0x5826), two(0xF1C0, 0xFC7F), "Ii;bF7", mfloat },
3106: {"fscaled", 4, two(0xF000, 0x5426), two(0xF1C0, 0xFC7F), "Ii;FF7", mfloat },
3107: {"fscalel", 4, two(0xF000, 0x4026), two(0xF1C0, 0xFC7F), "Ii;lF7", mfloat },
3108: {"fscalep", 4, two(0xF000, 0x4C26), two(0xF1C0, 0xFC7F), "Ii;pF7", mfloat },
3109: {"fscales", 4, two(0xF000, 0x4426), two(0xF1C0, 0xFC7F), "Ii;fF7", mfloat },
3110: {"fscalew", 4, two(0xF000, 0x5026), two(0xF1C0, 0xFC7F), "Ii;wF7", mfloat },
3111: {"fscalex", 4, two(0xF000, 0x0026), two(0xF1C0, 0xE07F), "IiF8F7", mfloat },
3112: {"fscalex", 4, two(0xF000, 0x4826), two(0xF1C0, 0xFC7F), "Ii;xF7", mfloat },
3113:
3114: /* $ is necessary to prevent the assembler from using PC-relative.
3115: If @ were used, "label: fseq label" could produce "ftrapeq", 2,
3116: because "label" became "pc@label". */
3117: {"fseq", 4, two(0xF040, 0x0001), two(0xF1C0, 0xFFFF), "Ii$s", mfloat },
3118: {"fsf", 4, two(0xF040, 0x0000), two(0xF1C0, 0xFFFF), "Ii$s", mfloat },
3119: {"fsge", 4, two(0xF040, 0x0013), two(0xF1C0, 0xFFFF), "Ii$s", mfloat },
3120: {"fsgl", 4, two(0xF040, 0x0016), two(0xF1C0, 0xFFFF), "Ii$s", mfloat },
3121: {"fsgle", 4, two(0xF040, 0x0017), two(0xF1C0, 0xFFFF), "Ii$s", mfloat },
3122: {"fsgt", 4, two(0xF040, 0x0012), two(0xF1C0, 0xFFFF), "Ii$s", mfloat },
3123: {"fsle", 4, two(0xF040, 0x0015), two(0xF1C0, 0xFFFF), "Ii$s", mfloat },
3124: {"fslt", 4, two(0xF040, 0x0014), two(0xF1C0, 0xFFFF), "Ii$s", mfloat },
3125: {"fsne", 4, two(0xF040, 0x000E), two(0xF1C0, 0xFFFF), "Ii$s", mfloat },
3126: {"fsnge", 4, two(0xF040, 0x001C), two(0xF1C0, 0xFFFF), "Ii$s", mfloat },
3127: {"fsngl", 4, two(0xF040, 0x0019), two(0xF1C0, 0xFFFF), "Ii$s", mfloat },
3128: {"fsngle", 4, two(0xF040, 0x0018), two(0xF1C0, 0xFFFF), "Ii$s", mfloat },
3129: {"fsngt", 4, two(0xF040, 0x001D), two(0xF1C0, 0xFFFF), "Ii$s", mfloat },
3130: {"fsnle", 4, two(0xF040, 0x001A), two(0xF1C0, 0xFFFF), "Ii$s", mfloat },
3131: {"fsnlt", 4, two(0xF040, 0x001B), two(0xF1C0, 0xFFFF), "Ii$s", mfloat },
3132: {"fsoge", 4, two(0xF040, 0x0003), two(0xF1C0, 0xFFFF), "Ii$s", mfloat },
3133: {"fsogl", 4, two(0xF040, 0x0006), two(0xF1C0, 0xFFFF), "Ii$s", mfloat },
3134: {"fsogt", 4, two(0xF040, 0x0002), two(0xF1C0, 0xFFFF), "Ii$s", mfloat },
3135: {"fsole", 4, two(0xF040, 0x0005), two(0xF1C0, 0xFFFF), "Ii$s", mfloat },
3136: {"fsolt", 4, two(0xF040, 0x0004), two(0xF1C0, 0xFFFF), "Ii$s", mfloat },
3137: {"fsor", 4, two(0xF040, 0x0007), two(0xF1C0, 0xFFFF), "Ii$s", mfloat },
3138: {"fsseq", 4, two(0xF040, 0x0011), two(0xF1C0, 0xFFFF), "Ii$s", mfloat },
3139: {"fssf", 4, two(0xF040, 0x0010), two(0xF1C0, 0xFFFF), "Ii$s", mfloat },
3140: {"fssne", 4, two(0xF040, 0x001E), two(0xF1C0, 0xFFFF), "Ii$s", mfloat },
3141: {"fsst", 4, two(0xF040, 0x001F), two(0xF1C0, 0xFFFF), "Ii$s", mfloat },
3142: {"fst", 4, two(0xF040, 0x000F), two(0xF1C0, 0xFFFF), "Ii$s", mfloat },
3143: {"fsueq", 4, two(0xF040, 0x0009), two(0xF1C0, 0xFFFF), "Ii$s", mfloat },
3144: {"fsuge", 4, two(0xF040, 0x000B), two(0xF1C0, 0xFFFF), "Ii$s", mfloat },
3145: {"fsugt", 4, two(0xF040, 0x000A), two(0xF1C0, 0xFFFF), "Ii$s", mfloat },
3146: {"fsule", 4, two(0xF040, 0x000D), two(0xF1C0, 0xFFFF), "Ii$s", mfloat },
3147: {"fsult", 4, two(0xF040, 0x000C), two(0xF1C0, 0xFFFF), "Ii$s", mfloat },
3148: {"fsun", 4, two(0xF040, 0x0008), two(0xF1C0, 0xFFFF), "Ii$s", mfloat },
3149:
3150: {"fsgldivb", 4, two(0xF000, 0x5824), two(0xF1C0, 0xFC7F), "Ii;bF7", mfloat },
3151: {"fsgldivd", 4, two(0xF000, 0x5424), two(0xF1C0, 0xFC7F), "Ii;FF7", mfloat },
3152: {"fsgldivl", 4, two(0xF000, 0x4024), two(0xF1C0, 0xFC7F), "Ii;lF7", mfloat },
3153: {"fsgldivp", 4, two(0xF000, 0x4C24), two(0xF1C0, 0xFC7F), "Ii;pF7", mfloat },
3154: {"fsgldivs", 4, two(0xF000, 0x4424), two(0xF1C0, 0xFC7F), "Ii;fF7", mfloat },
3155: {"fsgldivw", 4, two(0xF000, 0x5024), two(0xF1C0, 0xFC7F), "Ii;wF7", mfloat },
3156: {"fsgldivx", 4, two(0xF000, 0x0024), two(0xF1C0, 0xE07F), "IiF8F7", mfloat },
3157: {"fsgldivx", 4, two(0xF000, 0x4824), two(0xF1C0, 0xFC7F), "Ii;xF7", mfloat },
3158: {"fsgldivx", 4, two(0xF000, 0x0024), two(0xF1C0, 0xE07F), "IiFt", mfloat },
3159:
3160: {"fsglmulb", 4, two(0xF000, 0x5827), two(0xF1C0, 0xFC7F), "Ii;bF7", mfloat },
3161: {"fsglmuld", 4, two(0xF000, 0x5427), two(0xF1C0, 0xFC7F), "Ii;FF7", mfloat },
3162: {"fsglmull", 4, two(0xF000, 0x4027), two(0xF1C0, 0xFC7F), "Ii;lF7", mfloat },
3163: {"fsglmulp", 4, two(0xF000, 0x4C27), two(0xF1C0, 0xFC7F), "Ii;pF7", mfloat },
3164: {"fsglmuls", 4, two(0xF000, 0x4427), two(0xF1C0, 0xFC7F), "Ii;fF7", mfloat },
3165: {"fsglmulw", 4, two(0xF000, 0x5027), two(0xF1C0, 0xFC7F), "Ii;wF7", mfloat },
3166: {"fsglmulx", 4, two(0xF000, 0x0027), two(0xF1C0, 0xE07F), "IiF8F7", mfloat },
3167: {"fsglmulx", 4, two(0xF000, 0x4827), two(0xF1C0, 0xFC7F), "Ii;xF7", mfloat },
3168: {"fsglmulx", 4, two(0xF000, 0x0027), two(0xF1C0, 0xE07F), "IiFt", mfloat },
3169:
3170: {"fsinb", 4, two(0xF000, 0x580E), two(0xF1C0, 0xFC7F), "Ii;bF7", mfloat },
3171: {"fsind", 4, two(0xF000, 0x540E), two(0xF1C0, 0xFC7F), "Ii;FF7", mfloat },
3172: {"fsinl", 4, two(0xF000, 0x400E), two(0xF1C0, 0xFC7F), "Ii;lF7", mfloat },
3173: {"fsinp", 4, two(0xF000, 0x4C0E), two(0xF1C0, 0xFC7F), "Ii;pF7", mfloat },
3174: {"fsins", 4, two(0xF000, 0x440E), two(0xF1C0, 0xFC7F), "Ii;fF7", mfloat },
3175: {"fsinw", 4, two(0xF000, 0x500E), two(0xF1C0, 0xFC7F), "Ii;wF7", mfloat },
3176: {"fsinx", 4, two(0xF000, 0x000E), two(0xF1C0, 0xE07F), "IiF8F7", mfloat },
3177: {"fsinx", 4, two(0xF000, 0x480E), two(0xF1C0, 0xFC7F), "Ii;xF7", mfloat },
3178: {"fsinx", 4, two(0xF000, 0x000E), two(0xF1C0, 0xE07F), "IiFt", mfloat },
3179:
3180: {"fsincosb", 4, two(0xF000, 0x5830), two(0xF1C0, 0xFC78), "Ii;bF3F7", mfloat },
3181: {"fsincosd", 4, two(0xF000, 0x5430), two(0xF1C0, 0xFC78), "Ii;FF3F7", mfloat },
3182: {"fsincosl", 4, two(0xF000, 0x4030), two(0xF1C0, 0xFC78), "Ii;lF3F7", mfloat },
3183: {"fsincosp", 4, two(0xF000, 0x4C30), two(0xF1C0, 0xFC78), "Ii;pF3F7", mfloat },
3184: {"fsincoss", 4, two(0xF000, 0x4430), two(0xF1C0, 0xFC78), "Ii;fF3F7", mfloat },
3185: {"fsincosw", 4, two(0xF000, 0x5030), two(0xF1C0, 0xFC78), "Ii;wF3F7", mfloat },
3186: {"fsincosx", 4, two(0xF000, 0x0030), two(0xF1C0, 0xE078), "IiF8F3F7", mfloat },
3187: {"fsincosx", 4, two(0xF000, 0x4830), two(0xF1C0, 0xFC78), "Ii;xF3F7", mfloat },
3188:
3189: {"fsinhb", 4, two(0xF000, 0x5802), two(0xF1C0, 0xFC7F), "Ii;bF7", mfloat },
3190: {"fsinhd", 4, two(0xF000, 0x5402), two(0xF1C0, 0xFC7F), "Ii;FF7", mfloat },
3191: {"fsinhl", 4, two(0xF000, 0x4002), two(0xF1C0, 0xFC7F), "Ii;lF7", mfloat },
3192: {"fsinhp", 4, two(0xF000, 0x4C02), two(0xF1C0, 0xFC7F), "Ii;pF7", mfloat },
3193: {"fsinhs", 4, two(0xF000, 0x4402), two(0xF1C0, 0xFC7F), "Ii;fF7", mfloat },
3194: {"fsinhw", 4, two(0xF000, 0x5002), two(0xF1C0, 0xFC7F), "Ii;wF7", mfloat },
3195: {"fsinhx", 4, two(0xF000, 0x0002), two(0xF1C0, 0xE07F), "IiF8F7", mfloat },
3196: {"fsinhx", 4, two(0xF000, 0x4802), two(0xF1C0, 0xFC7F), "Ii;xF7", mfloat },
3197: {"fsinhx", 4, two(0xF000, 0x0002), two(0xF1C0, 0xE07F), "IiFt", mfloat },
3198:
3199: {"fsqrtb", 4, two(0xF000, 0x5804), two(0xF1C0, 0xFC7F), "Ii;bF7", mfloat },
3200: {"fsqrtb", 4, two(0xF000, 0x5804), two(0xF1C0, 0xFC7F), "IibsF7", cfloat },
3201: {"fsqrtd", 4, two(0xF000, 0x0004), two(0xF1C0, 0xE07F), "IiF8F7", cfloat },
3202: {"fsqrtd", 4, two(0xF000, 0x0004), two(0xF1C0, 0xE07F), "IiFt", cfloat },
3203: {"fsqrtd", 4, two(0xF000, 0x5404), two(0xF1C0, 0xFC7F), "Ii;FF7", mfloat },
3204: {"fsqrtd", 4, two(0xF000, 0x5404), two(0xF1C0, 0xFC7F), "IiwsF7", cfloat },
3205: {"fsqrtl", 4, two(0xF000, 0x4004), two(0xF1C0, 0xFC7F), "Ii;lF7", mfloat },
3206: {"fsqrtl", 4, two(0xF000, 0x4004), two(0xF1C0, 0xFC7F), "IibsF7", cfloat },
3207: {"fsqrtp", 4, two(0xF000, 0x4C04), two(0xF1C0, 0xFC7F), "Ii;pF7", mfloat },
3208: {"fsqrts", 4, two(0xF000, 0x4404), two(0xF1C0, 0xFC7F), "Ii;fF7", mfloat },
3209: {"fsqrts", 4, two(0xF000, 0x4404), two(0xF1C0, 0xFC7F), "IibsF7", cfloat },
3210: {"fsqrtw", 4, two(0xF000, 0x5004), two(0xF1C0, 0xFC7F), "Ii;wF7", mfloat },
3211: {"fsqrtw", 4, two(0xF000, 0x5004), two(0xF1C0, 0xFC7F), "IibsF7", cfloat },
3212: {"fsqrtx", 4, two(0xF000, 0x0004), two(0xF1C0, 0xE07F), "IiF8F7", mfloat },
3213: {"fsqrtx", 4, two(0xF000, 0x4804), two(0xF1C0, 0xFC7F), "Ii;xF7", mfloat },
3214: {"fsqrtx", 4, two(0xF000, 0x0004), two(0xF1C0, 0xE07F), "IiFt", mfloat },
3215:
3216: {"fssqrtb", 4, two(0xF000, 0x5841), two(0xF1C0, 0xFC7F), "Ii;bF7", m68040up },
3217: {"fssqrtb", 4, two(0xF000, 0x5841), two(0xF1C0, 0xFC7F), "IibsF7", cfloat },
3218: {"fssqrtd", 4, two(0xF000, 0x0041), two(0xF1C0, 0xE07F), "IiF8F7", cfloat },
3219: {"fssqrtd", 4, two(0xF000, 0x0041), two(0xF1C0, 0xE07F), "IiFt", cfloat },
3220: {"fssqrtd", 4, two(0xF000, 0x5441), two(0xF1C0, 0xFC7F), "Ii;FF7", m68040up },
3221: {"fssqrtd", 4, two(0xF000, 0x5441), two(0xF1C0, 0xFC7F), "IiwsF7", cfloat },
3222: {"fssqrtl", 4, two(0xF000, 0x4041), two(0xF1C0, 0xFC7F), "Ii;lF7", m68040up },
3223: {"fssqrtl", 4, two(0xF000, 0x4041), two(0xF1C0, 0xFC7F), "IibsF7", cfloat },
3224: {"fssqrtp", 4, two(0xF000, 0x4C41), two(0xF1C0, 0xFC7F), "Ii;pF7", m68040up },
3225: {"fssqrts", 4, two(0xF000, 0x4441), two(0xF1C0, 0xFC7F), "Ii;fF7", m68040up },
3226: {"fssqrts", 4, two(0xF000, 0x4441), two(0xF1C0, 0xFC7F), "IibsF7", cfloat },
3227: {"fssqrtw", 4, two(0xF000, 0x5041), two(0xF1C0, 0xFC7F), "Ii;wF7", m68040up },
3228: {"fssqrtw", 4, two(0xF000, 0x5041), two(0xF1C0, 0xFC7F), "IibsF7", cfloat },
3229: {"fssqrtx", 4, two(0xF000, 0x0041), two(0xF1C0, 0xE07F), "IiF8F7", m68040up },
3230: {"fssqrtx", 4, two(0xF000, 0x4841), two(0xF1C0, 0xFC7F), "Ii;xF7", m68040up },
3231: {"fssqrtx", 4, two(0xF000, 0x0041), two(0xF1C0, 0xE07F), "IiFt", m68040up },
3232:
3233: {"fdsqrtb", 4, two(0xF000, 0x5845), two(0xF1C0, 0xFC7F), "Ii;bF7", m68040up },
3234: {"fdsqrtb", 4, two(0xF000, 0x5845), two(0xF1C0, 0xFC7F), "IibsF7", cfloat },
3235: {"fdsqrtd", 4, two(0xF000, 0x0045), two(0xF1C0, 0xE07F), "IiF8F7", cfloat },
3236: {"fdsqrtd", 4, two(0xF000, 0x0045), two(0xF1C0, 0xE07F), "IiFt", cfloat },
3237: {"fdsqrtd", 4, two(0xF000, 0x5445), two(0xF1C0, 0xFC7F), "Ii;FF7", m68040up },
3238: {"fdsqrtl", 4, two(0xF000, 0x4045), two(0xF1C0, 0xFC7F), "Ii;lF7", m68040up },
3239: {"fdsqrtl", 4, two(0xF000, 0x4045), two(0xF1C0, 0xFC7F), "IibsF7", cfloat },
3240: {"fdsqrtp", 4, two(0xF000, 0x4C45), two(0xF1C0, 0xFC7F), "Ii;pF7", m68040up },
3241: {"fdsqrts", 4, two(0xF000, 0x4445), two(0xF1C0, 0xFC7F), "Ii;fF7", m68040up },
3242: {"fdsqrts", 4, two(0xF000, 0x4445), two(0xF1C0, 0xFC7F), "IibsF7", cfloat },
3243: {"fdsqrtw", 4, two(0xF000, 0x5045), two(0xF1C0, 0xFC7F), "Ii;wF7", m68040up },
3244: {"fdsqrtw", 4, two(0xF000, 0x5045), two(0xF1C0, 0xFC7F), "IibsF7", cfloat },
3245: {"fdsqrtx", 4, two(0xF000, 0x0045), two(0xF1C0, 0xE07F), "IiF8F7", m68040up },
3246: {"fdsqrtx", 4, two(0xF000, 0x4845), two(0xF1C0, 0xFC7F), "Ii;xF7", m68040up },
3247: {"fdsqrtx", 4, two(0xF000, 0x0045), two(0xF1C0, 0xE07F), "IiFt", m68040up },
3248:
3249: {"fsubb", 4, two(0xF000, 0x5828), two(0xF1C0, 0xFC7F), "Ii;bF7", mfloat },
3250: {"fsubb", 4, two(0xF000, 0x5828), two(0xF1C0, 0xFC7F), "IibsF7", cfloat },
3251: {"fsubd", 4, two(0xF000, 0x0028), two(0xF1C0, 0xE07F), "IiF8F7", cfloat },
3252: {"fsubd", 4, two(0xF000, 0x5428), two(0xF1C0, 0xFC7F), "Ii;FF7", mfloat },
3253: {"fsubd", 4, two(0xF000, 0x5428), two(0xF1C0, 0xFC7F), "IiwsF7", cfloat },
3254: {"fsubl", 4, two(0xF000, 0x4028), two(0xF1C0, 0xFC7F), "Ii;lF7", mfloat },
3255: {"fsubl", 4, two(0xF000, 0x4028), two(0xF1C0, 0xFC7F), "IibsF7", cfloat },
3256: {"fsubp", 4, two(0xF000, 0x4C28), two(0xF1C0, 0xFC7F), "Ii;pF7", mfloat },
3257: {"fsubs", 4, two(0xF000, 0x4428), two(0xF1C0, 0xFC7F), "Ii;fF7", mfloat },
3258: {"fsubs", 4, two(0xF000, 0x4428), two(0xF1C0, 0xFC7F), "IibsF7", cfloat },
3259: {"fsubw", 4, two(0xF000, 0x5028), two(0xF1C0, 0xFC7F), "Ii;wF7", mfloat },
3260: {"fsubw", 4, two(0xF000, 0x5028), two(0xF1C0, 0xFC7F), "IibsF7", cfloat },
3261: {"fsubx", 4, two(0xF000, 0x0028), two(0xF1C0, 0xE07F), "IiF8F7", mfloat },
3262: {"fsubx", 4, two(0xF000, 0x4828), two(0xF1C0, 0xFC7F), "Ii;xF7", mfloat },
3263: {"fsubx", 4, two(0xF000, 0x0028), two(0xF1C0, 0xE07F), "IiFt", mfloat },
3264:
3265: {"fssubb", 4, two(0xF000, 0x5828), two(0xF1C0, 0xFC7F), "IibsF7", cfloat },
3266: {"fssubb", 4, two(0xF000, 0x5868), two(0xF1C0, 0xFC7F), "Ii;bF7", m68040up },
3267: {"fssubd", 4, two(0xF000, 0x0068), two(0xF1C0, 0xE07F), "IiF8F7", cfloat },
3268: {"fssubd", 4, two(0xF000, 0x5468), two(0xF1C0, 0xFC7F), "Ii;FF7", m68040up },
3269: {"fssubd", 4, two(0xF000, 0x5468), two(0xF1C0, 0xFC7F), "IiwsF7", cfloat },
3270: {"fssubl", 4, two(0xF000, 0x4068), two(0xF1C0, 0xFC7F), "Ii;lF7", m68040up },
3271: {"fssubl", 4, two(0xF000, 0x4068), two(0xF1C0, 0xFC7F), "IibsF7", cfloat },
3272: {"fssubp", 4, two(0xF000, 0x4C68), two(0xF1C0, 0xFC7F), "Ii;pF7", m68040up },
3273: {"fssubs", 4, two(0xF000, 0x4468), two(0xF1C0, 0xFC7F), "Ii;fF7", m68040up },
3274: {"fssubs", 4, two(0xF000, 0x4468), two(0xF1C0, 0xFC7F), "IibsF7", cfloat },
3275: {"fssubw", 4, two(0xF000, 0x5068), two(0xF1C0, 0xFC7F), "Ii;wF7", m68040up },
3276: {"fssubw", 4, two(0xF000, 0x5068), two(0xF1C0, 0xFC7F), "IibsF7", cfloat },
3277: {"fssubx", 4, two(0xF000, 0x0068), two(0xF1C0, 0xE07F), "IiF8F7", m68040up },
3278: {"fssubx", 4, two(0xF000, 0x4868), two(0xF1C0, 0xFC7F), "Ii;xF7", m68040up },
3279: {"fssubx", 4, two(0xF000, 0x0068), two(0xF1C0, 0xE07F), "IiFt", m68040up },
3280:
3281: {"fdsubb", 4, two(0xF000, 0x586A), two(0xF1C0, 0xFC7F), "IibsF7", cfloat },
3282: {"fdsubb", 4, two(0xF000, 0x586c), two(0xF1C0, 0xFC7F), "Ii;bF7", m68040up },
3283: {"fdsubd", 4, two(0xF000, 0x006A), two(0xF1C0, 0xE07F), "IiF8F7", cfloat },
3284: {"fdsubd", 4, two(0xF000, 0x546A), two(0xF1C0, 0xFC7F), "IiwsF7", cfloat },
3285: {"fdsubd", 4, two(0xF000, 0x546c), two(0xF1C0, 0xFC7F), "Ii;FF7", m68040up },
3286: {"fdsubl", 4, two(0xF000, 0x406A), two(0xF1C0, 0xFC7F), "IibsF7", cfloat },
3287: {"fdsubl", 4, two(0xF000, 0x406c), two(0xF1C0, 0xFC7F), "Ii;lF7", m68040up },
3288: {"fdsubp", 4, two(0xF000, 0x4C6c), two(0xF1C0, 0xFC7F), "Ii;pF7", m68040up },
3289: {"fdsubs", 4, two(0xF000, 0x446A), two(0xF1C0, 0xFC7F), "IibsF7", cfloat },
3290: {"fdsubs", 4, two(0xF000, 0x446c), two(0xF1C0, 0xFC7F), "Ii;fF7", m68040up },
3291: {"fdsubw", 4, two(0xF000, 0x506A), two(0xF1C0, 0xFC7F), "IibsF7", cfloat },
3292: {"fdsubw", 4, two(0xF000, 0x506c), two(0xF1C0, 0xFC7F), "Ii;wF7", m68040up },
3293: {"fdsubx", 4, two(0xF000, 0x006c), two(0xF1C0, 0xE07F), "IiF8F7", m68040up },
3294: {"fdsubx", 4, two(0xF000, 0x486c), two(0xF1C0, 0xFC7F), "Ii;xF7", m68040up },
3295: {"fdsubx", 4, two(0xF000, 0x006c), two(0xF1C0, 0xE07F), "IiFt", m68040up },
3296:
3297: {"ftanb", 4, two(0xF000, 0x580F), two(0xF1C0, 0xFC7F), "Ii;bF7", mfloat },
3298: {"ftand", 4, two(0xF000, 0x540F), two(0xF1C0, 0xFC7F), "Ii;FF7", mfloat },
3299: {"ftanl", 4, two(0xF000, 0x400F), two(0xF1C0, 0xFC7F), "Ii;lF7", mfloat },
3300: {"ftanp", 4, two(0xF000, 0x4C0F), two(0xF1C0, 0xFC7F), "Ii;pF7", mfloat },
3301: {"ftans", 4, two(0xF000, 0x440F), two(0xF1C0, 0xFC7F), "Ii;fF7", mfloat },
3302: {"ftanw", 4, two(0xF000, 0x500F), two(0xF1C0, 0xFC7F), "Ii;wF7", mfloat },
3303: {"ftanx", 4, two(0xF000, 0x000F), two(0xF1C0, 0xE07F), "IiF8F7", mfloat },
3304: {"ftanx", 4, two(0xF000, 0x480F), two(0xF1C0, 0xFC7F), "Ii;xF7", mfloat },
3305: {"ftanx", 4, two(0xF000, 0x000F), two(0xF1C0, 0xE07F), "IiFt", mfloat },
3306:
3307: {"ftanhb", 4, two(0xF000, 0x5809), two(0xF1C0, 0xFC7F), "Ii;bF7", mfloat },
3308: {"ftanhd", 4, two(0xF000, 0x5409), two(0xF1C0, 0xFC7F), "Ii;FF7", mfloat },
3309: {"ftanhl", 4, two(0xF000, 0x4009), two(0xF1C0, 0xFC7F), "Ii;lF7", mfloat },
3310: {"ftanhp", 4, two(0xF000, 0x4C09), two(0xF1C0, 0xFC7F), "Ii;pF7", mfloat },
3311: {"ftanhs", 4, two(0xF000, 0x4409), two(0xF1C0, 0xFC7F), "Ii;fF7", mfloat },
3312: {"ftanhw", 4, two(0xF000, 0x5009), two(0xF1C0, 0xFC7F), "Ii;wF7", mfloat },
3313: {"ftanhx", 4, two(0xF000, 0x0009), two(0xF1C0, 0xE07F), "IiF8F7", mfloat },
3314: {"ftanhx", 4, two(0xF000, 0x4809), two(0xF1C0, 0xFC7F), "Ii;xF7", mfloat },
3315: {"ftanhx", 4, two(0xF000, 0x0009), two(0xF1C0, 0xE07F), "IiFt", mfloat },
3316:
3317: {"ftentoxb", 4, two(0xF000, 0x5812), two(0xF1C0, 0xFC7F), "Ii;bF7", mfloat },
3318: {"ftentoxd", 4, two(0xF000, 0x5412), two(0xF1C0, 0xFC7F), "Ii;FF7", mfloat },
3319: {"ftentoxl", 4, two(0xF000, 0x4012), two(0xF1C0, 0xFC7F), "Ii;lF7", mfloat },
3320: {"ftentoxp", 4, two(0xF000, 0x4C12), two(0xF1C0, 0xFC7F), "Ii;pF7", mfloat },
3321: {"ftentoxs", 4, two(0xF000, 0x4412), two(0xF1C0, 0xFC7F), "Ii;fF7", mfloat },
3322: {"ftentoxw", 4, two(0xF000, 0x5012), two(0xF1C0, 0xFC7F), "Ii;wF7", mfloat },
3323: {"ftentoxx", 4, two(0xF000, 0x0012), two(0xF1C0, 0xE07F), "IiF8F7", mfloat },
3324: {"ftentoxx", 4, two(0xF000, 0x4812), two(0xF1C0, 0xFC7F), "Ii;xF7", mfloat },
3325: {"ftentoxx", 4, two(0xF000, 0x0012), two(0xF1C0, 0xE07F), "IiFt", mfloat },
3326:
3327: {"ftrapeq", 4, two(0xF07C, 0x0001), two(0xF1FF, 0xFFFF), "Ii", mfloat },
3328: {"ftrapf", 4, two(0xF07C, 0x0000), two(0xF1FF, 0xFFFF), "Ii", mfloat },
3329: {"ftrapge", 4, two(0xF07C, 0x0013), two(0xF1FF, 0xFFFF), "Ii", mfloat },
3330: {"ftrapgl", 4, two(0xF07C, 0x0016), two(0xF1FF, 0xFFFF), "Ii", mfloat },
3331: {"ftrapgle", 4, two(0xF07C, 0x0017), two(0xF1FF, 0xFFFF), "Ii", mfloat },
3332: {"ftrapgt", 4, two(0xF07C, 0x0012), two(0xF1FF, 0xFFFF), "Ii", mfloat },
3333: {"ftraple", 4, two(0xF07C, 0x0015), two(0xF1FF, 0xFFFF), "Ii", mfloat },
3334: {"ftraplt", 4, two(0xF07C, 0x0014), two(0xF1FF, 0xFFFF), "Ii", mfloat },
3335: {"ftrapne", 4, two(0xF07C, 0x000E), two(0xF1FF, 0xFFFF), "Ii", mfloat },
3336: {"ftrapnge", 4, two(0xF07C, 0x001C), two(0xF1FF, 0xFFFF), "Ii", mfloat },
3337: {"ftrapngl", 4, two(0xF07C, 0x0019), two(0xF1FF, 0xFFFF), "Ii", mfloat },
3338: {"ftrapngle", 4,two(0xF07C, 0x0018), two(0xF1FF, 0xFFFF), "Ii", mfloat },
3339: {"ftrapngt", 4, two(0xF07C, 0x001D), two(0xF1FF, 0xFFFF), "Ii", mfloat },
3340: {"ftrapnle", 4, two(0xF07C, 0x001A), two(0xF1FF, 0xFFFF), "Ii", mfloat },
3341: {"ftrapnlt", 4, two(0xF07C, 0x001B), two(0xF1FF, 0xFFFF), "Ii", mfloat },
3342: {"ftrapoge", 4, two(0xF07C, 0x0003), two(0xF1FF, 0xFFFF), "Ii", mfloat },
3343: {"ftrapogl", 4, two(0xF07C, 0x0006), two(0xF1FF, 0xFFFF), "Ii", mfloat },
3344: {"ftrapogt", 4, two(0xF07C, 0x0002), two(0xF1FF, 0xFFFF), "Ii", mfloat },
3345: {"ftrapole", 4, two(0xF07C, 0x0005), two(0xF1FF, 0xFFFF), "Ii", mfloat },
3346: {"ftrapolt", 4, two(0xF07C, 0x0004), two(0xF1FF, 0xFFFF), "Ii", mfloat },
3347: {"ftrapor", 4, two(0xF07C, 0x0007), two(0xF1FF, 0xFFFF), "Ii", mfloat },
3348: {"ftrapseq", 4, two(0xF07C, 0x0011), two(0xF1FF, 0xFFFF), "Ii", mfloat },
3349: {"ftrapsf", 4, two(0xF07C, 0x0010), two(0xF1FF, 0xFFFF), "Ii", mfloat },
3350: {"ftrapsne", 4, two(0xF07C, 0x001E), two(0xF1FF, 0xFFFF), "Ii", mfloat },
3351: {"ftrapst", 4, two(0xF07C, 0x001F), two(0xF1FF, 0xFFFF), "Ii", mfloat },
3352: {"ftrapt", 4, two(0xF07C, 0x000F), two(0xF1FF, 0xFFFF), "Ii", mfloat },
3353: {"ftrapueq", 4, two(0xF07C, 0x0009), two(0xF1FF, 0xFFFF), "Ii", mfloat },
3354: {"ftrapuge", 4, two(0xF07C, 0x000B), two(0xF1FF, 0xFFFF), "Ii", mfloat },
3355: {"ftrapugt", 4, two(0xF07C, 0x000A), two(0xF1FF, 0xFFFF), "Ii", mfloat },
3356: {"ftrapule", 4, two(0xF07C, 0x000D), two(0xF1FF, 0xFFFF), "Ii", mfloat },
3357: {"ftrapult", 4, two(0xF07C, 0x000C), two(0xF1FF, 0xFFFF), "Ii", mfloat },
3358: {"ftrapun", 4, two(0xF07C, 0x0008), two(0xF1FF, 0xFFFF), "Ii", mfloat },
3359:
3360: {"ftrapeqw", 4, two(0xF07A, 0x0001), two(0xF1FF, 0xFFFF), "Ii^w", mfloat },
3361: {"ftrapfw", 4, two(0xF07A, 0x0000), two(0xF1FF, 0xFFFF), "Ii^w", mfloat },
3362: {"ftrapgew", 4, two(0xF07A, 0x0013), two(0xF1FF, 0xFFFF), "Ii^w", mfloat },
3363: {"ftrapglw", 4, two(0xF07A, 0x0016), two(0xF1FF, 0xFFFF), "Ii^w", mfloat },
3364: {"ftrapglew", 4,two(0xF07A, 0x0017), two(0xF1FF, 0xFFFF), "Ii^w", mfloat },
3365: {"ftrapgtw", 4, two(0xF07A, 0x0012), two(0xF1FF, 0xFFFF), "Ii^w", mfloat },
3366: {"ftraplew", 4, two(0xF07A, 0x0015), two(0xF1FF, 0xFFFF), "Ii^w", mfloat },
3367: {"ftrapltw", 4, two(0xF07A, 0x0014), two(0xF1FF, 0xFFFF), "Ii^w", mfloat },
3368: {"ftrapnew", 4, two(0xF07A, 0x000E), two(0xF1FF, 0xFFFF), "Ii^w", mfloat },
3369: {"ftrapngew", 4,two(0xF07A, 0x001C), two(0xF1FF, 0xFFFF), "Ii^w", mfloat },
3370: {"ftrapnglw", 4,two(0xF07A, 0x0019), two(0xF1FF, 0xFFFF), "Ii^w", mfloat },
3371: {"ftrapnglew", 4,two(0xF07A, 0x0018), two(0xF1FF, 0xFFFF), "Ii^w", mfloat },
3372: {"ftrapngtw", 4,two(0xF07A, 0x001D), two(0xF1FF, 0xFFFF), "Ii^w", mfloat },
3373: {"ftrapnlew", 4,two(0xF07A, 0x001A), two(0xF1FF, 0xFFFF), "Ii^w", mfloat },
3374: {"ftrapnltw", 4,two(0xF07A, 0x001B), two(0xF1FF, 0xFFFF), "Ii^w", mfloat },
3375: {"ftrapogew", 4,two(0xF07A, 0x0003), two(0xF1FF, 0xFFFF), "Ii^w", mfloat },
3376: {"ftrapoglw", 4,two(0xF07A, 0x0006), two(0xF1FF, 0xFFFF), "Ii^w", mfloat },
3377: {"ftrapogtw", 4,two(0xF07A, 0x0002), two(0xF1FF, 0xFFFF), "Ii^w", mfloat },
3378: {"ftrapolew", 4,two(0xF07A, 0x0005), two(0xF1FF, 0xFFFF), "Ii^w", mfloat },
3379: {"ftrapoltw", 4,two(0xF07A, 0x0004), two(0xF1FF, 0xFFFF), "Ii^w", mfloat },
3380: {"ftraporw", 4, two(0xF07A, 0x0007), two(0xF1FF, 0xFFFF), "Ii^w", mfloat },
3381: {"ftrapseqw", 4,two(0xF07A, 0x0011), two(0xF1FF, 0xFFFF), "Ii^w", mfloat },
3382: {"ftrapsfw", 4, two(0xF07A, 0x0010), two(0xF1FF, 0xFFFF), "Ii^w", mfloat },
3383: {"ftrapsnew", 4,two(0xF07A, 0x001E), two(0xF1FF, 0xFFFF), "Ii^w", mfloat },
3384: {"ftrapstw", 4, two(0xF07A, 0x001F), two(0xF1FF, 0xFFFF), "Ii^w", mfloat },
3385: {"ftraptw", 4, two(0xF07A, 0x000F), two(0xF1FF, 0xFFFF), "Ii^w", mfloat },
3386: {"ftrapueqw", 4,two(0xF07A, 0x0009), two(0xF1FF, 0xFFFF), "Ii^w", mfloat },
3387: {"ftrapugew", 4,two(0xF07A, 0x000B), two(0xF1FF, 0xFFFF), "Ii^w", mfloat },
3388: {"ftrapugtw", 4,two(0xF07A, 0x000A), two(0xF1FF, 0xFFFF), "Ii^w", mfloat },
3389: {"ftrapulew", 4,two(0xF07A, 0x000D), two(0xF1FF, 0xFFFF), "Ii^w", mfloat },
3390: {"ftrapultw", 4,two(0xF07A, 0x000C), two(0xF1FF, 0xFFFF), "Ii^w", mfloat },
3391: {"ftrapunw", 4, two(0xF07A, 0x0008), two(0xF1FF, 0xFFFF), "Ii^w", mfloat },
3392:
3393: {"ftrapeql", 4, two(0xF07B, 0x0001), two(0xF1FF, 0xFFFF), "Ii^l", mfloat },
3394: {"ftrapfl", 4, two(0xF07B, 0x0000), two(0xF1FF, 0xFFFF), "Ii^l", mfloat },
3395: {"ftrapgel", 4, two(0xF07B, 0x0013), two(0xF1FF, 0xFFFF), "Ii^l", mfloat },
3396: {"ftrapgll", 4, two(0xF07B, 0x0016), two(0xF1FF, 0xFFFF), "Ii^l", mfloat },
3397: {"ftrapglel", 4,two(0xF07B, 0x0017), two(0xF1FF, 0xFFFF), "Ii^l", mfloat },
3398: {"ftrapgtl", 4, two(0xF07B, 0x0012), two(0xF1FF, 0xFFFF), "Ii^l", mfloat },
3399: {"ftraplel", 4, two(0xF07B, 0x0015), two(0xF1FF, 0xFFFF), "Ii^l", mfloat },
3400: {"ftrapltl", 4, two(0xF07B, 0x0014), two(0xF1FF, 0xFFFF), "Ii^l", mfloat },
3401: {"ftrapnel", 4, two(0xF07B, 0x000E), two(0xF1FF, 0xFFFF), "Ii^l", mfloat },
3402: {"ftrapngel", 4,two(0xF07B, 0x001C), two(0xF1FF, 0xFFFF), "Ii^l", mfloat },
3403: {"ftrapngll", 4,two(0xF07B, 0x0019), two(0xF1FF, 0xFFFF), "Ii^l", mfloat },
3404: {"ftrapnglel", 4,two(0xF07B, 0x0018), two(0xF1FF, 0xFFFF), "Ii^l", mfloat },
3405: {"ftrapngtl", 4,two(0xF07B, 0x001D), two(0xF1FF, 0xFFFF), "Ii^l", mfloat },
3406: {"ftrapnlel", 4,two(0xF07B, 0x001A), two(0xF1FF, 0xFFFF), "Ii^l", mfloat },
3407: {"ftrapnltl", 4,two(0xF07B, 0x001B), two(0xF1FF, 0xFFFF), "Ii^l", mfloat },
3408: {"ftrapogel", 4,two(0xF07B, 0x0003), two(0xF1FF, 0xFFFF), "Ii^l", mfloat },
3409: {"ftrapogll", 4,two(0xF07B, 0x0006), two(0xF1FF, 0xFFFF), "Ii^l", mfloat },
3410: {"ftrapogtl", 4,two(0xF07B, 0x0002), two(0xF1FF, 0xFFFF), "Ii^l", mfloat },
3411: {"ftrapolel", 4,two(0xF07B, 0x0005), two(0xF1FF, 0xFFFF), "Ii^l", mfloat },
3412: {"ftrapoltl", 4,two(0xF07B, 0x0004), two(0xF1FF, 0xFFFF), "Ii^l", mfloat },
3413: {"ftraporl", 4, two(0xF07B, 0x0007), two(0xF1FF, 0xFFFF), "Ii^l", mfloat },
3414: {"ftrapseql", 4,two(0xF07B, 0x0011), two(0xF1FF, 0xFFFF), "Ii^l", mfloat },
3415: {"ftrapsfl", 4, two(0xF07B, 0x0010), two(0xF1FF, 0xFFFF), "Ii^l", mfloat },
3416: {"ftrapsnel", 4,two(0xF07B, 0x001E), two(0xF1FF, 0xFFFF), "Ii^l", mfloat },
3417: {"ftrapstl", 4, two(0xF07B, 0x001F), two(0xF1FF, 0xFFFF), "Ii^l", mfloat },
3418: {"ftraptl", 4, two(0xF07B, 0x000F), two(0xF1FF, 0xFFFF), "Ii^l", mfloat },
3419: {"ftrapueql", 4,two(0xF07B, 0x0009), two(0xF1FF, 0xFFFF), "Ii^l", mfloat },
3420: {"ftrapugel", 4,two(0xF07B, 0x000B), two(0xF1FF, 0xFFFF), "Ii^l", mfloat },
3421: {"ftrapugtl", 4,two(0xF07B, 0x000A), two(0xF1FF, 0xFFFF), "Ii^l", mfloat },
3422: {"ftrapulel", 4,two(0xF07B, 0x000D), two(0xF1FF, 0xFFFF), "Ii^l", mfloat },
3423: {"ftrapultl", 4,two(0xF07B, 0x000C), two(0xF1FF, 0xFFFF), "Ii^l", mfloat },
3424: {"ftrapunl", 4, two(0xF07B, 0x0008), two(0xF1FF, 0xFFFF), "Ii^l", mfloat },
3425:
3426: {"ftstb", 4, two(0xF000, 0x583A), two(0xF1C0, 0xFC7F), "Ii;b", mfloat },
3427: {"ftstb", 4, two(0xF000, 0x583A), two(0xF1C0, 0xFC7F), "Iibs", cfloat },
3428: {"ftstd", 4, two(0xF000, 0x003A), two(0xF1C0, 0xE07F), "IiF8", cfloat },
3429: {"ftstd", 4, two(0xF000, 0x543A), two(0xF1C0, 0xFC7F), "Ii;F", mfloat },
3430: {"ftstd", 4, two(0xF000, 0x543A), two(0xF1C0, 0xFC7F), "Iibs", cfloat },
3431: {"ftstl", 4, two(0xF000, 0x403A), two(0xF1C0, 0xFC7F), "Ii;l", mfloat },
3432: {"ftstl", 4, two(0xF000, 0x403A), two(0xF1C0, 0xFC7F), "Iibs", cfloat },
3433: {"ftstp", 4, two(0xF000, 0x4C3A), two(0xF1C0, 0xFC7F), "Ii;p", mfloat },
3434: {"ftsts", 4, two(0xF000, 0x443A), two(0xF1C0, 0xFC7F), "Ii;f", mfloat },
3435: {"ftsts", 4, two(0xF000, 0x443A), two(0xF1C0, 0xFC7F), "Iibs", cfloat },
3436: {"ftstw", 4, two(0xF000, 0x503A), two(0xF1C0, 0xFC7F), "Ii;w", mfloat },
3437: {"ftstw", 4, two(0xF000, 0x503A), two(0xF1C0, 0xFC7F), "Iibs", cfloat },
3438: {"ftstx", 4, two(0xF000, 0x003A), two(0xF1C0, 0xE07F), "IiF8", mfloat },
3439: {"ftstx", 4, two(0xF000, 0x483A), two(0xF1C0, 0xFC7F), "Ii;x", mfloat },
3440:
3441: {"ftwotoxb", 4, two(0xF000, 0x5811), two(0xF1C0, 0xFC7F), "Ii;bF7", mfloat },
3442: {"ftwotoxd", 4, two(0xF000, 0x5411), two(0xF1C0, 0xFC7F), "Ii;FF7", mfloat },
3443: {"ftwotoxl", 4, two(0xF000, 0x4011), two(0xF1C0, 0xFC7F), "Ii;lF7", mfloat },
3444: {"ftwotoxp", 4, two(0xF000, 0x4C11), two(0xF1C0, 0xFC7F), "Ii;pF7", mfloat },
3445: {"ftwotoxs", 4, two(0xF000, 0x4411), two(0xF1C0, 0xFC7F), "Ii;fF7", mfloat },
3446: {"ftwotoxw", 4, two(0xF000, 0x5011), two(0xF1C0, 0xFC7F), "Ii;wF7", mfloat },
3447: {"ftwotoxx", 4, two(0xF000, 0x0011), two(0xF1C0, 0xE07F), "IiF8F7", mfloat },
3448: {"ftwotoxx", 4, two(0xF000, 0x4811), two(0xF1C0, 0xFC7F), "Ii;xF7", mfloat },
3449: {"ftwotoxx", 4, two(0xF000, 0x0011), two(0xF1C0, 0xE07F), "IiFt", mfloat },
3450:
3451: {"halt", 2, one(0045310), one(0177777), "", m68060 | mcfisa_a },
3452:
3453: {"illegal", 2, one(0045374), one(0177777), "", m68000up | mcfisa_a },
3454: {"intouch", 2, one(0xf428), one(0xfff8), "As", mcfisa_b },
3455:
3456: {"jmp", 2, one(0047300), one(0177700), "!s", m68000up | mcfisa_a },
3457:
3458: {"jra", 2, one(0060000), one(0177400), "Bg", m68000up | mcfisa_a },
3459: {"jra", 2, one(0047300), one(0177700), "!s", m68000up | mcfisa_a },
3460:
3461: {"jsr", 2, one(0047200), one(0177700), "!s", m68000up | mcfisa_a },
3462:
3463: {"jbsr", 2, one(0060400), one(0177400), "Bg", m68000up | mcfisa_a },
3464: {"jbsr", 2, one(0047200), one(0177700), "!s", m68000up | mcfisa_a },
3465:
3466: {"lea", 2, one(0040700), one(0170700), "!sAd", m68000up | mcfisa_a },
3467:
3468: {"lpstop", 6, two(0174000,0000700),two(0177777,0177777),"#w", cpu32|m68060 },
3469:
3470: {"linkw", 4, one(0047120), one(0177770), "As#w", m68000up | mcfisa_a },
3471: {"linkl", 6, one(0044010), one(0177770), "As#l", m68020up | cpu32 },
3472: {"link", 4, one(0047120), one(0177770), "As#W", m68000up | mcfisa_a },
3473: {"link", 6, one(0044010), one(0177770), "As#l", m68020up | cpu32 },
3474:
3475: {"lslb", 2, one(0160410), one(0170770), "QdDs", m68000up },
3476: {"lslb", 2, one(0160450), one(0170770), "DdDs", m68000up },
3477: {"lslw", 2, one(0160510), one(0170770), "QdDs", m68000up },
3478: {"lslw", 2, one(0160550), one(0170770), "DdDs", m68000up },
3479: {"lslw", 2, one(0161700), one(0177700), "~s", m68000up },
3480: {"lsll", 2, one(0160610), one(0170770), "QdDs", m68000up | mcfisa_a },
3481: {"lsll", 2, one(0160650), one(0170770), "DdDs", m68000up | mcfisa_a },
3482:
3483: {"lsrb", 2, one(0160010), one(0170770), "QdDs", m68000up },
3484: {"lsrb", 2, one(0160050), one(0170770), "DdDs", m68000up },
3485: {"lsrw", 2, one(0160110), one(0170770), "QdDs", m68000up },
3486: {"lsrw", 2, one(0160150), one(0170770), "DdDs", m68000up },
3487: {"lsrw", 2, one(0161300), one(0177700), "~s", m68000up },
3488: {"lsrl", 2, one(0160210), one(0170770), "QdDs", m68000up | mcfisa_a },
3489: {"lsrl", 2, one(0160250), one(0170770), "DdDs", m68000up | mcfisa_a },
3490:
3491: {"macw", 4, two(0xa080, 0x0000), two(0xf180, 0x0910), "uNuoiI4/Rn", mcfmac },
3492: {"macw", 4, two(0xa080, 0x0200), two(0xf180, 0x0910), "uNuoMh4/Rn", mcfmac },
3493: {"macw", 4, two(0xa080, 0x0000), two(0xf180, 0x0f10), "uNuo4/Rn", mcfmac },
3494: {"macw", 4, two(0xa000, 0x0000), two(0xf1b0, 0x0900), "uMumiI", mcfmac },
3495: {"macw", 4, two(0xa000, 0x0200), two(0xf1b0, 0x0900), "uMumMh", mcfmac },
3496: {"macw", 4, two(0xa000, 0x0000), two(0xf1b0, 0x0f00), "uMum", mcfmac },
3497:
3498: {"macw", 4, two(0xa000, 0x0000), two(0xf100, 0x0900), "uNuoiI4/RneG", mcfemac },/* Ry,Rx,SF,<ea>,accX. */
3499: {"macw", 4, two(0xa000, 0x0200), two(0xf100, 0x0900), "uNuoMh4/RneG", mcfemac },/* Ry,Rx,+1/-1,<ea>,accX. */
3500: {"macw", 4, two(0xa000, 0x0000), two(0xf100, 0x0f00), "uNuo4/RneG", mcfemac },/* Ry,Rx,<ea>,accX. */
3501: {"macw", 4, two(0xa000, 0x0000), two(0xf130, 0x0900), "uMumiIeH", mcfemac },/* Ry,Rx,SF,accX. */
3502: {"macw", 4, two(0xa000, 0x0200), two(0xf130, 0x0900), "uMumMheH", mcfemac },/* Ry,Rx,+1/-1,accX. */
3503: {"macw", 4, two(0xa000, 0x0000), two(0xf130, 0x0f00), "uMumeH", mcfemac }, /* Ry,Rx,accX. */
3504:
3505: {"macl", 4, two(0xa080, 0x0800), two(0xf180, 0x0910), "RNRoiI4/Rn", mcfmac },
3506: {"macl", 4, two(0xa080, 0x0a00), two(0xf180, 0x0910), "RNRoMh4/Rn", mcfmac },
3507: {"macl", 4, two(0xa080, 0x0800), two(0xf180, 0x0f10), "RNRo4/Rn", mcfmac },
3508: {"macl", 4, two(0xa000, 0x0800), two(0xf1b0, 0x0b00), "RMRmiI", mcfmac },
3509: {"macl", 4, two(0xa000, 0x0a00), two(0xf1b0, 0x0b00), "RMRmMh", mcfmac },
3510: {"macl", 4, two(0xa000, 0x0800), two(0xf1b0, 0x0800), "RMRm", mcfmac },
3511:
3512: {"macl", 4, two(0xa000, 0x0800), two(0xf100, 0x0900), "R3R1iI4/RneG", mcfemac },
3513: {"macl", 4, two(0xa000, 0x0a00), two(0xf100, 0x0900), "R3R1Mh4/RneG", mcfemac },
3514: {"macl", 4, two(0xa000, 0x0800), two(0xf100, 0x0f00), "R3R14/RneG", mcfemac },
3515: {"macl", 4, two(0xa000, 0x0800), two(0xf130, 0x0900), "RMRmiIeH", mcfemac },
3516: {"macl", 4, two(0xa000, 0x0a00), two(0xf130, 0x0900), "RMRmMheH", mcfemac },
3517: {"macl", 4, two(0xa000, 0x0800), two(0xf130, 0x0f00), "RMRmeH", mcfemac },
3518:
3519: /* NOTE: The mcf5200 family programmer's reference manual does not
3520: indicate the byte form of the movea instruction is invalid (as it
3521: is on 68000 family cpus). However, experiments on the 5202 yeild
3522: unexpected results. The value is copied, but it is not sign extended
3523: (as is done with movea.w) and the top three bytes in the address
3524: register are not disturbed. I don't know if this is the intended
3525: behavior --- it could be a hole in instruction decoding (Motorola
3526: decided not to trap all invalid instructions for performance reasons)
3527: --- but I suspect that it is not.
3528:
3529: I reported this to Motorola ISD Technical Communications Support,
3530: which replied that other coldfire assemblers reject movea.b. For
3531: this reason I've decided to not allow moveab.
3532:
3533: [email protected] - 97/01/24. */
3534:
3535: {"moveal", 2, one(0020100), one(0170700), "*lAd", m68000up | mcfisa_a },
3536: {"moveaw", 2, one(0030100), one(0170700), "*wAd", m68000up | mcfisa_a },
3537:
3538: {"movclrl", 2, one(0xA1C0), one(0xf9f0), "eFRs", mcfemac },
3539:
3540: {"movec", 4, one(0047173), one(0177777), "R1Jj", m68010up | mcfisa_a },
3541: {"movec", 4, one(0047173), one(0177777), "R1#j", m68010up | mcfisa_a },
3542: {"movec", 4, one(0047172), one(0177777), "JjR1", m68010up },
3543: {"movec", 4, one(0047172), one(0177777), "#jR1", m68010up },
3544:
3545: {"movemw", 4, one(0044200), one(0177700), "Lw&s", m68000up },
3546: {"movemw", 4, one(0044240), one(0177770), "lw-s", m68000up },
3547: {"movemw", 4, one(0044200), one(0177700), "#w>s", m68000up },
3548: {"movemw", 4, one(0046200), one(0177700), "<sLw", m68000up },
3549: {"movemw", 4, one(0046200), one(0177700), "<s#w", m68000up },
3550: {"moveml", 4, one(0044300), one(0177700), "Lw&s", m68000up },
3551: {"moveml", 4, one(0044340), one(0177770), "lw-s", m68000up },
3552: {"moveml", 4, one(0044300), one(0177700), "#w>s", m68000up },
3553: {"moveml", 4, one(0046300), one(0177700), "<sLw", m68000up },
3554: {"moveml", 4, one(0046300), one(0177700), "<s#w", m68000up },
3555: /* FIXME: need specifier for mode 2 and 5 to simplify below insn patterns. */
3556: {"moveml", 4, one(0044320), one(0177770), "Lwas", mcfisa_a },
3557: {"moveml", 4, one(0044320), one(0177770), "#was", mcfisa_a },
3558: {"moveml", 4, one(0044350), one(0177770), "Lwds", mcfisa_a },
3559: {"moveml", 4, one(0044350), one(0177770), "#wds", mcfisa_a },
3560: {"moveml", 4, one(0046320), one(0177770), "asLw", mcfisa_a },
3561: {"moveml", 4, one(0046320), one(0177770), "as#w", mcfisa_a },
3562: {"moveml", 4, one(0046350), one(0177770), "dsLw", mcfisa_a },
3563: {"moveml", 4, one(0046350), one(0177770), "ds#w", mcfisa_a },
3564:
3565: {"movepw", 2, one(0000410), one(0170770), "dsDd", m68000up },
3566: {"movepw", 2, one(0000610), one(0170770), "Ddds", m68000up },
3567: {"movepl", 2, one(0000510), one(0170770), "dsDd", m68000up },
3568: {"movepl", 2, one(0000710), one(0170770), "Ddds", m68000up },
3569:
3570: {"moveq", 2, one(0070000), one(0170400), "MsDd", m68000up | mcfisa_a },
3571: {"moveq", 2, one(0070000), one(0170400), "#BDd", m68000up | mcfisa_a },
3572:
3573: /* The move opcode can generate the movea and moveq instructions. */
3574: {"moveb", 2, one(0010000), one(0170000), ";b$d", m68000up },
3575: {"moveb", 2, one(0010000), one(0170070), "Ds$d", mcfisa_a },
3576: {"moveb", 2, one(0010020), one(0170070), "as$d", mcfisa_a },
3577: {"moveb", 2, one(0010030), one(0170070), "+s$d", mcfisa_a },
3578: {"moveb", 2, one(0010040), one(0170070), "-s$d", mcfisa_a },
3579: {"moveb", 2, one(0010000), one(0170000), "nsqd", mcfisa_a },
3580: {"moveb", 2, one(0010000), one(0170700), "obDd", mcfisa_a },
3581: {"moveb", 2, one(0010200), one(0170700), "obad", mcfisa_a },
3582: {"moveb", 2, one(0010300), one(0170700), "ob+d", mcfisa_a },
3583: {"moveb", 2, one(0010400), one(0170700), "ob-d", mcfisa_a },
3584: {"moveb", 2, one(0010000), one(0170000), "obnd", mcfisa_b },
3585:
3586: {"movew", 2, one(0030000), one(0170000), "*w%d", m68000up },
3587: {"movew", 2, one(0030000), one(0170000), "ms%d", mcfisa_a },
3588: {"movew", 2, one(0030000), one(0170000), "nspd", mcfisa_a },
3589: {"movew", 2, one(0030000), one(0170000), "owmd", mcfisa_a },
3590: {"movew", 2, one(0030000), one(0170000), "ownd", mcfisa_b },
3591: {"movew", 2, one(0040300), one(0177700), "Ss$s", m68000up },
3592: {"movew", 2, one(0040300), one(0177770), "SsDs", mcfisa_a },
3593: {"movew", 2, one(0041300), one(0177700), "Cs$s", m68010up },
3594: {"movew", 2, one(0041300), one(0177770), "CsDs", mcfisa_a },
3595: {"movew", 2, one(0042300), one(0177700), ";wCd", m68000up },
3596: {"movew", 2, one(0042300), one(0177700), "DsCd", mcfisa_a },
3597: {"movew", 4, one(0042374), one(0177777), "#wCd", mcfisa_a },
3598: {"movew", 2, one(0043300), one(0177700), ";wSd", m68000up },
3599: {"movew", 2, one(0043300), one(0177700), "DsSd", mcfisa_a },
3600: {"movew", 4, one(0043374), one(0177777), "#wSd", mcfisa_a },
3601:
3602: {"movel", 2, one(0070000), one(0170400), "MsDd", m68000up | mcfisa_a },
3603: {"movel", 2, one(0020000), one(0170000), "*l%d", m68000up },
3604: {"movel", 2, one(0020000), one(0170000), "ms%d", mcfisa_a },
3605: {"movel", 2, one(0020000), one(0170000), "nspd", mcfisa_a },
3606: {"movel", 2, one(0020000), one(0170000), "olmd", mcfisa_a },
3607: {"movel", 2, one(0020000), one(0170000), "olnd", mcfisa_b },
3608: {"movel", 2, one(0047140), one(0177770), "AsUd", m68000up | mcfusp },
3609: {"movel", 2, one(0047150), one(0177770), "UdAs", m68000up | mcfusp },
3610: {"movel", 2, one(0120600), one(0177760), "EsRs", mcfmac },
3611: {"movel", 2, one(0120400), one(0177760), "RsEs", mcfmac },
3612: {"movel", 6, one(0120474), one(0177777), "#lEs", mcfmac },
3613: {"movel", 2, one(0124600), one(0177760), "GsRs", mcfmac },
3614: {"movel", 2, one(0124400), one(0177760), "RsGs", mcfmac },
3615: {"movel", 6, one(0124474), one(0177777), "#lGs", mcfmac },
3616: {"movel", 2, one(0126600), one(0177760), "HsRs", mcfmac },
3617: {"movel", 2, one(0126400), one(0177760), "RsHs", mcfmac },
3618: {"movel", 6, one(0126474), one(0177777), "#lHs", mcfmac },
3619: {"movel", 2, one(0124700), one(0177777), "GsCs", mcfmac },
3620:
3621: {"movel", 2, one(0xa180), one(0xf9f0), "eFRs", mcfemac }, /* ACCx,Rx. */
3622: {"movel", 2, one(0xab80), one(0xfbf0), "g]Rs", mcfemac }, /* ACCEXTx,Rx. */
3623: {"movel", 2, one(0xa980), one(0xfff0), "G-Rs", mcfemac }, /* macsr,Rx. */
3624: {"movel", 2, one(0xad80), one(0xfff0), "H-Rs", mcfemac }, /* mask,Rx. */
3625: {"movel", 2, one(0xa110), one(0xf9fc), "efeF", mcfemac }, /* ACCy,ACCx. */
3626: {"movel", 2, one(0xa9c0), one(0xffff), "G-C-", mcfemac }, /* macsr,ccr. */
3627: {"movel", 2, one(0xa100), one(0xf9f0), "RseF", mcfemac }, /* Rx,ACCx. */
3628: {"movel", 6, one(0xa13c), one(0xf9ff), "#leF", mcfemac }, /* #,ACCx. */
3629: {"movel", 2, one(0xab00), one(0xfbc0), "Rsg]", mcfemac }, /* Rx,ACCEXTx. */
3630: {"movel", 6, one(0xab3c), one(0xfbff), "#lg]", mcfemac }, /* #,ACCEXTx. */
3631: {"movel", 2, one(0xa900), one(0xffc0), "RsG-", mcfemac }, /* Rx,macsr. */
3632: {"movel", 6, one(0xa93c), one(0xffff), "#lG-", mcfemac }, /* #,macsr. */
3633: {"movel", 2, one(0xad00), one(0xffc0), "RsH-", mcfemac }, /* Rx,mask. */
3634: {"movel", 6, one(0xad3c), one(0xffff), "#lH-", mcfemac }, /* #,mask. */
3635:
3636: {"move", 2, one(0030000), one(0170000), "*w%d", m68000up },
3637: {"move", 2, one(0030000), one(0170000), "ms%d", mcfisa_a },
3638: {"move", 2, one(0030000), one(0170000), "nspd", mcfisa_a },
3639: {"move", 2, one(0030000), one(0170000), "owmd", mcfisa_a },
3640: {"move", 2, one(0030000), one(0170000), "ownd", mcfisa_b },
3641: {"move", 2, one(0040300), one(0177700), "Ss$s", m68000up },
3642: {"move", 2, one(0040300), one(0177770), "SsDs", mcfisa_a },
3643: {"move", 2, one(0041300), one(0177700), "Cs$s", m68010up },
3644: {"move", 2, one(0041300), one(0177770), "CsDs", mcfisa_a },
3645: {"move", 2, one(0042300), one(0177700), ";wCd", m68000up },
3646: {"move", 2, one(0042300), one(0177700), "DsCd", mcfisa_a },
3647: {"move", 4, one(0042374), one(0177777), "#wCd", mcfisa_a },
3648: {"move", 2, one(0043300), one(0177700), ";wSd", m68000up },
3649: {"move", 2, one(0043300), one(0177700), "DsSd", mcfisa_a },
3650: {"move", 4, one(0043374), one(0177777), "#wSd", mcfisa_a },
3651:
3652: {"move", 2, one(0047140), one(0177770), "AsUd", m68000up },
3653: {"move", 2, one(0047150), one(0177770), "UdAs", m68000up },
3654:
3655: {"mov3ql", 2, one(0120500), one(0170700), "xd%s", mcfisa_b },
3656: {"mvsb", 2, one(0070400), one(0170700), "*bDd", mcfisa_b },
3657: {"mvsw", 2, one(0070500), one(0170700), "*wDd", mcfisa_b },
3658: {"mvzb", 2, one(0070600), one(0170700), "*bDd", mcfisa_b },
3659: {"mvzw", 2, one(0070700), one(0170700), "*wDd", mcfisa_b },
3660:
3661: {"movesb", 4, two(0007000, 0), two(0177700, 07777), "~sR1", m68010up },
3662: {"movesb", 4, two(0007000, 04000), two(0177700, 07777), "R1~s", m68010up },
3663: {"movesw", 4, two(0007100, 0), two(0177700, 07777), "~sR1", m68010up },
3664: {"movesw", 4, two(0007100, 04000), two(0177700, 07777), "R1~s", m68010up },
3665: {"movesl", 4, two(0007200, 0), two(0177700, 07777), "~sR1", m68010up },
3666: {"movesl", 4, two(0007200, 04000), two(0177700, 07777), "R1~s", m68010up },
3667:
3668: {"move16", 4, two(0xf620, 0x8000), two(0xfff8, 0x8fff), "+s+1", m68040up },
3669: {"move16", 2, one(0xf600), one(0xfff8), "+s_L", m68040up },
3670: {"move16", 2, one(0xf608), one(0xfff8), "_L+s", m68040up },
3671: {"move16", 2, one(0xf610), one(0xfff8), "as_L", m68040up },
3672: {"move16", 2, one(0xf618), one(0xfff8), "_Las", m68040up },
3673:
3674: {"msacw", 4, two(0xa080, 0x0100), two(0xf180, 0x0910), "uNuoiI4/Rn", mcfmac },
3675: {"msacw", 4, two(0xa080, 0x0300), two(0xf180, 0x0910), "uNuoMh4/Rn", mcfmac },
3676: {"msacw", 4, two(0xa080, 0x0100), two(0xf180, 0x0f10), "uNuo4/Rn", mcfmac },
3677: {"msacw", 4, two(0xa000, 0x0100), two(0xf1b0, 0x0900), "uMumiI", mcfmac },
3678: {"msacw", 4, two(0xa000, 0x0300), two(0xf1b0, 0x0900), "uMumMh", mcfmac },
3679: {"msacw", 4, two(0xa000, 0x0100), two(0xf1b0, 0x0f00), "uMum", mcfmac },
3680:
3681: {"msacw", 4, two(0xa000, 0x0100), two(0xf100, 0x0900), "uMumiI4/RneG", mcfemac },/* Ry,Rx,SF,<ea>,accX. */
3682: {"msacw", 4, two(0xa000, 0x0300), two(0xf100, 0x0900), "uMumMh4/RneG", mcfemac },/* Ry,Rx,+1/-1,<ea>,accX. */
3683: {"msacw", 4, two(0xa000, 0x0100), two(0xf100, 0x0f00), "uMum4/RneG", mcfemac },/* Ry,Rx,<ea>,accX. */
3684: {"msacw", 4, two(0xa000, 0x0100), two(0xf130, 0x0900), "uMumiIeH", mcfemac },/* Ry,Rx,SF,accX. */
3685: {"msacw", 4, two(0xa000, 0x0300), two(0xf130, 0x0900), "uMumMheH", mcfemac },/* Ry,Rx,+1/-1,accX. */
3686: {"msacw", 4, two(0xa000, 0x0100), two(0xf130, 0x0f00), "uMumeH", mcfemac }, /* Ry,Rx,accX. */
3687:
3688: {"msacl", 4, two(0xa080, 0x0900), two(0xf180, 0x0910), "RNRoiI4/Rn", mcfmac },
3689: {"msacl", 4, two(0xa080, 0x0b00), two(0xf180, 0x0910), "RNRoMh4/Rn", mcfmac },
3690: {"msacl", 4, two(0xa080, 0x0900), two(0xf180, 0x0f10), "RNRo4/Rn", mcfmac },
3691: {"msacl", 4, two(0xa000, 0x0900), two(0xf1b0, 0x0b00), "RMRmiI", mcfmac },
3692: {"msacl", 4, two(0xa000, 0x0b00), two(0xf1b0, 0x0b00), "RMRmMh", mcfmac },
3693: {"msacl", 4, two(0xa000, 0x0900), two(0xf1b0, 0x0800), "RMRm", mcfmac },
3694:
3695: {"msacl", 4, two(0xa000, 0x0900), two(0xf100, 0x0900), "R3R1iI4/RneG", mcfemac },
3696: {"msacl", 4, two(0xa000, 0x0b00), two(0xf100, 0x0900), "R3R1Mh4/RneG", mcfemac },
3697: {"msacl", 4, two(0xa000, 0x0900), two(0xf100, 0x0f00), "R3R14/RneG", mcfemac },
3698: {"msacl", 4, two(0xa000, 0x0900), two(0xf130, 0x0900), "RMRmiIeH", mcfemac },
3699: {"msacl", 4, two(0xa000, 0x0b00), two(0xf130, 0x0900), "RMRmMheH", mcfemac },
3700: {"msacl", 4, two(0xa000, 0x0900), two(0xf130, 0x0f00), "RMRmeH", mcfemac },
3701:
3702: {"mulsw", 2, one(0140700), one(0170700), ";wDd", m68000up|mcfisa_a },
3703: {"mulsl", 4, two(0046000,004000), two(0177700,0107770), ";lD1", m68020up|cpu32 },
3704: {"mulsl", 4, two(0046000,004000), two(0177700,0107770), "qsD1", mcfisa_a },
3705: {"mulsl", 4, two(0046000,006000), two(0177700,0107770), ";lD3D1",m68020up|cpu32 },
3706:
3707: {"muluw", 2, one(0140300), one(0170700), ";wDd", m68000up|mcfisa_a },
3708: {"mulul", 4, two(0046000,000000), two(0177700,0107770), ";lD1", m68020up|cpu32 },
3709: {"mulul", 4, two(0046000,000000), two(0177700,0107770), "qsD1", mcfisa_a },
3710: {"mulul", 4, two(0046000,002000), two(0177700,0107770), ";lD3D1",m68020up|cpu32 },
3711:
3712: {"nbcd", 2, one(0044000), one(0177700), "$s", m68000up },
3713:
3714: {"negb", 2, one(0042000), one(0177700), "$s", m68000up },
3715: {"negw", 2, one(0042100), one(0177700), "$s", m68000up },
3716: {"negl", 2, one(0042200), one(0177700), "$s", m68000up },
3717: {"negl", 2, one(0042200), one(0177700), "Ds", mcfisa_a},
3718:
3719: {"negxb", 2, one(0040000), one(0177700), "$s", m68000up },
3720: {"negxw", 2, one(0040100), one(0177700), "$s", m68000up },
3721: {"negxl", 2, one(0040200), one(0177700), "$s", m68000up },
3722: {"negxl", 2, one(0040200), one(0177700), "Ds", mcfisa_a},
3723:
3724: {"nop", 2, one(0047161), one(0177777), "", m68000up | mcfisa_a},
3725:
3726: {"notb", 2, one(0043000), one(0177700), "$s", m68000up },
3727: {"notw", 2, one(0043100), one(0177700), "$s", m68000up },
3728: {"notl", 2, one(0043200), one(0177700), "$s", m68000up },
3729: {"notl", 2, one(0043200), one(0177700), "Ds", mcfisa_a},
3730:
3731: {"orib", 4, one(0000000), one(0177700), "#b$s", m68000up },
3732: {"orib", 4, one(0000074), one(0177777), "#bCs", m68000up },
3733: {"oriw", 4, one(0000100), one(0177700), "#w$s", m68000up },
3734: {"oriw", 4, one(0000174), one(0177777), "#wSs", m68000up },
3735: {"oril", 6, one(0000200), one(0177700), "#l$s", m68000up },
3736: {"oril", 6, one(0000200), one(0177700), "#lDs", mcfisa_a },
3737: {"ori", 4, one(0000074), one(0177777), "#bCs", m68000up },
3738: {"ori", 4, one(0000100), one(0177700), "#w$s", m68000up },
3739: {"ori", 4, one(0000174), one(0177777), "#wSs", m68000up },
3740:
3741: /* The or opcode can generate the ori instruction. */
3742: {"orb", 4, one(0000000), one(0177700), "#b$s", m68000up },
3743: {"orb", 4, one(0000074), one(0177777), "#bCs", m68000up },
3744: {"orb", 2, one(0100000), one(0170700), ";bDd", m68000up },
3745: {"orb", 2, one(0100400), one(0170700), "Dd~s", m68000up },
3746: {"orw", 4, one(0000100), one(0177700), "#w$s", m68000up },
3747: {"orw", 4, one(0000174), one(0177777), "#wSs", m68000up },
3748: {"orw", 2, one(0100100), one(0170700), ";wDd", m68000up },
3749: {"orw", 2, one(0100500), one(0170700), "Dd~s", m68000up },
3750: {"orl", 6, one(0000200), one(0177700), "#l$s", m68000up },
3751: {"orl", 6, one(0000200), one(0177700), "#lDs", mcfisa_a },
3752: {"orl", 2, one(0100200), one(0170700), ";lDd", m68000up | mcfisa_a },
3753: {"orl", 2, one(0100600), one(0170700), "Dd~s", m68000up | mcfisa_a },
3754: {"or", 4, one(0000074), one(0177777), "#bCs", m68000up },
3755: {"or", 4, one(0000100), one(0177700), "#w$s", m68000up },
3756: {"or", 4, one(0000174), one(0177777), "#wSs", m68000up },
3757: {"or", 2, one(0100100), one(0170700), ";wDd", m68000up },
3758: {"or", 2, one(0100500), one(0170700), "Dd~s", m68000up },
3759:
3760: {"pack", 4, one(0100500), one(0170770), "DsDd#w", m68020up },
3761: {"pack", 4, one(0100510), one(0170770), "-s-d#w", m68020up },
3762:
3763: {"pbac", 2, one(0xf087), one(0xffbf), "Bc", m68851 },
3764: {"pbacw", 2, one(0xf087), one(0xffff), "BW", m68851 },
3765: {"pbas", 2, one(0xf086), one(0xffbf), "Bc", m68851 },
3766: {"pbasw", 2, one(0xf086), one(0xffff), "BW", m68851 },
3767: {"pbbc", 2, one(0xf081), one(0xffbf), "Bc", m68851 },
3768: {"pbbcw", 2, one(0xf081), one(0xffff), "BW", m68851 },
3769: {"pbbs", 2, one(0xf080), one(0xffbf), "Bc", m68851 },
3770: {"pbbsw", 2, one(0xf080), one(0xffff), "BW", m68851 },
3771: {"pbcc", 2, one(0xf08f), one(0xffbf), "Bc", m68851 },
3772: {"pbccw", 2, one(0xf08f), one(0xffff), "BW", m68851 },
3773: {"pbcs", 2, one(0xf08e), one(0xffbf), "Bc", m68851 },
3774: {"pbcsw", 2, one(0xf08e), one(0xffff), "BW", m68851 },
3775: {"pbgc", 2, one(0xf08d), one(0xffbf), "Bc", m68851 },
3776: {"pbgcw", 2, one(0xf08d), one(0xffff), "BW", m68851 },
3777: {"pbgs", 2, one(0xf08c), one(0xffbf), "Bc", m68851 },
3778: {"pbgsw", 2, one(0xf08c), one(0xffff), "BW", m68851 },
3779: {"pbic", 2, one(0xf08b), one(0xffbf), "Bc", m68851 },
3780: {"pbicw", 2, one(0xf08b), one(0xffff), "BW", m68851 },
3781: {"pbis", 2, one(0xf08a), one(0xffbf), "Bc", m68851 },
3782: {"pbisw", 2, one(0xf08a), one(0xffff), "BW", m68851 },
3783: {"pblc", 2, one(0xf083), one(0xffbf), "Bc", m68851 },
3784: {"pblcw", 2, one(0xf083), one(0xffff), "BW", m68851 },
3785: {"pbls", 2, one(0xf082), one(0xffbf), "Bc", m68851 },
3786: {"pblsw", 2, one(0xf082), one(0xffff), "BW", m68851 },
3787: {"pbsc", 2, one(0xf085), one(0xffbf), "Bc", m68851 },
3788: {"pbscw", 2, one(0xf085), one(0xffff), "BW", m68851 },
3789: {"pbss", 2, one(0xf084), one(0xffbf), "Bc", m68851 },
3790: {"pbssw", 2, one(0xf084), one(0xffff), "BW", m68851 },
3791: {"pbwc", 2, one(0xf089), one(0xffbf), "Bc", m68851 },
3792: {"pbwcw", 2, one(0xf089), one(0xffff), "BW", m68851 },
3793: {"pbws", 2, one(0xf088), one(0xffbf), "Bc", m68851 },
3794: {"pbwsw", 2, one(0xf088), one(0xffff), "BW", m68851 },
3795:
3796: {"pdbac", 4, two(0xf048, 0x0007), two(0xfff8, 0xffff), "DsBw", m68851 },
3797: {"pdbas", 4, two(0xf048, 0x0006), two(0xfff8, 0xffff), "DsBw", m68851 },
3798: {"pdbbc", 4, two(0xf048, 0x0001), two(0xfff8, 0xffff), "DsBw", m68851 },
3799: {"pdbbs", 4, two(0xf048, 0x0000), two(0xfff8, 0xffff), "DsBw", m68851 },
3800: {"pdbcc", 4, two(0xf048, 0x000f), two(0xfff8, 0xffff), "DsBw", m68851 },
3801: {"pdbcs", 4, two(0xf048, 0x000e), two(0xfff8, 0xffff), "DsBw", m68851 },
3802: {"pdbgc", 4, two(0xf048, 0x000d), two(0xfff8, 0xffff), "DsBw", m68851 },
3803: {"pdbgs", 4, two(0xf048, 0x000c), two(0xfff8, 0xffff), "DsBw", m68851 },
3804: {"pdbic", 4, two(0xf048, 0x000b), two(0xfff8, 0xffff), "DsBw", m68851 },
3805: {"pdbis", 4, two(0xf048, 0x000a), two(0xfff8, 0xffff), "DsBw", m68851 },
3806: {"pdblc", 4, two(0xf048, 0x0003), two(0xfff8, 0xffff), "DsBw", m68851 },
3807: {"pdbls", 4, two(0xf048, 0x0002), two(0xfff8, 0xffff), "DsBw", m68851 },
3808: {"pdbsc", 4, two(0xf048, 0x0005), two(0xfff8, 0xffff), "DsBw", m68851 },
3809: {"pdbss", 4, two(0xf048, 0x0004), two(0xfff8, 0xffff), "DsBw", m68851 },
3810: {"pdbwc", 4, two(0xf048, 0x0009), two(0xfff8, 0xffff), "DsBw", m68851 },
3811: {"pdbws", 4, two(0xf048, 0x0008), two(0xfff8, 0xffff), "DsBw", m68851 },
3812:
3813: {"pea", 2, one(0044100), one(0177700), "!s", m68000up|mcfisa_a },
3814:
3815: {"pflusha", 2, one(0xf518), one(0xfff8), "", m68040up },
3816: {"pflusha", 4, two(0xf000,0x2400), two(0xffff,0xffff), "", m68030 | m68851 },
3817:
3818: {"pflush", 4, two(0xf000,0x3010), two(0xffc0,0xfe10), "T3T9", m68030|m68851 },
3819: {"pflush", 4, two(0xf000,0x3810), two(0xffc0,0xfe10), "T3T9&s", m68030|m68851 },
3820: {"pflush", 4, two(0xf000,0x3008), two(0xffc0,0xfe18), "D3T9", m68030|m68851 },
3821: {"pflush", 4, two(0xf000,0x3808), two(0xffc0,0xfe18), "D3T9&s", m68030|m68851 },
3822: {"pflush", 4, two(0xf000,0x3000), two(0xffc0,0xfe1e), "f3T9", m68030|m68851 },
3823: {"pflush", 4, two(0xf000,0x3800), two(0xffc0,0xfe1e), "f3T9&s", m68030|m68851 },
3824: {"pflush", 2, one(0xf508), one(0xfff8), "as", m68040up },
3825: {"pflush", 2, one(0xf508), one(0xfff8), "As", m68040up },
3826:
3827: {"pflushan", 2, one(0xf510), one(0xfff8), "", m68040up },
3828: {"pflushn", 2, one(0xf500), one(0xfff8), "as", m68040up },
3829: {"pflushn", 2, one(0xf500), one(0xfff8), "As", m68040up },
3830:
3831: {"pflushr", 4, two(0xf000, 0xa000), two(0xffc0, 0xffff), "|s", m68851 },
3832:
3833: {"pflushs", 4, two(0xf000, 0x3410), two(0xfff8, 0xfe10), "T3T9", m68851 },
3834: {"pflushs", 4, two(0xf000, 0x3c10), two(0xfff8, 0xfe10), "T3T9&s", m68851 },
3835: {"pflushs", 4, two(0xf000, 0x3408), two(0xfff8, 0xfe18), "D3T9", m68851 },
3836: {"pflushs", 4, two(0xf000, 0x3c08), two(0xfff8, 0xfe18), "D3T9&s", m68851 },
3837: {"pflushs", 4, two(0xf000, 0x3400), two(0xfff8, 0xfe1e), "f3T9", m68851 },
3838: {"pflushs", 4, two(0xf000, 0x3c00), two(0xfff8, 0xfe1e), "f3T9&s", m68851 },
3839:
3840: {"ploadr", 4, two(0xf000,0x2210), two(0xffc0,0xfff0), "T3&s", m68030|m68851 },
3841: {"ploadr", 4, two(0xf000,0x2208), two(0xffc0,0xfff8), "D3&s", m68030|m68851 },
3842: {"ploadr", 4, two(0xf000,0x2200), two(0xffc0,0xfffe), "f3&s", m68030|m68851 },
3843: {"ploadw", 4, two(0xf000,0x2010), two(0xffc0,0xfff0), "T3&s", m68030|m68851 },
3844: {"ploadw", 4, two(0xf000,0x2008), two(0xffc0,0xfff8), "D3&s", m68030|m68851 },
3845: {"ploadw", 4, two(0xf000,0x2000), two(0xffc0,0xfffe), "f3&s", m68030|m68851 },
3846:
3847: {"plpar", 2, one(0xf5c8), one(0xfff8), "as", m68060 },
3848: {"plpaw", 2, one(0xf588), one(0xfff8), "as", m68060 },
3849:
3850: {"pmove", 4, two(0xf000,0x4000), two(0xffc0,0xffff), "*l08", m68030|m68851 },
3851: {"pmove", 4, two(0xf000,0x5c00), two(0xffc0,0xffff), "*w18", m68851 },
3852: {"pmove", 4, two(0xf000,0x4000), two(0xffc0,0xe3ff), "*b28", m68851 },
3853: {"pmove", 4, two(0xf000,0x4200), two(0xffc0,0xffff), "08%s", m68030|m68851 },
3854: {"pmove", 4, two(0xf000,0x5e00), two(0xffc0,0xffff), "18%s", m68851 },
3855: {"pmove", 4, two(0xf000,0x4200), two(0xffc0,0xe3ff), "28%s", m68851 },
3856: {"pmove", 4, two(0xf000,0x4000), two(0xffc0,0xe3ff), "|sW8", m68030|m68851 },
3857: {"pmove", 4, two(0xf000,0x4200), two(0xffc0,0xe3ff), "W8~s", m68030|m68851 },
3858: {"pmove", 4, two(0xf000,0x6200), two(0xffc0,0xe3e3), "*wX3", m68851 },
3859: {"pmove", 4, two(0xf000,0x6000), two(0xffc0,0xe3e3), "X3%s", m68851 },
3860: {"pmove", 4, two(0xf000,0x6000), two(0xffc0,0xffff), "*wY8", m68030|m68851 },
3861: {"pmove", 4, two(0xf000,0x6200), two(0xffc0,0xffff), "Y8%s", m68030|m68851 },
3862: {"pmove", 4, two(0xf000,0x6600), two(0xffc0,0xffff), "Z8%s", m68851 },
3863: {"pmove", 4, two(0xf000,0x0800), two(0xffc0,0xfbff), "*l38", m68030 },
3864: {"pmove", 4, two(0xf000,0x0a00), two(0xffc0,0xfbff), "38%s", m68030 },
3865:
3866: {"pmovefd", 4, two(0xf000, 0x4100), two(0xffc0, 0xe3ff), "*l08", m68030 },
3867: {"pmovefd", 4, two(0xf000, 0x4100), two(0xffc0, 0xe3ff), "|sW8", m68030 },
3868: {"pmovefd", 4, two(0xf000, 0x0900), two(0xffc0, 0xfbff), "*l38", m68030 },
3869:
3870: {"prestore", 2, one(0xf140), one(0xffc0), "<s", m68851 },
3871:
3872: {"psave", 2, one(0xf100), one(0xffc0), ">s", m68851 },
3873:
3874: {"psac", 4, two(0xf040, 0x0007), two(0xffc0, 0xffff), "$s", m68851 },
3875: {"psas", 4, two(0xf040, 0x0006), two(0xffc0, 0xffff), "$s", m68851 },
3876: {"psbc", 4, two(0xf040, 0x0001), two(0xffc0, 0xffff), "$s", m68851 },
3877: {"psbs", 4, two(0xf040, 0x0000), two(0xffc0, 0xffff), "$s", m68851 },
3878: {"pscc", 4, two(0xf040, 0x000f), two(0xffc0, 0xffff), "$s", m68851 },
3879: {"pscs", 4, two(0xf040, 0x000e), two(0xffc0, 0xffff), "$s", m68851 },
3880: {"psgc", 4, two(0xf040, 0x000d), two(0xffc0, 0xffff), "$s", m68851 },
3881: {"psgs", 4, two(0xf040, 0x000c), two(0xffc0, 0xffff), "$s", m68851 },
3882: {"psic", 4, two(0xf040, 0x000b), two(0xffc0, 0xffff), "$s", m68851 },
3883: {"psis", 4, two(0xf040, 0x000a), two(0xffc0, 0xffff), "$s", m68851 },
3884: {"pslc", 4, two(0xf040, 0x0003), two(0xffc0, 0xffff), "$s", m68851 },
3885: {"psls", 4, two(0xf040, 0x0002), two(0xffc0, 0xffff), "$s", m68851 },
3886: {"pssc", 4, two(0xf040, 0x0005), two(0xffc0, 0xffff), "$s", m68851 },
3887: {"psss", 4, two(0xf040, 0x0004), two(0xffc0, 0xffff), "$s", m68851 },
3888: {"pswc", 4, two(0xf040, 0x0009), two(0xffc0, 0xffff), "$s", m68851 },
3889: {"psws", 4, two(0xf040, 0x0008), two(0xffc0, 0xffff), "$s", m68851 },
3890:
3891: {"ptestr", 4, two(0xf000,0x8210), two(0xffc0, 0xe3f0), "T3&st8", m68030|m68851 },
3892: {"ptestr", 4, two(0xf000,0x8310), two(0xffc0,0xe310), "T3&st8A9", m68030|m68851 },
3893: {"ptestr", 4, two(0xf000,0x8208), two(0xffc0,0xe3f8), "D3&st8", m68030|m68851 },
3894: {"ptestr", 4, two(0xf000,0x8308), two(0xffc0,0xe318), "D3&st8A9", m68030|m68851 },
3895: {"ptestr", 4, two(0xf000,0x8200), two(0xffc0,0xe3fe), "f3&st8", m68030|m68851 },
3896: {"ptestr", 4, two(0xf000,0x8300), two(0xffc0,0xe31e), "f3&st8A9", m68030|m68851 },
3897: {"ptestr", 2, one(0xf568), one(0xfff8), "as", m68040 },
3898:
3899: {"ptestw", 4, two(0xf000,0x8010), two(0xffc0,0xe3f0), "T3&st8", m68030|m68851 },
3900: {"ptestw", 4, two(0xf000,0x8110), two(0xffc0,0xe310), "T3&st8A9", m68030|m68851 },
3901: {"ptestw", 4, two(0xf000,0x8008), two(0xffc0,0xe3f8), "D3&st8", m68030|m68851 },
3902: {"ptestw", 4, two(0xf000,0x8108), two(0xffc0,0xe318), "D3&st8A9", m68030|m68851 },
3903: {"ptestw", 4, two(0xf000,0x8000), two(0xffc0,0xe3fe), "f3&st8", m68030|m68851 },
3904: {"ptestw", 4, two(0xf000,0x8100), two(0xffc0,0xe31e), "f3&st8A9", m68030|m68851 },
3905: {"ptestw", 2, one(0xf548), one(0xfff8), "as", m68040 },
3906:
3907: {"ptrapacw", 6, two(0xf07a, 0x0007), two(0xffff, 0xffff), "#w", m68851 },
3908: {"ptrapacl", 6, two(0xf07b, 0x0007), two(0xffff, 0xffff), "#l", m68851 },
3909: {"ptrapac", 4, two(0xf07c, 0x0007), two(0xffff, 0xffff), "", m68851 },
3910:
3911: {"ptrapasw", 6, two(0xf07a, 0x0006), two(0xffff, 0xffff), "#w", m68851 },
3912: {"ptrapasl", 6, two(0xf07b, 0x0006), two(0xffff, 0xffff), "#l", m68851 },
3913: {"ptrapas", 4, two(0xf07c, 0x0006), two(0xffff, 0xffff), "", m68851 },
3914:
3915: {"ptrapbcw", 6, two(0xf07a, 0x0001), two(0xffff, 0xffff), "#w", m68851 },
3916: {"ptrapbcl", 6, two(0xf07b, 0x0001), two(0xffff, 0xffff), "#l", m68851 },
3917: {"ptrapbc", 4, two(0xf07c, 0x0001), two(0xffff, 0xffff), "", m68851 },
3918:
3919: {"ptrapbsw", 6, two(0xf07a, 0x0000), two(0xffff, 0xffff), "#w", m68851 },
3920: {"ptrapbsl", 6, two(0xf07b, 0x0000), two(0xffff, 0xffff), "#l", m68851 },
3921: {"ptrapbs", 4, two(0xf07c, 0x0000), two(0xffff, 0xffff), "", m68851 },
3922:
3923: {"ptrapccw", 6, two(0xf07a, 0x000f), two(0xffff, 0xffff), "#w", m68851 },
3924: {"ptrapccl", 6, two(0xf07b, 0x000f), two(0xffff, 0xffff), "#l", m68851 },
3925: {"ptrapcc", 4, two(0xf07c, 0x000f), two(0xffff, 0xffff), "", m68851 },
3926:
3927: {"ptrapcsw", 6, two(0xf07a, 0x000e), two(0xffff, 0xffff), "#w", m68851 },
3928: {"ptrapcsl", 6, two(0xf07b, 0x000e), two(0xffff, 0xffff), "#l", m68851 },
3929: {"ptrapcs", 4, two(0xf07c, 0x000e), two(0xffff, 0xffff), "", m68851 },
3930:
3931: {"ptrapgcw", 6, two(0xf07a, 0x000d), two(0xffff, 0xffff), "#w", m68851 },
3932: {"ptrapgcl", 6, two(0xf07b, 0x000d), two(0xffff, 0xffff), "#l", m68851 },
3933: {"ptrapgc", 4, two(0xf07c, 0x000d), two(0xffff, 0xffff), "", m68851 },
3934:
3935: {"ptrapgsw", 6, two(0xf07a, 0x000c), two(0xffff, 0xffff), "#w", m68851 },
3936: {"ptrapgsl", 6, two(0xf07b, 0x000c), two(0xffff, 0xffff), "#l", m68851 },
3937: {"ptrapgs", 4, two(0xf07c, 0x000c), two(0xffff, 0xffff), "", m68851 },
3938:
3939: {"ptrapicw", 6, two(0xf07a, 0x000b), two(0xffff, 0xffff), "#w", m68851 },
3940: {"ptrapicl", 6, two(0xf07b, 0x000b), two(0xffff, 0xffff), "#l", m68851 },
3941: {"ptrapic", 4, two(0xf07c, 0x000b), two(0xffff, 0xffff), "", m68851 },
3942:
3943: {"ptrapisw", 6, two(0xf07a, 0x000a), two(0xffff, 0xffff), "#w", m68851 },
3944: {"ptrapisl", 6, two(0xf07b, 0x000a), two(0xffff, 0xffff), "#l", m68851 },
3945: {"ptrapis", 4, two(0xf07c, 0x000a), two(0xffff, 0xffff), "", m68851 },
3946:
3947: {"ptraplcw", 6, two(0xf07a, 0x0003), two(0xffff, 0xffff), "#w", m68851 },
3948: {"ptraplcl", 6, two(0xf07b, 0x0003), two(0xffff, 0xffff), "#l", m68851 },
3949: {"ptraplc", 4, two(0xf07c, 0x0003), two(0xffff, 0xffff), "", m68851 },
3950:
3951: {"ptraplsw", 6, two(0xf07a, 0x0002), two(0xffff, 0xffff), "#w", m68851 },
3952: {"ptraplsl", 6, two(0xf07b, 0x0002), two(0xffff, 0xffff), "#l", m68851 },
3953: {"ptrapls", 4, two(0xf07c, 0x0002), two(0xffff, 0xffff), "", m68851 },
3954:
3955: {"ptrapscw", 6, two(0xf07a, 0x0005), two(0xffff, 0xffff), "#w", m68851 },
3956: {"ptrapscl", 6, two(0xf07b, 0x0005), two(0xffff, 0xffff), "#l", m68851 },
3957: {"ptrapsc", 4, two(0xf07c, 0x0005), two(0xffff, 0xffff), "", m68851 },
3958:
3959: {"ptrapssw", 6, two(0xf07a, 0x0004), two(0xffff, 0xffff), "#w", m68851 },
3960: {"ptrapssl", 6, two(0xf07b, 0x0004), two(0xffff, 0xffff), "#l", m68851 },
3961: {"ptrapss", 4, two(0xf07c, 0x0004), two(0xffff, 0xffff), "", m68851 },
3962:
3963: {"ptrapwcw", 6, two(0xf07a, 0x0009), two(0xffff, 0xffff), "#w", m68851 },
3964: {"ptrapwcl", 6, two(0xf07b, 0x0009), two(0xffff, 0xffff), "#l", m68851 },
3965: {"ptrapwc", 4, two(0xf07c, 0x0009), two(0xffff, 0xffff), "", m68851 },
3966:
3967: {"ptrapwsw", 6, two(0xf07a, 0x0008), two(0xffff, 0xffff), "#w", m68851 },
3968: {"ptrapwsl", 6, two(0xf07b, 0x0008), two(0xffff, 0xffff), "#l", m68851 },
3969: {"ptrapws", 4, two(0xf07c, 0x0008), two(0xffff, 0xffff), "", m68851 },
3970:
3971: {"pulse", 2, one(0045314), one(0177777), "", m68060 | mcfisa_a },
3972:
3973: {"pvalid", 4, two(0xf000, 0x2800), two(0xffc0, 0xffff), "Vs&s", m68851 },
3974: {"pvalid", 4, two(0xf000, 0x2c00), two(0xffc0, 0xfff8), "A3&s", m68851 },
3975:
3976: /* FIXME: don't allow Dw==Dx. */
3977: {"remsl", 4, two(0x4c40, 0x0800), two(0xffc0, 0x8ff8), "qsD3D1", mcfhwdiv },
3978: {"remul", 4, two(0x4c40, 0x0000), two(0xffc0, 0x8ff8), "qsD3D1", mcfhwdiv },
3979:
3980: {"reset", 2, one(0047160), one(0177777), "", m68000up },
3981:
3982: {"rolb", 2, one(0160430), one(0170770), "QdDs", m68000up },
3983: {"rolb", 2, one(0160470), one(0170770), "DdDs", m68000up },
3984: {"rolw", 2, one(0160530), one(0170770), "QdDs", m68000up },
3985: {"rolw", 2, one(0160570), one(0170770), "DdDs", m68000up },
3986: {"rolw", 2, one(0163700), one(0177700), "~s", m68000up },
3987: {"roll", 2, one(0160630), one(0170770), "QdDs", m68000up },
3988: {"roll", 2, one(0160670), one(0170770), "DdDs", m68000up },
3989:
3990: {"rorb", 2, one(0160030), one(0170770), "QdDs", m68000up },
3991: {"rorb", 2, one(0160070), one(0170770), "DdDs", m68000up },
3992: {"rorw", 2, one(0160130), one(0170770), "QdDs", m68000up },
3993: {"rorw", 2, one(0160170), one(0170770), "DdDs", m68000up },
3994: {"rorw", 2, one(0163300), one(0177700), "~s", m68000up },
3995: {"rorl", 2, one(0160230), one(0170770), "QdDs", m68000up },
3996: {"rorl", 2, one(0160270), one(0170770), "DdDs", m68000up },
3997:
3998: {"roxlb", 2, one(0160420), one(0170770), "QdDs", m68000up },
3999: {"roxlb", 2, one(0160460), one(0170770), "DdDs", m68000up },
4000: {"roxlw", 2, one(0160520), one(0170770), "QdDs", m68000up },
4001: {"roxlw", 2, one(0160560), one(0170770), "DdDs", m68000up },
4002: {"roxlw", 2, one(0162700), one(0177700), "~s", m68000up },
4003: {"roxll", 2, one(0160620), one(0170770), "QdDs", m68000up },
4004: {"roxll", 2, one(0160660), one(0170770), "DdDs", m68000up },
4005:
4006: {"roxrb", 2, one(0160020), one(0170770), "QdDs", m68000up },
4007: {"roxrb", 2, one(0160060), one(0170770), "DdDs", m68000up },
4008: {"roxrw", 2, one(0160120), one(0170770), "QdDs", m68000up },
4009: {"roxrw", 2, one(0160160), one(0170770), "DdDs", m68000up },
4010: {"roxrw", 2, one(0162300), one(0177700), "~s", m68000up },
4011: {"roxrl", 2, one(0160220), one(0170770), "QdDs", m68000up },
4012: {"roxrl", 2, one(0160260), one(0170770), "DdDs", m68000up },
4013:
4014: {"rtd", 4, one(0047164), one(0177777), "#w", m68010up },
1.1.1.2 root 4015:
1.1 root 4016: {"rte", 2, one(0047163), one(0177777), "", m68000up | mcfisa_a },
1.1.1.2 root 4017:
1.1 root 4018: {"rtm", 2, one(0003300), one(0177760), "Rs", m68020 },
1.1.1.2 root 4019:
1.1 root 4020: {"rtr", 2, one(0047167), one(0177777), "", m68000up },
1.1.1.2 root 4021:
1.1 root 4022: {"rts", 2, one(0047165), one(0177777), "", m68000up | mcfisa_a },
4023:
4024: {"satsl", 2, one(0046200), one(0177770), "Ds", mcfisa_b },
4025:
4026: {"sbcd", 2, one(0100400), one(0170770), "DsDd", m68000up },
4027: {"sbcd", 2, one(0100410), one(0170770), "-s-d", m68000up },
4028:
4029: {"scc", 2, one(0052300), one(0177700), "$s", m68000up },
4030: {"scc", 2, one(0052300), one(0177700), "Ds", mcfisa_a },
4031: {"scs", 2, one(0052700), one(0177700), "$s", m68000up },
4032: {"scs", 2, one(0052700), one(0177700), "Ds", mcfisa_a },
4033: {"seq", 2, one(0053700), one(0177700), "$s", m68000up },
4034: {"seq", 2, one(0053700), one(0177700), "Ds", mcfisa_a },
4035: {"sf", 2, one(0050700), one(0177700), "$s", m68000up },
4036: {"sf", 2, one(0050700), one(0177700), "Ds", mcfisa_a },
4037: {"sge", 2, one(0056300), one(0177700), "$s", m68000up },
4038: {"sge", 2, one(0056300), one(0177700), "Ds", mcfisa_a },
4039: {"sgt", 2, one(0057300), one(0177700), "$s", m68000up },
4040: {"sgt", 2, one(0057300), one(0177700), "Ds", mcfisa_a },
4041: {"shi", 2, one(0051300), one(0177700), "$s", m68000up },
4042: {"shi", 2, one(0051300), one(0177700), "Ds", mcfisa_a },
4043: {"sle", 2, one(0057700), one(0177700), "$s", m68000up },
4044: {"sle", 2, one(0057700), one(0177700), "Ds", mcfisa_a },
4045: {"sls", 2, one(0051700), one(0177700), "$s", m68000up },
4046: {"sls", 2, one(0051700), one(0177700), "Ds", mcfisa_a },
4047: {"slt", 2, one(0056700), one(0177700), "$s", m68000up },
4048: {"slt", 2, one(0056700), one(0177700), "Ds", mcfisa_a },
4049: {"smi", 2, one(0055700), one(0177700), "$s", m68000up },
4050: {"smi", 2, one(0055700), one(0177700), "Ds", mcfisa_a },
4051: {"sne", 2, one(0053300), one(0177700), "$s", m68000up },
4052: {"sne", 2, one(0053300), one(0177700), "Ds", mcfisa_a },
4053: {"spl", 2, one(0055300), one(0177700), "$s", m68000up },
4054: {"spl", 2, one(0055300), one(0177700), "Ds", mcfisa_a },
4055: {"st", 2, one(0050300), one(0177700), "$s", m68000up },
4056: {"st", 2, one(0050300), one(0177700), "Ds", mcfisa_a },
4057: {"svc", 2, one(0054300), one(0177700), "$s", m68000up },
4058: {"svc", 2, one(0054300), one(0177700), "Ds", mcfisa_a },
4059: {"svs", 2, one(0054700), one(0177700), "$s", m68000up },
4060: {"svs", 2, one(0054700), one(0177700), "Ds", mcfisa_a },
4061:
4062: {"stop", 4, one(0047162), one(0177777), "#w", m68000up | mcfisa_a },
4063:
4064: {"strldsr", 4, two(0040347,0043374), two(0177777,0177777), "#w", mcfisa_aa},
4065:
4066: {"subal", 2, one(0110700), one(0170700), "*lAd", m68000up | mcfisa_a },
4067: {"subaw", 2, one(0110300), one(0170700), "*wAd", m68000up },
4068:
4069: {"subib", 4, one(0002000), one(0177700), "#b$s", m68000up },
4070: {"subiw", 4, one(0002100), one(0177700), "#w$s", m68000up },
4071: {"subil", 6, one(0002200), one(0177700), "#l$s", m68000up },
4072: {"subil", 6, one(0002200), one(0177700), "#lDs", mcfisa_a },
4073:
4074: {"subqb", 2, one(0050400), one(0170700), "Qd%s", m68000up },
4075: {"subqw", 2, one(0050500), one(0170700), "Qd%s", m68000up },
4076: {"subql", 2, one(0050600), one(0170700), "Qd%s", m68000up | mcfisa_a },
4077:
4078: /* The sub opcode can generate the suba, subi, and subq instructions. */
4079: {"subb", 2, one(0050400), one(0170700), "Qd%s", m68000up },
4080: {"subb", 4, one(0002000), one(0177700), "#b$s", m68000up },
4081: {"subb", 2, one(0110000), one(0170700), ";bDd", m68000up },
4082: {"subb", 2, one(0110400), one(0170700), "Dd~s", m68000up },
4083: {"subw", 2, one(0050500), one(0170700), "Qd%s", m68000up },
4084: {"subw", 4, one(0002100), one(0177700), "#w$s", m68000up },
4085: {"subw", 2, one(0110300), one(0170700), "*wAd", m68000up },
4086: {"subw", 2, one(0110100), one(0170700), "*wDd", m68000up },
4087: {"subw", 2, one(0110500), one(0170700), "Dd~s", m68000up },
4088: {"subl", 2, one(0050600), one(0170700), "Qd%s", m68000up | mcfisa_a },
4089: {"subl", 6, one(0002200), one(0177700), "#l$s", m68000up },
4090: {"subl", 6, one(0002200), one(0177700), "#lDs", mcfisa_a },
4091: {"subl", 2, one(0110700), one(0170700), "*lAd", m68000up | mcfisa_a },
4092: {"subl", 2, one(0110200), one(0170700), "*lDd", m68000up | mcfisa_a },
4093: {"subl", 2, one(0110600), one(0170700), "Dd~s", m68000up | mcfisa_a },
4094:
4095: {"subxb", 2, one(0110400), one(0170770), "DsDd", m68000up },
4096: {"subxb", 2, one(0110410), one(0170770), "-s-d", m68000up },
4097: {"subxw", 2, one(0110500), one(0170770), "DsDd", m68000up },
4098: {"subxw", 2, one(0110510), one(0170770), "-s-d", m68000up },
4099: {"subxl", 2, one(0110600), one(0170770), "DsDd", m68000up | mcfisa_a },
4100: {"subxl", 2, one(0110610), one(0170770), "-s-d", m68000up },
4101:
4102: {"swap", 2, one(0044100), one(0177770), "Ds", m68000up | mcfisa_a },
4103:
4104: /* swbeg and swbegl are magic constants used on sysV68. The compiler
4105: generates them before a switch table. They tell the debugger and
4106: disassembler that a switch table follows. The parameter is the
4107: number of elements in the table. swbeg means that the entries in
4108: the table are word (2 byte) sized, and swbegl means that the
4109: entries in the table are longword (4 byte) sized. */
4110: {"swbeg", 4, one(0045374), one(0177777), "#w", m68000up | mcfisa_a },
4111: {"swbegl", 6, one(0045375), one(0177777), "#l", m68000up | mcfisa_a },
4112:
4113: {"tas", 2, one(0045300), one(0177700), "$s", m68000up | mcfisa_b},
4114:
4115: #define TBL1(name,insn_size,signed,round,size) \
4116: {name, insn_size, two(0174000, (signed<<11)|(!round<<10)|(size<<6)|0000400), \
4117: two(0177700,0107777), "!sD1", cpu32 }, \
4118: {name, insn_size, two(0174000, (signed<<11)|(!round<<10)|(size<<6)), \
4119: two(0177770,0107770), "DsD3D1", cpu32 }
4120: #define TBL(name1, name2, name3, s, r) \
4121: TBL1(name1, 4, s, r, 0), TBL1(name2, 4, s, r, 1), TBL1(name3, 4, s, r, 2)
4122: TBL("tblsb", "tblsw", "tblsl", 2, 1),
4123: TBL("tblsnb", "tblsnw", "tblsnl", 2, 0),
4124: TBL("tblub", "tbluw", "tblul", 0, 1),
4125: TBL("tblunb", "tblunw", "tblunl", 0, 0),
4126:
4127: {"trap", 2, one(0047100), one(0177760), "Ts", m68000up | mcfisa_a },
4128:
4129: {"trapcc", 2, one(0052374), one(0177777), "", m68020up | cpu32 },
4130: {"trapcs", 2, one(0052774), one(0177777), "", m68020up | cpu32 },
4131: {"trapeq", 2, one(0053774), one(0177777), "", m68020up | cpu32 },
4132: {"trapf", 2, one(0050774), one(0177777), "", m68020up | cpu32 | mcfisa_a },
4133: {"trapge", 2, one(0056374), one(0177777), "", m68020up | cpu32 },
4134: {"trapgt", 2, one(0057374), one(0177777), "", m68020up | cpu32 },
4135: {"traphi", 2, one(0051374), one(0177777), "", m68020up | cpu32 },
4136: {"traple", 2, one(0057774), one(0177777), "", m68020up | cpu32 },
4137: {"trapls", 2, one(0051774), one(0177777), "", m68020up | cpu32 },
4138: {"traplt", 2, one(0056774), one(0177777), "", m68020up | cpu32 },
4139: {"trapmi", 2, one(0055774), one(0177777), "", m68020up | cpu32 },
4140: {"trapne", 2, one(0053374), one(0177777), "", m68020up | cpu32 },
4141: {"trappl", 2, one(0055374), one(0177777), "", m68020up | cpu32 },
4142: {"trapt", 2, one(0050374), one(0177777), "", m68020up | cpu32 },
4143: {"trapvc", 2, one(0054374), one(0177777), "", m68020up | cpu32 },
4144: {"trapvs", 2, one(0054774), one(0177777), "", m68020up | cpu32 },
4145:
4146: {"trapccw", 4, one(0052372), one(0177777), "#w", m68020up|cpu32 },
4147: {"trapcsw", 4, one(0052772), one(0177777), "#w", m68020up|cpu32 },
4148: {"trapeqw", 4, one(0053772), one(0177777), "#w", m68020up|cpu32 },
4149: {"trapfw", 4, one(0050772), one(0177777), "#w", m68020up|cpu32|mcfisa_a},
4150: {"trapgew", 4, one(0056372), one(0177777), "#w", m68020up|cpu32 },
4151: {"trapgtw", 4, one(0057372), one(0177777), "#w", m68020up|cpu32 },
4152: {"traphiw", 4, one(0051372), one(0177777), "#w", m68020up|cpu32 },
4153: {"traplew", 4, one(0057772), one(0177777), "#w", m68020up|cpu32 },
4154: {"traplsw", 4, one(0051772), one(0177777), "#w", m68020up|cpu32 },
4155: {"trapltw", 4, one(0056772), one(0177777), "#w", m68020up|cpu32 },
4156: {"trapmiw", 4, one(0055772), one(0177777), "#w", m68020up|cpu32 },
4157: {"trapnew", 4, one(0053372), one(0177777), "#w", m68020up|cpu32 },
4158: {"trapplw", 4, one(0055372), one(0177777), "#w", m68020up|cpu32 },
4159: {"traptw", 4, one(0050372), one(0177777), "#w", m68020up|cpu32 },
4160: {"trapvcw", 4, one(0054372), one(0177777), "#w", m68020up|cpu32 },
4161: {"trapvsw", 4, one(0054772), one(0177777), "#w", m68020up|cpu32 },
4162:
4163: {"trapccl", 6, one(0052373), one(0177777), "#l", m68020up|cpu32 },
4164: {"trapcsl", 6, one(0052773), one(0177777), "#l", m68020up|cpu32 },
4165: {"trapeql", 6, one(0053773), one(0177777), "#l", m68020up|cpu32 },
4166: {"trapfl", 6, one(0050773), one(0177777), "#l", m68020up|cpu32|mcfisa_a},
4167: {"trapgel", 6, one(0056373), one(0177777), "#l", m68020up|cpu32 },
4168: {"trapgtl", 6, one(0057373), one(0177777), "#l", m68020up|cpu32 },
4169: {"traphil", 6, one(0051373), one(0177777), "#l", m68020up|cpu32 },
4170: {"traplel", 6, one(0057773), one(0177777), "#l", m68020up|cpu32 },
4171: {"traplsl", 6, one(0051773), one(0177777), "#l", m68020up|cpu32 },
4172: {"trapltl", 6, one(0056773), one(0177777), "#l", m68020up|cpu32 },
4173: {"trapmil", 6, one(0055773), one(0177777), "#l", m68020up|cpu32 },
4174: {"trapnel", 6, one(0053373), one(0177777), "#l", m68020up|cpu32 },
4175: {"trappll", 6, one(0055373), one(0177777), "#l", m68020up|cpu32 },
4176: {"traptl", 6, one(0050373), one(0177777), "#l", m68020up|cpu32 },
4177: {"trapvcl", 6, one(0054373), one(0177777), "#l", m68020up|cpu32 },
4178: {"trapvsl", 6, one(0054773), one(0177777), "#l", m68020up|cpu32 },
4179:
4180: {"trapv", 2, one(0047166), one(0177777), "", m68000up },
4181:
4182: {"tstb", 2, one(0045000), one(0177700), ";b", m68020up|cpu32|mcfisa_a },
4183: {"tstb", 2, one(0045000), one(0177700), "$b", m68000up },
4184: {"tstw", 2, one(0045100), one(0177700), "*w", m68020up|cpu32|mcfisa_a },
4185: {"tstw", 2, one(0045100), one(0177700), "$w", m68000up },
4186: {"tstl", 2, one(0045200), one(0177700), "*l", m68020up|cpu32|mcfisa_a },
4187: {"tstl", 2, one(0045200), one(0177700), "$l", m68000up },
4188:
4189: {"unlk", 2, one(0047130), one(0177770), "As", m68000up | mcfisa_a },
4190:
4191: {"unpk", 4, one(0100600), one(0170770), "DsDd#w", m68020up },
4192: {"unpk", 4, one(0100610), one(0170770), "-s-d#w", m68020up },
4193:
4194: {"wddatab", 2, one(0175400), one(0177700), "~s", mcfisa_a },
4195: {"wddataw", 2, one(0175500), one(0177700), "~s", mcfisa_a },
4196: {"wddatal", 2, one(0175600), one(0177700), "~s", mcfisa_a },
4197:
4198: {"wdebug", 4, two(0175720, 03), two(0177770, 0xffff), "as", mcfisa_a },
4199: {"wdebug", 4, two(0175750, 03), two(0177770, 0xffff), "ds", mcfisa_a },
4200: };
4201:
4202: const int m68k_numopcodes = sizeof m68k_opcodes / sizeof m68k_opcodes[0];
4203:
4204: /* These aliases used to be in the above table, each one duplicating
4205: all of the entries for its primary exactly. This table was
4206: constructed by mechanical processing of the opcode table, with a
4207: small number of tweaks done by hand. There are probably a lot more
4208: aliases above that could be moved down here, except for very minor
4209: differences. */
4210:
4211: const struct m68k_opcode_alias m68k_opcode_aliases[] =
4212: {
4213: { "add", "addw", },
4214: { "adda", "addaw", },
4215: { "addi", "addiw", },
4216: { "addq", "addqw", },
4217: { "addx", "addxw", },
4218: { "asl", "aslw", },
4219: { "asr", "asrw", },
4220: { "bhi", "bhiw", },
4221: { "bls", "blsw", },
4222: { "bcc", "bccw", },
4223: { "bcs", "bcsw", },
4224: { "bne", "bnew", },
4225: { "beq", "beqw", },
4226: { "bvc", "bvcw", },
4227: { "bvs", "bvsw", },
4228: { "bpl", "bplw", },
4229: { "bmi", "bmiw", },
4230: { "bge", "bgew", },
4231: { "blt", "bltw", },
4232: { "bgt", "bgtw", },
4233: { "ble", "blew", },
4234: { "bra", "braw", },
4235: { "bsr", "bsrw", },
4236: { "bhib", "bhis", },
4237: { "blsb", "blss", },
4238: { "bccb", "bccs", },
4239: { "bcsb", "bcss", },
4240: { "bneb", "bnes", },
4241: { "beqb", "beqs", },
4242: { "bvcb", "bvcs", },
4243: { "bvsb", "bvss", },
4244: { "bplb", "bpls", },
4245: { "bmib", "bmis", },
4246: { "bgeb", "bges", },
4247: { "bltb", "blts", },
4248: { "bgtb", "bgts", },
4249: { "bleb", "bles", },
4250: { "brab", "bras", },
4251: { "bsrb", "bsrs", },
4252: { "bhs", "bccw" },
4253: { "bhss", "bccs" },
4254: { "bhsb", "bccs" },
4255: { "bhsw", "bccw" },
4256: { "bhsl", "bccl" },
4257: { "blo", "bcsw" },
4258: { "blos", "bcss" },
4259: { "blob", "bcss" },
4260: { "blow", "bcsw" },
4261: { "blol", "bcsl" },
4262: { "br", "braw", },
4263: { "brs", "bras", },
4264: { "brb", "bras", },
4265: { "brw", "braw", },
4266: { "brl", "bral", },
4267: { "jfnlt", "bcc", }, /* Apparently a sun alias. */
4268: { "jfngt", "ble", }, /* Apparently a sun alias. */
4269: { "jfeq", "beqs", }, /* Apparently a sun alias. */
4270: { "bchgb", "bchg", },
4271: { "bchgl", "bchg", },
4272: { "bclrb", "bclr", },
4273: { "bclrl", "bclr", },
4274: { "bsetb", "bset", },
4275: { "bsetl", "bset", },
4276: { "btstb", "btst", },
4277: { "btstl", "btst", },
4278: { "cas2", "cas2w", },
4279: { "cas", "casw", },
4280: { "chk2", "chk2w", },
4281: { "chk", "chkw", },
4282: { "clr", "clrw", },
4283: { "cmp2", "cmp2w", },
4284: { "cmpa", "cmpaw", },
4285: { "cmpi", "cmpiw", },
4286: { "cmpm", "cmpmw", },
4287: { "cmp", "cmpw", },
4288: { "dbccw", "dbcc", },
4289: { "dbcsw", "dbcs", },
4290: { "dbeqw", "dbeq", },
4291: { "dbfw", "dbf", },
4292: { "dbgew", "dbge", },
4293: { "dbgtw", "dbgt", },
4294: { "dbhiw", "dbhi", },
4295: { "dblew", "dble", },
4296: { "dblsw", "dbls", },
4297: { "dbltw", "dblt", },
4298: { "dbmiw", "dbmi", },
4299: { "dbnew", "dbne", },
4300: { "dbplw", "dbpl", },
4301: { "dbtw", "dbt", },
4302: { "dbvcw", "dbvc", },
4303: { "dbvsw", "dbvs", },
4304: { "dbhs", "dbcc", },
4305: { "dbhsw", "dbcc", },
4306: { "dbra", "dbf", },
4307: { "dbraw", "dbf", },
4308: { "tdivsl", "divsl", },
4309: { "divs", "divsw", },
4310: { "divu", "divuw", },
4311: { "ext", "extw", },
4312: { "extbw", "extw", },
4313: { "extwl", "extl", },
4314: { "fbneq", "fbne", },
4315: { "fbsneq", "fbsne", },
4316: { "fdbneq", "fdbne", },
4317: { "fdbsneq", "fdbsne", },
4318: { "fmovecr", "fmovecrx", },
4319: { "fmovm", "fmovem", },
4320: { "fsneq", "fsne", },
4321: { "fssneq", "fssne", },
4322: { "ftrapneq", "ftrapne", },
4323: { "ftrapsneq", "ftrapsne", },
4324: { "fjneq", "fjne", },
4325: { "fjsneq", "fjsne", },
4326: { "jmpl", "jmp", },
4327: { "jmps", "jmp", },
4328: { "jsrl", "jsr", },
4329: { "jsrs", "jsr", },
4330: { "leal", "lea", },
4331: { "lsl", "lslw", },
4332: { "lsr", "lsrw", },
4333: { "mac", "macw" },
4334: { "movea", "moveaw", },
4335: { "movem", "movemw", },
4336: { "movml", "moveml", },
4337: { "movmw", "movemw", },
4338: { "movm", "movemw", },
4339: { "movep", "movepw", },
4340: { "movpw", "movepw", },
4341: { "moves", "movesw" },
4342: { "muls", "mulsw", },
4343: { "mulu", "muluw", },
4344: { "msac", "msacw" },
4345: { "nbcdb", "nbcd" },
4346: { "neg", "negw", },
4347: { "negx", "negxw", },
4348: { "not", "notw", },
4349: { "peal", "pea", },
4350: { "rol", "rolw", },
4351: { "ror", "rorw", },
4352: { "roxl", "roxlw", },
4353: { "roxr", "roxrw", },
4354: { "sats", "satsl", },
4355: { "sbcdb", "sbcd", },
4356: { "sccb", "scc", },
4357: { "scsb", "scs", },
4358: { "seqb", "seq", },
4359: { "sfb", "sf", },
4360: { "sgeb", "sge", },
4361: { "sgtb", "sgt", },
4362: { "shib", "shi", },
4363: { "sleb", "sle", },
4364: { "slsb", "sls", },
4365: { "sltb", "slt", },
4366: { "smib", "smi", },
4367: { "sneb", "sne", },
4368: { "splb", "spl", },
4369: { "stb", "st", },
4370: { "svcb", "svc", },
4371: { "svsb", "svs", },
4372: { "sfge", "sge", },
4373: { "sfgt", "sgt", },
4374: { "sfle", "sle", },
4375: { "sflt", "slt", },
4376: { "sfneq", "sne", },
4377: { "suba", "subaw", },
4378: { "subi", "subiw", },
4379: { "subq", "subqw", },
4380: { "sub", "subw", },
4381: { "subx", "subxw", },
4382: { "swapw", "swap", },
4383: { "tasb", "tas", },
4384: { "tpcc", "trapcc", },
4385: { "tcc", "trapcc", },
4386: { "tst", "tstw", },
4387: { "jbra", "jra", },
4388: { "jbhi", "jhi", },
4389: { "jbls", "jls", },
4390: { "jbcc", "jcc", },
4391: { "jbcs", "jcs", },
4392: { "jbne", "jne", },
4393: { "jbeq", "jeq", },
4394: { "jbvc", "jvc", },
4395: { "jbvs", "jvs", },
4396: { "jbpl", "jpl", },
4397: { "jbmi", "jmi", },
4398: { "jbge", "jge", },
4399: { "jblt", "jlt", },
4400: { "jbgt", "jgt", },
4401: { "jble", "jle", },
4402: { "movql", "moveq", },
4403: { "moveql", "moveq", },
4404: { "movl", "movel", },
4405: { "movq", "moveq", },
4406: { "moval", "moveal", },
4407: { "movaw", "moveaw", },
4408: { "movb", "moveb", },
4409: { "movc", "movec", },
4410: { "movecl", "movec", },
4411: { "movpl", "movepl", },
4412: { "movw", "movew", },
4413: { "movsb", "movesb", },
4414: { "movsl", "movesl", },
4415: { "movsw", "movesw", },
4416: { "mov3q", "mov3ql", },
4417:
4418: { "tdivul", "divul", }, /* For m68k-svr4. */
4419: { "fmovb", "fmoveb", },
4420: { "fsmovb", "fsmoveb", },
4421: { "fdmovb", "fdmoveb", },
4422: { "fmovd", "fmoved", },
4423: { "fsmovd", "fsmoved", },
4424: { "fmovl", "fmovel", },
4425: { "fsmovl", "fsmovel", },
4426: { "fdmovl", "fdmovel", },
4427: { "fmovp", "fmovep", },
4428: { "fsmovp", "fsmovep", },
4429: { "fdmovp", "fdmovep", },
4430: { "fmovs", "fmoves", },
4431: { "fsmovs", "fsmoves", },
4432: { "fdmovs", "fdmoves", },
4433: { "fmovw", "fmovew", },
4434: { "fsmovw", "fsmovew", },
4435: { "fdmovw", "fdmovew", },
4436: { "fmovx", "fmovex", },
4437: { "fsmovx", "fsmovex", },
4438: { "fdmovx", "fdmovex", },
4439: { "fmovcr", "fmovecr", },
4440: { "fmovcrx", "fmovecrx", },
4441: { "ftestb", "ftstb", },
4442: { "ftestd", "ftstd", },
4443: { "ftestl", "ftstl", },
4444: { "ftestp", "ftstp", },
4445: { "ftests", "ftsts", },
4446: { "ftestw", "ftstw", },
4447: { "ftestx", "ftstx", },
4448:
4449: { "bitrevl", "bitrev", },
4450: { "byterevl", "byterev", },
4451: { "ff1l", "ff1", },
4452:
4453: };
4454:
4455: const int m68k_numaliases =
4456: sizeof m68k_opcode_aliases / sizeof m68k_opcode_aliases[0];
4457: /* **** End of m68k-opc.c */
4458: /* **** floatformat.c from sourceware.org CVS 2005-08-14. */
4459: /* IEEE floating point support routines, for GDB, the GNU Debugger.
4460: Copyright (C) 1991, 1994, 1999, 2000, 2003 Free Software Foundation, Inc.
4461:
4462: This file is part of GDB.
4463:
4464: This program is free software; you can redistribute it and/or modify
4465: it under the terms of the GNU General Public License as published by
4466: the Free Software Foundation; either version 2 of the License, or
4467: (at your option) any later version.
4468:
4469: This program is distributed in the hope that it will be useful,
4470: but WITHOUT ANY WARRANTY; without even the implied warranty of
4471: MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
4472: GNU General Public License for more details.
4473:
4474: You should have received a copy of the GNU General Public License
1.1.1.4 root 4475: along with this program; if not, see <http://www.gnu.org/licenses/>. */
1.1 root 4476:
4477: /* This is needed to pick up the NAN macro on some systems. */
4478: //#define _GNU_SOURCE
4479:
4480: #ifndef INFINITY
4481: #ifdef HUGE_VAL
4482: #define INFINITY HUGE_VAL
4483: #else
4484: #define INFINITY (1.0 / 0.0)
4485: #endif
4486: #endif
4487:
4488: #ifndef NAN
4489: #define NAN (0.0 / 0.0)
4490: #endif
4491:
4492: static unsigned long get_field (const unsigned char *,
4493: enum floatformat_byteorders,
4494: unsigned int,
4495: unsigned int,
4496: unsigned int);
4497: static int floatformat_always_valid (const struct floatformat *fmt,
4498: const char *from);
4499:
4500: static int
4501: floatformat_always_valid (const struct floatformat *fmt ATTRIBUTE_UNUSED,
4502: const char *from ATTRIBUTE_UNUSED)
4503: {
4504: return 1;
4505: }
4506:
4507: /* The odds that CHAR_BIT will be anything but 8 are low enough that I'm not
4508: going to bother with trying to muck around with whether it is defined in
4509: a system header, what we do if not, etc. */
4510: #define FLOATFORMAT_CHAR_BIT 8
4511:
4512: /* floatformats for IEEE single and double, big and little endian. */
4513: const struct floatformat floatformat_ieee_single_big =
4514: {
4515: floatformat_big, 32, 0, 1, 8, 127, 255, 9, 23,
4516: floatformat_intbit_no,
4517: "floatformat_ieee_single_big",
4518: floatformat_always_valid
4519: };
4520: const struct floatformat floatformat_ieee_single_little =
4521: {
4522: floatformat_little, 32, 0, 1, 8, 127, 255, 9, 23,
4523: floatformat_intbit_no,
4524: "floatformat_ieee_single_little",
4525: floatformat_always_valid
4526: };
4527: const struct floatformat floatformat_ieee_double_big =
4528: {
4529: floatformat_big, 64, 0, 1, 11, 1023, 2047, 12, 52,
4530: floatformat_intbit_no,
4531: "floatformat_ieee_double_big",
4532: floatformat_always_valid
4533: };
4534: const struct floatformat floatformat_ieee_double_little =
4535: {
4536: floatformat_little, 64, 0, 1, 11, 1023, 2047, 12, 52,
4537: floatformat_intbit_no,
4538: "floatformat_ieee_double_little",
4539: floatformat_always_valid
4540: };
4541:
4542: /* floatformat for IEEE double, little endian byte order, with big endian word
4543: ordering, as on the ARM. */
4544:
4545: const struct floatformat floatformat_ieee_double_littlebyte_bigword =
4546: {
4547: floatformat_littlebyte_bigword, 64, 0, 1, 11, 1023, 2047, 12, 52,
4548: floatformat_intbit_no,
4549: "floatformat_ieee_double_littlebyte_bigword",
4550: floatformat_always_valid
4551: };
4552:
4553: static int floatformat_i387_ext_is_valid (const struct floatformat *fmt, const char *from);
4554:
4555: static int
4556: floatformat_i387_ext_is_valid (const struct floatformat *fmt, const char *from)
4557: {
4558: /* In the i387 double-extended format, if the exponent is all ones,
4559: then the integer bit must be set. If the exponent is neither 0
4560: nor ~0, the intbit must also be set. Only if the exponent is
4561: zero can it be zero, and then it must be zero. */
4562: unsigned long exponent, int_bit;
4563: const unsigned char *ufrom = (const unsigned char *) from;
1.1.1.2 root 4564:
1.1 root 4565: exponent = get_field (ufrom, fmt->byteorder, fmt->totalsize,
4566: fmt->exp_start, fmt->exp_len);
4567: int_bit = get_field (ufrom, fmt->byteorder, fmt->totalsize,
4568: fmt->man_start, 1);
1.1.1.2 root 4569:
1.1 root 4570: if ((exponent == 0) != (int_bit == 0))
4571: return 0;
4572: else
4573: return 1;
4574: }
4575:
4576: const struct floatformat floatformat_i387_ext =
4577: {
4578: floatformat_little, 80, 0, 1, 15, 0x3fff, 0x7fff, 16, 64,
4579: floatformat_intbit_yes,
4580: "floatformat_i387_ext",
4581: floatformat_i387_ext_is_valid
4582: };
4583: const struct floatformat floatformat_m68881_ext =
4584: {
4585: /* Note that the bits from 16 to 31 are unused. */
4586: floatformat_big, 96, 0, 1, 15, 0x3fff, 0x7fff, 32, 64,
4587: floatformat_intbit_yes,
4588: "floatformat_m68881_ext",
4589: floatformat_always_valid
4590: };
4591: const struct floatformat floatformat_i960_ext =
4592: {
4593: /* Note that the bits from 0 to 15 are unused. */
4594: floatformat_little, 96, 16, 17, 15, 0x3fff, 0x7fff, 32, 64,
4595: floatformat_intbit_yes,
4596: "floatformat_i960_ext",
4597: floatformat_always_valid
4598: };
4599: const struct floatformat floatformat_m88110_ext =
4600: {
4601: floatformat_big, 80, 0, 1, 15, 0x3fff, 0x7fff, 16, 64,
4602: floatformat_intbit_yes,
4603: "floatformat_m88110_ext",
4604: floatformat_always_valid
4605: };
4606: const struct floatformat floatformat_m88110_harris_ext =
4607: {
4608: /* Harris uses raw format 128 bytes long, but the number is just an ieee
4609: double, and the last 64 bits are wasted. */
4610: floatformat_big,128, 0, 1, 11, 0x3ff, 0x7ff, 12, 52,
4611: floatformat_intbit_no,
4612: "floatformat_m88110_ext_harris",
4613: floatformat_always_valid
4614: };
4615: const struct floatformat floatformat_arm_ext_big =
4616: {
4617: /* Bits 1 to 16 are unused. */
4618: floatformat_big, 96, 0, 17, 15, 0x3fff, 0x7fff, 32, 64,
4619: floatformat_intbit_yes,
4620: "floatformat_arm_ext_big",
4621: floatformat_always_valid
4622: };
4623: const struct floatformat floatformat_arm_ext_littlebyte_bigword =
4624: {
4625: /* Bits 1 to 16 are unused. */
4626: floatformat_littlebyte_bigword, 96, 0, 17, 15, 0x3fff, 0x7fff, 32, 64,
4627: floatformat_intbit_yes,
4628: "floatformat_arm_ext_littlebyte_bigword",
4629: floatformat_always_valid
4630: };
4631: const struct floatformat floatformat_ia64_spill_big =
4632: {
4633: floatformat_big, 128, 0, 1, 17, 65535, 0x1ffff, 18, 64,
4634: floatformat_intbit_yes,
4635: "floatformat_ia64_spill_big",
4636: floatformat_always_valid
4637: };
4638: const struct floatformat floatformat_ia64_spill_little =
4639: {
4640: floatformat_little, 128, 0, 1, 17, 65535, 0x1ffff, 18, 64,
4641: floatformat_intbit_yes,
4642: "floatformat_ia64_spill_little",
4643: floatformat_always_valid
4644: };
4645: const struct floatformat floatformat_ia64_quad_big =
4646: {
4647: floatformat_big, 128, 0, 1, 15, 16383, 0x7fff, 16, 112,
4648: floatformat_intbit_no,
4649: "floatformat_ia64_quad_big",
4650: floatformat_always_valid
4651: };
4652: const struct floatformat floatformat_ia64_quad_little =
4653: {
4654: floatformat_little, 128, 0, 1, 15, 16383, 0x7fff, 16, 112,
4655: floatformat_intbit_no,
4656: "floatformat_ia64_quad_little",
4657: floatformat_always_valid
4658: };
4659:
4660: /* Extract a field which starts at START and is LEN bits long. DATA and
4661: TOTAL_LEN are the thing we are extracting it from, in byteorder ORDER. */
4662: static unsigned long
4663: get_field (const unsigned char *data, enum floatformat_byteorders order,
4664: unsigned int total_len, unsigned int start, unsigned int len)
4665: {
4666: unsigned long result;
4667: unsigned int cur_byte;
4668: int cur_bitshift;
4669:
4670: /* Start at the least significant part of the field. */
4671: cur_byte = (start + len) / FLOATFORMAT_CHAR_BIT;
4672: if (order == floatformat_little)
4673: cur_byte = (total_len / FLOATFORMAT_CHAR_BIT) - cur_byte - 1;
4674: cur_bitshift =
4675: ((start + len) % FLOATFORMAT_CHAR_BIT) - FLOATFORMAT_CHAR_BIT;
4676: result = *(data + cur_byte) >> (-cur_bitshift);
4677: cur_bitshift += FLOATFORMAT_CHAR_BIT;
4678: if (order == floatformat_little)
4679: ++cur_byte;
4680: else
4681: --cur_byte;
4682:
4683: /* Move towards the most significant part of the field. */
4684: while ((unsigned int) cur_bitshift < len)
4685: {
4686: if (len - cur_bitshift < FLOATFORMAT_CHAR_BIT)
4687: /* This is the last byte; zero out the bits which are not part of
4688: this field. */
4689: result |=
4690: (*(data + cur_byte) & ((1 << (len - cur_bitshift)) - 1))
4691: << cur_bitshift;
4692: else
4693: result |= *(data + cur_byte) << cur_bitshift;
4694: cur_bitshift += FLOATFORMAT_CHAR_BIT;
4695: if (order == floatformat_little)
4696: ++cur_byte;
4697: else
4698: --cur_byte;
4699: }
4700: return result;
4701: }
1.1.1.2 root 4702:
1.1 root 4703: #ifndef min
4704: #define min(a, b) ((a) < (b) ? (a) : (b))
4705: #endif
4706:
4707: /* Convert from FMT to a double.
4708: FROM is the address of the extended float.
4709: Store the double in *TO. */
4710:
4711: void
4712: floatformat_to_double (const struct floatformat *fmt,
4713: const char *from, double *to)
4714: {
4715: const unsigned char *ufrom = (const unsigned char *)from;
4716: double dto;
4717: long exponent;
4718: unsigned long mant;
4719: unsigned int mant_bits, mant_off;
4720: int mant_bits_left;
4721: int special_exponent; /* It's a NaN, denorm or zero */
4722:
4723: exponent = get_field (ufrom, fmt->byteorder, fmt->totalsize,
4724: fmt->exp_start, fmt->exp_len);
4725:
4726: /* If the exponent indicates a NaN, we don't have information to
4727: decide what to do. So we handle it like IEEE, except that we
4728: don't try to preserve the type of NaN. FIXME. */
4729: if ((unsigned long) exponent == fmt->exp_nan)
4730: {
4731: int nan;
4732:
4733: mant_off = fmt->man_start;
4734: mant_bits_left = fmt->man_len;
4735: nan = 0;
4736: while (mant_bits_left > 0)
4737: {
4738: mant_bits = min (mant_bits_left, 32);
4739:
4740: if (get_field (ufrom, fmt->byteorder, fmt->totalsize,
4741: mant_off, mant_bits) != 0)
4742: {
4743: /* This is a NaN. */
4744: nan = 1;
4745: break;
4746: }
4747:
4748: mant_off += mant_bits;
4749: mant_bits_left -= mant_bits;
4750: }
4751:
4752: /* On certain systems (such as GNU/Linux), the use of the
4753: INFINITY macro below may generate a warning that can not be
4754: silenced due to a bug in GCC (PR preprocessor/11931). The
4755: preprocessor fails to recognise the __extension__ keyword in
4756: conjunction with the GNU/C99 extension for hexadecimal
4757: floating point constants and will issue a warning when
4758: compiling with -pedantic. */
4759: if (nan)
4760: dto = NAN;
4761: else
4762: dto = INFINITY;
4763:
4764: if (get_field (ufrom, fmt->byteorder, fmt->totalsize, fmt->sign_start, 1))
4765: dto = -dto;
4766:
4767: *to = dto;
4768:
4769: return;
4770: }
4771:
4772: mant_bits_left = fmt->man_len;
4773: mant_off = fmt->man_start;
4774: dto = 0.0;
4775:
4776: special_exponent = exponent == 0 || (unsigned long) exponent == fmt->exp_nan;
4777:
4778: /* Don't bias zero's, denorms or NaNs. */
4779: if (!special_exponent)
4780: exponent -= fmt->exp_bias;
4781:
4782: /* Build the result algebraically. Might go infinite, underflow, etc;
4783: who cares. */
4784:
4785: /* If this format uses a hidden bit, explicitly add it in now. Otherwise,
4786: increment the exponent by one to account for the integer bit. */
4787:
4788: if (!special_exponent)
4789: {
4790: if (fmt->intbit == floatformat_intbit_no)
4791: dto = ldexp (1.0, exponent);
4792: else
4793: exponent++;
4794: }
4795:
4796: while (mant_bits_left > 0)
4797: {
4798: mant_bits = min (mant_bits_left, 32);
4799:
4800: mant = get_field (ufrom, fmt->byteorder, fmt->totalsize,
4801: mant_off, mant_bits);
4802:
4803: /* Handle denormalized numbers. FIXME: What should we do for
4804: non-IEEE formats? */
4805: if (exponent == 0 && mant != 0)
4806: dto += ldexp ((double)mant,
4807: (- fmt->exp_bias
4808: - mant_bits
4809: - (mant_off - fmt->man_start)
4810: + 1));
4811: else
4812: dto += ldexp ((double)mant, exponent - mant_bits);
4813: if (exponent != 0)
4814: exponent -= mant_bits;
4815: mant_off += mant_bits;
4816: mant_bits_left -= mant_bits;
4817: }
4818:
4819: /* Negate it if negative. */
4820: if (get_field (ufrom, fmt->byteorder, fmt->totalsize, fmt->sign_start, 1))
4821: dto = -dto;
4822: *to = dto;
4823: }
4824:
4825: static void put_field (unsigned char *, enum floatformat_byteorders,
4826: unsigned int,
4827: unsigned int,
4828: unsigned int,
4829: unsigned long);
4830:
4831: /* Set a field which starts at START and is LEN bits long. DATA and
4832: TOTAL_LEN are the thing we are extracting it from, in byteorder ORDER. */
4833: static void
4834: put_field (unsigned char *data, enum floatformat_byteorders order,
4835: unsigned int total_len, unsigned int start, unsigned int len,
4836: unsigned long stuff_to_put)
4837: {
4838: unsigned int cur_byte;
4839: int cur_bitshift;
4840:
4841: /* Start at the least significant part of the field. */
4842: cur_byte = (start + len) / FLOATFORMAT_CHAR_BIT;
4843: if (order == floatformat_little)
4844: cur_byte = (total_len / FLOATFORMAT_CHAR_BIT) - cur_byte - 1;
4845: cur_bitshift =
4846: ((start + len) % FLOATFORMAT_CHAR_BIT) - FLOATFORMAT_CHAR_BIT;
4847: *(data + cur_byte) &=
4848: ~(((1 << ((start + len) % FLOATFORMAT_CHAR_BIT)) - 1) << (-cur_bitshift));
4849: *(data + cur_byte) |=
4850: (stuff_to_put & ((1 << FLOATFORMAT_CHAR_BIT) - 1)) << (-cur_bitshift);
4851: cur_bitshift += FLOATFORMAT_CHAR_BIT;
4852: if (order == floatformat_little)
4853: ++cur_byte;
4854: else
4855: --cur_byte;
4856:
4857: /* Move towards the most significant part of the field. */
4858: while ((unsigned int) cur_bitshift < len)
4859: {
4860: if (len - cur_bitshift < FLOATFORMAT_CHAR_BIT)
4861: {
4862: /* This is the last byte. */
4863: *(data + cur_byte) &=
4864: ~((1 << (len - cur_bitshift)) - 1);
4865: *(data + cur_byte) |= (stuff_to_put >> cur_bitshift);
4866: }
4867: else
4868: *(data + cur_byte) = ((stuff_to_put >> cur_bitshift)
4869: & ((1 << FLOATFORMAT_CHAR_BIT) - 1));
4870: cur_bitshift += FLOATFORMAT_CHAR_BIT;
4871: if (order == floatformat_little)
4872: ++cur_byte;
4873: else
4874: --cur_byte;
4875: }
4876: }
4877:
4878: /* The converse: convert the double *FROM to an extended float
4879: and store where TO points. Neither FROM nor TO have any alignment
4880: restrictions. */
4881:
4882: void
4883: floatformat_from_double (const struct floatformat *fmt,
4884: const double *from, char *to)
4885: {
4886: double dfrom;
4887: int exponent;
4888: double mant;
4889: unsigned int mant_bits, mant_off;
4890: int mant_bits_left;
4891: unsigned char *uto = (unsigned char *)to;
4892:
4893: dfrom = *from;
4894: memset (uto, 0, fmt->totalsize / FLOATFORMAT_CHAR_BIT);
4895:
4896: /* If negative, set the sign bit. */
4897: if (dfrom < 0)
4898: {
4899: put_field (uto, fmt->byteorder, fmt->totalsize, fmt->sign_start, 1, 1);
4900: dfrom = -dfrom;
4901: }
4902:
4903: if (dfrom == 0)
4904: {
4905: /* 0.0. */
4906: return;
4907: }
4908:
4909: if (dfrom != dfrom)
4910: {
4911: /* NaN. */
4912: put_field (uto, fmt->byteorder, fmt->totalsize, fmt->exp_start,
4913: fmt->exp_len, fmt->exp_nan);
4914: /* Be sure it's not infinity, but NaN value is irrelevant. */
4915: put_field (uto, fmt->byteorder, fmt->totalsize, fmt->man_start,
4916: 32, 1);
4917: return;
4918: }
4919:
4920: if (dfrom + dfrom == dfrom)
4921: {
4922: /* This can only happen for an infinite value (or zero, which we
4923: already handled above). */
4924: put_field (uto, fmt->byteorder, fmt->totalsize, fmt->exp_start,
4925: fmt->exp_len, fmt->exp_nan);
4926: return;
4927: }
4928:
4929: mant = frexp (dfrom, &exponent);
4930: if (exponent + fmt->exp_bias - 1 > 0)
4931: put_field (uto, fmt->byteorder, fmt->totalsize, fmt->exp_start,
4932: fmt->exp_len, exponent + fmt->exp_bias - 1);
4933: else
4934: {
4935: /* Handle a denormalized number. FIXME: What should we do for
4936: non-IEEE formats? */
4937: put_field (uto, fmt->byteorder, fmt->totalsize, fmt->exp_start,
4938: fmt->exp_len, 0);
4939: mant = ldexp (mant, exponent + fmt->exp_bias - 1);
4940: }
4941:
4942: mant_bits_left = fmt->man_len;
4943: mant_off = fmt->man_start;
4944: while (mant_bits_left > 0)
4945: {
4946: unsigned long mant_long;
4947: mant_bits = mant_bits_left < 32 ? mant_bits_left : 32;
4948:
4949: mant *= 4294967296.0;
4950: mant_long = (unsigned long)mant;
4951: mant -= mant_long;
4952:
4953: /* If the integer bit is implicit, and we are not creating a
4954: denormalized number, then we need to discard it. */
4955: if ((unsigned int) mant_bits_left == fmt->man_len
4956: && fmt->intbit == floatformat_intbit_no
4957: && exponent + fmt->exp_bias - 1 > 0)
4958: {
4959: mant_long &= 0x7fffffff;
4960: mant_bits -= 1;
4961: }
4962: else if (mant_bits < 32)
4963: {
4964: /* The bits we want are in the most significant MANT_BITS bits of
4965: mant_long. Move them to the least significant. */
4966: mant_long >>= 32 - mant_bits;
4967: }
4968:
4969: put_field (uto, fmt->byteorder, fmt->totalsize,
4970: mant_off, mant_bits, mant_long);
4971: mant_off += mant_bits;
4972: mant_bits_left -= mant_bits;
4973: }
4974: }
4975:
4976: /* Return non-zero iff the data at FROM is a valid number in format FMT. */
4977:
4978: int
4979: floatformat_is_valid (const struct floatformat *fmt, const char *from)
4980: {
4981: return fmt->is_valid (fmt, from);
4982: }
4983:
4984:
4985: #ifdef IEEE_DEBUG
4986:
4987: /* This is to be run on a host which uses IEEE floating point. */
4988:
4989: void
4990: ieee_test (double n)
4991: {
4992: double result;
4993:
4994: floatformat_to_double (&floatformat_ieee_double_little, (char *) &n,
4995: &result);
4996: if ((n != result && (! isnan (n) || ! isnan (result)))
4997: || (n < 0 && result >= 0)
4998: || (n >= 0 && result < 0))
4999: printf ("Differ(to): %.20g -> %.20g\n", n, result);
5000:
5001: floatformat_from_double (&floatformat_ieee_double_little, &n,
5002: (char *) &result);
5003: if ((n != result && (! isnan (n) || ! isnan (result)))
5004: || (n < 0 && result >= 0)
5005: || (n >= 0 && result < 0))
5006: printf ("Differ(from): %.20g -> %.20g\n", n, result);
5007:
5008: #if 0
5009: {
5010: char exten[16];
5011:
5012: floatformat_from_double (&floatformat_m68881_ext, &n, exten);
5013: floatformat_to_double (&floatformat_m68881_ext, exten, &result);
5014: if (n != result)
5015: printf ("Differ(to+from): %.20g -> %.20g\n", n, result);
5016: }
5017: #endif
5018:
5019: #if IEEE_DEBUG > 1
5020: /* This is to be run on a host which uses 68881 format. */
5021: {
5022: long double ex = *(long double *)exten;
5023: if (ex != n)
5024: printf ("Differ(from vs. extended): %.20g\n", n);
5025: }
5026: #endif
5027: }
5028:
5029: int
5030: main (void)
5031: {
5032: ieee_test (0.0);
5033: ieee_test (0.5);
5034: ieee_test (256.0);
5035: ieee_test (0.12345);
5036: ieee_test (234235.78907234);
5037: ieee_test (-512.0);
5038: ieee_test (-0.004321);
5039: ieee_test (1.2E-70);
5040: ieee_test (1.2E-316);
5041: ieee_test (4.9406564584124654E-324);
5042: ieee_test (- 4.9406564584124654E-324);
5043: ieee_test (- 0.0);
5044: ieee_test (- INFINITY);
5045: ieee_test (- NAN);
5046: ieee_test (INFINITY);
5047: ieee_test (NAN);
5048: return 0;
5049: }
5050: #endif
5051: /* **** End of floatformat.c */
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