File:  [Qemu by Fabrice Bellard] / qemu / microblaze-dis.c
Revision 1.1.1.4 (vendor branch): download - view: text, annotated - select for diffs
Tue Apr 24 18:33:11 2018 UTC (3 years, 4 months ago) by root
Branches: qemu, MAIN
CVS tags: qemu1101, qemu1001, qemu1000, qemu0151, qemu0150, qemu0141, qemu0140, HEAD
qemu 0.14.0

    1: /* Disassemble Xilinx microblaze instructions.
    2:    Copyright (C) 1993, 1999, 2000 Free Software Foundation, Inc.
    3: 
    4: This program is free software; you can redistribute it and/or modify
    5: it under the terms of the GNU General Public License as published by
    6: the Free Software Foundation; either version 2 of the License, or
    7: (at your option) any later version.
    8: 
    9: This program is distributed in the hope that it will be useful,
   10: but WITHOUT ANY WARRANTY; without even the implied warranty of
   11: MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
   12: GNU General Public License for more details.
   13: 
   14: You should have received a copy of the GNU General Public License
   15: along with this program; if not, see <http://www.gnu.org/licenses/>. */
   16: 
   17: /*
   18:  * Copyright (c) 2001 Xilinx, Inc.  All rights reserved. 
   19:  *
   20:  * Redistribution and use in source and binary forms are permitted
   21:  * provided that the above copyright notice and this paragraph are
   22:  * duplicated in all such forms and that any documentation,
   23:  * advertising materials, and other materials related to such
   24:  * distribution and use acknowledge that the software was developed
   25:  * by Xilinx, Inc.  The name of the Company may not be used to endorse 
   26:  * or promote products derived from this software without specific prior 
   27:  * written permission.
   28:  * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
   29:  * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
   30:  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.
   31:  *
   32:  *	Xilinx, Inc.
   33:  */
   34: 
   35: 
   36: #include <stdio.h>
   37: #define STATIC_TABLE
   38: #define DEFINE_TABLE
   39: 
   40: #define TRUE   1
   41: #define FALSE  0
   42: 
   43: #ifndef MICROBLAZE_OPC
   44: #define MICROBLAZE_OPC
   45: /* Assembler instructions for Xilinx's microblaze processor
   46:    Copyright (C) 1999, 2000 Free Software Foundation, Inc.
   47: 
   48:    
   49: This program is free software; you can redistribute it and/or modify
   50: it under the terms of the GNU General Public License as published by
   51: the Free Software Foundation; either version 2 of the License, or
   52: (at your option) any later version.
   53: 
   54: This program is distributed in the hope that it will be useful,
   55: but WITHOUT ANY WARRANTY; without even the implied warranty of
   56: MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
   57: GNU General Public License for more details.
   58: 
   59: You should have received a copy of the GNU General Public License
   60: along with this program; if not, see <http://www.gnu.org/licenses/>.  */
   61: 
   62: /*
   63:  * Copyright (c) 2001 Xilinx, Inc.  All rights reserved. 
   64:  *
   65:  * Redistribution and use in source and binary forms are permitted
   66:  * provided that the above copyright notice and this paragraph are
   67:  * duplicated in all such forms and that any documentation,
   68:  * advertising materials, and other materials related to such
   69:  * distribution and use acknowledge that the software was developed
   70:  * by Xilinx, Inc.  The name of the Company may not be used to endorse 
   71:  * or promote products derived from this software without specific prior 
   72:  * written permission.
   73:  * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
   74:  * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
   75:  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.
   76:  *
   77:  *	Xilinx, Inc.
   78:  */
   79: 
   80: 
   81: #ifndef MICROBLAZE_OPCM
   82: #define MICROBLAZE_OPCM
   83: 
   84: /*
   85:  * Copyright (c) 2001 Xilinx, Inc.  All rights reserved. 
   86:  *
   87:  * Redistribution and use in source and binary forms are permitted
   88:  * provided that the above copyright notice and this paragraph are
   89:  * duplicated in all such forms and that any documentation,
   90:  * advertising materials, and other materials related to such
   91:  * distribution and use acknowledge that the software was developed
   92:  * by Xilinx, Inc.  The name of the Company may not be used to endorse 
   93:  * or promote products derived from this software without specific prior 
   94:  * written permission.
   95:  * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
   96:  * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
   97:  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.
   98:  *
   99:  *	Xilinx, Inc.
  100:  * $Header:
  101:  */
  102: 
  103: enum microblaze_instr {
  104:    add, rsub, addc, rsubc, addk, rsubk, addkc, rsubkc, cmp, cmpu,
  105:    addi, rsubi, addic, rsubic, addik, rsubik, addikc, rsubikc, mul, mulh, mulhu, mulhsu,
  106:    idiv, idivu, bsll, bsra, bsrl, get, put, nget, nput, cget, cput,
  107:    ncget, ncput, muli, bslli, bsrai, bsrli, mului, or, and, xor,
  108:    andn, pcmpbf, pcmpbc, pcmpeq, pcmpne, sra, src, srl, sext8, sext16, wic, wdc, wdcclear, wdcflush, mts, mfs, br, brd,
  109:    brld, bra, brad, brald, microblaze_brk, beq, beqd, bne, bned, blt,
  110:    bltd, ble, bled, bgt, bgtd, bge, bged, ori, andi, xori, andni,
  111:    imm, rtsd, rtid, rtbd, rted, bri, brid, brlid, brai, braid, bralid,
  112:    brki, beqi, beqid, bnei, bneid, blti, bltid, blei, bleid, bgti,
  113:    bgtid, bgei, bgeid, lbu, lhu, lw, lwx, sb, sh, sw, swx, lbui, lhui, lwi,
  114:    sbi, shi, swi, msrset, msrclr, tuqula, fadd, frsub, fmul, fdiv, 
  115:    fcmp_lt, fcmp_eq, fcmp_le, fcmp_gt, fcmp_ne, fcmp_ge, fcmp_un, flt, fint, fsqrt, 
  116:    tget, tcget, tnget, tncget, tput, tcput, tnput, tncput,
  117:    eget, ecget, neget, necget, eput, ecput, neput, necput,
  118:    teget, tecget, tneget, tnecget, teput, tecput, tneput, tnecput,
  119:    aget, caget, naget, ncaget, aput, caput, naput, ncaput,
  120:    taget, tcaget, tnaget, tncaget, taput, tcaput, tnaput, tncaput,
  121:    eaget, ecaget, neaget, necaget, eaput, ecaput, neaput, necaput,
  122:    teaget, tecaget, tneaget, tnecaget, teaput, tecaput, tneaput, tnecaput,
  123:    getd, tgetd, cgetd, tcgetd, ngetd, tngetd, ncgetd, tncgetd,
  124:    putd, tputd, cputd, tcputd, nputd, tnputd, ncputd, tncputd,
  125:    egetd, tegetd, ecgetd, tecgetd, negetd, tnegetd, necgetd, tnecgetd,
  126:    eputd, teputd, ecputd, tecputd, neputd, tneputd, necputd, tnecputd,
  127:    agetd, tagetd, cagetd, tcagetd, nagetd, tnagetd, ncagetd, tncagetd,
  128:    aputd, taputd, caputd, tcaputd, naputd, tnaputd, ncaputd, tncaputd,
  129:    eagetd, teagetd, ecagetd, tecagetd, neagetd, tneagetd, necagetd, tnecagetd,
  130:    eaputd, teaputd, ecaputd, tecaputd, neaputd, tneaputd, necaputd, tnecaputd,
  131:    invalid_inst } ;
  132: 
  133: enum microblaze_instr_type {
  134:    arithmetic_inst, logical_inst, mult_inst, div_inst, branch_inst,
  135:    return_inst, immediate_inst, special_inst, memory_load_inst,
  136:    memory_store_inst, barrel_shift_inst, anyware_inst };
  137: 
  138: #define INST_WORD_SIZE 4
  139: 
  140: /* gen purpose regs go from 0 to 31 */
  141: /* mask is reg num - max_reg_num, ie reg_num - 32 in this case */
  142: 
  143: #define REG_PC_MASK 0x8000
  144: #define REG_MSR_MASK 0x8001
  145: #define REG_EAR_MASK 0x8003
  146: #define REG_ESR_MASK 0x8005
  147: #define REG_FSR_MASK 0x8007
  148: #define REG_BTR_MASK 0x800b
  149: #define REG_EDR_MASK 0x800d
  150: #define REG_PVR_MASK 0xa000
  151: 
  152: #define REG_PID_MASK   0x9000
  153: #define REG_ZPR_MASK   0x9001
  154: #define REG_TLBX_MASK  0x9002
  155: #define REG_TLBLO_MASK 0x9003
  156: #define REG_TLBHI_MASK 0x9004
  157: #define REG_TLBSX_MASK 0x9005
  158: 
  159: #define MIN_REGNUM 0
  160: #define MAX_REGNUM 31
  161: 
  162: #define MIN_PVR_REGNUM 0
  163: #define MAX_PVR_REGNUM 15
  164: 
  165: #define REG_PC  32 /* PC */
  166: #define REG_MSR 33 /* machine status reg */
  167: #define REG_EAR 35 /* Exception reg */
  168: #define REG_ESR 37 /* Exception reg */
  169: #define REG_FSR 39 /* FPU Status reg */
  170: #define REG_BTR 43 /* Branch Target reg */
  171: #define REG_EDR 45 /* Exception reg */
  172: #define REG_PVR 40960 /* Program Verification reg */
  173: 
  174: #define REG_PID   36864 /* MMU: Process ID reg       */
  175: #define REG_ZPR   36865 /* MMU: Zone Protect reg     */
  176: #define REG_TLBX  36866 /* MMU: TLB Index reg        */
  177: #define REG_TLBLO 36867 /* MMU: TLB Low reg          */
  178: #define REG_TLBHI 36868 /* MMU: TLB High reg         */
  179: #define REG_TLBSX 36869 /* MMU: TLB Search Index reg */
  180: 
  181: /* alternate names for gen purpose regs */
  182: #define REG_SP  1 /* stack pointer */
  183: #define REG_ROSDP 2 /* read-only small data pointer */
  184: #define REG_RWSDP 13 /* read-write small data pointer */
  185: 
  186: /* Assembler Register - Used in Delay Slot Optimization */
  187: #define REG_AS    18
  188: #define REG_ZERO  0
  189:  
  190: #define RD_LOW  21 /* low bit for RD */
  191: #define RA_LOW  16 /* low bit for RA */
  192: #define RB_LOW  11 /* low bit for RB */
  193: #define IMM_LOW  0 /* low bit for immediate */
  194: 
  195: #define RD_MASK 0x03E00000
  196: #define RA_MASK 0x001F0000
  197: #define RB_MASK 0x0000F800
  198: #define IMM_MASK 0x0000FFFF
  199: 
  200: // imm mask for barrel shifts
  201: #define IMM5_MASK 0x0000001F
  202: 
  203: 
  204: // FSL imm mask for get, put instructions
  205: #define  RFSL_MASK 0x000000F
  206: 
  207: // imm mask for msrset, msrclr instructions
  208: #define  IMM15_MASK 0x00007FFF
  209: 
  210: #endif /* MICROBLAZE-OPCM */
  211: 
  212: #define INST_TYPE_RD_R1_R2 0
  213: #define INST_TYPE_RD_R1_IMM 1
  214: #define INST_TYPE_RD_R1_UNSIGNED_IMM 2
  215: #define INST_TYPE_RD_R1 3
  216: #define INST_TYPE_RD_R2 4
  217: #define INST_TYPE_RD_IMM 5
  218: #define INST_TYPE_R2 6
  219: #define INST_TYPE_R1_R2 7
  220: #define INST_TYPE_R1_IMM 8
  221: #define INST_TYPE_IMM 9
  222: #define INST_TYPE_SPECIAL_R1 10
  223: #define INST_TYPE_RD_SPECIAL 11
  224: #define INST_TYPE_R1 12
  225:   // new instn type for barrel shift imms
  226: #define INST_TYPE_RD_R1_IMM5  13
  227: #define INST_TYPE_RD_RFSL    14
  228: #define INST_TYPE_R1_RFSL    15
  229: 
  230:   // new insn type for insn cache
  231: #define INST_TYPE_RD_R1_SPECIAL 16
  232: 
  233: // new insn type for msrclr, msrset insns.
  234: #define INST_TYPE_RD_IMM15    17
  235: 
  236: // new insn type for tuqula rd - addik rd, r0, 42
  237: #define INST_TYPE_RD    18
  238: 
  239: // new insn type for t*put
  240: #define INST_TYPE_RFSL  19
  241: 
  242: #define INST_TYPE_NONE 25
  243: 
  244: 
  245: 
  246: #define INST_PC_OFFSET 1 /* instructions where the label address is resolved as a PC offset (for branch label)*/
  247: #define INST_NO_OFFSET 0 /* instructions where the label address is resolved as an absolute value (for data mem or abs address)*/
  248: 
  249: #define IMMVAL_MASK_NON_SPECIAL 0x0000
  250: #define IMMVAL_MASK_MTS 0x4000
  251: #define IMMVAL_MASK_MFS 0x0000
  252: 
  253: #define OPCODE_MASK_H   0xFC000000 /* High 6 bits only */
  254: #define OPCODE_MASK_H1  0xFFE00000 /* High 11 bits */
  255: #define OPCODE_MASK_H2  0xFC1F0000 /* High 6 and bits 20-16 */
  256: #define OPCODE_MASK_H12 0xFFFF0000 /* High 16 */
  257: #define OPCODE_MASK_H4  0xFC0007FF /* High 6 and low 11 bits */
  258: #define OPCODE_MASK_H13S 0xFFE0EFF0 /* High 11 and 15:1 bits and last nibble of last byte for spr */
  259: #define OPCODE_MASK_H23S 0xFC1FC000 /* High 6, 20-16 and 15:1 bits and last nibble of last byte for spr */
  260: #define OPCODE_MASK_H34 0xFC00FFFF /* High 6 and low 16 bits */
  261: #define OPCODE_MASK_H14 0xFFE007FF /* High 11 and low 11 bits */
  262: #define OPCODE_MASK_H24 0xFC1F07FF /* High 6, bits 20-16 and low 11 bits */
  263: #define OPCODE_MASK_H124  0xFFFF07FF /* High 16, and low 11 bits */
  264: #define OPCODE_MASK_H1234 0xFFFFFFFF /* All 32 bits */
  265: #define OPCODE_MASK_H3  0xFC000600 /* High 6 bits and bits 21, 22 */  
  266: #define OPCODE_MASK_H32 0xFC00FC00 /* High 6 bits and bit 16-21 */
  267: #define OPCODE_MASK_H34B   0xFC0000FF /* High 6 bits and low 8 bits */
  268: #define OPCODE_MASK_H34C   0xFC0007E0 /* High 6 bits and bits 21-26 */
  269: 
  270: // New Mask for msrset, msrclr insns.
  271: #define OPCODE_MASK_H23N  0xFC1F8000 /* High 6 and bits 11 - 16 */
  272: 
  273: #define DELAY_SLOT 1
  274: #define NO_DELAY_SLOT 0
  275: 
  276: #define MAX_OPCODES 280
  277: 
  278: struct op_code_struct {
  279:   const char *name;
  280:   short inst_type; /* registers and immediate values involved */
  281:   short inst_offset_type; /* immediate vals offset from PC? (= 1 for branches) */
  282:   short delay_slots; /* info about delay slots needed after this instr. */
  283:   short immval_mask;
  284:   unsigned long bit_sequence; /* all the fixed bits for the op are set and all the variable bits (reg names, imm vals) are set to 0 */ 
  285:   unsigned long opcode_mask; /* which bits define the opcode */
  286:   enum microblaze_instr instr;
  287:   enum microblaze_instr_type instr_type;
  288:   /* more info about output format here */
  289: } opcodes[MAX_OPCODES] = 
  290: 
  291: { 
  292:   {"add",   INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x00000000, OPCODE_MASK_H4, add, arithmetic_inst },
  293:   {"rsub",  INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x04000000, OPCODE_MASK_H4, rsub, arithmetic_inst },
  294:   {"addc",  INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x08000000, OPCODE_MASK_H4, addc, arithmetic_inst },
  295:   {"rsubc", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x0C000000, OPCODE_MASK_H4, rsubc, arithmetic_inst },
  296:   {"addk",  INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x10000000, OPCODE_MASK_H4, addk, arithmetic_inst },
  297:   {"rsubk", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x14000000, OPCODE_MASK_H4, rsubk, arithmetic_inst },
  298:   {"cmp",   INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x14000001, OPCODE_MASK_H4, cmp, arithmetic_inst },
  299:   {"cmpu",  INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x14000003, OPCODE_MASK_H4, cmpu, arithmetic_inst },
  300:   {"addkc", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x18000000, OPCODE_MASK_H4, addkc, arithmetic_inst },
  301:   {"rsubkc",INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x1C000000, OPCODE_MASK_H4, rsubkc, arithmetic_inst },
  302:   {"addi",  INST_TYPE_RD_R1_IMM, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x20000000, OPCODE_MASK_H, addi, arithmetic_inst },
  303:   {"rsubi", INST_TYPE_RD_R1_IMM, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x24000000, OPCODE_MASK_H, rsubi, arithmetic_inst },
  304:   {"addic", INST_TYPE_RD_R1_IMM, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x28000000, OPCODE_MASK_H, addic, arithmetic_inst },
  305:   {"rsubic",INST_TYPE_RD_R1_IMM, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x2C000000, OPCODE_MASK_H, rsubic, arithmetic_inst },
  306:   {"addik", INST_TYPE_RD_R1_IMM, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x30000000, OPCODE_MASK_H, addik, arithmetic_inst },
  307:   {"rsubik",INST_TYPE_RD_R1_IMM, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x34000000, OPCODE_MASK_H, rsubik, arithmetic_inst },
  308:   {"addikc",INST_TYPE_RD_R1_IMM, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x38000000, OPCODE_MASK_H, addikc, arithmetic_inst },
  309:   {"rsubikc",INST_TYPE_RD_R1_IMM, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x3C000000, OPCODE_MASK_H, rsubikc, arithmetic_inst },
  310:   {"mul",   INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x40000000, OPCODE_MASK_H4, mul, mult_inst },
  311:   {"mulh",  INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x40000001, OPCODE_MASK_H4, mulh, mult_inst },
  312:   {"mulhu", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x40000003, OPCODE_MASK_H4, mulhu, mult_inst },
  313:   {"mulhsu",INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x40000002, OPCODE_MASK_H4, mulhsu, mult_inst },
  314:   {"idiv",  INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x48000000, OPCODE_MASK_H4, idiv, div_inst },
  315:   {"idivu", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x48000002, OPCODE_MASK_H4, idivu, div_inst },
  316:   {"bsll",  INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x44000400, OPCODE_MASK_H3, bsll, barrel_shift_inst },
  317:   {"bsra",  INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x44000200, OPCODE_MASK_H3, bsra, barrel_shift_inst },
  318:   {"bsrl",  INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x44000000, OPCODE_MASK_H3, bsrl, barrel_shift_inst },
  319:   {"get",   INST_TYPE_RD_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C000000, OPCODE_MASK_H32, get, anyware_inst },
  320:   {"put",   INST_TYPE_R1_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C008000, OPCODE_MASK_H32, put, anyware_inst },
  321:   {"nget",  INST_TYPE_RD_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C004000, OPCODE_MASK_H32, nget, anyware_inst },
  322:   {"nput",  INST_TYPE_R1_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C00C000, OPCODE_MASK_H32, nput, anyware_inst },
  323:   {"cget",  INST_TYPE_RD_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C002000, OPCODE_MASK_H32, cget, anyware_inst },
  324:   {"cput",  INST_TYPE_R1_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C00A000, OPCODE_MASK_H32, cput, anyware_inst },
  325:   {"ncget", INST_TYPE_RD_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C006000, OPCODE_MASK_H32, ncget, anyware_inst },
  326:   {"ncput", INST_TYPE_R1_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C00E000, OPCODE_MASK_H32, ncput, anyware_inst },
  327:   {"muli",  INST_TYPE_RD_R1_IMM, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x60000000, OPCODE_MASK_H, muli, mult_inst },
  328:   {"bslli", INST_TYPE_RD_R1_IMM5, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x64000400, OPCODE_MASK_H3, bslli, barrel_shift_inst },
  329:   {"bsrai", INST_TYPE_RD_R1_IMM5, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x64000200, OPCODE_MASK_H3, bsrai, barrel_shift_inst },
  330:   {"bsrli", INST_TYPE_RD_R1_IMM5, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x64000000, OPCODE_MASK_H3, bsrli, barrel_shift_inst },
  331:   {"or",    INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x80000000, OPCODE_MASK_H4, or, logical_inst },
  332:   {"and",   INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x84000000, OPCODE_MASK_H4, and, logical_inst },
  333:   {"xor",   INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x88000000, OPCODE_MASK_H4, xor, logical_inst },
  334:   {"andn",  INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x8C000000, OPCODE_MASK_H4, andn, logical_inst },
  335:   {"pcmpbf",INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x80000400, OPCODE_MASK_H4, pcmpbf, logical_inst },
  336:   {"pcmpbc",INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x84000400, OPCODE_MASK_H4, pcmpbc, logical_inst },
  337:   {"pcmpeq",INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x88000400, OPCODE_MASK_H4, pcmpeq, logical_inst },
  338:   {"pcmpne",INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x8C000400, OPCODE_MASK_H4, pcmpne, logical_inst },
  339:   {"sra",   INST_TYPE_RD_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x90000001, OPCODE_MASK_H34, sra, logical_inst },
  340:   {"src",   INST_TYPE_RD_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x90000021, OPCODE_MASK_H34, src, logical_inst },
  341:   {"srl",   INST_TYPE_RD_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x90000041, OPCODE_MASK_H34, srl, logical_inst },
  342:   {"sext8", INST_TYPE_RD_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x90000060, OPCODE_MASK_H34, sext8, logical_inst },
  343:   {"sext16",INST_TYPE_RD_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x90000061, OPCODE_MASK_H34, sext16, logical_inst },
  344:   {"wic",   INST_TYPE_RD_R1_SPECIAL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x90000068, OPCODE_MASK_H34B, wic, special_inst },
  345:   {"wdc",   INST_TYPE_RD_R1_SPECIAL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x90000064, OPCODE_MASK_H34B, wdc, special_inst },
  346:   {"wdc.clear", INST_TYPE_RD_R1_SPECIAL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x90000066, OPCODE_MASK_H34B, wdcclear, special_inst },
  347:   {"wdc.flush", INST_TYPE_RD_R1_SPECIAL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x90000074, OPCODE_MASK_H34B, wdcflush, special_inst },
  348:   {"mts",   INST_TYPE_SPECIAL_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_MTS, 0x9400C000, OPCODE_MASK_H13S, mts, special_inst },
  349:   {"mfs",   INST_TYPE_RD_SPECIAL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_MFS, 0x94008000, OPCODE_MASK_H23S, mfs, special_inst },
  350:   {"br",    INST_TYPE_R2, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x98000000, OPCODE_MASK_H124, br, branch_inst },
  351:   {"brd",   INST_TYPE_R2, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x98100000, OPCODE_MASK_H124, brd, branch_inst },
  352:   {"brld",  INST_TYPE_RD_R2, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x98140000, OPCODE_MASK_H24, brld, branch_inst },
  353:   {"bra",   INST_TYPE_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x98080000, OPCODE_MASK_H124, bra, branch_inst },
  354:   {"brad",  INST_TYPE_R2, INST_NO_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x98180000, OPCODE_MASK_H124, brad, branch_inst },
  355:   {"brald", INST_TYPE_RD_R2, INST_NO_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x981C0000, OPCODE_MASK_H24, brald, branch_inst },
  356:   {"brk",   INST_TYPE_RD_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x980C0000, OPCODE_MASK_H24, microblaze_brk, branch_inst },
  357:   {"beq",   INST_TYPE_R1_R2, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9C000000, OPCODE_MASK_H14, beq, branch_inst },
  358:   {"beqd",  INST_TYPE_R1_R2, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9E000000, OPCODE_MASK_H14, beqd, branch_inst },
  359:   {"bne",   INST_TYPE_R1_R2, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9C200000, OPCODE_MASK_H14, bne, branch_inst },
  360:   {"bned",  INST_TYPE_R1_R2, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9E200000, OPCODE_MASK_H14, bned, branch_inst },
  361:   {"blt",   INST_TYPE_R1_R2, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9C400000, OPCODE_MASK_H14, blt, branch_inst },
  362:   {"bltd",  INST_TYPE_R1_R2, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9E400000, OPCODE_MASK_H14, bltd, branch_inst },
  363:   {"ble",   INST_TYPE_R1_R2, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9C600000, OPCODE_MASK_H14, ble, branch_inst },
  364:   {"bled",  INST_TYPE_R1_R2, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9E600000, OPCODE_MASK_H14, bled, branch_inst },
  365:   {"bgt",   INST_TYPE_R1_R2, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9C800000, OPCODE_MASK_H14, bgt, branch_inst },
  366:   {"bgtd",  INST_TYPE_R1_R2, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9E800000, OPCODE_MASK_H14, bgtd, branch_inst },
  367:   {"bge",   INST_TYPE_R1_R2, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9CA00000, OPCODE_MASK_H14, bge, branch_inst },
  368:   {"bged",  INST_TYPE_R1_R2, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9EA00000, OPCODE_MASK_H14, bged, branch_inst },
  369:   {"ori",   INST_TYPE_RD_R1_IMM, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xA0000000, OPCODE_MASK_H, ori, logical_inst },
  370:   {"andi",  INST_TYPE_RD_R1_IMM, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xA4000000, OPCODE_MASK_H, andi, logical_inst },
  371:   {"xori",  INST_TYPE_RD_R1_IMM, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xA8000000, OPCODE_MASK_H, xori, logical_inst },
  372:   {"andni", INST_TYPE_RD_R1_IMM, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xAC000000, OPCODE_MASK_H, andni, logical_inst },
  373:   {"imm",   INST_TYPE_IMM, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xB0000000, OPCODE_MASK_H12, imm, immediate_inst },
  374:   {"rtsd",  INST_TYPE_R1_IMM, INST_NO_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xB6000000, OPCODE_MASK_H1, rtsd, return_inst },
  375:   {"rtid",  INST_TYPE_R1_IMM, INST_NO_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xB6200000, OPCODE_MASK_H1, rtid, return_inst },
  376:   {"rtbd",  INST_TYPE_R1_IMM, INST_NO_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xB6400000, OPCODE_MASK_H1, rtbd, return_inst },
  377:   {"rted",  INST_TYPE_R1_IMM, INST_NO_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xB6800000, OPCODE_MASK_H1, rted, return_inst },
  378:   {"bri",   INST_TYPE_IMM, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xB8000000, OPCODE_MASK_H12, bri, branch_inst },
  379:   {"brid",  INST_TYPE_IMM, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xB8100000, OPCODE_MASK_H12, brid, branch_inst },
  380:   {"brlid", INST_TYPE_RD_IMM, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xB8140000, OPCODE_MASK_H2, brlid, branch_inst },
  381:   {"brai",  INST_TYPE_IMM, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xB8080000, OPCODE_MASK_H12, brai, branch_inst },
  382:   {"braid", INST_TYPE_IMM, INST_NO_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xB8180000, OPCODE_MASK_H12, braid, branch_inst },
  383:   {"bralid",INST_TYPE_RD_IMM, INST_NO_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xB81C0000, OPCODE_MASK_H2, bralid, branch_inst },
  384:   {"brki",  INST_TYPE_RD_IMM, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xB80C0000, OPCODE_MASK_H2, brki, branch_inst },
  385:   {"beqi",  INST_TYPE_R1_IMM, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBC000000, OPCODE_MASK_H1, beqi, branch_inst },
  386:   {"beqid", INST_TYPE_R1_IMM, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBE000000, OPCODE_MASK_H1, beqid, branch_inst },
  387:   {"bnei",  INST_TYPE_R1_IMM, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBC200000, OPCODE_MASK_H1, bnei, branch_inst },
  388:   {"bneid", INST_TYPE_R1_IMM, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBE200000, OPCODE_MASK_H1, bneid, branch_inst },
  389:   {"blti",  INST_TYPE_R1_IMM, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBC400000, OPCODE_MASK_H1, blti, branch_inst },
  390:   {"bltid", INST_TYPE_R1_IMM, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBE400000, OPCODE_MASK_H1, bltid, branch_inst },
  391:   {"blei",  INST_TYPE_R1_IMM, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBC600000, OPCODE_MASK_H1, blei, branch_inst },
  392:   {"bleid", INST_TYPE_R1_IMM, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBE600000, OPCODE_MASK_H1, bleid, branch_inst },
  393:   {"bgti",  INST_TYPE_R1_IMM, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBC800000, OPCODE_MASK_H1, bgti, branch_inst },
  394:   {"bgtid", INST_TYPE_R1_IMM, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBE800000, OPCODE_MASK_H1, bgtid, branch_inst },
  395:   {"bgei",  INST_TYPE_R1_IMM, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBCA00000, OPCODE_MASK_H1, bgei, branch_inst },
  396:   {"bgeid", INST_TYPE_R1_IMM, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBEA00000, OPCODE_MASK_H1, bgeid, branch_inst },
  397:   {"lbu",   INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xC0000000, OPCODE_MASK_H4, lbu, memory_load_inst },
  398:   {"lhu",   INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xC4000000, OPCODE_MASK_H4, lhu, memory_load_inst },
  399:   {"lw",    INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xC8000000, OPCODE_MASK_H4, lw, memory_load_inst },
  400:   {"lwx",   INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xC8000400, OPCODE_MASK_H4, lwx, memory_load_inst },
  401:   {"sb",    INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xD0000000, OPCODE_MASK_H4, sb, memory_store_inst },
  402:   {"sh",    INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xD4000000, OPCODE_MASK_H4, sh, memory_store_inst },
  403:   {"sw",    INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xD8000000, OPCODE_MASK_H4, sw, memory_store_inst },
  404:   {"swx",   INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xD8000400, OPCODE_MASK_H4, swx, memory_store_inst },
  405:   {"lbui",  INST_TYPE_RD_R1_IMM, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xE0000000, OPCODE_MASK_H, lbui, memory_load_inst },
  406:   {"lhui",  INST_TYPE_RD_R1_IMM, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xE4000000, OPCODE_MASK_H, lhui, memory_load_inst },
  407:   {"lwi",   INST_TYPE_RD_R1_IMM, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xE8000000, OPCODE_MASK_H, lwi, memory_load_inst },
  408:   {"sbi",   INST_TYPE_RD_R1_IMM, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xF0000000, OPCODE_MASK_H, sbi, memory_store_inst },
  409:   {"shi",   INST_TYPE_RD_R1_IMM, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xF4000000, OPCODE_MASK_H, shi, memory_store_inst },
  410:   {"swi",   INST_TYPE_RD_R1_IMM, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xF8000000, OPCODE_MASK_H, swi, memory_store_inst },
  411:   {"nop",   INST_TYPE_NONE, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x80000000, OPCODE_MASK_H1234, invalid_inst, logical_inst }, /* translates to or r0, r0, r0 */
  412:   {"la",    INST_TYPE_RD_R1_IMM, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x30000000, OPCODE_MASK_H, invalid_inst, arithmetic_inst }, /* la translates to addik */
  413:   {"tuqula",INST_TYPE_RD, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x3000002A, OPCODE_MASK_H, invalid_inst, arithmetic_inst }, /* tuqula rd translates to addik rd, r0, 42 */
  414:   {"not",   INST_TYPE_RD_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xA800FFFF, OPCODE_MASK_H34, invalid_inst, logical_inst }, /* not translates to xori rd,ra,-1 */
  415:   {"neg",   INST_TYPE_RD_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x04000000, OPCODE_MASK_H, invalid_inst, arithmetic_inst }, /* neg translates to rsub rd, ra, r0 */
  416:   {"rtb",   INST_TYPE_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xB6000004, OPCODE_MASK_H1, invalid_inst, return_inst }, /* rtb translates to rts rd, 4 */
  417:   {"sub",   INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x04000000, OPCODE_MASK_H, invalid_inst, arithmetic_inst }, /* sub translates to rsub rd, rb, ra */
  418:   {"lmi",   INST_TYPE_RD_R1_IMM, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xE8000000, OPCODE_MASK_H, invalid_inst, memory_load_inst },
  419:   {"smi",   INST_TYPE_RD_R1_IMM, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xF8000000, OPCODE_MASK_H, invalid_inst, memory_store_inst },
  420:   {"msrset",INST_TYPE_RD_IMM15, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x94100000, OPCODE_MASK_H23N, msrset, special_inst },
  421:   {"msrclr",INST_TYPE_RD_IMM15, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x94110000, OPCODE_MASK_H23N, msrclr, special_inst },
  422:   {"fadd",  INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000000, OPCODE_MASK_H4, fadd, arithmetic_inst },
  423:   {"frsub",  INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000080, OPCODE_MASK_H4, frsub, arithmetic_inst },
  424:   {"fmul",  INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000100, OPCODE_MASK_H4, fmul, arithmetic_inst },
  425:   {"fdiv",  INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000180, OPCODE_MASK_H4, fdiv, arithmetic_inst },
  426:   {"fcmp.lt", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000210, OPCODE_MASK_H4, fcmp_lt, arithmetic_inst },
  427:   {"fcmp.eq", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000220, OPCODE_MASK_H4, fcmp_eq, arithmetic_inst },
  428:   {"fcmp.le", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000230, OPCODE_MASK_H4, fcmp_le, arithmetic_inst },
  429:   {"fcmp.gt", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000240, OPCODE_MASK_H4, fcmp_gt, arithmetic_inst },
  430:   {"fcmp.ne", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000250, OPCODE_MASK_H4, fcmp_ne, arithmetic_inst },
  431:   {"fcmp.ge", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000260, OPCODE_MASK_H4, fcmp_ge, arithmetic_inst },
  432:   {"fcmp.un", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000200, OPCODE_MASK_H4, fcmp_un, arithmetic_inst },
  433:   {"flt",   INST_TYPE_RD_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000280, OPCODE_MASK_H4, flt,   arithmetic_inst },
  434:   {"fint",  INST_TYPE_RD_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000300, OPCODE_MASK_H4, fint,  arithmetic_inst },
  435:   {"fsqrt", INST_TYPE_RD_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000380, OPCODE_MASK_H4, fsqrt, arithmetic_inst },
  436:   {"tget",   INST_TYPE_RD_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C001000, OPCODE_MASK_H32, tget,   anyware_inst },
  437:   {"tcget",  INST_TYPE_RD_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C003000, OPCODE_MASK_H32, tcget,  anyware_inst },
  438:   {"tnget",  INST_TYPE_RD_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C005000, OPCODE_MASK_H32, tnget,  anyware_inst },
  439:   {"tncget", INST_TYPE_RD_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C007000, OPCODE_MASK_H32, tncget, anyware_inst },
  440:   {"tput",   INST_TYPE_RFSL,    INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C009000, OPCODE_MASK_H32, tput,   anyware_inst },
  441:   {"tcput",  INST_TYPE_RFSL,    INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C00B000, OPCODE_MASK_H32, tcput,  anyware_inst },
  442:   {"tnput",  INST_TYPE_RFSL,    INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C00D000, OPCODE_MASK_H32, tnput,  anyware_inst },
  443:   {"tncput", INST_TYPE_RFSL,    INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C00F000, OPCODE_MASK_H32, tncput, anyware_inst },
  444:  
  445:   {"eget",   INST_TYPE_RD_RFSL,  INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C000400, OPCODE_MASK_H32, eget,   anyware_inst },
  446:   {"ecget",  INST_TYPE_RD_RFSL,  INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C002400, OPCODE_MASK_H32, ecget,  anyware_inst },
  447:   {"neget",  INST_TYPE_RD_RFSL,  INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C004400, OPCODE_MASK_H32, neget,  anyware_inst },
  448:   {"necget", INST_TYPE_RD_RFSL,  INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C006400, OPCODE_MASK_H32, necget, anyware_inst },
  449:   {"eput",   INST_TYPE_R1_RFSL,  INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C008400, OPCODE_MASK_H32, eput,   anyware_inst },
  450:   {"ecput",  INST_TYPE_R1_RFSL,  INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C00A400, OPCODE_MASK_H32, ecput,  anyware_inst },
  451:   {"neput",  INST_TYPE_R1_RFSL,  INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C00C400, OPCODE_MASK_H32, neput,  anyware_inst },
  452:   {"necput", INST_TYPE_R1_RFSL,  INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C00E400, OPCODE_MASK_H32, necput, anyware_inst },
  453:  
  454:   {"teget",   INST_TYPE_RD_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C001400, OPCODE_MASK_H32, teget,   anyware_inst },
  455:   {"tecget",  INST_TYPE_RD_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C003400, OPCODE_MASK_H32, tecget,  anyware_inst },
  456:   {"tneget",  INST_TYPE_RD_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C005400, OPCODE_MASK_H32, tneget,  anyware_inst },
  457:   {"tnecget", INST_TYPE_RD_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C007400, OPCODE_MASK_H32, tnecget, anyware_inst },
  458:   {"teput",   INST_TYPE_RFSL,    INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C009400, OPCODE_MASK_H32, teput,   anyware_inst },
  459:   {"tecput",  INST_TYPE_RFSL,    INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C00B400, OPCODE_MASK_H32, tecput,  anyware_inst },
  460:   {"tneput",  INST_TYPE_RFSL,    INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C00D400, OPCODE_MASK_H32, tneput,  anyware_inst },
  461:   {"tnecput", INST_TYPE_RFSL,    INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C00F400, OPCODE_MASK_H32, tnecput, anyware_inst },
  462:  
  463:   {"aget",   INST_TYPE_RD_RFSL,  INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C000800, OPCODE_MASK_H32, aget,   anyware_inst },
  464:   {"caget",  INST_TYPE_RD_RFSL,  INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C002800, OPCODE_MASK_H32, caget,  anyware_inst },
  465:   {"naget",  INST_TYPE_RD_RFSL,  INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C004800, OPCODE_MASK_H32, naget,  anyware_inst },
  466:   {"ncaget", INST_TYPE_RD_RFSL,  INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C006800, OPCODE_MASK_H32, ncaget, anyware_inst },
  467:   {"aput",   INST_TYPE_R1_RFSL,  INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C008800, OPCODE_MASK_H32, aput,   anyware_inst },
  468:   {"caput",  INST_TYPE_R1_RFSL,  INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C00A800, OPCODE_MASK_H32, caput,  anyware_inst },
  469:   {"naput",  INST_TYPE_R1_RFSL,  INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C00C800, OPCODE_MASK_H32, naput,  anyware_inst },
  470:   {"ncaput", INST_TYPE_R1_RFSL,  INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C00E800, OPCODE_MASK_H32, ncaput, anyware_inst },
  471:  
  472:   {"taget",   INST_TYPE_RD_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C001800, OPCODE_MASK_H32, taget,   anyware_inst },
  473:   {"tcaget",  INST_TYPE_RD_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C003800, OPCODE_MASK_H32, tcaget,  anyware_inst },
  474:   {"tnaget",  INST_TYPE_RD_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C005800, OPCODE_MASK_H32, tnaget,  anyware_inst },
  475:   {"tncaget", INST_TYPE_RD_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C007800, OPCODE_MASK_H32, tncaget, anyware_inst },
  476:   {"taput",   INST_TYPE_RFSL,    INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C009800, OPCODE_MASK_H32, taput,   anyware_inst },
  477:   {"tcaput",  INST_TYPE_RFSL,    INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C00B800, OPCODE_MASK_H32, tcaput,  anyware_inst },
  478:   {"tnaput",  INST_TYPE_RFSL,    INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C00D800, OPCODE_MASK_H32, tnaput,  anyware_inst },
  479:   {"tncaput", INST_TYPE_RFSL,    INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C00F800, OPCODE_MASK_H32, tncaput, anyware_inst },
  480:  
  481:   {"eaget",   INST_TYPE_RD_RFSL,  INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C000C00, OPCODE_MASK_H32, eget,   anyware_inst },
  482:   {"ecaget",  INST_TYPE_RD_RFSL,  INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C002C00, OPCODE_MASK_H32, ecget,  anyware_inst },
  483:   {"neaget",  INST_TYPE_RD_RFSL,  INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C004C00, OPCODE_MASK_H32, neget,  anyware_inst },
  484:   {"necaget", INST_TYPE_RD_RFSL,  INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C006C00, OPCODE_MASK_H32, necget, anyware_inst },
  485:   {"eaput",   INST_TYPE_R1_RFSL,  INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C008C00, OPCODE_MASK_H32, eput,   anyware_inst },
  486:   {"ecaput",  INST_TYPE_R1_RFSL,  INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C00AC00, OPCODE_MASK_H32, ecput,  anyware_inst },
  487:   {"neaput",  INST_TYPE_R1_RFSL,  INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C00CC00, OPCODE_MASK_H32, neput,  anyware_inst },
  488:   {"necaput", INST_TYPE_R1_RFSL,  INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C00EC00, OPCODE_MASK_H32, necput, anyware_inst },
  489:  
  490:   {"teaget",   INST_TYPE_RD_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C001C00, OPCODE_MASK_H32, teaget,   anyware_inst },
  491:   {"tecaget",  INST_TYPE_RD_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C003C00, OPCODE_MASK_H32, tecaget,  anyware_inst },
  492:   {"tneaget",  INST_TYPE_RD_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C005C00, OPCODE_MASK_H32, tneaget,  anyware_inst },
  493:   {"tnecaget", INST_TYPE_RD_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C007C00, OPCODE_MASK_H32, tnecaget, anyware_inst },
  494:   {"teaput",   INST_TYPE_RFSL,    INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C009C00, OPCODE_MASK_H32, teaput,   anyware_inst },
  495:   {"tecaput",  INST_TYPE_RFSL,    INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C00BC00, OPCODE_MASK_H32, tecaput,  anyware_inst },
  496:   {"tneaput",  INST_TYPE_RFSL,    INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C00DC00, OPCODE_MASK_H32, tneaput,  anyware_inst },
  497:   {"tnecaput", INST_TYPE_RFSL,    INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C00FC00, OPCODE_MASK_H32, tnecaput, anyware_inst },
  498:  
  499:   {"getd",    INST_TYPE_RD_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000000, OPCODE_MASK_H34C, getd,    anyware_inst },
  500:   {"tgetd",   INST_TYPE_RD_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000080, OPCODE_MASK_H34C, tgetd,   anyware_inst },
  501:   {"cgetd",   INST_TYPE_RD_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000100, OPCODE_MASK_H34C, cgetd,   anyware_inst },
  502:   {"tcgetd",  INST_TYPE_RD_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000180, OPCODE_MASK_H34C, tcgetd,  anyware_inst },
  503:   {"ngetd",   INST_TYPE_RD_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000200, OPCODE_MASK_H34C, ngetd,   anyware_inst },
  504:   {"tngetd",  INST_TYPE_RD_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000280, OPCODE_MASK_H34C, tngetd,  anyware_inst },
  505:   {"ncgetd",  INST_TYPE_RD_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000300, OPCODE_MASK_H34C, ncgetd,  anyware_inst },
  506:   {"tncgetd", INST_TYPE_RD_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000380, OPCODE_MASK_H34C, tncgetd, anyware_inst },
  507:   {"putd",    INST_TYPE_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000400, OPCODE_MASK_H34C, putd,    anyware_inst },
  508:   {"tputd",   INST_TYPE_R2,    INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000480, OPCODE_MASK_H34C, tputd,   anyware_inst },
  509:   {"cputd",   INST_TYPE_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000500, OPCODE_MASK_H34C, cputd,   anyware_inst },
  510:   {"tcputd",  INST_TYPE_R2,    INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000580, OPCODE_MASK_H34C, tcputd,  anyware_inst },
  511:   {"nputd",   INST_TYPE_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000600, OPCODE_MASK_H34C, nputd,   anyware_inst },
  512:   {"tnputd",  INST_TYPE_R2,    INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000680, OPCODE_MASK_H34C, tnputd,  anyware_inst },
  513:   {"ncputd",  INST_TYPE_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000700, OPCODE_MASK_H34C, ncputd,  anyware_inst },
  514:   {"tncputd", INST_TYPE_R2,    INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000780, OPCODE_MASK_H34C, tncputd, anyware_inst },
  515:  
  516:   {"egetd",    INST_TYPE_RD_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000020, OPCODE_MASK_H34C, egetd,    anyware_inst },
  517:   {"tegetd",   INST_TYPE_RD_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C0000A0, OPCODE_MASK_H34C, tegetd,   anyware_inst },
  518:   {"ecgetd",   INST_TYPE_RD_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000120, OPCODE_MASK_H34C, ecgetd,   anyware_inst },
  519:   {"tecgetd",  INST_TYPE_RD_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C0001A0, OPCODE_MASK_H34C, tecgetd,  anyware_inst },
  520:   {"negetd",   INST_TYPE_RD_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000220, OPCODE_MASK_H34C, negetd,   anyware_inst },
  521:   {"tnegetd",  INST_TYPE_RD_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C0002A0, OPCODE_MASK_H34C, tnegetd,  anyware_inst },
  522:   {"necgetd",  INST_TYPE_RD_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000320, OPCODE_MASK_H34C, necgetd,  anyware_inst },
  523:   {"tnecgetd", INST_TYPE_RD_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C0003A0, OPCODE_MASK_H34C, tnecgetd, anyware_inst },
  524:   {"eputd",    INST_TYPE_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000420, OPCODE_MASK_H34C, eputd,    anyware_inst },
  525:   {"teputd",   INST_TYPE_R2,    INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C0004A0, OPCODE_MASK_H34C, teputd,   anyware_inst },
  526:   {"ecputd",   INST_TYPE_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000520, OPCODE_MASK_H34C, ecputd,   anyware_inst },
  527:   {"tecputd",  INST_TYPE_R2,    INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C0005A0, OPCODE_MASK_H34C, tecputd,  anyware_inst },
  528:   {"neputd",   INST_TYPE_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000620, OPCODE_MASK_H34C, neputd,   anyware_inst },
  529:   {"tneputd",  INST_TYPE_R2,    INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C0006A0, OPCODE_MASK_H34C, tneputd,  anyware_inst },
  530:   {"necputd",  INST_TYPE_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000720, OPCODE_MASK_H34C, necputd,  anyware_inst },
  531:   {"tnecputd", INST_TYPE_R2,    INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C0007A0, OPCODE_MASK_H34C, tnecputd, anyware_inst },
  532:  
  533:   {"agetd",    INST_TYPE_RD_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000040, OPCODE_MASK_H34C, agetd,    anyware_inst },
  534:   {"tagetd",   INST_TYPE_RD_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C0000C0, OPCODE_MASK_H34C, tagetd,   anyware_inst },
  535:   {"cagetd",   INST_TYPE_RD_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000140, OPCODE_MASK_H34C, cagetd,   anyware_inst },
  536:   {"tcagetd",  INST_TYPE_RD_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C0001C0, OPCODE_MASK_H34C, tcagetd,  anyware_inst },
  537:   {"nagetd",   INST_TYPE_RD_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000240, OPCODE_MASK_H34C, nagetd,   anyware_inst },
  538:   {"tnagetd",  INST_TYPE_RD_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C0002C0, OPCODE_MASK_H34C, tnagetd,  anyware_inst },
  539:   {"ncagetd",  INST_TYPE_RD_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000340, OPCODE_MASK_H34C, ncagetd,  anyware_inst },
  540:   {"tncagetd", INST_TYPE_RD_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C0003C0, OPCODE_MASK_H34C, tncagetd, anyware_inst },
  541:   {"aputd",    INST_TYPE_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000440, OPCODE_MASK_H34C, aputd,    anyware_inst },
  542:   {"taputd",   INST_TYPE_R2,    INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C0004C0, OPCODE_MASK_H34C, taputd,   anyware_inst },
  543:   {"caputd",   INST_TYPE_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000540, OPCODE_MASK_H34C, caputd,   anyware_inst },
  544:   {"tcaputd",  INST_TYPE_R2,    INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C0005C0, OPCODE_MASK_H34C, tcaputd,  anyware_inst },
  545:   {"naputd",   INST_TYPE_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000640, OPCODE_MASK_H34C, naputd,   anyware_inst },
  546:   {"tnaputd",  INST_TYPE_R2,    INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C0006C0, OPCODE_MASK_H34C, tnaputd,  anyware_inst },
  547:   {"ncaputd",  INST_TYPE_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000740, OPCODE_MASK_H34C, ncaputd,  anyware_inst },
  548:   {"tncaputd", INST_TYPE_R2,    INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C0007C0, OPCODE_MASK_H34C, tncaputd, anyware_inst },
  549:  
  550:   {"eagetd",    INST_TYPE_RD_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000060, OPCODE_MASK_H34C, eagetd,    anyware_inst },
  551:   {"teagetd",   INST_TYPE_RD_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C0000E0, OPCODE_MASK_H34C, teagetd,   anyware_inst },
  552:   {"ecagetd",   INST_TYPE_RD_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000160, OPCODE_MASK_H34C, ecagetd,   anyware_inst },
  553:   {"tecagetd",  INST_TYPE_RD_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C0001E0, OPCODE_MASK_H34C, tecagetd,  anyware_inst },
  554:   {"neagetd",   INST_TYPE_RD_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000260, OPCODE_MASK_H34C, neagetd,   anyware_inst },
  555:   {"tneagetd",  INST_TYPE_RD_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C0002E0, OPCODE_MASK_H34C, tneagetd,  anyware_inst },
  556:   {"necagetd",  INST_TYPE_RD_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000360, OPCODE_MASK_H34C, necagetd,  anyware_inst },
  557:   {"tnecagetd", INST_TYPE_RD_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C0003E0, OPCODE_MASK_H34C, tnecagetd, anyware_inst },
  558:   {"eaputd",    INST_TYPE_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000460, OPCODE_MASK_H34C, eaputd,    anyware_inst },
  559:   {"teaputd",   INST_TYPE_R2,    INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C0004E0, OPCODE_MASK_H34C, teaputd,   anyware_inst },
  560:   {"ecaputd",   INST_TYPE_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000560, OPCODE_MASK_H34C, ecaputd,   anyware_inst },
  561:   {"tecaputd",  INST_TYPE_R2,    INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C0005E0, OPCODE_MASK_H34C, tecaputd,  anyware_inst },
  562:   {"neaputd",   INST_TYPE_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000660, OPCODE_MASK_H34C, neaputd,   anyware_inst },
  563:   {"tneaputd",  INST_TYPE_R2,    INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C0006E0, OPCODE_MASK_H34C, tneaputd,  anyware_inst },
  564:   {"necaputd",  INST_TYPE_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000760, OPCODE_MASK_H34C, necaputd,  anyware_inst },
  565:   {"tnecaputd", INST_TYPE_R2,    INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C0007E0, OPCODE_MASK_H34C, tnecaputd, anyware_inst },
  566:   {"", 0, 0, 0, 0, 0, 0, 0, 0},
  567: };
  568: 
  569: /* prefix for register names */
  570: char register_prefix[] = "r";
  571: char special_register_prefix[] = "spr";
  572: char fsl_register_prefix[] = "rfsl";
  573: char pvr_register_prefix[] = "rpvr";
  574: 
  575: 
  576: /* #defines for valid immediate range */
  577: #define MIN_IMM  ((int) 0x80000000)
  578: #define MAX_IMM  ((int) 0x7fffffff)
  579: 
  580: #define MIN_IMM15 ((int) 0x0000)
  581: #define MAX_IMM15 ((int) 0x7fff)
  582: 
  583: #endif /* MICROBLAZE_OPC */
  584: 
  585: #include "dis-asm.h"
  586: #include <strings.h>
  587: 
  588: #define get_field_rd(instr) get_field(instr, RD_MASK, RD_LOW)
  589: #define get_field_r1(instr) get_field(instr, RA_MASK, RA_LOW)
  590: #define get_field_r2(instr) get_field(instr, RB_MASK, RB_LOW)
  591: #define get_int_field_imm(instr) ((instr & IMM_MASK) >> IMM_LOW)
  592: #define get_int_field_r1(instr) ((instr & RA_MASK) >> RA_LOW)
  593: 
  594: /* Local function prototypes. */
  595: 
  596: static char * get_field (long instr, long mask, unsigned short low);
  597: static char * get_field_imm (long instr);
  598: static char * get_field_imm5 (long instr);
  599: static char * get_field_rfsl (long instr);
  600: static char * get_field_imm15 (long instr);
  601: #if 0
  602: static char * get_field_unsigned_imm (long instr);
  603: #endif
  604: char * get_field_special (long instr, struct op_code_struct * op);
  605: unsigned long read_insn_microblaze (bfd_vma memaddr, 
  606: 		      struct disassemble_info *info,
  607: 		      struct op_code_struct **opr);
  608: enum microblaze_instr get_insn_microblaze (long inst,
  609:   		     bfd_boolean *isunsignedimm,
  610:   		     enum microblaze_instr_type *insn_type,
  611:   		     short *delay_slots);
  612: short get_delay_slots_microblaze (long inst);
  613: enum microblaze_instr microblaze_decode_insn (long insn,
  614: 		        int *rd, 
  615: 			int *ra, 
  616: 			int *rb, 
  617: 			int *imm);
  618: unsigned long
  619: microblaze_get_target_address (long inst,
  620: 			       bfd_boolean immfound,
  621: 			       int immval,
  622: 			       long pcval,
  623: 			       long r1val,
  624: 			       long r2val,
  625: 			       bfd_boolean *targetvalid,
  626: 			       bfd_boolean *unconditionalbranch);
  627: 
  628: static char *
  629: get_field (long instr, long mask, unsigned short low)
  630: {
  631:   char tmpstr[25];
  632:   sprintf(tmpstr, "%s%d", register_prefix, (int)((instr & mask) >> low));
  633:   return(strdup(tmpstr));
  634: }
  635: 
  636: static char *
  637: get_field_imm (long instr)
  638: {
  639:   char tmpstr[25];
  640:   sprintf(tmpstr, "%d", (short)((instr & IMM_MASK) >> IMM_LOW));
  641:   return(strdup(tmpstr));
  642: }
  643: 
  644: static char *
  645: get_field_imm5 (long instr)
  646: {
  647:   char tmpstr[25];
  648:   sprintf(tmpstr, "%d", (short)((instr & IMM5_MASK) >> IMM_LOW));
  649:   return(strdup(tmpstr));
  650: }
  651: 
  652: static char *
  653: get_field_rfsl (long instr)
  654: {
  655:   char tmpstr[25];
  656:   sprintf(tmpstr, "%s%d", fsl_register_prefix, (short)((instr & RFSL_MASK) >> IMM_LOW));
  657:   return(strdup(tmpstr));
  658: }
  659: 
  660: static char *
  661: get_field_imm15 (long instr)
  662: {
  663:   char tmpstr[25];
  664:   sprintf(tmpstr, "%d", (short)((instr & IMM15_MASK) >> IMM_LOW));
  665:   return(strdup(tmpstr));
  666: }
  667: 
  668: #if 0
  669: static char *
  670: get_field_unsigned_imm (long instr)
  671: {
  672:   char tmpstr[25];
  673:   sprintf(tmpstr, "%d", (int)((instr & IMM_MASK) >> IMM_LOW));
  674:   return(strdup(tmpstr));
  675: }
  676: #endif
  677: 
  678: /*
  679:   char *
  680:   get_field_special (instr) 
  681:   long instr;
  682:   {
  683:   char tmpstr[25];
  684:   
  685:   sprintf(tmpstr, "%s%s", register_prefix, (((instr & IMM_MASK) >> IMM_LOW) & REG_MSR_MASK) == 0 ? "pc" : "msr");
  686:   
  687:   return(strdup(tmpstr));
  688:   }
  689: */
  690: 
  691: char *
  692: get_field_special (long instr, struct op_code_struct * op)
  693: {
  694:    char tmpstr[25];
  695:    char spr[6];
  696: 
  697:    switch ( (((instr & IMM_MASK) >> IMM_LOW) ^ op->immval_mask) ) {
  698: 
  699:    case REG_MSR_MASK :
  700:       strcpy(spr, "msr");
  701:       break;
  702:    case REG_PC_MASK :
  703:       strcpy(spr, "pc");
  704:       break;
  705:    case REG_EAR_MASK :
  706:       strcpy(spr, "ear");
  707:       break;
  708:    case REG_ESR_MASK :
  709:       strcpy(spr, "esr");
  710:       break;
  711:    case REG_FSR_MASK :
  712:       strcpy(spr, "fsr");
  713:       break;
  714:    case REG_BTR_MASK :
  715:       strcpy(spr, "btr");
  716:       break;      
  717:    case REG_EDR_MASK :
  718:       strcpy(spr, "edr");
  719:       break;
  720:    case REG_PID_MASK :
  721:       strcpy(spr, "pid");
  722:       break;
  723:    case REG_ZPR_MASK :
  724:       strcpy(spr, "zpr");
  725:       break;
  726:    case REG_TLBX_MASK :
  727:       strcpy(spr, "tlbx");
  728:       break;
  729:    case REG_TLBLO_MASK :
  730:       strcpy(spr, "tlblo");
  731:       break;
  732:    case REG_TLBHI_MASK :
  733:       strcpy(spr, "tlbhi");
  734:       break;
  735:    case REG_TLBSX_MASK :
  736:       strcpy(spr, "tlbsx");
  737:       break;
  738:    default :
  739:      {
  740:        if ( ((((instr & IMM_MASK) >> IMM_LOW) ^ op->immval_mask) & 0xE000) == REG_PVR_MASK) {
  741: 	 sprintf(tmpstr, "%spvr%d", register_prefix, (unsigned short)(((instr & IMM_MASK) >> IMM_LOW) ^ op->immval_mask) ^ REG_PVR_MASK);
  742: 	 return(strdup(tmpstr));
  743:        } else {
  744: 	 strcpy(spr, "pc");
  745:        }
  746:      }
  747:      break;
  748:    }
  749:    
  750:    sprintf(tmpstr, "%s%s", register_prefix, spr);
  751:    return(strdup(tmpstr));
  752: }
  753: 
  754: unsigned long
  755: read_insn_microblaze (bfd_vma memaddr, 
  756: 		      struct disassemble_info *info,
  757: 		      struct op_code_struct **opr)
  758: {
  759:   unsigned char       ibytes[4];
  760:   int                 status;
  761:   struct op_code_struct * op;
  762:   unsigned long inst;
  763: 
  764:   status = info->read_memory_func (memaddr, ibytes, 4, info);
  765: 
  766:   if (status != 0) 
  767:     {
  768:       info->memory_error_func (status, memaddr, info);
  769:       return 0;
  770:     }
  771: 
  772:   if (info->endian == BFD_ENDIAN_BIG)
  773:     inst = (ibytes[0] << 24) | (ibytes[1] << 16) | (ibytes[2] << 8) | ibytes[3];
  774:   else if (info->endian == BFD_ENDIAN_LITTLE)
  775:     inst = (ibytes[3] << 24) | (ibytes[2] << 16) | (ibytes[1] << 8) | ibytes[0];
  776:   else
  777:     abort ();
  778: 
  779:   /* Just a linear search of the table.  */
  780:   for (op = opcodes; op->name != 0; op ++)
  781:     if (op->bit_sequence == (inst & op->opcode_mask))
  782:       break;
  783: 
  784:   *opr = op;
  785:   return inst;
  786: }
  787: 
  788: 
  789: int 
  790: print_insn_microblaze (bfd_vma memaddr, struct disassemble_info * info)
  791: {
  792:   fprintf_function    fprintf_func = info->fprintf_func;
  793:   void *              stream = info->stream;
  794:   unsigned long       inst, prev_inst;
  795:   struct op_code_struct * op, *pop;
  796:   int                 immval = 0;
  797:   bfd_boolean         immfound = FALSE;
  798:   static bfd_vma prev_insn_addr = -1; /*init the prev insn addr */
  799:   static int     prev_insn_vma = -1;  /*init the prev insn vma */
  800:   int            curr_insn_vma = info->buffer_vma;
  801: 
  802:   info->bytes_per_chunk = 4;
  803: 
  804:   inst = read_insn_microblaze (memaddr, info, &op);
  805:   if (inst == 0) {
  806:     return -1;
  807:   }
  808:   
  809:   if (prev_insn_vma == curr_insn_vma) {
  810:   if (memaddr-(info->bytes_per_chunk) == prev_insn_addr) {
  811:     prev_inst = read_insn_microblaze (prev_insn_addr, info, &pop);
  812:     if (prev_inst == 0)
  813:       return -1;
  814:     if (pop->instr == imm) {
  815:       immval = (get_int_field_imm(prev_inst) << 16) & 0xffff0000;
  816:       immfound = TRUE;
  817:     }
  818:     else {
  819:       immval = 0;
  820:       immfound = FALSE;
  821:     }
  822:   }
  823:   }
  824:   /* make curr insn as prev insn */
  825:   prev_insn_addr = memaddr;
  826:   prev_insn_vma = curr_insn_vma;
  827: 
  828:   if (op->name == 0) {
  829:     fprintf_func (stream, ".short 0x%04lx", inst);
  830:   }
  831:   else
  832:     {
  833:       fprintf_func (stream, "%s", op->name);
  834:       
  835:       switch (op->inst_type)
  836: 	{
  837:   case INST_TYPE_RD_R1_R2:
  838:      fprintf_func(stream, "\t%s, %s, %s", get_field_rd(inst), get_field_r1(inst), get_field_r2(inst));
  839:      break;
  840:         case INST_TYPE_RD_R1_IMM:
  841: 	  fprintf_func(stream, "\t%s, %s, %s", get_field_rd(inst), get_field_r1(inst), get_field_imm(inst));
  842: 	  if (info->print_address_func && get_int_field_r1(inst) == 0 && info->symbol_at_address_func) {
  843: 	    if (immfound)
  844: 	      immval |= (get_int_field_imm(inst) & 0x0000ffff);
  845: 	    else {
  846: 	      immval = get_int_field_imm(inst);
  847: 	      if (immval & 0x8000)
  848: 		immval |= 0xFFFF0000;
  849: 	    }
  850: 	    if (immval > 0 && info->symbol_at_address_func(immval, info)) {
  851: 	      fprintf_func (stream, "\t// ");
  852: 	      info->print_address_func (immval, info);
  853: 	    }
  854: 	  }
  855: 	  break;
  856: 	case INST_TYPE_RD_R1_IMM5:
  857: 	  fprintf_func(stream, "\t%s, %s, %s", get_field_rd(inst), get_field_r1(inst), get_field_imm5(inst));
  858: 	  break;
  859: 	case INST_TYPE_RD_RFSL:
  860: 	  fprintf_func(stream, "\t%s, %s", get_field_rd(inst), get_field_rfsl(inst));
  861: 	  break;
  862: 	case INST_TYPE_R1_RFSL:
  863: 	  fprintf_func(stream, "\t%s, %s", get_field_r1(inst), get_field_rfsl(inst));
  864: 	  break;
  865: 	case INST_TYPE_RD_SPECIAL:
  866: 	  fprintf_func(stream, "\t%s, %s", get_field_rd(inst), get_field_special(inst, op));
  867: 	  break;
  868: 	case INST_TYPE_SPECIAL_R1:
  869: 	  fprintf_func(stream, "\t%s, %s", get_field_special(inst, op), get_field_r1(inst));
  870: 	  break;
  871: 	case INST_TYPE_RD_R1:
  872: 	  fprintf_func(stream, "\t%s, %s", get_field_rd(inst), get_field_r1(inst));
  873: 	  break;
  874: 	case INST_TYPE_R1_R2:
  875: 	  fprintf_func(stream, "\t%s, %s", get_field_r1(inst), get_field_r2(inst));
  876: 	  break;
  877: 	case INST_TYPE_R1_IMM:
  878: 	  fprintf_func(stream, "\t%s, %s", get_field_r1(inst), get_field_imm(inst));
  879: 	  /* The non-pc relative instructions are returns, which shouldn't 
  880: 	     have a label printed */
  881: 	  if (info->print_address_func && op->inst_offset_type == INST_PC_OFFSET && info->symbol_at_address_func) {
  882: 	    if (immfound)
  883: 	      immval |= (get_int_field_imm(inst) & 0x0000ffff);
  884: 	    else {
  885: 	      immval = get_int_field_imm(inst);
  886: 	      if (immval & 0x8000)
  887: 		immval |= 0xFFFF0000;
  888: 	    }
  889: 	    immval += memaddr;
  890: 	    if (immval > 0 && info->symbol_at_address_func(immval, info)) {
  891: 	      fprintf_func (stream, "\t// ");
  892: 	      info->print_address_func (immval, info);
  893: 	    } else {
  894: 	      fprintf_func (stream, "\t\t// ");
  895: 	      fprintf_func (stream, "%x", immval);
  896: 	    }
  897: 	  }
  898: 	  break;
  899:         case INST_TYPE_RD_IMM:
  900: 	  fprintf_func(stream, "\t%s, %s", get_field_rd(inst), get_field_imm(inst));
  901: 	  if (info->print_address_func && info->symbol_at_address_func) {
  902: 	    if (immfound)
  903: 	      immval |= (get_int_field_imm(inst) & 0x0000ffff);
  904: 	    else {
  905: 	      immval = get_int_field_imm(inst);
  906: 	      if (immval & 0x8000)
  907: 		immval |= 0xFFFF0000;
  908: 	    }
  909: 	    if (op->inst_offset_type == INST_PC_OFFSET)
  910: 	      immval += (int) memaddr;
  911: 	    if (info->symbol_at_address_func(immval, info)) {
  912: 	      fprintf_func (stream, "\t// ");
  913: 	      info->print_address_func (immval, info);
  914: 	    } 
  915: 	  }
  916: 	  break;
  917:         case INST_TYPE_IMM:
  918: 	  fprintf_func(stream, "\t%s", get_field_imm(inst));
  919: 	  if (info->print_address_func && info->symbol_at_address_func && op->instr != imm) {
  920: 	    if (immfound)
  921: 	      immval |= (get_int_field_imm(inst) & 0x0000ffff);
  922: 	    else {
  923: 	      immval = get_int_field_imm(inst);
  924: 	      if (immval & 0x8000)
  925: 		immval |= 0xFFFF0000;
  926: 	    }
  927: 	    if (op->inst_offset_type == INST_PC_OFFSET)
  928: 	      immval += (int) memaddr;
  929: 	    if (immval > 0 && info->symbol_at_address_func(immval, info)) {
  930: 	      fprintf_func (stream, "\t// ");
  931: 	      info->print_address_func (immval, info);
  932: 	    } else if (op->inst_offset_type == INST_PC_OFFSET) {
  933: 	      fprintf_func (stream, "\t\t// ");
  934: 	      fprintf_func (stream, "%x", immval);
  935: 	    }
  936: 	  }
  937: 	  break;
  938:         case INST_TYPE_RD_R2:
  939: 	  fprintf_func(stream, "\t%s, %s", get_field_rd(inst), get_field_r2(inst));
  940: 	  break;
  941:   case INST_TYPE_R2:
  942:      fprintf_func(stream, "\t%s", get_field_r2(inst));
  943:      break;
  944:   case INST_TYPE_R1:
  945:      fprintf_func(stream, "\t%s", get_field_r1(inst));
  946:      break;
  947:   case INST_TYPE_RD_R1_SPECIAL:
  948:      fprintf_func(stream, "\t%s, %s", get_field_rd(inst), get_field_r2(inst));
  949:      break;
  950:   case INST_TYPE_RD_IMM15:
  951:      fprintf_func(stream, "\t%s, %s", get_field_rd(inst), get_field_imm15(inst));
  952:      break;
  953:      /* For tuqula instruction */
  954:   case INST_TYPE_RD:
  955:      fprintf_func(stream, "\t%s", get_field_rd(inst));
  956:      break;
  957:   case INST_TYPE_RFSL:
  958:      fprintf_func(stream, "\t%s", get_field_rfsl(inst));
  959:      break;
  960:   default:
  961: 	  /* if the disassembler lags the instruction set */
  962: 	  fprintf_func (stream, "\tundecoded operands, inst is 0x%04lx", inst);
  963: 	  break;
  964: 	}
  965:     }
  966:   
  967:   /* Say how many bytes we consumed? */
  968:   return 4;
  969: }
  970: 
  971: enum microblaze_instr
  972: get_insn_microblaze (long inst,
  973:   		     bfd_boolean *isunsignedimm,
  974:   		     enum microblaze_instr_type *insn_type,
  975:   		     short *delay_slots)
  976: {
  977:   struct op_code_struct * op;
  978:   *isunsignedimm = FALSE;
  979: 
  980:   /* Just a linear search of the table.  */
  981:   for (op = opcodes; op->name != 0; op ++)
  982:     if (op->bit_sequence == (inst & op->opcode_mask))
  983:       break;
  984: 
  985:   if (op->name == 0)
  986:     return invalid_inst;
  987:   else {
  988:     *isunsignedimm = (op->inst_type == INST_TYPE_RD_R1_UNSIGNED_IMM);
  989:     *insn_type = op->instr_type;
  990:     *delay_slots = op->delay_slots;
  991:     return op->instr;
  992:   }
  993: }
  994: 
  995: short
  996: get_delay_slots_microblaze (long inst)
  997: {
  998:   bfd_boolean isunsignedimm;
  999:   enum microblaze_instr_type insn_type;
 1000:   enum microblaze_instr op;
 1001:   short delay_slots;
 1002: 
 1003:   op = get_insn_microblaze( inst, &isunsignedimm, &insn_type, &delay_slots);
 1004:   if (op == invalid_inst)
 1005:     return 0;
 1006:   else 
 1007:     return delay_slots;
 1008: }
 1009: 
 1010: enum microblaze_instr
 1011: microblaze_decode_insn (long insn,
 1012: 		        int *rd, 
 1013: 			int *ra, 
 1014: 			int *rb, 
 1015: 			int *imm)
 1016: {
 1017:   enum microblaze_instr op;
 1018:   bfd_boolean t1;
 1019:   enum microblaze_instr_type t2;
 1020:   short t3;
 1021: 
 1022:   op = get_insn_microblaze(insn, &t1, &t2, &t3);
 1023:   *rd = (insn & RD_MASK) >> RD_LOW;
 1024:   *ra = (insn & RA_MASK) >> RA_LOW;
 1025:   *rb = (insn & RB_MASK) >> RB_LOW;
 1026:   t3 = (insn & IMM_MASK) >> IMM_LOW;
 1027:   *imm = (int) t3;
 1028:   return (op);
 1029: }
 1030: 
 1031: unsigned long
 1032: microblaze_get_target_address (long inst,
 1033: 			       bfd_boolean immfound,
 1034: 			       int immval,
 1035: 			       long pcval,
 1036: 			       long r1val,
 1037: 			       long r2val,
 1038: 			       bfd_boolean *targetvalid,
 1039: 			       bfd_boolean *unconditionalbranch)
 1040: {
 1041:   struct op_code_struct * op;
 1042:   long targetaddr = 0;
 1043: 
 1044:   *unconditionalbranch = FALSE;
 1045:   /* Just a linear search of the table.  */
 1046:   for (op = opcodes; op->name != 0; op ++)
 1047:     if (op->bit_sequence == (inst & op->opcode_mask))
 1048:       break;
 1049: 
 1050:   if (op->name == 0) {
 1051:     *targetvalid = FALSE;
 1052:   } else if (op->instr_type == branch_inst) {
 1053:     switch (op->inst_type) {
 1054:     case INST_TYPE_R2:
 1055:       *unconditionalbranch = TRUE;
 1056:       /* fallthru */
 1057:     case INST_TYPE_RD_R2:
 1058:     case INST_TYPE_R1_R2:
 1059:       targetaddr = r2val;
 1060:       *targetvalid = TRUE;
 1061:       if (op->inst_offset_type == INST_PC_OFFSET)
 1062: 	targetaddr += pcval;
 1063:       break;
 1064:     case INST_TYPE_IMM:
 1065:       *unconditionalbranch = TRUE;
 1066:       /* fallthru */
 1067:     case INST_TYPE_RD_IMM:
 1068:     case INST_TYPE_R1_IMM:
 1069:       if (immfound) {
 1070: 	targetaddr = (immval << 16) & 0xffff0000;
 1071: 	targetaddr |= (get_int_field_imm(inst) & 0x0000ffff);
 1072:       } else {
 1073: 	targetaddr = get_int_field_imm(inst);
 1074: 	if (targetaddr & 0x8000)
 1075: 	  targetaddr |= 0xFFFF0000;
 1076:       }
 1077:       if (op->inst_offset_type == INST_PC_OFFSET)
 1078: 	targetaddr += pcval;
 1079:       *targetvalid = TRUE;
 1080:       break;
 1081:     default:
 1082:       *targetvalid = FALSE;
 1083:       break;
 1084:     }
 1085:   } else if (op->instr_type == return_inst) {
 1086:       if (immfound) {
 1087: 	targetaddr = (immval << 16) & 0xffff0000;
 1088: 	targetaddr |= (get_int_field_imm(inst) & 0x0000ffff);
 1089:       } else {
 1090: 	targetaddr = get_int_field_imm(inst);
 1091: 	if (targetaddr & 0x8000)
 1092: 	  targetaddr |= 0xFFFF0000;
 1093:       }
 1094:       targetaddr += r1val;
 1095:       *targetvalid = TRUE;
 1096:   } else {
 1097:     *targetvalid = FALSE;
 1098:   }
 1099:   return targetaddr;
 1100: }

unix.superglobalmegacorp.com