Diff for /qemu/mips-dis.c between versions 1.1.1.4 and 1.1.1.9

version 1.1.1.4, 2018/04/24 16:47:22 version 1.1.1.9, 2018/04/24 19:17:16
Line 17  MERCHANTABILITY or FITNESS FOR A PARTICU Line 17  MERCHANTABILITY or FITNESS FOR A PARTICU
 GNU General Public License for more details.  GNU General Public License for more details.
   
 You should have received a copy of the GNU General Public License  You should have received a copy of the GNU General Public License
 along with this program; if not, write to the Free Software  along with this program; if not, see <http://www.gnu.org/licenses/>.  */
 Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */  
   
 #include "dis-asm.h"  #include "dis-asm.h"
   
Line 41  warranty of MERCHANTABILITY or FITNESS F Line 40  warranty of MERCHANTABILITY or FITNESS F
 the GNU General Public License for more details.  the GNU General Public License for more details.
   
 You should have received a copy of the GNU General Public License  You should have received a copy of the GNU General Public License
 along with this file; see the file COPYING.  If not, write to the Free  along with this file; see the file COPYING.  If not,
 Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */  see <http://www.gnu.org/licenses/>.  */
   
 /* mips.h.  Mips opcode list for GDB, the GNU debugger.  
    Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003  
    Free Software Foundation, Inc.  
    Contributed by Ralph Campbell and OSF  
    Commented and modified by Ian Lance Taylor, Cygnus Support  
   
 This file is part of GDB, GAS, and the GNU binutils.  
   
 GDB, GAS, and the GNU binutils are free software; you can redistribute  
 them and/or modify them under the terms of the GNU General Public  
 License as published by the Free Software Foundation; either version  
 1, or (at your option) any later version.  
   
 GDB, GAS, and the GNU binutils are distributed in the hope that they  
 will be useful, but WITHOUT ANY WARRANTY; without even the implied  
 warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See  
 the GNU General Public License for more details.  
   
 You should have received a copy of the GNU General Public License  
 along with this file; see the file COPYING.  If not, write to the Free  
 Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */  
   
 /* These are bit masks and shift counts to use to access the various  /* These are bit masks and shift counts to use to access the various
    fields of an instruction.  To retrieve the X field of an     fields of an instruction.  To retrieve the X field of an
Line 588  struct mips_opcode Line 565  struct mips_opcode
 /* DSP R2 ASE  */  /* DSP R2 ASE  */
 #define INSN_DSPR2                0x20000000  #define INSN_DSPR2                0x20000000
   
   /* ST Microelectronics Loongson 2E.  */
   #define INSN_LOONGSON_2E          0x40000000
   /* ST Microelectronics Loongson 2F.  */
   #define INSN_LOONGSON_2F          0x80000000
   
 /* MIPS ISA defines, use instead of hardcoding ISA level.  */  /* MIPS ISA defines, use instead of hardcoding ISA level.  */
   
 #define       ISA_UNKNOWN     0               /* Gas internal use.  */  #define       ISA_UNKNOWN     0               /* Gas internal use.  */
Line 1152  extern const int bfd_mips16_num_opcodes; Line 1134  extern const int bfd_mips16_num_opcodes;
 /* MIPS64 MDMX ASE support.  */  /* MIPS64 MDMX ASE support.  */
 #define MX      INSN_MDMX  #define MX      INSN_MDMX
   
   #define IL2E    (INSN_LOONGSON_2E)
   #define IL2F    (INSN_LOONGSON_2F)
   
 #define P3      INSN_4650  #define P3      INSN_4650
 #define L1      INSN_4010  #define L1      INSN_4010
 #define V1      (INSN_4100 | INSN_4111 | INSN_4120)  #define V1      (INSN_4100 | INSN_4111 | INSN_4120)
Line 2742  const struct mips_opcode mips_builtin_op Line 2727  const struct mips_opcode mips_builtin_op
 {"bc0fl",   "p",        0x41020000, 0xffff0000, CBL|RD_CC,              0,              I2|T3   },  {"bc0fl",   "p",        0x41020000, 0xffff0000, CBL|RD_CC,              0,              I2|T3   },
 {"bc0t",    "p",        0x41010000, 0xffff0000, CBD|RD_CC,              0,              I1      },  {"bc0t",    "p",        0x41010000, 0xffff0000, CBD|RD_CC,              0,              I1      },
 {"bc0tl",   "p",        0x41030000, 0xffff0000, CBL|RD_CC,              0,              I2|T3   },  {"bc0tl",   "p",        0x41030000, 0xffff0000, CBL|RD_CC,              0,              I2|T3   },
   /* ST Microelectronics Loongson-2E and -2F.  */
   {"mult.g",      "d,s,t",        0x7c000018,     0xfc0007ff,     RD_s|RD_t|WR_d, 0,      IL2E    },
   {"mult.g",      "d,s,t",        0x70000010,     0xfc0007ff,     RD_s|RD_t|WR_d, 0,      IL2F    },
   {"multu.g",     "d,s,t",        0x7c000019,     0xfc0007ff,     RD_s|RD_t|WR_d, 0,      IL2E    },
   {"multu.g",     "d,s,t",        0x70000012,     0xfc0007ff,     RD_s|RD_t|WR_d, 0,      IL2F    },
   {"dmult.g",     "d,s,t",        0x7c00001c,     0xfc0007ff,     RD_s|RD_t|WR_d, 0,      IL2E    },
   {"dmult.g",     "d,s,t",        0x70000011,     0xfc0007ff,     RD_s|RD_t|WR_d, 0,      IL2F    },
   {"dmultu.g",    "d,s,t",        0x7c00001d,     0xfc0007ff,     RD_s|RD_t|WR_d, 0,      IL2E    },
   {"dmultu.g",    "d,s,t",        0x70000013,     0xfc0007ff,     RD_s|RD_t|WR_d, 0,      IL2F    },
   {"div.g",       "d,s,t",        0x7c00001a,     0xfc0007ff,     RD_s|RD_t|WR_d, 0,      IL2E    },
   {"div.g",       "d,s,t",        0x70000014,     0xfc0007ff,     RD_s|RD_t|WR_d, 0,      IL2F    },
   {"divu.g",      "d,s,t",        0x7c00001b,     0xfc0007ff,     RD_s|RD_t|WR_d, 0,      IL2E    },
   {"divu.g",      "d,s,t",        0x70000016,     0xfc0007ff,     RD_s|RD_t|WR_d, 0,      IL2F    },
   {"ddiv.g",      "d,s,t",        0x7c00001e,     0xfc0007ff,     RD_s|RD_t|WR_d, 0,      IL2E    },
   {"ddiv.g",      "d,s,t",        0x70000015,     0xfc0007ff,     RD_s|RD_t|WR_d, 0,      IL2F    },
   {"ddivu.g",     "d,s,t",        0x7c00001f,     0xfc0007ff,     RD_s|RD_t|WR_d, 0,      IL2E    },
   {"ddivu.g",     "d,s,t",        0x70000017,     0xfc0007ff,     RD_s|RD_t|WR_d, 0,      IL2F    },
   {"mod.g",       "d,s,t",        0x7c000022,     0xfc0007ff,     RD_s|RD_t|WR_d, 0,      IL2E    },
   {"mod.g",       "d,s,t",        0x7000001c,     0xfc0007ff,     RD_s|RD_t|WR_d, 0,      IL2F    },
   {"modu.g",      "d,s,t",        0x7c000023,     0xfc0007ff,     RD_s|RD_t|WR_d, 0,      IL2E    },
   {"modu.g",      "d,s,t",        0x7000001e,     0xfc0007ff,     RD_s|RD_t|WR_d, 0,      IL2F    },
   {"dmod.g",      "d,s,t",        0x7c000026,     0xfc0007ff,     RD_s|RD_t|WR_d, 0,      IL2E    },
   {"dmod.g",      "d,s,t",        0x7000001d,     0xfc0007ff,     RD_s|RD_t|WR_d, 0,      IL2F    },
   {"dmodu.g",     "d,s,t",        0x7c000027,     0xfc0007ff,     RD_s|RD_t|WR_d, 0,      IL2E    },
   {"dmodu.g",     "d,s,t",        0x7000001f,     0xfc0007ff,     RD_s|RD_t|WR_d, 0,      IL2F    },
 };  };
   
 #define MIPS_NUM_OPCODES \  #define MIPS_NUM_OPCODES \
Line 3058  struct mips_abi_choice Line 3068  struct mips_abi_choice
   const char * const *fpr_names;    const char * const *fpr_names;
 };  };
   
 struct mips_abi_choice mips_abi_choices[] =  static struct mips_abi_choice mips_abi_choices[] =
 {  {
   { "numeric", mips_gpr_names_numeric, mips_fpr_names_numeric },    { "numeric", mips_gpr_names_numeric, mips_fpr_names_numeric },
   { "32", mips_gpr_names_oldabi, mips_fpr_names_32 },    { "32", mips_gpr_names_oldabi, mips_fpr_names_32 },
Line 3107  struct mips_arch_choice Line 3117  struct mips_arch_choice
 #define bfd_mach_mipsisa64             64  #define bfd_mach_mipsisa64             64
 #define bfd_mach_mipsisa64r2           65  #define bfd_mach_mipsisa64r2           65
   
 #define ARRAY_SIZE(a) (sizeof(a) / sizeof(a[0]))  static const struct mips_arch_choice mips_arch_choices[] =
   
 const struct mips_arch_choice mips_arch_choices[] =  
 {  {
   { "numeric",  0, 0, 0, 0,    { "numeric",  0, 0, 0, 0,
     mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },      mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
Line 3272  choose_arch_by_number (unsigned long mac Line 3280  choose_arch_by_number (unsigned long mac
   return c;    return c;
 }  }
   
 void  static void
 set_default_mips_dis_options (struct disassemble_info *info)  set_default_mips_dis_options (struct disassemble_info *info)
 {  {
   const struct mips_arch_choice *chosen_arch;    const struct mips_arch_choice *chosen_arch;
Line 3302  set_default_mips_dis_options (struct dis Line 3310  set_default_mips_dis_options (struct dis
 #endif  #endif
   
   /* Set ISA, architecture, and cp0 register names as best we can.  */    /* Set ISA, architecture, and cp0 register names as best we can.  */
 #if ! SYMTAB_AVAILABLE && 0  #if !defined(SYMTAB_AVAILABLE) && 0
   /* This is running out on a target machine, not in a host tool.    /* This is running out on a target machine, not in a host tool.
      FIXME: Where does mips_target_info come from?  */       FIXME: Where does mips_target_info come from?  */
   target_processor = mips_target_info.processor;    target_processor = mips_target_info.processor;
Line 3321  set_default_mips_dis_options (struct dis Line 3329  set_default_mips_dis_options (struct dis
 #endif  #endif
 }  }
   
 void  static void
 parse_mips_dis_option (option, len)  parse_mips_dis_option (const char *option, unsigned int len)
      const char *option;  
      unsigned int len;  
 {  {
   unsigned int i, optionlen, vallen;    unsigned int i, optionlen, vallen;
   const char *val;    const char *val;
Line 4811  print_mips16_insn_arg (char type, Line 4817  print_mips16_insn_arg (char type,
       abort ();        abort ();
     }      }
 }  }
 #endif  
   
 void  void
 print_mips_disassembler_options (FILE *stream)  print_mips_disassembler_options (FILE *stream)
Line 4836  with the -M switch (multiple options sho Line 4841  with the -M switch (multiple options sho
                            Default: based on binary being disassembled.\n"));                             Default: based on binary being disassembled.\n"));
   
   fprintf (stream, _("\n\    fprintf (stream, _("\n\
   hwr-names=ARCH           Print HWR names according to specified \n\    hwr-names=ARCH           Print HWR names according to specified\n\
                            architecture.\n\                             architecture.\n\
                            Default: based on binary being disassembled.\n"));                             Default: based on binary being disassembled.\n"));
   
Line 4865  with the -M switch (multiple options sho Line 4870  with the -M switch (multiple options sho
   
   fprintf (stream, _("\n"));    fprintf (stream, _("\n"));
 }  }
   #endif

Removed from v.1.1.1.4  
changed lines
  Added in v.1.1.1.9


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