Annotation of qemu/mips-dis.c, revision 1.1.1.3

1.1       root        1: /* Print mips instructions for GDB, the GNU debugger, or for objdump.
                      2:    Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
                      3:    2000, 2001, 2002, 2003
                      4:    Free Software Foundation, Inc.
                      5:    Contributed by Nobuyuki Hikichi(hikichi@sra.co.jp).
                      6: 
                      7: This file is part of GDB, GAS, and the GNU binutils.
                      8: 
                      9: This program is free software; you can redistribute it and/or modify
                     10: it under the terms of the GNU General Public License as published by
                     11: the Free Software Foundation; either version 2 of the License, or
                     12: (at your option) any later version.
                     13: 
                     14: This program is distributed in the hope that it will be useful,
                     15: but WITHOUT ANY WARRANTY; without even the implied warranty of
                     16: MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
                     17: GNU General Public License for more details.
                     18: 
                     19: You should have received a copy of the GNU General Public License
                     20: along with this program; if not, write to the Free Software
                     21: Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
                     22: 
                     23: #include "dis-asm.h"
                     24: 
                     25: /* mips.h.  Mips opcode list for GDB, the GNU debugger.
                     26:    Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003
                     27:    Free Software Foundation, Inc.
                     28:    Contributed by Ralph Campbell and OSF
                     29:    Commented and modified by Ian Lance Taylor, Cygnus Support
                     30: 
                     31: This file is part of GDB, GAS, and the GNU binutils.
                     32: 
                     33: GDB, GAS, and the GNU binutils are free software; you can redistribute
                     34: them and/or modify them under the terms of the GNU General Public
                     35: License as published by the Free Software Foundation; either version
                     36: 1, or (at your option) any later version.
                     37: 
                     38: GDB, GAS, and the GNU binutils are distributed in the hope that they
                     39: will be useful, but WITHOUT ANY WARRANTY; without even the implied
                     40: warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See
                     41: the GNU General Public License for more details.
                     42: 
                     43: You should have received a copy of the GNU General Public License
                     44: along with this file; see the file COPYING.  If not, write to the Free
                     45: Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
                     46: 
                     47: /* mips.h.  Mips opcode list for GDB, the GNU debugger.
                     48:    Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003
                     49:    Free Software Foundation, Inc.
                     50:    Contributed by Ralph Campbell and OSF
                     51:    Commented and modified by Ian Lance Taylor, Cygnus Support
                     52: 
                     53: This file is part of GDB, GAS, and the GNU binutils.
                     54: 
                     55: GDB, GAS, and the GNU binutils are free software; you can redistribute
                     56: them and/or modify them under the terms of the GNU General Public
                     57: License as published by the Free Software Foundation; either version
                     58: 1, or (at your option) any later version.
                     59: 
                     60: GDB, GAS, and the GNU binutils are distributed in the hope that they
                     61: will be useful, but WITHOUT ANY WARRANTY; without even the implied
                     62: warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See
                     63: the GNU General Public License for more details.
                     64: 
                     65: You should have received a copy of the GNU General Public License
                     66: along with this file; see the file COPYING.  If not, write to the Free
                     67: Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
                     68: 
                     69: /* These are bit masks and shift counts to use to access the various
                     70:    fields of an instruction.  To retrieve the X field of an
                     71:    instruction, use the expression
                     72:        (i >> OP_SH_X) & OP_MASK_X
                     73:    To set the same field (to j), use
                     74:        i = (i &~ (OP_MASK_X << OP_SH_X)) | (j << OP_SH_X)
                     75: 
                     76:    Make sure you use fields that are appropriate for the instruction,
                     77:    of course.
                     78: 
                     79:    The 'i' format uses OP, RS, RT and IMMEDIATE.
                     80: 
                     81:    The 'j' format uses OP and TARGET.
                     82: 
                     83:    The 'r' format uses OP, RS, RT, RD, SHAMT and FUNCT.
                     84: 
                     85:    The 'b' format uses OP, RS, RT and DELTA.
                     86: 
                     87:    The floating point 'i' format uses OP, RS, RT and IMMEDIATE.
                     88: 
                     89:    The floating point 'r' format uses OP, FMT, FT, FS, FD and FUNCT.
                     90: 
                     91:    A breakpoint instruction uses OP, CODE and SPEC (10 bits of the
                     92:    breakpoint instruction are not defined; Kane says the breakpoint
                     93:    code field in BREAK is 20 bits; yet MIPS assemblers and debuggers
                     94:    only use ten bits).  An optional two-operand form of break/sdbbp
                     95:    allows the lower ten bits to be set too, and MIPS32 and later
                     96:    architectures allow 20 bits to be set with a signal operand
                     97:    (using CODE20).
                     98: 
                     99:    The syscall instruction uses CODE20.
                    100: 
                    101:    The general coprocessor instructions use COPZ.  */
                    102: 
                    103: #define OP_MASK_OP             0x3f
                    104: #define OP_SH_OP               26
                    105: #define OP_MASK_RS             0x1f
                    106: #define OP_SH_RS               21
                    107: #define OP_MASK_FR             0x1f
                    108: #define OP_SH_FR               21
                    109: #define OP_MASK_FMT            0x1f
                    110: #define OP_SH_FMT              21
                    111: #define OP_MASK_BCC            0x7
                    112: #define OP_SH_BCC              18
                    113: #define OP_MASK_CODE           0x3ff
                    114: #define OP_SH_CODE             16
                    115: #define OP_MASK_CODE2          0x3ff
                    116: #define OP_SH_CODE2            6
                    117: #define OP_MASK_RT             0x1f
                    118: #define OP_SH_RT               16
                    119: #define OP_MASK_FT             0x1f
                    120: #define OP_SH_FT               16
                    121: #define OP_MASK_CACHE          0x1f
                    122: #define OP_SH_CACHE            16
                    123: #define OP_MASK_RD             0x1f
                    124: #define OP_SH_RD               11
                    125: #define OP_MASK_FS             0x1f
                    126: #define OP_SH_FS               11
                    127: #define OP_MASK_PREFX          0x1f
                    128: #define OP_SH_PREFX            11
                    129: #define OP_MASK_CCC            0x7
                    130: #define OP_SH_CCC              8
                    131: #define OP_MASK_CODE20         0xfffff /* 20 bit syscall/breakpoint code.  */
                    132: #define OP_SH_CODE20           6
                    133: #define OP_MASK_SHAMT          0x1f
                    134: #define OP_SH_SHAMT            6
                    135: #define OP_MASK_FD             0x1f
                    136: #define OP_SH_FD               6
                    137: #define OP_MASK_TARGET         0x3ffffff
                    138: #define OP_SH_TARGET           0
                    139: #define OP_MASK_COPZ           0x1ffffff
                    140: #define OP_SH_COPZ             0
                    141: #define OP_MASK_IMMEDIATE      0xffff
                    142: #define OP_SH_IMMEDIATE                0
                    143: #define OP_MASK_DELTA          0xffff
                    144: #define OP_SH_DELTA            0
                    145: #define OP_MASK_FUNCT          0x3f
                    146: #define OP_SH_FUNCT            0
                    147: #define OP_MASK_SPEC           0x3f
                    148: #define OP_SH_SPEC             0
                    149: #define OP_SH_LOCC              8       /* FP condition code.  */
                    150: #define OP_SH_HICC              18      /* FP condition code.  */
                    151: #define OP_MASK_CC              0x7
                    152: #define OP_SH_COP1NORM          25      /* Normal COP1 encoding.  */
                    153: #define OP_MASK_COP1NORM        0x1     /* a single bit.  */
                    154: #define OP_SH_COP1SPEC          21      /* COP1 encodings.  */
                    155: #define OP_MASK_COP1SPEC        0xf
                    156: #define OP_MASK_COP1SCLR        0x4
                    157: #define OP_MASK_COP1CMP         0x3
                    158: #define OP_SH_COP1CMP           4
                    159: #define OP_SH_FORMAT            21      /* FP short format field.  */
                    160: #define OP_MASK_FORMAT          0x7
                    161: #define OP_SH_TRUE              16
                    162: #define OP_MASK_TRUE            0x1
                    163: #define OP_SH_GE                17
                    164: #define OP_MASK_GE              0x01
                    165: #define OP_SH_UNSIGNED          16
                    166: #define OP_MASK_UNSIGNED        0x1
                    167: #define OP_SH_HINT              16
                    168: #define OP_MASK_HINT            0x1f
                    169: #define OP_SH_MMI               0       /* Multimedia (parallel) op.  */
                    170: #define OP_MASK_MMI             0x3f
                    171: #define OP_SH_MMISUB            6
                    172: #define OP_MASK_MMISUB          0x1f
                    173: #define OP_MASK_PERFREG                0x1f    /* Performance monitoring.  */
                    174: #define OP_SH_PERFREG          1
                    175: #define OP_SH_SEL              0       /* Coprocessor select field.  */
                    176: #define OP_MASK_SEL            0x7     /* The sel field of mfcZ and mtcZ.  */
                    177: #define OP_SH_CODE19           6       /* 19 bit wait code.  */
                    178: #define OP_MASK_CODE19         0x7ffff
                    179: #define OP_SH_ALN              21
                    180: #define OP_MASK_ALN            0x7
                    181: #define OP_SH_VSEL             21
                    182: #define OP_MASK_VSEL           0x1f
                    183: #define OP_MASK_VECBYTE                0x7     /* Selector field is really 4 bits,
                    184:                                           but 0x8-0xf don't select bytes.  */
                    185: #define OP_SH_VECBYTE          22
                    186: #define OP_MASK_VECALIGN       0x7     /* Vector byte-align (alni.ob) op.  */
                    187: #define OP_SH_VECALIGN         21
                    188: #define OP_MASK_INSMSB         0x1f    /* "ins" MSB.  */
                    189: #define OP_SH_INSMSB           11
                    190: #define OP_MASK_EXTMSBD                0x1f    /* "ext" MSBD.  */
                    191: #define OP_SH_EXTMSBD          11
                    192: 
                    193: #define        OP_OP_COP0              0x10
                    194: #define        OP_OP_COP1              0x11
                    195: #define        OP_OP_COP2              0x12
                    196: #define        OP_OP_COP3              0x13
                    197: #define        OP_OP_LWC1              0x31
                    198: #define        OP_OP_LWC2              0x32
                    199: #define        OP_OP_LWC3              0x33    /* a.k.a. pref */
                    200: #define        OP_OP_LDC1              0x35
                    201: #define        OP_OP_LDC2              0x36
                    202: #define        OP_OP_LDC3              0x37    /* a.k.a. ld */
                    203: #define        OP_OP_SWC1              0x39
                    204: #define        OP_OP_SWC2              0x3a
                    205: #define        OP_OP_SWC3              0x3b
                    206: #define        OP_OP_SDC1              0x3d
                    207: #define        OP_OP_SDC2              0x3e
                    208: #define        OP_OP_SDC3              0x3f    /* a.k.a. sd */
                    209: 
                    210: /* Values in the 'VSEL' field.  */
                    211: #define MDMX_FMTSEL_IMM_QH     0x1d
                    212: #define MDMX_FMTSEL_IMM_OB     0x1e
                    213: #define MDMX_FMTSEL_VEC_QH     0x15
                    214: #define MDMX_FMTSEL_VEC_OB     0x16
                    215: 
                    216: /* This structure holds information for a particular instruction.  */
                    217: 
                    218: struct mips_opcode
                    219: {
                    220:   /* The name of the instruction.  */
                    221:   const char *name;
                    222:   /* A string describing the arguments for this instruction.  */
                    223:   const char *args;
                    224:   /* The basic opcode for the instruction.  When assembling, this
                    225:      opcode is modified by the arguments to produce the actual opcode
                    226:      that is used.  If pinfo is INSN_MACRO, then this is 0.  */
                    227:   unsigned long match;
                    228:   /* If pinfo is not INSN_MACRO, then this is a bit mask for the
                    229:      relevant portions of the opcode when disassembling.  If the
                    230:      actual opcode anded with the match field equals the opcode field,
                    231:      then we have found the correct instruction.  If pinfo is
                    232:      INSN_MACRO, then this field is the macro identifier.  */
                    233:   unsigned long mask;
                    234:   /* For a macro, this is INSN_MACRO.  Otherwise, it is a collection
                    235:      of bits describing the instruction, notably any relevant hazard
                    236:      information.  */
                    237:   unsigned long pinfo;
                    238:   /* A collection of bits describing the instruction sets of which this
                    239:      instruction or macro is a member. */
                    240:   unsigned long membership;
                    241: };
                    242: 
                    243: /* These are the characters which may appear in the args field of an
                    244:    instruction.  They appear in the order in which the fields appear
                    245:    when the instruction is used.  Commas and parentheses in the args
                    246:    string are ignored when assembling, and written into the output
                    247:    when disassembling.
                    248: 
                    249:    Each of these characters corresponds to a mask field defined above.
                    250: 
                    251:    "<" 5 bit shift amount (OP_*_SHAMT)
                    252:    ">" shift amount between 32 and 63, stored after subtracting 32 (OP_*_SHAMT)
                    253:    "a" 26 bit target address (OP_*_TARGET)
                    254:    "b" 5 bit base register (OP_*_RS)
                    255:    "c" 10 bit breakpoint code (OP_*_CODE)
                    256:    "d" 5 bit destination register specifier (OP_*_RD)
                    257:    "h" 5 bit prefx hint (OP_*_PREFX)
                    258:    "i" 16 bit unsigned immediate (OP_*_IMMEDIATE)
                    259:    "j" 16 bit signed immediate (OP_*_DELTA)
                    260:    "k" 5 bit cache opcode in target register position (OP_*_CACHE)
                    261:        Also used for immediate operands in vr5400 vector insns.
                    262:    "o" 16 bit signed offset (OP_*_DELTA)
                    263:    "p" 16 bit PC relative branch target address (OP_*_DELTA)
                    264:    "q" 10 bit extra breakpoint code (OP_*_CODE2)
                    265:    "r" 5 bit same register used as both source and target (OP_*_RS)
                    266:    "s" 5 bit source register specifier (OP_*_RS)
                    267:    "t" 5 bit target register (OP_*_RT)
                    268:    "u" 16 bit upper 16 bits of address (OP_*_IMMEDIATE)
                    269:    "v" 5 bit same register used as both source and destination (OP_*_RS)
                    270:    "w" 5 bit same register used as both target and destination (OP_*_RT)
                    271:    "U" 5 bit same destination register in both OP_*_RD and OP_*_RT
                    272:        (used by clo and clz)
                    273:    "C" 25 bit coprocessor function code (OP_*_COPZ)
                    274:    "B" 20 bit syscall/breakpoint function code (OP_*_CODE20)
                    275:    "J" 19 bit wait function code (OP_*_CODE19)
                    276:    "x" accept and ignore register name
                    277:    "z" must be zero register
                    278:    "K" 5 bit Hardware Register (rdhwr instruction) (OP_*_RD)
                    279:    "+A" 5 bit ins/ext position, which becomes LSB (OP_*_SHAMT).
                    280:        Enforces: 0 <= pos < 32.
                    281:    "+B" 5 bit ins size, which becomes MSB (OP_*_INSMSB).
                    282:        Requires that "+A" or "+E" occur first to set position.
                    283:        Enforces: 0 < (pos+size) <= 32.
                    284:    "+C" 5 bit ext size, which becomes MSBD (OP_*_EXTMSBD).
                    285:        Requires that "+A" or "+E" occur first to set position.
                    286:        Enforces: 0 < (pos+size) <= 32.
                    287:        (Also used by "dext" w/ different limits, but limits for
                    288:        that are checked by the M_DEXT macro.)
                    289:    "+E" 5 bit dins/dext position, which becomes LSB-32 (OP_*_SHAMT).
                    290:        Enforces: 32 <= pos < 64.
                    291:    "+F" 5 bit "dinsm" size, which becomes MSB-32 (OP_*_INSMSB).
                    292:        Requires that "+A" or "+E" occur first to set position.
                    293:        Enforces: 32 < (pos+size) <= 64.
                    294:    "+G" 5 bit "dextm" size, which becomes MSBD-32 (OP_*_EXTMSBD).
                    295:        Requires that "+A" or "+E" occur first to set position.
                    296:        Enforces: 32 < (pos+size) <= 64.
                    297:    "+H" 5 bit "dextu" size, which becomes MSBD (OP_*_EXTMSBD).
                    298:        Requires that "+A" or "+E" occur first to set position.
                    299:        Enforces: 32 < (pos+size) <= 64.
                    300: 
                    301:    Floating point instructions:
                    302:    "D" 5 bit destination register (OP_*_FD)
                    303:    "M" 3 bit compare condition code (OP_*_CCC) (only used for mips4 and up)
                    304:    "N" 3 bit branch condition code (OP_*_BCC) (only used for mips4 and up)
                    305:    "S" 5 bit fs source 1 register (OP_*_FS)
                    306:    "T" 5 bit ft source 2 register (OP_*_FT)
                    307:    "R" 5 bit fr source 3 register (OP_*_FR)
                    308:    "V" 5 bit same register used as floating source and destination (OP_*_FS)
                    309:    "W" 5 bit same register used as floating target and destination (OP_*_FT)
                    310: 
                    311:    Coprocessor instructions:
                    312:    "E" 5 bit target register (OP_*_RT)
                    313:    "G" 5 bit destination register (OP_*_RD)
                    314:    "H" 3 bit sel field for (d)mtc* and (d)mfc* (OP_*_SEL)
                    315:    "P" 5 bit performance-monitor register (OP_*_PERFREG)
                    316:    "e" 5 bit vector register byte specifier (OP_*_VECBYTE)
                    317:    "%" 3 bit immediate vr5400 vector alignment operand (OP_*_VECALIGN)
                    318:    see also "k" above
                    319:    "+D" Combined destination register ("G") and sel ("H") for CP0 ops,
                    320:        for pretty-printing in disassembly only.
                    321: 
                    322:    Macro instructions:
                    323:    "A" General 32 bit expression
                    324:    "I" 32 bit immediate (value placed in imm_expr).
                    325:    "+I" 32 bit immediate (value placed in imm2_expr).
                    326:    "F" 64 bit floating point constant in .rdata
                    327:    "L" 64 bit floating point constant in .lit8
                    328:    "f" 32 bit floating point constant
                    329:    "l" 32 bit floating point constant in .lit4
                    330: 
                    331:    MDMX instruction operands (note that while these use the FP register
                    332:    fields, they accept both $fN and $vN names for the registers):  
                    333:    "O" MDMX alignment offset (OP_*_ALN)
                    334:    "Q" MDMX vector/scalar/immediate source (OP_*_VSEL and OP_*_FT)
                    335:    "X" MDMX destination register (OP_*_FD) 
                    336:    "Y" MDMX source register (OP_*_FS)
                    337:    "Z" MDMX source register (OP_*_FT)
                    338: 
                    339:    Other:
                    340:    "()" parens surrounding optional value
                    341:    ","  separates operands
                    342:    "[]" brackets around index for vector-op scalar operand specifier (vr5400)
                    343:    "+"  Start of extension sequence.
                    344: 
                    345:    Characters used so far, for quick reference when adding more:
                    346:    "%[]<>(),+"
                    347:    "ABCDEFGHIJKLMNOPQRSTUVWXYZ"
                    348:    "abcdefhijklopqrstuvwxz"
                    349: 
                    350:    Extension character sequences used so far ("+" followed by the
                    351:    following), for quick reference when adding more:
                    352:    "ABCDEFGHI"
                    353: */
                    354: 
                    355: /* These are the bits which may be set in the pinfo field of an
                    356:    instructions, if it is not equal to INSN_MACRO.  */
                    357: 
                    358: /* Modifies the general purpose register in OP_*_RD.  */
                    359: #define INSN_WRITE_GPR_D            0x00000001
                    360: /* Modifies the general purpose register in OP_*_RT.  */
                    361: #define INSN_WRITE_GPR_T            0x00000002
                    362: /* Modifies general purpose register 31.  */
                    363: #define INSN_WRITE_GPR_31           0x00000004
                    364: /* Modifies the floating point register in OP_*_FD.  */
                    365: #define INSN_WRITE_FPR_D            0x00000008
                    366: /* Modifies the floating point register in OP_*_FS.  */
                    367: #define INSN_WRITE_FPR_S            0x00000010
                    368: /* Modifies the floating point register in OP_*_FT.  */
                    369: #define INSN_WRITE_FPR_T            0x00000020
                    370: /* Reads the general purpose register in OP_*_RS.  */
                    371: #define INSN_READ_GPR_S             0x00000040
                    372: /* Reads the general purpose register in OP_*_RT.  */
                    373: #define INSN_READ_GPR_T             0x00000080
                    374: /* Reads the floating point register in OP_*_FS.  */
                    375: #define INSN_READ_FPR_S             0x00000100
                    376: /* Reads the floating point register in OP_*_FT.  */
                    377: #define INSN_READ_FPR_T             0x00000200
                    378: /* Reads the floating point register in OP_*_FR.  */
                    379: #define INSN_READ_FPR_R                    0x00000400
                    380: /* Modifies coprocessor condition code.  */
                    381: #define INSN_WRITE_COND_CODE        0x00000800
                    382: /* Reads coprocessor condition code.  */
                    383: #define INSN_READ_COND_CODE         0x00001000
                    384: /* TLB operation.  */
                    385: #define INSN_TLB                    0x00002000
                    386: /* Reads coprocessor register other than floating point register.  */
                    387: #define INSN_COP                    0x00004000
                    388: /* Instruction loads value from memory, requiring delay.  */
                    389: #define INSN_LOAD_MEMORY_DELAY      0x00008000
                    390: /* Instruction loads value from coprocessor, requiring delay.  */
                    391: #define INSN_LOAD_COPROC_DELAY     0x00010000
                    392: /* Instruction has unconditional branch delay slot.  */
                    393: #define INSN_UNCOND_BRANCH_DELAY    0x00020000
                    394: /* Instruction has conditional branch delay slot.  */
                    395: #define INSN_COND_BRANCH_DELAY      0x00040000
                    396: /* Conditional branch likely: if branch not taken, insn nullified.  */
                    397: #define INSN_COND_BRANCH_LIKELY            0x00080000
                    398: /* Moves to coprocessor register, requiring delay.  */
                    399: #define INSN_COPROC_MOVE_DELAY      0x00100000
                    400: /* Loads coprocessor register from memory, requiring delay.  */
                    401: #define INSN_COPROC_MEMORY_DELAY    0x00200000
                    402: /* Reads the HI register.  */
                    403: #define INSN_READ_HI               0x00400000
                    404: /* Reads the LO register.  */
                    405: #define INSN_READ_LO               0x00800000
                    406: /* Modifies the HI register.  */
                    407: #define INSN_WRITE_HI              0x01000000
                    408: /* Modifies the LO register.  */
                    409: #define INSN_WRITE_LO              0x02000000
                    410: /* Takes a trap (easier to keep out of delay slot).  */
                    411: #define INSN_TRAP                   0x04000000
                    412: /* Instruction stores value into memory.  */
                    413: #define INSN_STORE_MEMORY          0x08000000
                    414: /* Instruction uses single precision floating point.  */
                    415: #define FP_S                       0x10000000
                    416: /* Instruction uses double precision floating point.  */
                    417: #define FP_D                       0x20000000
                    418: /* Instruction is part of the tx39's integer multiply family.    */
                    419: #define INSN_MULT                   0x40000000
                    420: /* Instruction synchronize shared memory.  */
                    421: #define INSN_SYNC                  0x80000000
                    422: /* Instruction reads MDMX accumulator.  XXX FIXME: No bits left!  */
                    423: #define INSN_READ_MDMX_ACC         0
                    424: /* Instruction writes MDMX accumulator.  XXX FIXME: No bits left!  */
                    425: #define INSN_WRITE_MDMX_ACC        0
                    426: 
                    427: /* Instruction is actually a macro.  It should be ignored by the
                    428:    disassembler, and requires special treatment by the assembler.  */
                    429: #define INSN_MACRO                  0xffffffff
                    430: 
                    431: /* Masks used to mark instructions to indicate which MIPS ISA level
                    432:    they were introduced in.  ISAs, as defined below, are logical
                    433:    ORs of these bits, indicating that they support the instructions
                    434:    defined at the given level.  */
                    435: 
                    436: #define INSN_ISA_MASK            0x00000fff
                    437: #define INSN_ISA1                 0x00000001
                    438: #define INSN_ISA2                 0x00000002
                    439: #define INSN_ISA3                 0x00000004
                    440: #define INSN_ISA4                 0x00000008
                    441: #define INSN_ISA5                 0x00000010
                    442: #define INSN_ISA32                0x00000020
                    443: #define INSN_ISA64                0x00000040
                    444: #define INSN_ISA32R2              0x00000080
                    445: #define INSN_ISA64R2              0x00000100
                    446: 
                    447: /* Masks used for MIPS-defined ASEs.  */
                    448: #define INSN_ASE_MASK            0x0000f000
                    449: 
                    450: /* MIPS 16 ASE */
                    451: #define INSN_MIPS16               0x00002000
                    452: /* MIPS-3D ASE */
                    453: #define INSN_MIPS3D               0x00004000
                    454: /* MDMX ASE */ 
                    455: #define INSN_MDMX                 0x00008000
                    456: 
                    457: /* Chip specific instructions.  These are bitmasks.  */
                    458: 
                    459: /* MIPS R4650 instruction.  */
                    460: #define INSN_4650                 0x00010000
                    461: /* LSI R4010 instruction.  */
                    462: #define INSN_4010                 0x00020000
                    463: /* NEC VR4100 instruction.  */
                    464: #define INSN_4100                 0x00040000
                    465: /* Toshiba R3900 instruction.  */
                    466: #define INSN_3900                 0x00080000
                    467: /* MIPS R10000 instruction.  */
                    468: #define INSN_10000                0x00100000
                    469: /* Broadcom SB-1 instruction.  */
                    470: #define INSN_SB1                  0x00200000
                    471: /* NEC VR4111/VR4181 instruction.  */
                    472: #define INSN_4111                 0x00400000
                    473: /* NEC VR4120 instruction.  */
                    474: #define INSN_4120                 0x00800000
                    475: /* NEC VR5400 instruction.  */
                    476: #define INSN_5400                0x01000000
                    477: /* NEC VR5500 instruction.  */
                    478: #define INSN_5500                0x02000000
                    479: 
                    480: /* MIPS ISA defines, use instead of hardcoding ISA level.  */
                    481: 
                    482: #define       ISA_UNKNOWN     0               /* Gas internal use.  */
                    483: #define       ISA_MIPS1       (INSN_ISA1)
                    484: #define       ISA_MIPS2       (ISA_MIPS1 | INSN_ISA2)
                    485: #define       ISA_MIPS3       (ISA_MIPS2 | INSN_ISA3)
                    486: #define       ISA_MIPS4       (ISA_MIPS3 | INSN_ISA4)
                    487: #define       ISA_MIPS5       (ISA_MIPS4 | INSN_ISA5)
                    488: 
                    489: #define       ISA_MIPS32      (ISA_MIPS2 | INSN_ISA32)
                    490: #define       ISA_MIPS64      (ISA_MIPS5 | INSN_ISA32 | INSN_ISA64)
                    491: 
                    492: #define       ISA_MIPS32R2    (ISA_MIPS32 | INSN_ISA32R2)
                    493: #define       ISA_MIPS64R2    (ISA_MIPS64 | INSN_ISA32R2 | INSN_ISA64R2)
                    494: 
                    495: 
                    496: /* CPU defines, use instead of hardcoding processor number. Keep this
                    497:    in sync with bfd/archures.c in order for machine selection to work.  */
                    498: #define CPU_UNKNOWN    0               /* Gas internal use.  */
                    499: #define CPU_R3000      3000
                    500: #define CPU_R3900      3900
                    501: #define CPU_R4000      4000
                    502: #define CPU_R4010      4010
                    503: #define CPU_VR4100     4100
                    504: #define CPU_R4111      4111
                    505: #define CPU_VR4120     4120
                    506: #define CPU_R4300      4300
                    507: #define CPU_R4400      4400
                    508: #define CPU_R4600      4600
                    509: #define CPU_R4650      4650
                    510: #define CPU_R5000      5000
                    511: #define CPU_VR5400     5400
                    512: #define CPU_VR5500     5500
                    513: #define CPU_R6000      6000
                    514: #define CPU_RM7000     7000
                    515: #define CPU_R8000      8000
                    516: #define CPU_R10000     10000
                    517: #define CPU_R12000     12000
                    518: #define CPU_MIPS16     16
                    519: #define CPU_MIPS32     32
                    520: #define CPU_MIPS32R2   33
                    521: #define CPU_MIPS5       5
                    522: #define CPU_MIPS64      64
                    523: #define CPU_MIPS64R2   65
                    524: #define CPU_SB1         12310201        /* octal 'SB', 01.  */
                    525: 
                    526: /* Test for membership in an ISA including chip specific ISAs.  INSN
                    527:    is pointer to an element of the opcode table; ISA is the specified
                    528:    ISA/ASE bitmask to test against; and CPU is the CPU specific ISA to
                    529:    test, or zero if no CPU specific ISA test is desired.  */
                    530: 
1.1.1.3 ! root      531: #if 0
1.1       root      532: #define OPCODE_IS_MEMBER(insn, isa, cpu)                               \
                    533:     (((insn)->membership & isa) != 0                                   \
                    534:      || (cpu == CPU_R4650 && ((insn)->membership & INSN_4650) != 0)    \
                    535:      || (cpu == CPU_RM7000 && ((insn)->membership & INSN_4650) != 0)   \
                    536:      || (cpu == CPU_R4010 && ((insn)->membership & INSN_4010) != 0)    \
                    537:      || (cpu == CPU_VR4100 && ((insn)->membership & INSN_4100) != 0)   \
                    538:      || (cpu == CPU_R3900 && ((insn)->membership & INSN_3900) != 0)    \
                    539:      || ((cpu == CPU_R10000 || cpu == CPU_R12000)                      \
                    540:         && ((insn)->membership & INSN_10000) != 0)                     \
                    541:      || (cpu == CPU_SB1 && ((insn)->membership & INSN_SB1) != 0)       \
                    542:      || (cpu == CPU_R4111 && ((insn)->membership & INSN_4111) != 0)    \
                    543:      || (cpu == CPU_VR4120 && ((insn)->membership & INSN_4120) != 0)   \
                    544:      || (cpu == CPU_VR5400 && ((insn)->membership & INSN_5400) != 0)   \
                    545:      || (cpu == CPU_VR5500 && ((insn)->membership & INSN_5500) != 0)   \
                    546:      || 0)     /* Please keep this term for easier source merging.  */
1.1.1.3 ! root      547: #else
        !           548: #define OPCODE_IS_MEMBER(insn, isa, cpu)                               \
        !           549:     (1 != 0)
        !           550: #endif
1.1       root      551: 
                    552: /* This is a list of macro expanded instructions.
                    553: 
                    554:    _I appended means immediate
                    555:    _A appended means address
                    556:    _AB appended means address with base register
                    557:    _D appended means 64 bit floating point constant
                    558:    _S appended means 32 bit floating point constant.  */
                    559: 
                    560: enum
                    561: {
                    562:   M_ABS,
                    563:   M_ADD_I,
                    564:   M_ADDU_I,
                    565:   M_AND_I,
                    566:   M_BEQ,
                    567:   M_BEQ_I,
                    568:   M_BEQL_I,
                    569:   M_BGE,
                    570:   M_BGEL,
                    571:   M_BGE_I,
                    572:   M_BGEL_I,
                    573:   M_BGEU,
                    574:   M_BGEUL,
                    575:   M_BGEU_I,
                    576:   M_BGEUL_I,
                    577:   M_BGT,
                    578:   M_BGTL,
                    579:   M_BGT_I,
                    580:   M_BGTL_I,
                    581:   M_BGTU,
                    582:   M_BGTUL,
                    583:   M_BGTU_I,
                    584:   M_BGTUL_I,
                    585:   M_BLE,
                    586:   M_BLEL,
                    587:   M_BLE_I,
                    588:   M_BLEL_I,
                    589:   M_BLEU,
                    590:   M_BLEUL,
                    591:   M_BLEU_I,
                    592:   M_BLEUL_I,
                    593:   M_BLT,
                    594:   M_BLTL,
                    595:   M_BLT_I,
                    596:   M_BLTL_I,
                    597:   M_BLTU,
                    598:   M_BLTUL,
                    599:   M_BLTU_I,
                    600:   M_BLTUL_I,
                    601:   M_BNE,
                    602:   M_BNE_I,
                    603:   M_BNEL_I,
                    604:   M_DABS,
                    605:   M_DADD_I,
                    606:   M_DADDU_I,
                    607:   M_DDIV_3,
                    608:   M_DDIV_3I,
                    609:   M_DDIVU_3,
                    610:   M_DDIVU_3I,
                    611:   M_DEXT,
                    612:   M_DINS,
                    613:   M_DIV_3,
                    614:   M_DIV_3I,
                    615:   M_DIVU_3,
                    616:   M_DIVU_3I,
                    617:   M_DLA_AB,
                    618:   M_DLCA_AB,
                    619:   M_DLI,
                    620:   M_DMUL,
                    621:   M_DMUL_I,
                    622:   M_DMULO,
                    623:   M_DMULO_I,
                    624:   M_DMULOU,
                    625:   M_DMULOU_I,
                    626:   M_DREM_3,
                    627:   M_DREM_3I,
                    628:   M_DREMU_3,
                    629:   M_DREMU_3I,
                    630:   M_DSUB_I,
                    631:   M_DSUBU_I,
                    632:   M_DSUBU_I_2,
                    633:   M_J_A,
                    634:   M_JAL_1,
                    635:   M_JAL_2,
                    636:   M_JAL_A,
                    637:   M_L_DOB,
                    638:   M_L_DAB,
                    639:   M_LA_AB,
                    640:   M_LB_A,
                    641:   M_LB_AB,
                    642:   M_LBU_A,
                    643:   M_LBU_AB,
                    644:   M_LCA_AB,
                    645:   M_LD_A,
                    646:   M_LD_OB,
                    647:   M_LD_AB,
                    648:   M_LDC1_AB,
                    649:   M_LDC2_AB,
                    650:   M_LDC3_AB,
                    651:   M_LDL_AB,
                    652:   M_LDR_AB,
                    653:   M_LH_A,
                    654:   M_LH_AB,
                    655:   M_LHU_A,
                    656:   M_LHU_AB,
                    657:   M_LI,
                    658:   M_LI_D,
                    659:   M_LI_DD,
                    660:   M_LI_S,
                    661:   M_LI_SS,
                    662:   M_LL_AB,
                    663:   M_LLD_AB,
                    664:   M_LS_A,
                    665:   M_LW_A,
                    666:   M_LW_AB,
                    667:   M_LWC0_A,
                    668:   M_LWC0_AB,
                    669:   M_LWC1_A,
                    670:   M_LWC1_AB,
                    671:   M_LWC2_A,
                    672:   M_LWC2_AB,
                    673:   M_LWC3_A,
                    674:   M_LWC3_AB,
                    675:   M_LWL_A,
                    676:   M_LWL_AB,
                    677:   M_LWR_A,
                    678:   M_LWR_AB,
                    679:   M_LWU_AB,
                    680:   M_MOVE,
                    681:   M_MUL,
                    682:   M_MUL_I,
                    683:   M_MULO,
                    684:   M_MULO_I,
                    685:   M_MULOU,
                    686:   M_MULOU_I,
                    687:   M_NOR_I,
                    688:   M_OR_I,
                    689:   M_REM_3,
                    690:   M_REM_3I,
                    691:   M_REMU_3,
                    692:   M_REMU_3I,
                    693:   M_DROL,
                    694:   M_ROL,
                    695:   M_DROL_I,
                    696:   M_ROL_I,
                    697:   M_DROR,
                    698:   M_ROR,
                    699:   M_DROR_I,
                    700:   M_ROR_I,
                    701:   M_S_DA,
                    702:   M_S_DOB,
                    703:   M_S_DAB,
                    704:   M_S_S,
                    705:   M_SC_AB,
                    706:   M_SCD_AB,
                    707:   M_SD_A,
                    708:   M_SD_OB,
                    709:   M_SD_AB,
                    710:   M_SDC1_AB,
                    711:   M_SDC2_AB,
                    712:   M_SDC3_AB,
                    713:   M_SDL_AB,
                    714:   M_SDR_AB,
                    715:   M_SEQ,
                    716:   M_SEQ_I,
                    717:   M_SGE,
                    718:   M_SGE_I,
                    719:   M_SGEU,
                    720:   M_SGEU_I,
                    721:   M_SGT,
                    722:   M_SGT_I,
                    723:   M_SGTU,
                    724:   M_SGTU_I,
                    725:   M_SLE,
                    726:   M_SLE_I,
                    727:   M_SLEU,
                    728:   M_SLEU_I,
                    729:   M_SLT_I,
                    730:   M_SLTU_I,
                    731:   M_SNE,
                    732:   M_SNE_I,
                    733:   M_SB_A,
                    734:   M_SB_AB,
                    735:   M_SH_A,
                    736:   M_SH_AB,
                    737:   M_SW_A,
                    738:   M_SW_AB,
                    739:   M_SWC0_A,
                    740:   M_SWC0_AB,
                    741:   M_SWC1_A,
                    742:   M_SWC1_AB,
                    743:   M_SWC2_A,
                    744:   M_SWC2_AB,
                    745:   M_SWC3_A,
                    746:   M_SWC3_AB,
                    747:   M_SWL_A,
                    748:   M_SWL_AB,
                    749:   M_SWR_A,
                    750:   M_SWR_AB,
                    751:   M_SUB_I,
                    752:   M_SUBU_I,
                    753:   M_SUBU_I_2,
                    754:   M_TEQ_I,
                    755:   M_TGE_I,
                    756:   M_TGEU_I,
                    757:   M_TLT_I,
                    758:   M_TLTU_I,
                    759:   M_TNE_I,
                    760:   M_TRUNCWD,
                    761:   M_TRUNCWS,
                    762:   M_ULD,
                    763:   M_ULD_A,
                    764:   M_ULH,
                    765:   M_ULH_A,
                    766:   M_ULHU,
                    767:   M_ULHU_A,
                    768:   M_ULW,
                    769:   M_ULW_A,
                    770:   M_USH,
                    771:   M_USH_A,
                    772:   M_USW,
                    773:   M_USW_A,
                    774:   M_USD,
                    775:   M_USD_A,
                    776:   M_XOR_I,
                    777:   M_COP0,
                    778:   M_COP1,
                    779:   M_COP2,
                    780:   M_COP3,
                    781:   M_NUM_MACROS
                    782: };
                    783: 
                    784: 
                    785: /* The order of overloaded instructions matters.  Label arguments and
                    786:    register arguments look the same. Instructions that can have either
                    787:    for arguments must apear in the correct order in this table for the
                    788:    assembler to pick the right one. In other words, entries with
                    789:    immediate operands must apear after the same instruction with
                    790:    registers.
                    791: 
                    792:    Many instructions are short hand for other instructions (i.e., The
                    793:    jal <register> instruction is short for jalr <register>).  */
                    794: 
                    795: extern const struct mips_opcode mips_builtin_opcodes[];
                    796: extern const int bfd_mips_num_builtin_opcodes;
                    797: extern struct mips_opcode *mips_opcodes;
                    798: extern int bfd_mips_num_opcodes;
                    799: #define NUMOPCODES bfd_mips_num_opcodes
                    800: 
                    801: 
                    802: /* The rest of this file adds definitions for the mips16 TinyRISC
                    803:    processor.  */
                    804: 
                    805: /* These are the bitmasks and shift counts used for the different
                    806:    fields in the instruction formats.  Other than OP, no masks are
                    807:    provided for the fixed portions of an instruction, since they are
                    808:    not needed.
                    809: 
                    810:    The I format uses IMM11.
                    811: 
                    812:    The RI format uses RX and IMM8.
                    813: 
                    814:    The RR format uses RX, and RY.
                    815: 
                    816:    The RRI format uses RX, RY, and IMM5.
                    817: 
                    818:    The RRR format uses RX, RY, and RZ.
                    819: 
                    820:    The RRI_A format uses RX, RY, and IMM4.
                    821: 
                    822:    The SHIFT format uses RX, RY, and SHAMT.
                    823: 
                    824:    The I8 format uses IMM8.
                    825: 
                    826:    The I8_MOVR32 format uses RY and REGR32.
                    827: 
                    828:    The IR_MOV32R format uses REG32R and MOV32Z.
                    829: 
                    830:    The I64 format uses IMM8.
                    831: 
                    832:    The RI64 format uses RY and IMM5.
                    833:    */
                    834: 
                    835: #define MIPS16OP_MASK_OP       0x1f
                    836: #define MIPS16OP_SH_OP         11
                    837: #define MIPS16OP_MASK_IMM11    0x7ff
                    838: #define MIPS16OP_SH_IMM11      0
                    839: #define MIPS16OP_MASK_RX       0x7
                    840: #define MIPS16OP_SH_RX         8
                    841: #define MIPS16OP_MASK_IMM8     0xff
                    842: #define MIPS16OP_SH_IMM8       0
                    843: #define MIPS16OP_MASK_RY       0x7
                    844: #define MIPS16OP_SH_RY         5
                    845: #define MIPS16OP_MASK_IMM5     0x1f
                    846: #define MIPS16OP_SH_IMM5       0
                    847: #define MIPS16OP_MASK_RZ       0x7
                    848: #define MIPS16OP_SH_RZ         2
                    849: #define MIPS16OP_MASK_IMM4     0xf
                    850: #define MIPS16OP_SH_IMM4       0
                    851: #define MIPS16OP_MASK_REGR32   0x1f
                    852: #define MIPS16OP_SH_REGR32     0
                    853: #define MIPS16OP_MASK_REG32R   0x1f
                    854: #define MIPS16OP_SH_REG32R     3
                    855: #define MIPS16OP_EXTRACT_REG32R(i) ((((i) >> 5) & 7) | ((i) & 0x18))
                    856: #define MIPS16OP_MASK_MOVE32Z  0x7
                    857: #define MIPS16OP_SH_MOVE32Z    0
                    858: #define MIPS16OP_MASK_IMM6     0x3f
                    859: #define MIPS16OP_SH_IMM6       5
                    860: 
                    861: /* These are the characters which may appears in the args field of an
                    862:    instruction.  They appear in the order in which the fields appear
                    863:    when the instruction is used.  Commas and parentheses in the args
                    864:    string are ignored when assembling, and written into the output
                    865:    when disassembling.
                    866: 
                    867:    "y" 3 bit register (MIPS16OP_*_RY)
                    868:    "x" 3 bit register (MIPS16OP_*_RX)
                    869:    "z" 3 bit register (MIPS16OP_*_RZ)
                    870:    "Z" 3 bit register (MIPS16OP_*_MOVE32Z)
                    871:    "v" 3 bit same register as source and destination (MIPS16OP_*_RX)
                    872:    "w" 3 bit same register as source and destination (MIPS16OP_*_RY)
                    873:    "0" zero register ($0)
                    874:    "S" stack pointer ($sp or $29)
                    875:    "P" program counter
                    876:    "R" return address register ($ra or $31)
                    877:    "X" 5 bit MIPS register (MIPS16OP_*_REGR32)
                    878:    "Y" 5 bit MIPS register (MIPS16OP_*_REG32R)
                    879:    "6" 6 bit unsigned break code (MIPS16OP_*_IMM6)
                    880:    "a" 26 bit jump address
                    881:    "e" 11 bit extension value
                    882:    "l" register list for entry instruction
                    883:    "L" register list for exit instruction
                    884: 
                    885:    The remaining codes may be extended.  Except as otherwise noted,
                    886:    the full extended operand is a 16 bit signed value.
                    887:    "<" 3 bit unsigned shift count * 0 (MIPS16OP_*_RZ) (full 5 bit unsigned)
                    888:    ">" 3 bit unsigned shift count * 0 (MIPS16OP_*_RX) (full 5 bit unsigned)
                    889:    "[" 3 bit unsigned shift count * 0 (MIPS16OP_*_RZ) (full 6 bit unsigned)
                    890:    "]" 3 bit unsigned shift count * 0 (MIPS16OP_*_RX) (full 6 bit unsigned)
                    891:    "4" 4 bit signed immediate * 0 (MIPS16OP_*_IMM4) (full 15 bit signed)
                    892:    "5" 5 bit unsigned immediate * 0 (MIPS16OP_*_IMM5)
                    893:    "H" 5 bit unsigned immediate * 2 (MIPS16OP_*_IMM5)
                    894:    "W" 5 bit unsigned immediate * 4 (MIPS16OP_*_IMM5)
                    895:    "D" 5 bit unsigned immediate * 8 (MIPS16OP_*_IMM5)
                    896:    "j" 5 bit signed immediate * 0 (MIPS16OP_*_IMM5)
                    897:    "8" 8 bit unsigned immediate * 0 (MIPS16OP_*_IMM8)
                    898:    "V" 8 bit unsigned immediate * 4 (MIPS16OP_*_IMM8)
                    899:    "C" 8 bit unsigned immediate * 8 (MIPS16OP_*_IMM8)
                    900:    "U" 8 bit unsigned immediate * 0 (MIPS16OP_*_IMM8) (full 16 bit unsigned)
                    901:    "k" 8 bit signed immediate * 0 (MIPS16OP_*_IMM8)
                    902:    "K" 8 bit signed immediate * 8 (MIPS16OP_*_IMM8)
                    903:    "p" 8 bit conditional branch address (MIPS16OP_*_IMM8)
                    904:    "q" 11 bit branch address (MIPS16OP_*_IMM11)
                    905:    "A" 8 bit PC relative address * 4 (MIPS16OP_*_IMM8)
                    906:    "B" 5 bit PC relative address * 8 (MIPS16OP_*_IMM5)
                    907:    "E" 5 bit PC relative address * 4 (MIPS16OP_*_IMM5)
                    908:    */
                    909: 
                    910: /* For the mips16, we use the same opcode table format and a few of
                    911:    the same flags.  However, most of the flags are different.  */
                    912: 
                    913: /* Modifies the register in MIPS16OP_*_RX.  */
                    914: #define MIPS16_INSN_WRITE_X                0x00000001
                    915: /* Modifies the register in MIPS16OP_*_RY.  */
                    916: #define MIPS16_INSN_WRITE_Y                0x00000002
                    917: /* Modifies the register in MIPS16OP_*_RZ.  */
                    918: #define MIPS16_INSN_WRITE_Z                0x00000004
                    919: /* Modifies the T ($24) register.  */
                    920: #define MIPS16_INSN_WRITE_T                0x00000008
                    921: /* Modifies the SP ($29) register.  */
                    922: #define MIPS16_INSN_WRITE_SP               0x00000010
                    923: /* Modifies the RA ($31) register.  */
                    924: #define MIPS16_INSN_WRITE_31               0x00000020
                    925: /* Modifies the general purpose register in MIPS16OP_*_REG32R.  */
                    926: #define MIPS16_INSN_WRITE_GPR_Y                    0x00000040
                    927: /* Reads the register in MIPS16OP_*_RX.  */
                    928: #define MIPS16_INSN_READ_X                 0x00000080
                    929: /* Reads the register in MIPS16OP_*_RY.  */
                    930: #define MIPS16_INSN_READ_Y                 0x00000100
                    931: /* Reads the register in MIPS16OP_*_MOVE32Z.  */
                    932: #define MIPS16_INSN_READ_Z                 0x00000200
                    933: /* Reads the T ($24) register.  */
                    934: #define MIPS16_INSN_READ_T                 0x00000400
                    935: /* Reads the SP ($29) register.  */
                    936: #define MIPS16_INSN_READ_SP                0x00000800
                    937: /* Reads the RA ($31) register.  */
                    938: #define MIPS16_INSN_READ_31                0x00001000
                    939: /* Reads the program counter.  */
                    940: #define MIPS16_INSN_READ_PC                0x00002000
                    941: /* Reads the general purpose register in MIPS16OP_*_REGR32.  */
                    942: #define MIPS16_INSN_READ_GPR_X             0x00004000
                    943: /* Is a branch insn. */
                    944: #define MIPS16_INSN_BRANCH                  0x00010000
                    945: 
                    946: /* The following flags have the same value for the mips16 opcode
                    947:    table:
                    948:    INSN_UNCOND_BRANCH_DELAY
                    949:    INSN_COND_BRANCH_DELAY
                    950:    INSN_COND_BRANCH_LIKELY (never used)
                    951:    INSN_READ_HI
                    952:    INSN_READ_LO
                    953:    INSN_WRITE_HI
                    954:    INSN_WRITE_LO
                    955:    INSN_TRAP
                    956:    INSN_ISA3
                    957:    */
                    958: 
                    959: extern const struct mips_opcode mips16_opcodes[];
                    960: extern const int bfd_mips16_num_opcodes;
                    961: 
                    962: /* Short hand so the lines aren't too long.  */
                    963: 
                    964: #define LDD     INSN_LOAD_MEMORY_DELAY
                    965: #define LCD    INSN_LOAD_COPROC_DELAY
                    966: #define UBD     INSN_UNCOND_BRANCH_DELAY
                    967: #define CBD    INSN_COND_BRANCH_DELAY
                    968: #define COD     INSN_COPROC_MOVE_DELAY
                    969: #define CLD    INSN_COPROC_MEMORY_DELAY
                    970: #define CBL    INSN_COND_BRANCH_LIKELY
                    971: #define TRAP   INSN_TRAP
                    972: #define SM     INSN_STORE_MEMORY
                    973: 
                    974: #define WR_d    INSN_WRITE_GPR_D
                    975: #define WR_t    INSN_WRITE_GPR_T
                    976: #define WR_31   INSN_WRITE_GPR_31
                    977: #define WR_D    INSN_WRITE_FPR_D
                    978: #define WR_T   INSN_WRITE_FPR_T
                    979: #define WR_S   INSN_WRITE_FPR_S
                    980: #define RD_s    INSN_READ_GPR_S
                    981: #define RD_b    INSN_READ_GPR_S
                    982: #define RD_t    INSN_READ_GPR_T
                    983: #define RD_S    INSN_READ_FPR_S
                    984: #define RD_T    INSN_READ_FPR_T
                    985: #define RD_R   INSN_READ_FPR_R
                    986: #define WR_CC  INSN_WRITE_COND_CODE
                    987: #define RD_CC  INSN_READ_COND_CODE
                    988: #define RD_C0   INSN_COP
                    989: #define RD_C1  INSN_COP
                    990: #define RD_C2   INSN_COP
                    991: #define RD_C3   INSN_COP
                    992: #define WR_C0   INSN_COP
                    993: #define WR_C1  INSN_COP
                    994: #define WR_C2   INSN_COP
                    995: #define WR_C3   INSN_COP
                    996: 
                    997: #define WR_HI  INSN_WRITE_HI
                    998: #define RD_HI  INSN_READ_HI
                    999: #define MOD_HI  WR_HI|RD_HI
                   1000: 
                   1001: #define WR_LO  INSN_WRITE_LO
                   1002: #define RD_LO  INSN_READ_LO
                   1003: #define MOD_LO  WR_LO|RD_LO
                   1004: 
                   1005: #define WR_HILO WR_HI|WR_LO
                   1006: #define RD_HILO RD_HI|RD_LO
                   1007: #define MOD_HILO WR_HILO|RD_HILO
                   1008: 
                   1009: #define IS_M    INSN_MULT
                   1010: 
                   1011: #define WR_MACC INSN_WRITE_MDMX_ACC
                   1012: #define RD_MACC INSN_READ_MDMX_ACC
                   1013: 
                   1014: #define I1     INSN_ISA1
                   1015: #define I2     INSN_ISA2
                   1016: #define I3     INSN_ISA3
                   1017: #define I4     INSN_ISA4
                   1018: #define I5     INSN_ISA5
                   1019: #define I32    INSN_ISA32
                   1020: #define I64     INSN_ISA64
                   1021: #define I33    INSN_ISA32R2
                   1022: #define I65    INSN_ISA64R2
                   1023: 
                   1024: /* MIPS64 MIPS-3D ASE support.  */
                   1025: #define I16     INSN_MIPS16
                   1026: 
                   1027: /* MIPS64 MIPS-3D ASE support.  */
                   1028: #define M3D     INSN_MIPS3D
                   1029: 
                   1030: /* MIPS64 MDMX ASE support.  */
                   1031: #define MX      INSN_MDMX
                   1032: 
                   1033: #define P3     INSN_4650
                   1034: #define L1     INSN_4010
                   1035: #define V1     (INSN_4100 | INSN_4111 | INSN_4120)
                   1036: #define T3      INSN_3900
                   1037: #define M1     INSN_10000
                   1038: #define SB1     INSN_SB1
                   1039: #define N411   INSN_4111
                   1040: #define N412   INSN_4120
                   1041: #define N5     (INSN_5400 | INSN_5500)
                   1042: #define N54    INSN_5400
                   1043: #define N55    INSN_5500
                   1044: 
                   1045: #define G1      (T3             \
                   1046:                  )
                   1047: 
                   1048: #define G2      (T3             \
                   1049:                  )
                   1050: 
                   1051: #define G3      (I4             \
                   1052:                  )
                   1053: 
                   1054: /* The order of overloaded instructions matters.  Label arguments and
                   1055:    register arguments look the same. Instructions that can have either
                   1056:    for arguments must apear in the correct order in this table for the
                   1057:    assembler to pick the right one. In other words, entries with
                   1058:    immediate operands must apear after the same instruction with
                   1059:    registers.
                   1060: 
                   1061:    Because of the lookup algorithm used, entries with the same opcode
                   1062:    name must be contiguous.
                   1063:  
                   1064:    Many instructions are short hand for other instructions (i.e., The
                   1065:    jal <register> instruction is short for jalr <register>).  */
                   1066: 
                   1067: const struct mips_opcode mips_builtin_opcodes[] =
                   1068: {
                   1069: /* These instructions appear first so that the disassembler will find
                   1070:    them first.  The assemblers uses a hash table based on the
                   1071:    instruction name anyhow.  */
                   1072: /* name,    args,      match,      mask,       pinfo,                  membership */
                   1073: {"pref",    "k,o(b)",   0xcc000000, 0xfc000000, RD_b,                  I4|I32|G3       },
                   1074: {"prefx",   "h,t(b)",  0x4c00000f, 0xfc0007ff, RD_b|RD_t,              I4      },
                   1075: {"nop",     "",         0x00000000, 0xffffffff, 0,                     I1      }, /* sll */
                   1076: {"ssnop",   "",         0x00000040, 0xffffffff, 0,                     I32|N55 }, /* sll */
                   1077: {"ehb",     "",         0x000000c0, 0xffffffff, 0,                     I33     }, /* sll */
                   1078: {"li",      "t,j",      0x24000000, 0xffe00000, WR_t,                  I1      }, /* addiu */
                   1079: {"li",     "t,i",      0x34000000, 0xffe00000, WR_t,                   I1      }, /* ori */
                   1080: {"li",      "t,I",     0,    (int) M_LI,       INSN_MACRO,             I1      },
                   1081: {"move",    "d,s",     0,    (int) M_MOVE,     INSN_MACRO,             I1      },
                   1082: {"move",    "d,s",     0x0000002d, 0xfc1f07ff, WR_d|RD_s,              I3      },/* daddu */
                   1083: {"move",    "d,s",     0x00000021, 0xfc1f07ff, WR_d|RD_s,              I1      },/* addu */
                   1084: {"move",    "d,s",     0x00000025, 0xfc1f07ff, WR_d|RD_s,              I1      },/* or */
                   1085: {"b",       "p",       0x10000000, 0xffff0000, UBD,                    I1      },/* beq 0,0 */
                   1086: {"b",       "p",       0x04010000, 0xffff0000, UBD,                    I1      },/* bgez 0 */
                   1087: {"bal",     "p",       0x04110000, 0xffff0000, UBD|WR_31,              I1      },/* bgezal 0*/
                   1088: 
                   1089: {"abs",     "d,v",     0,    (int) M_ABS,      INSN_MACRO,             I1      },
                   1090: {"abs.s",   "D,V",     0x46000005, 0xffff003f, WR_D|RD_S|FP_S,         I1      },
                   1091: {"abs.d",   "D,V",     0x46200005, 0xffff003f, WR_D|RD_S|FP_D,         I1      },
                   1092: {"abs.ps",  "D,V",     0x46c00005, 0xffff003f, WR_D|RD_S|FP_D,         I5      },
                   1093: {"add",     "d,v,t",   0x00000020, 0xfc0007ff, WR_d|RD_s|RD_t,         I1      },
                   1094: {"add",     "t,r,I",   0,    (int) M_ADD_I,    INSN_MACRO,             I1      },
                   1095: {"add.s",   "D,V,T",   0x46000000, 0xffe0003f, WR_D|RD_S|RD_T|FP_S,    I1      },
                   1096: {"add.d",   "D,V,T",   0x46200000, 0xffe0003f, WR_D|RD_S|RD_T|FP_D,    I1      },
                   1097: {"add.ob",  "X,Y,Q",   0x7800000b, 0xfc20003f, WR_D|RD_S|RD_T|FP_D,    MX|SB1  },
                   1098: {"add.ob",  "D,S,T",   0x4ac0000b, 0xffe0003f, WR_D|RD_S|RD_T,         N54     },
                   1099: {"add.ob",  "D,S,T[e]",        0x4800000b, 0xfe20003f, WR_D|RD_S|RD_T,         N54     },
                   1100: {"add.ob",  "D,S,k",   0x4bc0000b, 0xffe0003f, WR_D|RD_S|RD_T,         N54     },
                   1101: {"add.ps",  "D,V,T",   0x46c00000, 0xffe0003f, WR_D|RD_S|RD_T|FP_D,    I5      },
                   1102: {"add.qh",  "X,Y,Q",   0x7820000b, 0xfc20003f, WR_D|RD_S|RD_T|FP_D,    MX      },
                   1103: {"adda.ob", "Y,Q",     0x78000037, 0xfc2007ff, WR_MACC|RD_S|RD_T|FP_D, MX|SB1  },
                   1104: {"adda.qh", "Y,Q",     0x78200037, 0xfc2007ff, WR_MACC|RD_S|RD_T|FP_D, MX      },
                   1105: {"addi",    "t,r,j",   0x20000000, 0xfc000000, WR_t|RD_s,              I1      },
                   1106: {"addiu",   "t,r,j",   0x24000000, 0xfc000000, WR_t|RD_s,              I1      },
                   1107: {"addl.ob", "Y,Q",     0x78000437, 0xfc2007ff, WR_MACC|RD_S|RD_T|FP_D, MX|SB1  },
                   1108: {"addl.qh", "Y,Q",     0x78200437, 0xfc2007ff, WR_MACC|RD_S|RD_T|FP_D, MX      },
                   1109: {"addr.ps", "D,S,T",   0x46c00018, 0xffe0003f, WR_D|RD_S|RD_T|FP_D,    M3D     },
                   1110: {"addu",    "d,v,t",   0x00000021, 0xfc0007ff, WR_d|RD_s|RD_t,         I1      },
                   1111: {"addu",    "t,r,I",   0,    (int) M_ADDU_I,   INSN_MACRO,             I1      },
                   1112: {"alni.ob", "X,Y,Z,O", 0x78000018, 0xff00003f, WR_D|RD_S|RD_T|FP_D,    MX|SB1  },
                   1113: {"alni.ob", "D,S,T,%", 0x48000018, 0xff00003f, WR_D|RD_S|RD_T,         N54     },
                   1114: {"alni.qh", "X,Y,Z,O", 0x7800001a, 0xff00003f, WR_D|RD_S|RD_T|FP_D,    MX      },
                   1115: {"alnv.ps", "D,V,T,s", 0x4c00001e, 0xfc00003f, WR_D|RD_S|RD_T|FP_D,    I5      },
                   1116: {"alnv.ob", "X,Y,Z,s", 0x78000019, 0xfc00003f, WR_D|RD_S|RD_T|RD_s|FP_D, MX|SB1        },
                   1117: {"alnv.qh", "X,Y,Z,s", 0x7800001b, 0xfc00003f, WR_D|RD_S|RD_T|RD_s|FP_D, MX    },
                   1118: {"and",     "d,v,t",   0x00000024, 0xfc0007ff, WR_d|RD_s|RD_t,         I1      },
                   1119: {"and",     "t,r,I",   0,    (int) M_AND_I,    INSN_MACRO,             I1      },
                   1120: {"and.ob",  "X,Y,Q",   0x7800000c, 0xfc20003f, WR_D|RD_S|RD_T|FP_D,    MX|SB1  },
                   1121: {"and.ob",  "D,S,T",   0x4ac0000c, 0xffe0003f, WR_D|RD_S|RD_T,         N54     },
                   1122: {"and.ob",  "D,S,T[e]",        0x4800000c, 0xfe20003f, WR_D|RD_S|RD_T,         N54     },
                   1123: {"and.ob",  "D,S,k",   0x4bc0000c, 0xffe0003f, WR_D|RD_S|RD_T,         N54     },
                   1124: {"and.qh",  "X,Y,Q",   0x7820000c, 0xfc20003f, WR_D|RD_S|RD_T|FP_D,    MX      },
                   1125: {"andi",    "t,r,i",   0x30000000, 0xfc000000, WR_t|RD_s,              I1      },
                   1126: /* b is at the top of the table.  */
                   1127: /* bal is at the top of the table.  */
                   1128: {"bc0f",    "p",       0x41000000, 0xffff0000, CBD|RD_CC,              I1      },
                   1129: {"bc0fl",   "p",       0x41020000, 0xffff0000, CBL|RD_CC,              I2|T3   },
                   1130: {"bc0t",    "p",       0x41010000, 0xffff0000, CBD|RD_CC,              I1      },
                   1131: {"bc0tl",   "p",       0x41030000, 0xffff0000, CBL|RD_CC,              I2|T3   },
                   1132: {"bc1any2f", "N,p",    0x45200000, 0xffe30000, CBD|RD_CC|FP_S,         M3D     },
                   1133: {"bc1any2t", "N,p",    0x45210000, 0xffe30000, CBD|RD_CC|FP_S,         M3D     },
                   1134: {"bc1any4f", "N,p",    0x45400000, 0xffe30000, CBD|RD_CC|FP_S,         M3D     },
                   1135: {"bc1any4t", "N,p",    0x45410000, 0xffe30000, CBD|RD_CC|FP_S,         M3D     },
                   1136: {"bc1f",    "p",       0x45000000, 0xffff0000, CBD|RD_CC|FP_S,         I1      },
                   1137: {"bc1f",    "N,p",      0x45000000, 0xffe30000, CBD|RD_CC|FP_S,        I4|I32  },
                   1138: {"bc1fl",   "p",       0x45020000, 0xffff0000, CBL|RD_CC|FP_S,         I2|T3   },
                   1139: {"bc1fl",   "N,p",      0x45020000, 0xffe30000, CBL|RD_CC|FP_S,        I4|I32  },
                   1140: {"bc1t",    "p",       0x45010000, 0xffff0000, CBD|RD_CC|FP_S,         I1      },
                   1141: {"bc1t",    "N,p",      0x45010000, 0xffe30000, CBD|RD_CC|FP_S,        I4|I32  },
                   1142: {"bc1tl",   "p",       0x45030000, 0xffff0000, CBL|RD_CC|FP_S,         I2|T3   },
                   1143: {"bc1tl",   "N,p",      0x45030000, 0xffe30000, CBL|RD_CC|FP_S,        I4|I32  },
                   1144: /* bc2* are at the bottom of the table.  */
                   1145: {"bc3f",    "p",       0x4d000000, 0xffff0000, CBD|RD_CC,              I1      },
                   1146: {"bc3fl",   "p",       0x4d020000, 0xffff0000, CBL|RD_CC,              I2|T3   },
                   1147: {"bc3t",    "p",       0x4d010000, 0xffff0000, CBD|RD_CC,              I1      },
                   1148: {"bc3tl",   "p",       0x4d030000, 0xffff0000, CBL|RD_CC,              I2|T3   },
                   1149: {"beqz",    "s,p",     0x10000000, 0xfc1f0000, CBD|RD_s,               I1      },
                   1150: {"beqzl",   "s,p",     0x50000000, 0xfc1f0000, CBL|RD_s,               I2|T3   },
                   1151: {"beq",     "s,t,p",   0x10000000, 0xfc000000, CBD|RD_s|RD_t,          I1      },
                   1152: {"beq",     "s,I,p",   0,    (int) M_BEQ_I,    INSN_MACRO,             I1      },
                   1153: {"beql",    "s,t,p",   0x50000000, 0xfc000000, CBL|RD_s|RD_t,          I2|T3   },
                   1154: {"beql",    "s,I,p",   0,    (int) M_BEQL_I,   INSN_MACRO,             I2|T3   },
                   1155: {"bge",     "s,t,p",   0,    (int) M_BGE,      INSN_MACRO,             I1      },
                   1156: {"bge",     "s,I,p",   0,    (int) M_BGE_I,    INSN_MACRO,             I1      },
                   1157: {"bgel",    "s,t,p",   0,    (int) M_BGEL,     INSN_MACRO,             I2|T3   },
                   1158: {"bgel",    "s,I,p",   0,    (int) M_BGEL_I,   INSN_MACRO,             I2|T3   },
                   1159: {"bgeu",    "s,t,p",   0,    (int) M_BGEU,     INSN_MACRO,             I1      },
                   1160: {"bgeu",    "s,I,p",   0,    (int) M_BGEU_I,   INSN_MACRO,             I1      },
                   1161: {"bgeul",   "s,t,p",   0,    (int) M_BGEUL,    INSN_MACRO,             I2|T3   },
                   1162: {"bgeul",   "s,I,p",   0,    (int) M_BGEUL_I,  INSN_MACRO,             I2|T3   },
                   1163: {"bgez",    "s,p",     0x04010000, 0xfc1f0000, CBD|RD_s,               I1      },
                   1164: {"bgezl",   "s,p",     0x04030000, 0xfc1f0000, CBL|RD_s,               I2|T3   },
                   1165: {"bgezal",  "s,p",     0x04110000, 0xfc1f0000, CBD|RD_s|WR_31,         I1      },
                   1166: {"bgezall", "s,p",     0x04130000, 0xfc1f0000, CBL|RD_s|WR_31,         I2|T3   },
                   1167: {"bgt",     "s,t,p",   0,    (int) M_BGT,      INSN_MACRO,             I1      },
                   1168: {"bgt",     "s,I,p",   0,    (int) M_BGT_I,    INSN_MACRO,             I1      },
                   1169: {"bgtl",    "s,t,p",   0,    (int) M_BGTL,     INSN_MACRO,             I2|T3   },
                   1170: {"bgtl",    "s,I,p",   0,    (int) M_BGTL_I,   INSN_MACRO,             I2|T3   },
                   1171: {"bgtu",    "s,t,p",   0,    (int) M_BGTU,     INSN_MACRO,             I1      },
                   1172: {"bgtu",    "s,I,p",   0,    (int) M_BGTU_I,   INSN_MACRO,             I1      },
                   1173: {"bgtul",   "s,t,p",   0,    (int) M_BGTUL,    INSN_MACRO,             I2|T3   },
                   1174: {"bgtul",   "s,I,p",   0,    (int) M_BGTUL_I,  INSN_MACRO,             I2|T3   },
                   1175: {"bgtz",    "s,p",     0x1c000000, 0xfc1f0000, CBD|RD_s,               I1      },
                   1176: {"bgtzl",   "s,p",     0x5c000000, 0xfc1f0000, CBL|RD_s,               I2|T3   },
                   1177: {"ble",     "s,t,p",   0,    (int) M_BLE,      INSN_MACRO,             I1      },
                   1178: {"ble",     "s,I,p",   0,    (int) M_BLE_I,    INSN_MACRO,             I1      },
                   1179: {"blel",    "s,t,p",   0,    (int) M_BLEL,     INSN_MACRO,             I2|T3   },
                   1180: {"blel",    "s,I,p",   0,    (int) M_BLEL_I,   INSN_MACRO,             I2|T3   },
                   1181: {"bleu",    "s,t,p",   0,    (int) M_BLEU,     INSN_MACRO,             I1      },
                   1182: {"bleu",    "s,I,p",   0,    (int) M_BLEU_I,   INSN_MACRO,             I1      },
                   1183: {"bleul",   "s,t,p",   0,    (int) M_BLEUL,    INSN_MACRO,             I2|T3   },
                   1184: {"bleul",   "s,I,p",   0,    (int) M_BLEUL_I,  INSN_MACRO,             I2|T3   },
                   1185: {"blez",    "s,p",     0x18000000, 0xfc1f0000, CBD|RD_s,               I1      },
                   1186: {"blezl",   "s,p",     0x58000000, 0xfc1f0000, CBL|RD_s,               I2|T3   },
                   1187: {"blt",     "s,t,p",   0,    (int) M_BLT,      INSN_MACRO,             I1      },
                   1188: {"blt",     "s,I,p",   0,    (int) M_BLT_I,    INSN_MACRO,             I1      },
                   1189: {"bltl",    "s,t,p",   0,    (int) M_BLTL,     INSN_MACRO,             I2|T3   },
                   1190: {"bltl",    "s,I,p",   0,    (int) M_BLTL_I,   INSN_MACRO,             I2|T3   },
                   1191: {"bltu",    "s,t,p",   0,    (int) M_BLTU,     INSN_MACRO,             I1      },
                   1192: {"bltu",    "s,I,p",   0,    (int) M_BLTU_I,   INSN_MACRO,             I1      },
                   1193: {"bltul",   "s,t,p",   0,    (int) M_BLTUL,    INSN_MACRO,             I2|T3   },
                   1194: {"bltul",   "s,I,p",   0,    (int) M_BLTUL_I,  INSN_MACRO,             I2|T3   },
                   1195: {"bltz",    "s,p",     0x04000000, 0xfc1f0000, CBD|RD_s,               I1      },
                   1196: {"bltzl",   "s,p",     0x04020000, 0xfc1f0000, CBL|RD_s,               I2|T3   },
                   1197: {"bltzal",  "s,p",     0x04100000, 0xfc1f0000, CBD|RD_s|WR_31,         I1      },
                   1198: {"bltzall", "s,p",     0x04120000, 0xfc1f0000, CBL|RD_s|WR_31,         I2|T3   },
                   1199: {"bnez",    "s,p",     0x14000000, 0xfc1f0000, CBD|RD_s,               I1      },
                   1200: {"bnezl",   "s,p",     0x54000000, 0xfc1f0000, CBL|RD_s,               I2|T3   },
                   1201: {"bne",     "s,t,p",   0x14000000, 0xfc000000, CBD|RD_s|RD_t,          I1      },
                   1202: {"bne",     "s,I,p",   0,    (int) M_BNE_I,    INSN_MACRO,             I1      },
                   1203: {"bnel",    "s,t,p",   0x54000000, 0xfc000000, CBL|RD_s|RD_t,          I2|T3   },
                   1204: {"bnel",    "s,I,p",   0,    (int) M_BNEL_I,   INSN_MACRO,             I2|T3   },
                   1205: {"break",   "",                0x0000000d, 0xffffffff, TRAP,                   I1      },
                   1206: {"break",   "c",       0x0000000d, 0xfc00ffff, TRAP,                   I1      },
                   1207: {"break",   "c,q",     0x0000000d, 0xfc00003f, TRAP,                   I1      },
                   1208: {"c.f.d",   "S,T",     0x46200030, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   I1      },
                   1209: {"c.f.d",   "M,S,T",    0x46200030, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   I4|I32 },
                   1210: {"c.f.s",   "S,T",      0x46000030, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S,   I1      },
                   1211: {"c.f.s",   "M,S,T",    0x46000030, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   I4|I32 },
                   1212: {"c.f.ps",  "S,T",     0x46c00030, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   I5      },
                   1213: {"c.f.ps",  "M,S,T",   0x46c00030, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   I5      },
                   1214: {"c.un.d",  "S,T",     0x46200031, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   I1      },
                   1215: {"c.un.d",  "M,S,T",    0x46200031, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   I4|I32 },
                   1216: {"c.un.s",  "S,T",      0x46000031, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S,   I1      },
                   1217: {"c.un.s",  "M,S,T",    0x46000031, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   I4|I32 },
                   1218: {"c.un.ps", "S,T",     0x46c00031, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   I5      },
                   1219: {"c.un.ps", "M,S,T",   0x46c00031, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   I5      },
                   1220: {"c.eq.d",  "S,T",     0x46200032, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   I1      },
                   1221: {"c.eq.d",  "M,S,T",    0x46200032, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   I4|I32 },
                   1222: {"c.eq.s",  "S,T",      0x46000032, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S,   I1      },
                   1223: {"c.eq.s",  "M,S,T",    0x46000032, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   I4|I32 },
                   1224: {"c.eq.ob", "Y,Q",     0x78000001, 0xfc2007ff, WR_CC|RD_S|RD_T|FP_D,   MX|SB1  },
                   1225: {"c.eq.ob", "S,T",     0x4ac00001, 0xffe007ff, WR_CC|RD_S|RD_T,        N54     },
                   1226: {"c.eq.ob", "S,T[e]",  0x48000001, 0xfe2007ff, WR_CC|RD_S|RD_T,        N54     },
                   1227: {"c.eq.ob", "S,k",     0x4bc00001, 0xffe007ff, WR_CC|RD_S|RD_T,        N54     },
                   1228: {"c.eq.ps", "S,T",     0x46c00032, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   I5      },
                   1229: {"c.eq.ps", "M,S,T",   0x46c00032, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   I5      },
                   1230: {"c.eq.qh", "Y,Q",     0x78200001, 0xfc2007ff, WR_CC|RD_S|RD_T|FP_D,   MX      },
                   1231: {"c.ueq.d", "S,T",     0x46200033, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   I1      },
                   1232: {"c.ueq.d", "M,S,T",    0x46200033, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   I4|I32 },
                   1233: {"c.ueq.s", "S,T",      0x46000033, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S,   I1      },
                   1234: {"c.ueq.s", "M,S,T",    0x46000033, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   I4|I32 },
                   1235: {"c.ueq.ps","S,T",     0x46c00033, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   I5      },
                   1236: {"c.ueq.ps","M,S,T",   0x46c00033, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   I5      },
                   1237: {"c.olt.d", "S,T",      0x46200034, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   I1      },
                   1238: {"c.olt.d", "M,S,T",    0x46200034, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   I4|I32 },
                   1239: {"c.olt.s", "S,T",     0x46000034, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S,   I1      },
                   1240: {"c.olt.s", "M,S,T",    0x46000034, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   I4|I32 },
                   1241: {"c.olt.ps","S,T",     0x46c00034, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   I5      },
                   1242: {"c.olt.ps","M,S,T",   0x46c00034, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   I5      },
                   1243: {"c.ult.d", "S,T",     0x46200035, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   I1      },
                   1244: {"c.ult.d", "M,S,T",    0x46200035, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   I4|I32 },
                   1245: {"c.ult.s", "S,T",      0x46000035, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S,   I1      },
                   1246: {"c.ult.s", "M,S,T",    0x46000035, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   I4|I32 },
                   1247: {"c.ult.ps","S,T",     0x46c00035, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   I5      },
                   1248: {"c.ult.ps","M,S,T",   0x46c00035, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   I5      },
                   1249: {"c.ole.d", "S,T",      0x46200036, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   I1      },
                   1250: {"c.ole.d", "M,S,T",    0x46200036, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   I4|I32 },
                   1251: {"c.ole.s", "S,T",      0x46000036, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S,   I1      },
                   1252: {"c.ole.s", "M,S,T",    0x46000036, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   I4|I32 },
                   1253: {"c.ole.ps","S,T",     0x46c00036, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   I5      },
                   1254: {"c.ole.ps","M,S,T",   0x46c00036, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   I5      },
                   1255: {"c.ule.d", "S,T",     0x46200037, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   I1      },
                   1256: {"c.ule.d", "M,S,T",    0x46200037, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   I4|I32 },
                   1257: {"c.ule.s", "S,T",      0x46000037, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S,   I1      },
                   1258: {"c.ule.s", "M,S,T",    0x46000037, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   I4|I32 },
                   1259: {"c.ule.ps","S,T",     0x46c00037, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   I5      },
                   1260: {"c.ule.ps","M,S,T",   0x46c00037, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   I5      },
                   1261: {"c.sf.d",  "S,T",     0x46200038, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   I1      },
                   1262: {"c.sf.d",  "M,S,T",    0x46200038, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   I4|I32 },
                   1263: {"c.sf.s",  "S,T",      0x46000038, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S,   I1      },
                   1264: {"c.sf.s",  "M,S,T",    0x46000038, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   I4|I32 },
                   1265: {"c.sf.ps", "S,T",     0x46c00038, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   I5      },
                   1266: {"c.sf.ps", "M,S,T",   0x46c00038, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   I5      },
                   1267: {"c.ngle.d","S,T",     0x46200039, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   I1      },
                   1268: {"c.ngle.d","M,S,T",    0x46200039, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   I4|I32 },
                   1269: {"c.ngle.s","S,T",      0x46000039, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S,   I1      },
                   1270: {"c.ngle.s","M,S,T",    0x46000039, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   I4|I32 },
                   1271: {"c.ngle.ps","S,T",    0x46c00039, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   I5      },
                   1272: {"c.ngle.ps","M,S,T",  0x46c00039, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   I5      },
                   1273: {"c.seq.d", "S,T",     0x4620003a, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   I1      },
                   1274: {"c.seq.d", "M,S,T",    0x4620003a, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   I4|I32 },
                   1275: {"c.seq.s", "S,T",      0x4600003a, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S,   I1      },
                   1276: {"c.seq.s", "M,S,T",    0x4600003a, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   I4|I32 },
                   1277: {"c.seq.ps","S,T",     0x46c0003a, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   I5      },
                   1278: {"c.seq.ps","M,S,T",   0x46c0003a, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   I5      },
                   1279: {"c.ngl.d", "S,T",     0x4620003b, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   I1      },
                   1280: {"c.ngl.d", "M,S,T",    0x4620003b, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   I4|I32 },
                   1281: {"c.ngl.s", "S,T",      0x4600003b, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S,   I1      },
                   1282: {"c.ngl.s", "M,S,T",    0x4600003b, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   I4|I32 },
                   1283: {"c.ngl.ps","S,T",     0x46c0003b, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   I5      },
                   1284: {"c.ngl.ps","M,S,T",   0x46c0003b, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   I5      },
                   1285: {"c.lt.d",  "S,T",     0x4620003c, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   I1      },
                   1286: {"c.lt.d",  "M,S,T",    0x4620003c, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   I4|I32 },
                   1287: {"c.lt.s",  "S,T",     0x4600003c, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S,   I1      },
                   1288: {"c.lt.s",  "M,S,T",    0x4600003c, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   I4|I32 },
                   1289: {"c.lt.ob", "Y,Q",     0x78000004, 0xfc2007ff, WR_CC|RD_S|RD_T|FP_D,   MX|SB1  },
                   1290: {"c.lt.ob", "S,T",     0x4ac00004, 0xffe007ff, WR_CC|RD_S|RD_T,        N54     },
                   1291: {"c.lt.ob", "S,T[e]",  0x48000004, 0xfe2007ff, WR_CC|RD_S|RD_T,        N54     },
                   1292: {"c.lt.ob", "S,k",     0x4bc00004, 0xffe007ff, WR_CC|RD_S|RD_T,        N54     },
                   1293: {"c.lt.ps", "S,T",     0x46c0003c, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   I5      },
                   1294: {"c.lt.ps", "M,S,T",   0x46c0003c, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   I5      },
                   1295: {"c.lt.qh", "Y,Q",     0x78200004, 0xfc2007ff, WR_CC|RD_S|RD_T|FP_D,   MX      },
                   1296: {"c.nge.d", "S,T",     0x4620003d, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   I1      },
                   1297: {"c.nge.d", "M,S,T",    0x4620003d, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   I4|I32 },
                   1298: {"c.nge.s", "S,T",      0x4600003d, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S,   I1      },
                   1299: {"c.nge.s", "M,S,T",    0x4600003d, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   I4|I32 },
                   1300: {"c.nge.ps","S,T",     0x46c0003d, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   I5      },
                   1301: {"c.nge.ps","M,S,T",   0x46c0003d, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   I5      },
                   1302: {"c.le.d",  "S,T",     0x4620003e, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   I1      },
                   1303: {"c.le.d",  "M,S,T",    0x4620003e, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   I4|I32 },
                   1304: {"c.le.s",  "S,T",     0x4600003e, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S,   I1      },
                   1305: {"c.le.s",  "M,S,T",    0x4600003e, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   I4|I32 },
                   1306: {"c.le.ob", "Y,Q",     0x78000005, 0xfc2007ff, WR_CC|RD_S|RD_T|FP_D,   MX|SB1  },
                   1307: {"c.le.ob", "S,T",     0x4ac00005, 0xffe007ff, WR_CC|RD_S|RD_T,        N54     },
                   1308: {"c.le.ob", "S,T[e]",  0x48000005, 0xfe2007ff, WR_CC|RD_S|RD_T,        N54     },
                   1309: {"c.le.ob", "S,k",     0x4bc00005, 0xffe007ff, WR_CC|RD_S|RD_T,        N54     },
                   1310: {"c.le.ps", "S,T",     0x46c0003e, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   I5      },
                   1311: {"c.le.ps", "M,S,T",   0x46c0003e, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   I5      },
                   1312: {"c.le.qh", "Y,Q",     0x78200005, 0xfc2007ff, WR_CC|RD_S|RD_T|FP_D,   MX      },
                   1313: {"c.ngt.d", "S,T",     0x4620003f, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   I1      },
                   1314: {"c.ngt.d", "M,S,T",    0x4620003f, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   I4|I32 },
                   1315: {"c.ngt.s", "S,T",      0x4600003f, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S,   I1      },
                   1316: {"c.ngt.s", "M,S,T",    0x4600003f, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   I4|I32 },
                   1317: {"c.ngt.ps","S,T",     0x46c0003f, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   I5      },
                   1318: {"c.ngt.ps","M,S,T",   0x46c0003f, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   I5      },
                   1319: {"cabs.eq.d",  "M,S,T",        0x46200072, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   M3D     },
                   1320: {"cabs.eq.ps", "M,S,T",        0x46c00072, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   M3D     },
                   1321: {"cabs.eq.s",  "M,S,T",        0x46000072, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   M3D     },
                   1322: {"cabs.f.d",   "M,S,T",        0x46200070, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   M3D     },
                   1323: {"cabs.f.ps",  "M,S,T",        0x46c00070, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   M3D     },
                   1324: {"cabs.f.s",   "M,S,T",        0x46000070, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   M3D     },
                   1325: {"cabs.le.d",  "M,S,T",        0x4620007e, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   M3D     },
                   1326: {"cabs.le.ps", "M,S,T",        0x46c0007e, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   M3D     },
                   1327: {"cabs.le.s",  "M,S,T",        0x4600007e, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   M3D     },
                   1328: {"cabs.lt.d",  "M,S,T",        0x4620007c, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   M3D     },
                   1329: {"cabs.lt.ps", "M,S,T",        0x46c0007c, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   M3D     },
                   1330: {"cabs.lt.s",  "M,S,T",        0x4600007c, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   M3D     },
                   1331: {"cabs.nge.d", "M,S,T",        0x4620007d, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   M3D     },
                   1332: {"cabs.nge.ps","M,S,T",        0x46c0007d, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   M3D     },
                   1333: {"cabs.nge.s", "M,S,T",        0x4600007d, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   M3D     },
                   1334: {"cabs.ngl.d", "M,S,T",        0x4620007b, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   M3D     },
                   1335: {"cabs.ngl.ps","M,S,T",        0x46c0007b, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   M3D     },
                   1336: {"cabs.ngl.s", "M,S,T",        0x4600007b, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   M3D     },
                   1337: {"cabs.ngle.d","M,S,T",        0x46200079, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   M3D     },
                   1338: {"cabs.ngle.ps","M,S,T",0x46c00079, 0xffe000ff,        RD_S|RD_T|WR_CC|FP_D,   M3D     },
                   1339: {"cabs.ngle.s","M,S,T",        0x46000079, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   M3D     },
                   1340: {"cabs.ngt.d", "M,S,T",        0x4620007f, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   M3D     },
                   1341: {"cabs.ngt.ps","M,S,T",        0x46c0007f, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   M3D     },
                   1342: {"cabs.ngt.s", "M,S,T",        0x4600007f, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   M3D     },
                   1343: {"cabs.ole.d", "M,S,T",        0x46200076, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   M3D     },
                   1344: {"cabs.ole.ps","M,S,T",        0x46c00076, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   M3D     },
                   1345: {"cabs.ole.s", "M,S,T",        0x46000076, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   M3D     },
                   1346: {"cabs.olt.d", "M,S,T",        0x46200074, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   M3D     },
                   1347: {"cabs.olt.ps","M,S,T",        0x46c00074, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   M3D     },
                   1348: {"cabs.olt.s", "M,S,T",        0x46000074, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   M3D     },
                   1349: {"cabs.seq.d", "M,S,T",        0x4620007a, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   M3D     },
                   1350: {"cabs.seq.ps","M,S,T",        0x46c0007a, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   M3D     },
                   1351: {"cabs.seq.s", "M,S,T",        0x4600007a, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   M3D     },
                   1352: {"cabs.sf.d",  "M,S,T",        0x46200078, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   M3D     },
                   1353: {"cabs.sf.ps", "M,S,T",        0x46c00078, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   M3D     },
                   1354: {"cabs.sf.s",  "M,S,T",        0x46000078, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   M3D     },
                   1355: {"cabs.ueq.d", "M,S,T",        0x46200073, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   M3D     },
                   1356: {"cabs.ueq.ps","M,S,T",        0x46c00073, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   M3D     },
                   1357: {"cabs.ueq.s", "M,S,T",        0x46000073, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   M3D     },
                   1358: {"cabs.ule.d", "M,S,T",        0x46200077, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   M3D     },
                   1359: {"cabs.ule.ps","M,S,T",        0x46c00077, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   M3D     },
                   1360: {"cabs.ule.s", "M,S,T",        0x46000077, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   M3D     },
                   1361: {"cabs.ult.d", "M,S,T",        0x46200075, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   M3D     },
                   1362: {"cabs.ult.ps","M,S,T",        0x46c00075, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   M3D     },
                   1363: {"cabs.ult.s", "M,S,T",        0x46000075, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   M3D     },
                   1364: {"cabs.un.d",  "M,S,T",        0x46200071, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   M3D     },
                   1365: {"cabs.un.ps", "M,S,T",        0x46c00071, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   M3D     },
                   1366: {"cabs.un.s",  "M,S,T",        0x46000071, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   M3D     },
                   1367: {"cache",   "k,o(b)",   0xbc000000, 0xfc000000, RD_b,                  I3|I32|T3},
                   1368: {"ceil.l.d", "D,S",    0x4620000a, 0xffff003f, WR_D|RD_S|FP_D,         I3      },
                   1369: {"ceil.l.s", "D,S",    0x4600000a, 0xffff003f, WR_D|RD_S|FP_S,         I3      },
                   1370: {"ceil.w.d", "D,S",    0x4620000e, 0xffff003f, WR_D|RD_S|FP_D,         I2      },
                   1371: {"ceil.w.s", "D,S",    0x4600000e, 0xffff003f, WR_D|RD_S|FP_S,         I2      },
                   1372: {"cfc0",    "t,G",     0x40400000, 0xffe007ff, LCD|WR_t|RD_C0,         I1      },
                   1373: {"cfc1",    "t,G",     0x44400000, 0xffe007ff, LCD|WR_t|RD_C1|FP_S,    I1      },
                   1374: {"cfc1",    "t,S",     0x44400000, 0xffe007ff, LCD|WR_t|RD_C1|FP_S,    I1      },
                   1375: /* cfc2 is at the bottom of the table.  */
                   1376: {"cfc3",    "t,G",     0x4c400000, 0xffe007ff, LCD|WR_t|RD_C3,         I1      },
                   1377: {"clo",     "U,s",      0x70000021, 0xfc0007ff, WR_d|WR_t|RD_s,        I32|N55 },
                   1378: {"clz",     "U,s",      0x70000020, 0xfc0007ff, WR_d|WR_t|RD_s,        I32|N55 },
                   1379: {"ctc0",    "t,G",     0x40c00000, 0xffe007ff, COD|RD_t|WR_CC,         I1      },
                   1380: {"ctc1",    "t,G",     0x44c00000, 0xffe007ff, COD|RD_t|WR_CC|FP_S,    I1      },
                   1381: {"ctc1",    "t,S",     0x44c00000, 0xffe007ff, COD|RD_t|WR_CC|FP_S,    I1      },
                   1382: /* ctc2 is at the bottom of the table.  */
                   1383: {"ctc3",    "t,G",     0x4cc00000, 0xffe007ff, COD|RD_t|WR_CC,         I1      },
                   1384: {"cvt.d.l", "D,S",     0x46a00021, 0xffff003f, WR_D|RD_S|FP_D,         I3      },
                   1385: {"cvt.d.s", "D,S",     0x46000021, 0xffff003f, WR_D|RD_S|FP_D|FP_S,    I1      },
                   1386: {"cvt.d.w", "D,S",     0x46800021, 0xffff003f, WR_D|RD_S|FP_D,         I1      },
                   1387: {"cvt.l.d", "D,S",     0x46200025, 0xffff003f, WR_D|RD_S|FP_D,         I3      },
                   1388: {"cvt.l.s", "D,S",     0x46000025, 0xffff003f, WR_D|RD_S|FP_S,         I3      },
                   1389: {"cvt.s.l", "D,S",     0x46a00020, 0xffff003f, WR_D|RD_S|FP_S,         I3      },
                   1390: {"cvt.s.d", "D,S",     0x46200020, 0xffff003f, WR_D|RD_S|FP_S|FP_D,    I1      },
                   1391: {"cvt.s.w", "D,S",     0x46800020, 0xffff003f, WR_D|RD_S|FP_S,         I1      },
                   1392: {"cvt.s.pl","D,S",     0x46c00028, 0xffff003f, WR_D|RD_S|FP_S|FP_D,    I5      },
                   1393: {"cvt.s.pu","D,S",     0x46c00020, 0xffff003f, WR_D|RD_S|FP_S|FP_D,    I5      },
                   1394: {"cvt.w.d", "D,S",     0x46200024, 0xffff003f, WR_D|RD_S|FP_D,         I1      },
                   1395: {"cvt.w.s", "D,S",     0x46000024, 0xffff003f, WR_D|RD_S|FP_S,         I1      },
                   1396: {"cvt.ps.pw", "D,S",   0x46800026, 0xffff003f, WR_D|RD_S|FP_S|FP_D,    M3D     },
                   1397: {"cvt.ps.s","D,V,T",   0x46000026, 0xffe0003f, WR_D|RD_S|RD_T|FP_D,    I5      },
                   1398: {"cvt.pw.ps", "D,S",   0x46c00024, 0xffff003f, WR_D|RD_S|FP_S|FP_D,    M3D     },
                   1399: {"dabs",    "d,v",     0,    (int) M_DABS,     INSN_MACRO,             I3      },
                   1400: {"dadd",    "d,v,t",   0x0000002c, 0xfc0007ff, WR_d|RD_s|RD_t,         I3      },
                   1401: {"dadd",    "t,r,I",   0,    (int) M_DADD_I,   INSN_MACRO,             I3      },
                   1402: {"daddi",   "t,r,j",   0x60000000, 0xfc000000, WR_t|RD_s,              I3      },
                   1403: {"daddiu",  "t,r,j",   0x64000000, 0xfc000000, WR_t|RD_s,              I3      },
                   1404: {"daddu",   "d,v,t",   0x0000002d, 0xfc0007ff, WR_d|RD_s|RD_t,         I3      },
                   1405: {"daddu",   "t,r,I",   0,    (int) M_DADDU_I,  INSN_MACRO,             I3      },
                   1406: {"dbreak",  "",                0x7000003f, 0xffffffff, 0,                      N5      },
                   1407: {"dclo",    "U,s",      0x70000025, 0xfc0007ff, RD_s|WR_d|WR_t,        I64|N55 },
                   1408: {"dclz",    "U,s",      0x70000024, 0xfc0007ff, RD_s|WR_d|WR_t,        I64|N55 },
                   1409: /* dctr and dctw are used on the r5000.  */
                   1410: {"dctr",    "o(b)",    0xbc050000, 0xfc1f0000, RD_b,                   I3      },
                   1411: {"dctw",    "o(b)",    0xbc090000, 0xfc1f0000, RD_b,                   I3      },
                   1412: {"deret",   "",         0x4200001f, 0xffffffff, 0,                     I32|G2  },
                   1413: {"dext",    "t,r,I,+I",        0,    (int) M_DEXT,     INSN_MACRO,             I65     },
                   1414: {"dext",    "t,r,+A,+C", 0x7c000003, 0xfc00003f, WR_t|RD_s,                    I65     },
                   1415: {"dextm",   "t,r,+A,+G", 0x7c000001, 0xfc00003f, WR_t|RD_s,                    I65     },
                   1416: {"dextu",   "t,r,+E,+H", 0x7c000002, 0xfc00003f, WR_t|RD_s,                    I65     },
                   1417: /* For ddiv, see the comments about div.  */
                   1418: {"ddiv",    "z,s,t",    0x0000001e, 0xfc00ffff, RD_s|RD_t|WR_HILO,      I3      },
                   1419: {"ddiv",    "d,v,t",   0,    (int) M_DDIV_3,   INSN_MACRO,             I3      },
                   1420: {"ddiv",    "d,v,I",   0,    (int) M_DDIV_3I,  INSN_MACRO,             I3      },
                   1421: /* For ddivu, see the comments about div.  */
                   1422: {"ddivu",   "z,s,t",    0x0000001f, 0xfc00ffff, RD_s|RD_t|WR_HILO,      I3      },
                   1423: {"ddivu",   "d,v,t",   0,    (int) M_DDIVU_3,  INSN_MACRO,             I3      },
                   1424: {"ddivu",   "d,v,I",   0,    (int) M_DDIVU_3I, INSN_MACRO,             I3      },
                   1425: {"di",      "",                0x41606000, 0xffffffff, WR_t|WR_C0,             I33     },
                   1426: {"di",      "t",       0x41606000, 0xffe0ffff, WR_t|WR_C0,             I33     },
                   1427: {"dins",    "t,r,I,+I",        0,    (int) M_DINS,     INSN_MACRO,             I65     },
                   1428: {"dins",    "t,r,+A,+B", 0x7c000007, 0xfc00003f, WR_t|RD_s,                    I65     },
                   1429: {"dinsm",   "t,r,+A,+F", 0x7c000005, 0xfc00003f, WR_t|RD_s,                    I65     },
                   1430: {"dinsu",   "t,r,+E,+F", 0x7c000006, 0xfc00003f, WR_t|RD_s,                    I65     },
                   1431: /* The MIPS assembler treats the div opcode with two operands as
                   1432:    though the first operand appeared twice (the first operand is both
                   1433:    a source and a destination).  To get the div machine instruction,
                   1434:    you must use an explicit destination of $0.  */
                   1435: {"div",     "z,s,t",    0x0000001a, 0xfc00ffff, RD_s|RD_t|WR_HILO,      I1      },
                   1436: {"div",     "z,t",      0x0000001a, 0xffe0ffff, RD_s|RD_t|WR_HILO,      I1      },
                   1437: {"div",     "d,v,t",   0,    (int) M_DIV_3,    INSN_MACRO,             I1      },
                   1438: {"div",     "d,v,I",   0,    (int) M_DIV_3I,   INSN_MACRO,             I1      },
                   1439: {"div.d",   "D,V,T",   0x46200003, 0xffe0003f, WR_D|RD_S|RD_T|FP_D,    I1      },
                   1440: {"div.s",   "D,V,T",   0x46000003, 0xffe0003f, WR_D|RD_S|RD_T|FP_S,    I1      },
                   1441: {"div.ps",  "D,V,T",   0x46c00003, 0xffe0003f, WR_D|RD_S|RD_T|FP_D,    SB1     },
                   1442: /* For divu, see the comments about div.  */
                   1443: {"divu",    "z,s,t",    0x0000001b, 0xfc00ffff, RD_s|RD_t|WR_HILO,      I1      },
                   1444: {"divu",    "z,t",      0x0000001b, 0xffe0ffff, RD_s|RD_t|WR_HILO,      I1      },
                   1445: {"divu",    "d,v,t",   0,    (int) M_DIVU_3,   INSN_MACRO,             I1      },
                   1446: {"divu",    "d,v,I",   0,    (int) M_DIVU_3I,  INSN_MACRO,             I1      },
                   1447: {"dla",     "t,A(b)",  0,    (int) M_DLA_AB,   INSN_MACRO,             I3      },
                   1448: {"dlca",    "t,A(b)",  0,    (int) M_DLCA_AB,  INSN_MACRO,             I3      },
                   1449: {"dli",     "t,j",      0x24000000, 0xffe00000, WR_t,                  I3      }, /* addiu */
                   1450: {"dli",            "t,i",      0x34000000, 0xffe00000, WR_t,                   I3      }, /* ori */
                   1451: {"dli",     "t,I",     0,    (int) M_DLI,      INSN_MACRO,             I3      },
                   1452: {"dmacc",   "d,s,t",   0x00000029, 0xfc0007ff, RD_s|RD_t|WR_LO|WR_d,   N412    },
                   1453: {"dmacchi", "d,s,t",   0x00000229, 0xfc0007ff, RD_s|RD_t|WR_LO|WR_d,   N412    },
                   1454: {"dmacchis", "d,s,t",  0x00000629, 0xfc0007ff, RD_s|RD_t|WR_LO|WR_d,   N412    },
                   1455: {"dmacchiu", "d,s,t",  0x00000269, 0xfc0007ff, RD_s|RD_t|WR_LO|WR_d,   N412    },
                   1456: {"dmacchius", "d,s,t", 0x00000669, 0xfc0007ff, RD_s|RD_t|WR_LO|WR_d,   N412    },
                   1457: {"dmaccs",  "d,s,t",   0x00000429, 0xfc0007ff, RD_s|RD_t|WR_LO|WR_d,   N412    },
                   1458: {"dmaccu",  "d,s,t",   0x00000069, 0xfc0007ff, RD_s|RD_t|WR_LO|WR_d,   N412    },
                   1459: {"dmaccus", "d,s,t",   0x00000469, 0xfc0007ff, RD_s|RD_t|WR_LO|WR_d,   N412    },
                   1460: {"dmadd16", "s,t",      0x00000029, 0xfc00ffff, RD_s|RD_t|MOD_LO,       N411    },
                   1461: {"dmfc0",   "t,G",     0x40200000, 0xffe007ff, LCD|WR_t|RD_C0,         I3      },
                   1462: {"dmfc0",   "t,+D",     0x40200000, 0xffe007f8, LCD|WR_t|RD_C0,        I64     },
                   1463: {"dmfc0",   "t,G,H",    0x40200000, 0xffe007f8, LCD|WR_t|RD_C0,        I64     },
                   1464: {"dmtc0",   "t,G",     0x40a00000, 0xffe007ff, COD|RD_t|WR_C0|WR_CC,   I3      },
                   1465: {"dmtc0",   "t,+D",     0x40a00000, 0xffe007f8, COD|RD_t|WR_C0|WR_CC,   I64     },
                   1466: {"dmtc0",   "t,G,H",    0x40a00000, 0xffe007f8, COD|RD_t|WR_C0|WR_CC,   I64     },
                   1467: {"dmfc1",   "t,S",     0x44200000, 0xffe007ff, LCD|WR_t|RD_S|FP_S,     I3      },
                   1468: {"dmfc1",   "t,G",      0x44200000, 0xffe007ff, LCD|WR_t|RD_S|FP_S,     I3      },
                   1469: {"dmtc1",   "t,S",     0x44a00000, 0xffe007ff, COD|RD_t|WR_S|FP_S,     I3      },
                   1470: {"dmtc1",   "t,G",      0x44a00000, 0xffe007ff, COD|RD_t|WR_S|FP_S,     I3      },
                   1471: /* dmfc2 is at the bottom of the table.  */
                   1472: /* dmtc2 is at the bottom of the table.  */
                   1473: {"dmfc3",   "t,G",      0x4c200000, 0xffe007ff, LCD|WR_t|RD_C3,        I3      },
                   1474: {"dmfc3",   "t,G,H",    0x4c200000, 0xffe007f8, LCD|WR_t|RD_C3,        I64     },
                   1475: {"dmtc3",   "t,G",      0x4ca00000, 0xffe007ff, COD|RD_t|WR_C3|WR_CC,   I3      },
                   1476: {"dmtc3",   "t,G,H",    0x4ca00000, 0xffe007f8, COD|RD_t|WR_C3|WR_CC,   I64     },
                   1477: {"dmul",    "d,v,t",   0,    (int) M_DMUL,     INSN_MACRO,             I3      },
                   1478: {"dmul",    "d,v,I",   0,    (int) M_DMUL_I,   INSN_MACRO,             I3      },
                   1479: {"dmulo",   "d,v,t",   0,    (int) M_DMULO,    INSN_MACRO,             I3      },
                   1480: {"dmulo",   "d,v,I",   0,    (int) M_DMULO_I,  INSN_MACRO,             I3      },
                   1481: {"dmulou",  "d,v,t",   0,    (int) M_DMULOU,   INSN_MACRO,             I3      },
                   1482: {"dmulou",  "d,v,I",   0,    (int) M_DMULOU_I, INSN_MACRO,             I3      },
                   1483: {"dmult",   "s,t",      0x0000001c, 0xfc00ffff, RD_s|RD_t|WR_HILO,      I3     },
                   1484: {"dmultu",  "s,t",      0x0000001d, 0xfc00ffff, RD_s|RD_t|WR_HILO,      I3     },
                   1485: {"dneg",    "d,w",     0x0000002e, 0xffe007ff, WR_d|RD_t,              I3      }, /* dsub 0 */
                   1486: {"dnegu",   "d,w",     0x0000002f, 0xffe007ff, WR_d|RD_t,              I3      }, /* dsubu 0*/
                   1487: {"drem",    "z,s,t",    0x0000001e, 0xfc00ffff, RD_s|RD_t|WR_HILO,      I3      },
                   1488: {"drem",    "d,v,t",   3,    (int) M_DREM_3,   INSN_MACRO,             I3      },
                   1489: {"drem",    "d,v,I",   3,    (int) M_DREM_3I,  INSN_MACRO,             I3      },
                   1490: {"dremu",   "z,s,t",    0x0000001f, 0xfc00ffff, RD_s|RD_t|WR_HILO,      I3      },
                   1491: {"dremu",   "d,v,t",   3,    (int) M_DREMU_3,  INSN_MACRO,             I3      },
                   1492: {"dremu",   "d,v,I",   3,    (int) M_DREMU_3I, INSN_MACRO,             I3      },
                   1493: {"dret",    "",                0x7000003e, 0xffffffff, 0,                      N5      },
                   1494: {"drol",    "d,v,t",   0,    (int) M_DROL,     INSN_MACRO,             I3      },
                   1495: {"drol",    "d,v,I",   0,    (int) M_DROL_I,   INSN_MACRO,             I3      },
                   1496: {"dror",    "d,v,t",   0,    (int) M_DROR,     INSN_MACRO,             I3      },
                   1497: {"dror",    "d,v,I",   0,    (int) M_DROR_I,   INSN_MACRO,             I3      },
                   1498: {"dror",    "d,w,<",   0x0020003a, 0xffe0003f, WR_d|RD_t,              N5|I65  },
                   1499: {"drorv",   "d,t,s",   0x00000056, 0xfc0007ff, RD_t|RD_s|WR_d,         N5|I65  },
                   1500: {"dror32",  "d,w,<",   0x0020003e, 0xffe0003f, WR_d|RD_t,              N5|I65  },
                   1501: {"drotl",   "d,v,t",   0,    (int) M_DROL,     INSN_MACRO,             I65     },
                   1502: {"drotl",   "d,v,I",   0,    (int) M_DROL_I,   INSN_MACRO,             I65     },
                   1503: {"drotr",   "d,v,t",   0,    (int) M_DROR,     INSN_MACRO,             I65     },
                   1504: {"drotr",   "d,v,I",   0,    (int) M_DROR_I,   INSN_MACRO,             I65     },
                   1505: {"drotrv",  "d,t,s",   0x00000056, 0xfc0007ff, RD_t|RD_s|WR_d,         I65     },
                   1506: {"drotr32", "d,w,<",   0x0020003e, 0xffe0003f, WR_d|RD_t,              I65     },
                   1507: {"dsbh",    "d,w",     0x7c0000a4, 0xffe007ff, WR_d|RD_t,              I65     },
                   1508: {"dshd",    "d,w",     0x7c000164, 0xffe007ff, WR_d|RD_t,              I65     },
                   1509: {"dsllv",   "d,t,s",   0x00000014, 0xfc0007ff, WR_d|RD_t|RD_s,         I3      },
                   1510: {"dsll32",  "d,w,<",   0x0000003c, 0xffe0003f, WR_d|RD_t,              I3      },
                   1511: {"dsll",    "d,w,s",   0x00000014, 0xfc0007ff, WR_d|RD_t|RD_s,         I3      }, /* dsllv */
                   1512: {"dsll",    "d,w,>",   0x0000003c, 0xffe0003f, WR_d|RD_t,              I3      }, /* dsll32 */
                   1513: {"dsll",    "d,w,<",   0x00000038, 0xffe0003f, WR_d|RD_t,              I3      },
                   1514: {"dsrav",   "d,t,s",   0x00000017, 0xfc0007ff, WR_d|RD_t|RD_s,         I3      },
                   1515: {"dsra32",  "d,w,<",   0x0000003f, 0xffe0003f, WR_d|RD_t,              I3      },
                   1516: {"dsra",    "d,w,s",   0x00000017, 0xfc0007ff, WR_d|RD_t|RD_s,         I3      }, /* dsrav */
                   1517: {"dsra",    "d,w,>",   0x0000003f, 0xffe0003f, WR_d|RD_t,              I3      }, /* dsra32 */
                   1518: {"dsra",    "d,w,<",   0x0000003b, 0xffe0003f, WR_d|RD_t,              I3      },
                   1519: {"dsrlv",   "d,t,s",   0x00000016, 0xfc0007ff, WR_d|RD_t|RD_s,         I3      },
                   1520: {"dsrl32",  "d,w,<",   0x0000003e, 0xffe0003f, WR_d|RD_t,              I3      },
                   1521: {"dsrl",    "d,w,s",   0x00000016, 0xfc0007ff, WR_d|RD_t|RD_s,         I3      }, /* dsrlv */
                   1522: {"dsrl",    "d,w,>",   0x0000003e, 0xffe0003f, WR_d|RD_t,              I3      }, /* dsrl32 */
                   1523: {"dsrl",    "d,w,<",   0x0000003a, 0xffe0003f, WR_d|RD_t,              I3      },
                   1524: {"dsub",    "d,v,t",   0x0000002e, 0xfc0007ff, WR_d|RD_s|RD_t,         I3      },
                   1525: {"dsub",    "d,v,I",   0,    (int) M_DSUB_I,   INSN_MACRO,             I3      },
                   1526: {"dsubu",   "d,v,t",   0x0000002f, 0xfc0007ff, WR_d|RD_s|RD_t,         I3      },
                   1527: {"dsubu",   "d,v,I",   0,    (int) M_DSUBU_I,  INSN_MACRO,             I3      },
                   1528: {"ei",      "",                0x41606020, 0xffffffff, WR_t|WR_C0,             I33     },
                   1529: {"ei",      "t",       0x41606020, 0xffe0ffff, WR_t|WR_C0,             I33     },
                   1530: {"eret",    "",         0x42000018, 0xffffffff, 0,                     I3|I32  },
                   1531: {"ext",     "t,r,+A,+C", 0x7c000000, 0xfc00003f, WR_t|RD_s,                    I33     },
                   1532: {"floor.l.d", "D,S",   0x4620000b, 0xffff003f, WR_D|RD_S|FP_D,         I3      },
                   1533: {"floor.l.s", "D,S",   0x4600000b, 0xffff003f, WR_D|RD_S|FP_S,         I3      },
                   1534: {"floor.w.d", "D,S",   0x4620000f, 0xffff003f, WR_D|RD_S|FP_D,         I2      },
                   1535: {"floor.w.s", "D,S",   0x4600000f, 0xffff003f, WR_D|RD_S|FP_S,         I2      },
                   1536: {"flushi",  "",                0xbc010000, 0xffffffff, 0,                      L1      },
                   1537: {"flushd",  "",                0xbc020000, 0xffffffff, 0,                      L1      },
                   1538: {"flushid", "",                0xbc030000, 0xffffffff, 0,                      L1      },
                   1539: {"hibernate","",        0x42000023, 0xffffffff,        0,                      V1      },
                   1540: {"ins",     "t,r,+A,+B", 0x7c000004, 0xfc00003f, WR_t|RD_s,                    I33     },
                   1541: {"jr",      "s",       0x00000008, 0xfc1fffff, UBD|RD_s,               I1      },
                   1542: {"jr.hb",   "s",       0x00000408, 0xfc1fffff, UBD|RD_s,               I33     },
                   1543: {"j",       "s",       0x00000008, 0xfc1fffff, UBD|RD_s,               I1      }, /* jr */
                   1544: /* SVR4 PIC code requires special handling for j, so it must be a
                   1545:    macro.  */
                   1546: {"j",      "a",        0,     (int) M_J_A,     INSN_MACRO,             I1      },
                   1547: /* This form of j is used by the disassembler and internally by the
                   1548:    assembler, but will never match user input (because the line above
                   1549:    will match first).  */
                   1550: {"j",       "a",       0x08000000, 0xfc000000, UBD,                    I1      },
                   1551: {"jalr",    "s",       0x0000f809, 0xfc1fffff, UBD|RD_s|WR_d,          I1      },
                   1552: {"jalr",    "d,s",     0x00000009, 0xfc1f07ff, UBD|RD_s|WR_d,          I1      },
                   1553: {"jalr.hb", "s",       0x0000fc09, 0xfc1fffff, UBD|RD_s|WR_d,          I33     },
                   1554: {"jalr.hb", "d,s",     0x00000409, 0xfc1f07ff, UBD|RD_s|WR_d,          I33     },
                   1555: /* SVR4 PIC code requires special handling for jal, so it must be a
                   1556:    macro.  */
                   1557: {"jal",     "d,s",     0,     (int) M_JAL_2,   INSN_MACRO,             I1      },
                   1558: {"jal",     "s",       0,     (int) M_JAL_1,   INSN_MACRO,             I1      },
                   1559: {"jal",     "a",       0,     (int) M_JAL_A,   INSN_MACRO,             I1      },
                   1560: /* This form of jal is used by the disassembler and internally by the
                   1561:    assembler, but will never match user input (because the line above
                   1562:    will match first).  */
                   1563: {"jal",     "a",       0x0c000000, 0xfc000000, UBD|WR_31,              I1      },
                   1564: {"jalx",    "a",       0x74000000, 0xfc000000, UBD|WR_31,              I16     },
                   1565: {"la",      "t,A(b)",  0,    (int) M_LA_AB,    INSN_MACRO,             I1      },
                   1566: {"lb",      "t,o(b)",  0x80000000, 0xfc000000, LDD|RD_b|WR_t,          I1      },
                   1567: {"lb",      "t,A(b)",  0,    (int) M_LB_AB,    INSN_MACRO,             I1      },
                   1568: {"lbu",     "t,o(b)",  0x90000000, 0xfc000000, LDD|RD_b|WR_t,          I1      },
                   1569: {"lbu",     "t,A(b)",  0,    (int) M_LBU_AB,   INSN_MACRO,             I1      },
                   1570: {"lca",     "t,A(b)",  0,    (int) M_LCA_AB,   INSN_MACRO,             I1      },
                   1571: {"ld",     "t,o(b)",   0xdc000000, 0xfc000000, WR_t|RD_b,              I3      },
                   1572: {"ld",      "t,o(b)",  0,    (int) M_LD_OB,    INSN_MACRO,             I1      },
                   1573: {"ld",      "t,A(b)",  0,    (int) M_LD_AB,    INSN_MACRO,             I1      },
                   1574: {"ldc1",    "T,o(b)",  0xd4000000, 0xfc000000, CLD|RD_b|WR_T|FP_D,     I2      },
                   1575: {"ldc1",    "E,o(b)",  0xd4000000, 0xfc000000, CLD|RD_b|WR_T|FP_D,     I2      },
                   1576: {"ldc1",    "T,A(b)",  0,    (int) M_LDC1_AB,  INSN_MACRO,             I2      },
                   1577: {"ldc1",    "E,A(b)",  0,    (int) M_LDC1_AB,  INSN_MACRO,             I2      },
                   1578: {"l.d",     "T,o(b)",  0xd4000000, 0xfc000000, CLD|RD_b|WR_T|FP_D,     I2      }, /* ldc1 */
                   1579: {"l.d",     "T,o(b)",  0,    (int) M_L_DOB,    INSN_MACRO,             I1      },
                   1580: {"l.d",     "T,A(b)",  0,    (int) M_L_DAB,    INSN_MACRO,             I1      },
                   1581: {"ldc2",    "E,o(b)",  0xd8000000, 0xfc000000, CLD|RD_b|WR_CC,         I2      },
                   1582: {"ldc2",    "E,A(b)",  0,    (int) M_LDC2_AB,  INSN_MACRO,             I2      },
                   1583: {"ldc3",    "E,o(b)",  0xdc000000, 0xfc000000, CLD|RD_b|WR_CC,         I2      },
                   1584: {"ldc3",    "E,A(b)",  0,    (int) M_LDC3_AB,  INSN_MACRO,             I2      },
                   1585: {"ldl",            "t,o(b)",   0x68000000, 0xfc000000, LDD|WR_t|RD_b,          I3      },
                   1586: {"ldl",            "t,A(b)",   0,    (int) M_LDL_AB,   INSN_MACRO,             I3      },
                   1587: {"ldr",            "t,o(b)",   0x6c000000, 0xfc000000, LDD|WR_t|RD_b,          I3      },
                   1588: {"ldr",     "t,A(b)",  0,    (int) M_LDR_AB,   INSN_MACRO,             I3      },
                   1589: {"ldxc1",   "D,t(b)",  0x4c000001, 0xfc00f83f, LDD|WR_D|RD_t|RD_b,     I4      },
                   1590: {"lh",      "t,o(b)",  0x84000000, 0xfc000000, LDD|RD_b|WR_t,          I1      },
                   1591: {"lh",      "t,A(b)",  0,    (int) M_LH_AB,    INSN_MACRO,             I1      },
                   1592: {"lhu",     "t,o(b)",  0x94000000, 0xfc000000, LDD|RD_b|WR_t,          I1      },
                   1593: {"lhu",     "t,A(b)",  0,    (int) M_LHU_AB,   INSN_MACRO,             I1      },
                   1594: /* li is at the start of the table.  */
                   1595: {"li.d",    "t,F",     0,    (int) M_LI_D,     INSN_MACRO,             I1      },
                   1596: {"li.d",    "T,L",     0,    (int) M_LI_DD,    INSN_MACRO,             I1      },
                   1597: {"li.s",    "t,f",     0,    (int) M_LI_S,     INSN_MACRO,             I1      },
                   1598: {"li.s",    "T,l",     0,    (int) M_LI_SS,    INSN_MACRO,             I1      },
                   1599: {"ll",     "t,o(b)",   0xc0000000, 0xfc000000, LDD|RD_b|WR_t,          I2      },
                   1600: {"ll",     "t,A(b)",   0,    (int) M_LL_AB,    INSN_MACRO,             I2      },
                   1601: {"lld",            "t,o(b)",   0xd0000000, 0xfc000000, LDD|RD_b|WR_t,          I3      },
                   1602: {"lld",     "t,A(b)",  0,    (int) M_LLD_AB,   INSN_MACRO,             I3      },
                   1603: {"lui",     "t,u",     0x3c000000, 0xffe00000, WR_t,                   I1      },
                   1604: {"luxc1",   "D,t(b)",  0x4c000005, 0xfc00f83f, LDD|WR_D|RD_t|RD_b,     I5|N55  },
                   1605: {"lw",      "t,o(b)",  0x8c000000, 0xfc000000, LDD|RD_b|WR_t,          I1      },
                   1606: {"lw",      "t,A(b)",  0,    (int) M_LW_AB,    INSN_MACRO,             I1      },
                   1607: {"lwc0",    "E,o(b)",  0xc0000000, 0xfc000000, CLD|RD_b|WR_CC,         I1      },
                   1608: {"lwc0",    "E,A(b)",  0,    (int) M_LWC0_AB,  INSN_MACRO,             I1      },
                   1609: {"lwc1",    "T,o(b)",  0xc4000000, 0xfc000000, CLD|RD_b|WR_T|FP_S,     I1      },
                   1610: {"lwc1",    "E,o(b)",  0xc4000000, 0xfc000000, CLD|RD_b|WR_T|FP_S,     I1      },
                   1611: {"lwc1",    "T,A(b)",  0,    (int) M_LWC1_AB,  INSN_MACRO,             I1      },
                   1612: {"lwc1",    "E,A(b)",  0,    (int) M_LWC1_AB,  INSN_MACRO,             I1      },
                   1613: {"l.s",     "T,o(b)",  0xc4000000, 0xfc000000, CLD|RD_b|WR_T|FP_S,     I1      }, /* lwc1 */
                   1614: {"l.s",     "T,A(b)",  0,    (int) M_LWC1_AB,  INSN_MACRO,             I1      },
                   1615: {"lwc2",    "E,o(b)",  0xc8000000, 0xfc000000, CLD|RD_b|WR_CC,         I1      },
                   1616: {"lwc2",    "E,A(b)",  0,    (int) M_LWC2_AB,  INSN_MACRO,             I1      },
                   1617: {"lwc3",    "E,o(b)",  0xcc000000, 0xfc000000, CLD|RD_b|WR_CC,         I1      },
                   1618: {"lwc3",    "E,A(b)",  0,    (int) M_LWC3_AB,  INSN_MACRO,             I1      },
                   1619: {"lwl",     "t,o(b)",  0x88000000, 0xfc000000, LDD|RD_b|WR_t,          I1      },
                   1620: {"lwl",     "t,A(b)",  0,    (int) M_LWL_AB,   INSN_MACRO,             I1      },
                   1621: {"lcache",  "t,o(b)",  0x88000000, 0xfc000000, LDD|RD_b|WR_t,          I2      }, /* same */
                   1622: {"lcache",  "t,A(b)",  0,    (int) M_LWL_AB,   INSN_MACRO,             I2      }, /* as lwl */
                   1623: {"lwr",     "t,o(b)",  0x98000000, 0xfc000000, LDD|RD_b|WR_t,          I1      },
                   1624: {"lwr",     "t,A(b)",  0,    (int) M_LWR_AB,   INSN_MACRO,             I1      },
                   1625: {"flush",   "t,o(b)",  0x98000000, 0xfc000000, LDD|RD_b|WR_t,          I2      }, /* same */
                   1626: {"flush",   "t,A(b)",  0,    (int) M_LWR_AB,   INSN_MACRO,             I2      }, /* as lwr */
                   1627: {"lwu",     "t,o(b)",  0x9c000000, 0xfc000000, LDD|RD_b|WR_t,          I3      },
                   1628: {"lwu",     "t,A(b)",  0,    (int) M_LWU_AB,   INSN_MACRO,             I3      },
                   1629: {"lwxc1",   "D,t(b)",  0x4c000000, 0xfc00f83f, LDD|WR_D|RD_t|RD_b,     I4      },
                   1630: {"macc",    "d,s,t",   0x00000028, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, N412    },
                   1631: {"macc",    "d,s,t",   0x00000158, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, N5      },
                   1632: {"maccs",   "d,s,t",   0x00000428, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, N412    },
                   1633: {"macchi",  "d,s,t",   0x00000228, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, N412    },
                   1634: {"macchi",  "d,s,t",   0x00000358, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, N5      },
                   1635: {"macchis", "d,s,t",   0x00000628, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, N412    },
                   1636: {"macchiu", "d,s,t",   0x00000268, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, N412    },
                   1637: {"macchiu", "d,s,t",   0x00000359, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, N5      },
                   1638: {"macchius","d,s,t",   0x00000668, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, N412    },
                   1639: {"maccu",   "d,s,t",   0x00000068, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, N412    },
                   1640: {"maccu",   "d,s,t",   0x00000159, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, N5      },
                   1641: {"maccus",  "d,s,t",   0x00000468, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, N412    },
                   1642: {"mad",     "s,t",      0x70000000, 0xfc00ffff, RD_s|RD_t|MOD_HILO,     P3      },
                   1643: {"madu",    "s,t",      0x70000001, 0xfc00ffff, RD_s|RD_t|MOD_HILO,     P3      },
                   1644: {"madd.d",  "D,R,S,T", 0x4c000021, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D,    I4 },
                   1645: {"madd.s",  "D,R,S,T", 0x4c000020, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_S,    I4 },
                   1646: {"madd.ps", "D,R,S,T", 0x4c000026, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D,    I5 },
                   1647: {"madd",    "s,t",      0x0000001c, 0xfc00ffff, RD_s|RD_t|WR_HILO,           L1 },
                   1648: {"madd",    "s,t",      0x70000000, 0xfc00ffff, RD_s|RD_t|MOD_HILO,          I32|N55},
                   1649: {"madd",    "s,t",      0x70000000, 0xfc00ffff, RD_s|RD_t|WR_HILO|IS_M,      G1 },
                   1650: {"madd",    "d,s,t",    0x70000000, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d|IS_M, G1 },
                   1651: {"maddu",   "s,t",      0x0000001d, 0xfc00ffff, RD_s|RD_t|WR_HILO,           L1 },
                   1652: {"maddu",   "s,t",      0x70000001, 0xfc00ffff, RD_s|RD_t|MOD_HILO,          I32|N55},
                   1653: {"maddu",   "s,t",      0x70000001, 0xfc00ffff, RD_s|RD_t|WR_HILO|IS_M,      G1        },
                   1654: {"maddu",   "d,s,t",    0x70000001, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d|IS_M, G1        },
                   1655: {"madd16",  "s,t",      0x00000028, 0xfc00ffff, RD_s|RD_t|MOD_HILO,    N411    },
                   1656: {"max.ob",  "X,Y,Q",   0x78000007, 0xfc20003f, WR_D|RD_S|RD_T|FP_D,    MX|SB1  },
                   1657: {"max.ob",  "D,S,T",   0x4ac00007, 0xffe0003f, WR_D|RD_S|RD_T,         N54     },
                   1658: {"max.ob",  "D,S,T[e]",        0x48000007, 0xfe20003f, WR_D|RD_S|RD_T,         N54     },
                   1659: {"max.ob",  "D,S,k",   0x4bc00007, 0xffe0003f, WR_D|RD_S|RD_T,         N54     },
                   1660: {"max.qh",  "X,Y,Q",   0x78200007, 0xfc20003f, WR_D|RD_S|RD_T|FP_D,    MX      },
                   1661: {"mfpc",    "t,P",     0x4000c801, 0xffe0ffc1, LCD|WR_t|RD_C0,         M1|N5   },
                   1662: {"mfps",    "t,P",     0x4000c800, 0xffe0ffc1, LCD|WR_t|RD_C0,         M1|N5   },
                   1663: {"mfc0",    "t,G",     0x40000000, 0xffe007ff, LCD|WR_t|RD_C0,         I1      },
                   1664: {"mfc0",    "t,+D",     0x40000000, 0xffe007f8, LCD|WR_t|RD_C0,        I32     },
                   1665: {"mfc0",    "t,G,H",    0x40000000, 0xffe007f8, LCD|WR_t|RD_C0,        I32     },
                   1666: {"mfc1",    "t,S",     0x44000000, 0xffe007ff, LCD|WR_t|RD_S|FP_S,     I1      },
                   1667: {"mfc1",    "t,G",     0x44000000, 0xffe007ff, LCD|WR_t|RD_S|FP_S,     I1      },
                   1668: {"mfhc1",   "t,S",     0x44600000, 0xffe007ff, LCD|WR_t|RD_S|FP_S,     I33     },
                   1669: {"mfhc1",   "t,G",     0x44600000, 0xffe007ff, LCD|WR_t|RD_S|FP_S,     I33     },
                   1670: /* mfc2 is at the bottom of the table.  */
                   1671: /* mfhc2 is at the bottom of the table.  */
                   1672: {"mfc3",    "t,G",     0x4c000000, 0xffe007ff, LCD|WR_t|RD_C3,         I1      },
                   1673: {"mfc3",    "t,G,H",    0x4c000000, 0xffe007f8, LCD|WR_t|RD_C3,        I32     },
                   1674: {"mfdr",    "t,G",     0x7000003d, 0xffe007ff, LCD|WR_t|RD_C0,         N5      },
                   1675: {"mfhi",    "d",       0x00000010, 0xffff07ff, WR_d|RD_HI,             I1      },
                   1676: {"mflo",    "d",       0x00000012, 0xffff07ff, WR_d|RD_LO,             I1      },
                   1677: {"min.ob",  "X,Y,Q",   0x78000006, 0xfc20003f, WR_D|RD_S|RD_T|FP_D,    MX|SB1  },
                   1678: {"min.ob",  "D,S,T",   0x4ac00006, 0xffe0003f, WR_D|RD_S|RD_T,         N54     },
                   1679: {"min.ob",  "D,S,T[e]",        0x48000006, 0xfe20003f, WR_D|RD_S|RD_T,         N54     },
                   1680: {"min.ob",  "D,S,k",   0x4bc00006, 0xffe0003f, WR_D|RD_S|RD_T,         N54     },
                   1681: {"min.qh",  "X,Y,Q",   0x78200006, 0xfc20003f, WR_D|RD_S|RD_T|FP_D,    MX      },
                   1682: {"mov.d",   "D,S",     0x46200006, 0xffff003f, WR_D|RD_S|FP_D,         I1      },
                   1683: {"mov.s",   "D,S",     0x46000006, 0xffff003f, WR_D|RD_S|FP_S,         I1      },
                   1684: {"mov.ps",  "D,S",     0x46c00006, 0xffff003f, WR_D|RD_S|FP_D,         I5      },
                   1685: {"movf",    "d,s,N",    0x00000001, 0xfc0307ff, WR_d|RD_s|RD_CC|FP_D|FP_S, I4|I32},
                   1686: {"movf.d",  "D,S,N",    0x46200011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D,   I4|I32 },
                   1687: {"movf.l",  "D,S,N",   0x46a00011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D,   MX|SB1  },
                   1688: {"movf.l",  "X,Y,N",   0x46a00011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D,   MX|SB1  },
                   1689: {"movf.s",  "D,S,N",    0x46000011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_S,   I4|I32 },
                   1690: {"movf.ps", "D,S,N",   0x46c00011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D,   I5      },
                   1691: {"movn",    "d,v,t",    0x0000000b, 0xfc0007ff, WR_d|RD_s|RD_t,        I4|I32  },
                   1692: {"ffc",     "d,v",     0x0000000b, 0xfc1f07ff, WR_d|RD_s,              L1      },
                   1693: {"movn.d",  "D,S,t",    0x46200013, 0xffe0003f, WR_D|RD_S|RD_t|FP_D,    I4|I32 },
                   1694: {"movn.l",  "D,S,t",    0x46a00013, 0xffe0003f, WR_D|RD_S|RD_t|FP_D,    MX|SB1 },
                   1695: {"movn.l",  "X,Y,t",    0x46a00013, 0xffe0003f, WR_D|RD_S|RD_t|FP_D,    MX|SB1 },
                   1696: {"movn.s",  "D,S,t",    0x46000013, 0xffe0003f, WR_D|RD_S|RD_t|FP_S,    I4|I32 },
                   1697: {"movn.ps", "D,S,t",    0x46c00013, 0xffe0003f, WR_D|RD_S|RD_t|FP_D,    I5     },
                   1698: {"movt",    "d,s,N",    0x00010001, 0xfc0307ff, WR_d|RD_s|RD_CC,        I4|I32 },
                   1699: {"movt.d",  "D,S,N",    0x46210011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D,   I4|I32 },
                   1700: {"movt.l",  "D,S,N",    0x46a10011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D,   MX|SB1 },
                   1701: {"movt.l",  "X,Y,N",    0x46a10011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D,   MX|SB1 },
                   1702: {"movt.s",  "D,S,N",    0x46010011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_S,   I4|I32 },
                   1703: {"movt.ps", "D,S,N",   0x46c10011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D,   I5      },
                   1704: {"movz",    "d,v,t",    0x0000000a, 0xfc0007ff, WR_d|RD_s|RD_t,        I4|I32  },
                   1705: {"ffs",     "d,v",     0x0000000a, 0xfc1f07ff, WR_d|RD_s,              L1      },
                   1706: {"movz.d",  "D,S,t",    0x46200012, 0xffe0003f, WR_D|RD_S|RD_t|FP_D,    I4|I32 },
                   1707: {"movz.l",  "D,S,t",    0x46a00012, 0xffe0003f, WR_D|RD_S|RD_t|FP_D,    MX|SB1 },
                   1708: {"movz.l",  "X,Y,t",    0x46a00012, 0xffe0003f, WR_D|RD_S|RD_t|FP_D,    MX|SB1 },
                   1709: {"movz.s",  "D,S,t",    0x46000012, 0xffe0003f, WR_D|RD_S|RD_t|FP_S,    I4|I32 },
                   1710: {"movz.ps", "D,S,t",    0x46c00012, 0xffe0003f, WR_D|RD_S|RD_t|FP_D,    I5     },
                   1711: {"msac",    "d,s,t",   0x000001d8, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, N5      },
                   1712: {"msacu",   "d,s,t",   0x000001d9, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, N5      },
                   1713: {"msachi",  "d,s,t",   0x000003d8, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, N5      },
                   1714: {"msachiu", "d,s,t",   0x000003d9, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, N5      },
                   1715: /* move is at the top of the table.  */
                   1716: {"msgn.qh", "X,Y,Q",   0x78200000, 0xfc20003f, WR_D|RD_S|RD_T|FP_D,    MX      },
                   1717: {"msub.d",  "D,R,S,T", 0x4c000029, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, I4    },
                   1718: {"msub.s",  "D,R,S,T", 0x4c000028, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_S, I4    },
                   1719: {"msub.ps", "D,R,S,T", 0x4c00002e, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, I5    },
                   1720: {"msub",    "s,t",      0x0000001e, 0xfc00ffff, RD_s|RD_t|WR_HILO,     L1      },
                   1721: {"msub",    "s,t",      0x70000004, 0xfc00ffff, RD_s|RD_t|MOD_HILO,     I32|N55 },
                   1722: {"msubu",   "s,t",      0x0000001f, 0xfc00ffff, RD_s|RD_t|WR_HILO,     L1      },
                   1723: {"msubu",   "s,t",      0x70000005, 0xfc00ffff, RD_s|RD_t|MOD_HILO,     I32|N55        },
                   1724: {"mtpc",    "t,P",     0x4080c801, 0xffe0ffc1, COD|RD_t|WR_C0,         M1|N5   },
                   1725: {"mtps",    "t,P",     0x4080c800, 0xffe0ffc1, COD|RD_t|WR_C0,         M1|N5   },
                   1726: {"mtc0",    "t,G",     0x40800000, 0xffe007ff, COD|RD_t|WR_C0|WR_CC,   I1      },
                   1727: {"mtc0",    "t,+D",     0x40800000, 0xffe007f8, COD|RD_t|WR_C0|WR_CC,   I32     },
                   1728: {"mtc0",    "t,G,H",    0x40800000, 0xffe007f8, COD|RD_t|WR_C0|WR_CC,   I32     },
                   1729: {"mtc1",    "t,S",     0x44800000, 0xffe007ff, COD|RD_t|WR_S|FP_S,     I1      },
                   1730: {"mtc1",    "t,G",     0x44800000, 0xffe007ff, COD|RD_t|WR_S|FP_S,     I1      },
                   1731: {"mthc1",   "t,S",     0x44e00000, 0xffe007ff, COD|RD_t|WR_S|FP_S,     I33     },
                   1732: {"mthc1",   "t,G",     0x44e00000, 0xffe007ff, COD|RD_t|WR_S|FP_S,     I33     },
                   1733: /* mtc2 is at the bottom of the table.  */
                   1734: /* mthc2 is at the bottom of the table.  */
                   1735: {"mtc3",    "t,G",     0x4c800000, 0xffe007ff, COD|RD_t|WR_C3|WR_CC,   I1      },
                   1736: {"mtc3",    "t,G,H",    0x4c800000, 0xffe007f8, COD|RD_t|WR_C3|WR_CC,   I32     },
                   1737: {"mtdr",    "t,G",     0x7080003d, 0xffe007ff, COD|RD_t|WR_C0,         N5      },
                   1738: {"mthi",    "s",       0x00000011, 0xfc1fffff, RD_s|WR_HI,             I1      },
                   1739: {"mtlo",    "s",       0x00000013, 0xfc1fffff, RD_s|WR_LO,             I1      },
                   1740: {"mul.d",   "D,V,T",   0x46200002, 0xffe0003f, WR_D|RD_S|RD_T|FP_D,    I1      },
                   1741: {"mul.s",   "D,V,T",   0x46000002, 0xffe0003f, WR_D|RD_S|RD_T|FP_S,    I1      },
                   1742: {"mul.ob",  "X,Y,Q",   0x78000030, 0xfc20003f, WR_D|RD_S|RD_T|FP_D,    MX|SB1  },
                   1743: {"mul.ob",  "D,S,T",   0x4ac00030, 0xffe0003f, WR_D|RD_S|RD_T,         N54     },
                   1744: {"mul.ob",  "D,S,T[e]",        0x48000030, 0xfe20003f, WR_D|RD_S|RD_T,         N54     },
                   1745: {"mul.ob",  "D,S,k",   0x4bc00030, 0xffe0003f, WR_D|RD_S|RD_T,         N54     },
                   1746: {"mul.ps",  "D,V,T",   0x46c00002, 0xffe0003f, WR_D|RD_S|RD_T|FP_D,    I5      },
                   1747: {"mul.qh",  "X,Y,Q",   0x78200030, 0xfc20003f, WR_D|RD_S|RD_T|FP_D,    MX      },
                   1748: {"mul",     "d,v,t",    0x70000002, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, I32|P3|N55},
                   1749: {"mul",     "d,s,t",   0x00000058, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, N54     },
                   1750: {"mul",     "d,v,t",   0,    (int) M_MUL,      INSN_MACRO,             I1      },
                   1751: {"mul",     "d,v,I",   0,    (int) M_MUL_I,    INSN_MACRO,             I1      },
                   1752: {"mula.ob", "Y,Q",     0x78000033, 0xfc2007ff, WR_MACC|RD_S|RD_T|FP_D, MX|SB1  },
                   1753: {"mula.ob", "S,T",     0x4ac00033, 0xffe007ff, WR_CC|RD_S|RD_T,        N54     },
                   1754: {"mula.ob", "S,T[e]",  0x48000033, 0xfe2007ff, WR_CC|RD_S|RD_T,        N54     },
                   1755: {"mula.ob", "S,k",     0x4bc00033, 0xffe007ff, WR_CC|RD_S|RD_T,        N54     },
                   1756: {"mula.qh", "Y,Q",     0x78200033, 0xfc2007ff, WR_MACC|RD_S|RD_T|FP_D, MX      },
                   1757: {"mulhi",   "d,s,t",   0x00000258, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, N5      },
                   1758: {"mulhiu",  "d,s,t",   0x00000259, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, N5      },
                   1759: {"mull.ob", "Y,Q",     0x78000433, 0xfc2007ff, WR_MACC|RD_S|RD_T|FP_D, MX|SB1  },
                   1760: {"mull.ob", "S,T",     0x4ac00433, 0xffe007ff, WR_CC|RD_S|RD_T,        N54     },
                   1761: {"mull.ob", "S,T[e]",  0x48000433, 0xfe2007ff, WR_CC|RD_S|RD_T,        N54     },
                   1762: {"mull.ob", "S,k",     0x4bc00433, 0xffe007ff, WR_CC|RD_S|RD_T,        N54     },
                   1763: {"mull.qh", "Y,Q",     0x78200433, 0xfc2007ff, WR_MACC|RD_S|RD_T|FP_D, MX      },
                   1764: {"mulo",    "d,v,t",   0,    (int) M_MULO,     INSN_MACRO,             I1      },
                   1765: {"mulo",    "d,v,I",   0,    (int) M_MULO_I,   INSN_MACRO,             I1      },
                   1766: {"mulou",   "d,v,t",   0,    (int) M_MULOU,    INSN_MACRO,             I1      },
                   1767: {"mulou",   "d,v,I",   0,    (int) M_MULOU_I,  INSN_MACRO,             I1      },
                   1768: {"mulr.ps", "D,S,T",   0x46c0001a, 0xffe0003f, WR_D|RD_S|RD_T|FP_D,    M3D     },
                   1769: {"muls",    "d,s,t",   0x000000d8, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, N5      },
                   1770: {"mulsu",   "d,s,t",   0x000000d9, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, N5      },
                   1771: {"mulshi",  "d,s,t",   0x000002d8, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, N5      },
                   1772: {"mulshiu", "d,s,t",   0x000002d9, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, N5      },
                   1773: {"muls.ob", "Y,Q",     0x78000032, 0xfc2007ff, WR_MACC|RD_S|RD_T|FP_D, MX|SB1  },
                   1774: {"muls.ob", "S,T",     0x4ac00032, 0xffe007ff, WR_CC|RD_S|RD_T,        N54     },
                   1775: {"muls.ob", "S,T[e]",  0x48000032, 0xfe2007ff, WR_CC|RD_S|RD_T,        N54     },
                   1776: {"muls.ob", "S,k",     0x4bc00032, 0xffe007ff, WR_CC|RD_S|RD_T,        N54     },
                   1777: {"muls.qh", "Y,Q",     0x78200032, 0xfc2007ff, WR_MACC|RD_S|RD_T|FP_D, MX      },
                   1778: {"mulsl.ob", "Y,Q",    0x78000432, 0xfc2007ff, WR_MACC|RD_S|RD_T|FP_D, MX|SB1  },
                   1779: {"mulsl.ob", "S,T",    0x4ac00432, 0xffe007ff, WR_CC|RD_S|RD_T,        N54     },
                   1780: {"mulsl.ob", "S,T[e]", 0x48000432, 0xfe2007ff, WR_CC|RD_S|RD_T,        N54     },
                   1781: {"mulsl.ob", "S,k",    0x4bc00432, 0xffe007ff, WR_CC|RD_S|RD_T,        N54     },
                   1782: {"mulsl.qh", "Y,Q",    0x78200432, 0xfc2007ff, WR_MACC|RD_S|RD_T|FP_D, MX      },
                   1783: {"mult",    "s,t",      0x00000018, 0xfc00ffff, RD_s|RD_t|WR_HILO|IS_M, I1     },
                   1784: {"mult",    "d,s,t",    0x00000018, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d|IS_M, G1        },
                   1785: {"multu",   "s,t",      0x00000019, 0xfc00ffff, RD_s|RD_t|WR_HILO|IS_M, I1     },
                   1786: {"multu",   "d,s,t",    0x00000019, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d|IS_M, G1        },
                   1787: {"mulu",    "d,s,t",   0x00000059, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, N5      },
                   1788: {"neg",     "d,w",     0x00000022, 0xffe007ff, WR_d|RD_t,              I1      }, /* sub 0 */
                   1789: {"negu",    "d,w",     0x00000023, 0xffe007ff, WR_d|RD_t,              I1      }, /* subu 0 */
                   1790: {"neg.d",   "D,V",     0x46200007, 0xffff003f, WR_D|RD_S|FP_D,         I1      },
                   1791: {"neg.s",   "D,V",     0x46000007, 0xffff003f, WR_D|RD_S|FP_S,         I1      },
                   1792: {"neg.ps",  "D,V",     0x46c00007, 0xffff003f, WR_D|RD_S|FP_D,         I5      },
                   1793: {"nmadd.d", "D,R,S,T", 0x4c000031, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, I4    },
                   1794: {"nmadd.s", "D,R,S,T", 0x4c000030, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_S, I4    },
                   1795: {"nmadd.ps","D,R,S,T", 0x4c000036, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, I5    },
                   1796: {"nmsub.d", "D,R,S,T", 0x4c000039, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, I4    },
                   1797: {"nmsub.s", "D,R,S,T", 0x4c000038, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_S, I4    },
                   1798: {"nmsub.ps","D,R,S,T", 0x4c00003e, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, I5    },
                   1799: /* nop is at the start of the table.  */
                   1800: {"nor",     "d,v,t",   0x00000027, 0xfc0007ff, WR_d|RD_s|RD_t,         I1      },
                   1801: {"nor",     "t,r,I",   0,    (int) M_NOR_I,    INSN_MACRO,             I1      },
                   1802: {"nor.ob",  "X,Y,Q",   0x7800000f, 0xfc20003f, WR_D|RD_S|RD_T|FP_D,    MX|SB1  },
                   1803: {"nor.ob",  "D,S,T",   0x4ac0000f, 0xffe0003f, WR_D|RD_S|RD_T,         N54     },
                   1804: {"nor.ob",  "D,S,T[e]",        0x4800000f, 0xfe20003f, WR_D|RD_S|RD_T,         N54     },
                   1805: {"nor.ob",  "D,S,k",   0x4bc0000f, 0xffe0003f, WR_D|RD_S|RD_T,         N54     },
                   1806: {"nor.qh",  "X,Y,Q",   0x7820000f, 0xfc20003f, WR_D|RD_S|RD_T|FP_D,    MX      },
                   1807: {"not",     "d,v",     0x00000027, 0xfc1f07ff, WR_d|RD_s|RD_t,         I1      },/*nor d,s,0*/
                   1808: {"or",      "d,v,t",   0x00000025, 0xfc0007ff, WR_d|RD_s|RD_t,         I1      },
                   1809: {"or",      "t,r,I",   0,    (int) M_OR_I,     INSN_MACRO,             I1      },
                   1810: {"or.ob",   "X,Y,Q",   0x7800000e, 0xfc20003f, WR_D|RD_S|RD_T|FP_D,    MX|SB1  },
                   1811: {"or.ob",   "D,S,T",   0x4ac0000e, 0xffe0003f, WR_D|RD_S|RD_T,         N54     },
                   1812: {"or.ob",   "D,S,T[e]",        0x4800000e, 0xfe20003f, WR_D|RD_S|RD_T,         N54     },
                   1813: {"or.ob",   "D,S,k",   0x4bc0000e, 0xffe0003f, WR_D|RD_S|RD_T,         N54     },
                   1814: {"or.qh",   "X,Y,Q",   0x7820000e, 0xfc20003f, WR_D|RD_S|RD_T|FP_D,    MX      },
                   1815: {"ori",     "t,r,i",   0x34000000, 0xfc000000, WR_t|RD_s,              I1      },
                   1816: {"pabsdiff.ob", "X,Y,Q",0x78000009, 0xfc20003f,        WR_D|RD_S|RD_T|FP_D,    SB1     },
                   1817: {"pabsdiffc.ob", "Y,Q",        0x78000035, 0xfc2007ff, WR_MACC|RD_S|RD_T|FP_D, SB1     },
                   1818: {"pavg.ob", "X,Y,Q",   0x78000008, 0xfc20003f, WR_D|RD_S|RD_T|FP_D,    SB1     },
                   1819: {"pickf.ob", "X,Y,Q",  0x78000002, 0xfc20003f, WR_D|RD_S|RD_T|FP_D,    MX|SB1  },
                   1820: {"pickf.ob", "D,S,T",  0x4ac00002, 0xffe0003f, WR_D|RD_S|RD_T,         N54     },
                   1821: {"pickf.ob", "D,S,T[e]",0x48000002, 0xfe20003f,        WR_D|RD_S|RD_T,         N54     },
                   1822: {"pickf.ob", "D,S,k",  0x4bc00002, 0xffe0003f, WR_D|RD_S|RD_T,         N54     },
                   1823: {"pickf.qh", "X,Y,Q",  0x78200002, 0xfc20003f, WR_D|RD_S|RD_T|FP_D,    MX      },
                   1824: {"pickt.ob", "X,Y,Q",  0x78000003, 0xfc20003f, WR_D|RD_S|RD_T|FP_D,    MX|SB1  },
                   1825: {"pickt.ob", "D,S,T",  0x4ac00003, 0xffe0003f, WR_D|RD_S|RD_T,         N54     },
                   1826: {"pickt.ob", "D,S,T[e]",0x48000003, 0xfe20003f,        WR_D|RD_S|RD_T,         N54     },
                   1827: {"pickt.ob", "D,S,k",  0x4bc00003, 0xffe0003f, WR_D|RD_S|RD_T,         N54     },
                   1828: {"pickt.qh", "X,Y,Q",  0x78200003, 0xfc20003f, WR_D|RD_S|RD_T|FP_D,    MX      },
                   1829: {"pll.ps",  "D,V,T",   0x46c0002c, 0xffe0003f, WR_D|RD_S|RD_T|FP_D,    I5      },
                   1830: {"plu.ps",  "D,V,T",   0x46c0002d, 0xffe0003f, WR_D|RD_S|RD_T|FP_D,    I5      },
                   1831:   /* pref and prefx are at the start of the table.  */
                   1832: {"pul.ps",  "D,V,T",   0x46c0002e, 0xffe0003f, WR_D|RD_S|RD_T|FP_D,    I5      },
                   1833: {"puu.ps",  "D,V,T",   0x46c0002f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D,    I5      },
                   1834: {"rach.ob", "X",       0x7a00003f, 0xfffff83f, WR_D|RD_MACC|FP_D,      MX|SB1  },
                   1835: {"rach.ob", "D",       0x4a00003f, 0xfffff83f, WR_D,                   N54     },
                   1836: {"rach.qh", "X",       0x7a20003f, 0xfffff83f, WR_D|RD_MACC|FP_D,      MX      },
                   1837: {"racl.ob", "X",       0x7800003f, 0xfffff83f, WR_D|RD_MACC|FP_D,      MX|SB1  },
                   1838: {"racl.ob", "D",       0x4800003f, 0xfffff83f, WR_D,                   N54     },
                   1839: {"racl.qh", "X",       0x7820003f, 0xfffff83f, WR_D|RD_MACC|FP_D,      MX      },
                   1840: {"racm.ob", "X",       0x7900003f, 0xfffff83f, WR_D|RD_MACC|FP_D,      MX|SB1  },
                   1841: {"racm.ob", "D",       0x4900003f, 0xfffff83f, WR_D,                   N54     },
                   1842: {"racm.qh", "X",       0x7920003f, 0xfffff83f, WR_D|RD_MACC|FP_D,      MX      },
                   1843: {"recip.d", "D,S",     0x46200015, 0xffff003f, WR_D|RD_S|FP_D,         I4      },
                   1844: {"recip.ps","D,S",     0x46c00015, 0xffff003f, WR_D|RD_S|FP_D,         SB1     },
                   1845: {"recip.s", "D,S",     0x46000015, 0xffff003f, WR_D|RD_S|FP_S,         I4      },
                   1846: {"recip1.d",  "D,S",   0x4620001d, 0xffff003f, WR_D|RD_S|FP_D,         M3D     },
                   1847: {"recip1.ps", "D,S",   0x46c0001d, 0xffff003f, WR_D|RD_S|FP_S,         M3D     },
                   1848: {"recip1.s",  "D,S",   0x4600001d, 0xffff003f, WR_D|RD_S|FP_S,         M3D     },
                   1849: {"recip2.d",  "D,S,T", 0x4620001c, 0xffe0003f, WR_D|RD_S|RD_T|FP_D,    M3D     },
                   1850: {"recip2.ps", "D,S,T", 0x46c0001c, 0xffe0003f, WR_D|RD_S|RD_T|FP_S,    M3D     },
                   1851: {"recip2.s",  "D,S,T", 0x4600001c, 0xffe0003f, WR_D|RD_S|RD_T|FP_S,    M3D     },
                   1852: {"rem",     "z,s,t",    0x0000001a, 0xfc00ffff, RD_s|RD_t|WR_HILO,      I1     },
                   1853: {"rem",     "d,v,t",   0,    (int) M_REM_3,    INSN_MACRO,             I1      },
                   1854: {"rem",     "d,v,I",   0,    (int) M_REM_3I,   INSN_MACRO,             I1      },
                   1855: {"remu",    "z,s,t",    0x0000001b, 0xfc00ffff, RD_s|RD_t|WR_HILO,      I1     },
                   1856: {"remu",    "d,v,t",   0,    (int) M_REMU_3,   INSN_MACRO,             I1      },
                   1857: {"remu",    "d,v,I",   0,    (int) M_REMU_3I,  INSN_MACRO,             I1      },
                   1858: {"rdhwr",   "t,K",     0x7c00003b, 0xffe007ff, WR_t,                   I33     },
                   1859: {"rdpgpr",  "d,w",     0x41400000, 0xffe007ff, WR_d,                   I33     },
                   1860: {"rfe",     "",                0x42000010, 0xffffffff, 0,                      I1|T3   },
                   1861: {"rnas.qh", "X,Q",     0x78200025, 0xfc20f83f, WR_D|RD_MACC|RD_T|FP_D, MX      },
                   1862: {"rnau.ob", "X,Q",     0x78000021, 0xfc20f83f, WR_D|RD_MACC|RD_T|FP_D, MX|SB1  },
                   1863: {"rnau.qh", "X,Q",     0x78200021, 0xfc20f83f, WR_D|RD_MACC|RD_T|FP_D, MX      },
                   1864: {"rnes.qh", "X,Q",     0x78200026, 0xfc20f83f, WR_D|RD_MACC|RD_T|FP_D, MX      },
                   1865: {"rneu.ob", "X,Q",     0x78000022, 0xfc20f83f, WR_D|RD_MACC|RD_T|FP_D, MX|SB1  },
                   1866: {"rneu.qh", "X,Q",     0x78200022, 0xfc20f83f, WR_D|RD_MACC|RD_T|FP_D, MX      },
                   1867: {"rol",     "d,v,t",   0,    (int) M_ROL,      INSN_MACRO,             I1      },
                   1868: {"rol",     "d,v,I",   0,    (int) M_ROL_I,    INSN_MACRO,             I1      },
                   1869: {"ror",     "d,v,t",   0,    (int) M_ROR,      INSN_MACRO,             I1      },
                   1870: {"ror",     "d,v,I",   0,    (int) M_ROR_I,    INSN_MACRO,             I1      },
                   1871: {"ror",            "d,w,<",    0x00200002, 0xffe0003f, WR_d|RD_t,              N5|I33  },
                   1872: {"rorv",    "d,t,s",   0x00000046, 0xfc0007ff, RD_t|RD_s|WR_d,         N5|I33  },
                   1873: {"rotl",    "d,v,t",   0,    (int) M_ROL,      INSN_MACRO,             I33     },
                   1874: {"rotl",    "d,v,I",   0,    (int) M_ROL_I,    INSN_MACRO,             I33     },
                   1875: {"rotr",    "d,v,t",   0,    (int) M_ROR,      INSN_MACRO,             I33     },
                   1876: {"rotr",    "d,v,I",   0,    (int) M_ROR_I,    INSN_MACRO,             I33     },
                   1877: {"rotrv",   "d,t,s",   0x00000046, 0xfc0007ff, RD_t|RD_s|WR_d,         I33     },
                   1878: {"round.l.d", "D,S",   0x46200008, 0xffff003f, WR_D|RD_S|FP_D,         I3      },
                   1879: {"round.l.s", "D,S",   0x46000008, 0xffff003f, WR_D|RD_S|FP_S,         I3      },
                   1880: {"round.w.d", "D,S",   0x4620000c, 0xffff003f, WR_D|RD_S|FP_D,         I2      },
                   1881: {"round.w.s", "D,S",   0x4600000c, 0xffff003f, WR_D|RD_S|FP_S,         I2      },
                   1882: {"rsqrt.d", "D,S",     0x46200016, 0xffff003f, WR_D|RD_S|FP_D,         I4      },
                   1883: {"rsqrt.ps","D,S",     0x46c00016, 0xffff003f, WR_D|RD_S|FP_D,         SB1     },
                   1884: {"rsqrt.s", "D,S",     0x46000016, 0xffff003f, WR_D|RD_S|FP_S,         I4      },
                   1885: {"rsqrt1.d",  "D,S",   0x4620001e, 0xffff003f, WR_D|RD_S|FP_D,         M3D     },
                   1886: {"rsqrt1.ps", "D,S",   0x46c0001e, 0xffff003f, WR_D|RD_S|FP_S,         M3D     },
                   1887: {"rsqrt1.s",  "D,S",   0x4600001e, 0xffff003f, WR_D|RD_S|FP_S,         M3D     },
                   1888: {"rsqrt2.d",  "D,S,T", 0x4620001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D,    M3D     },
                   1889: {"rsqrt2.ps", "D,S,T", 0x46c0001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_S,    M3D     },
                   1890: {"rsqrt2.s",  "D,S,T", 0x4600001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_S,    M3D     },
                   1891: {"rzs.qh",  "X,Q",     0x78200024, 0xfc20f83f, WR_D|RD_MACC|RD_T|FP_D, MX      },
                   1892: {"rzu.ob",  "X,Q",     0x78000020, 0xfc20f83f, WR_D|RD_MACC|RD_T|FP_D, MX|SB1  },
                   1893: {"rzu.ob",  "D,k",     0x4bc00020, 0xffe0f83f, WR_D|RD_S|RD_T,         N54     },
                   1894: {"rzu.qh",  "X,Q",     0x78200020, 0xfc20f83f, WR_D|RD_MACC|RD_T|FP_D, MX      },
                   1895: {"sb",      "t,o(b)",  0xa0000000, 0xfc000000, SM|RD_t|RD_b,           I1      },
                   1896: {"sb",      "t,A(b)",  0,    (int) M_SB_AB,    INSN_MACRO,             I1      },
                   1897: {"sc",     "t,o(b)",   0xe0000000, 0xfc000000, SM|RD_t|WR_t|RD_b,      I2      },
                   1898: {"sc",     "t,A(b)",   0,    (int) M_SC_AB,    INSN_MACRO,             I2      },
                   1899: {"scd",            "t,o(b)",   0xf0000000, 0xfc000000, SM|RD_t|WR_t|RD_b,      I3      },
                   1900: {"scd",            "t,A(b)",   0,    (int) M_SCD_AB,   INSN_MACRO,             I3      },
                   1901: {"sd",     "t,o(b)",   0xfc000000, 0xfc000000, SM|RD_t|RD_b,           I3      },
                   1902: {"sd",      "t,o(b)",  0,    (int) M_SD_OB,    INSN_MACRO,             I1      },
                   1903: {"sd",      "t,A(b)",  0,    (int) M_SD_AB,    INSN_MACRO,             I1      },
                   1904: {"sdbbp",   "",                0x0000000e, 0xffffffff, TRAP,                   G2      },
                   1905: {"sdbbp",   "c",       0x0000000e, 0xfc00ffff, TRAP,                   G2      },
                   1906: {"sdbbp",   "c,q",     0x0000000e, 0xfc00003f, TRAP,                   G2      },
                   1907: {"sdbbp",   "",         0x7000003f, 0xffffffff, TRAP,                  I32     },
                   1908: {"sdbbp",   "B",        0x7000003f, 0xfc00003f, TRAP,                  I32     },
                   1909: {"sdc1",    "T,o(b)",  0xf4000000, 0xfc000000, SM|RD_T|RD_b|FP_D,      I2      },
                   1910: {"sdc1",    "E,o(b)",  0xf4000000, 0xfc000000, SM|RD_T|RD_b|FP_D,      I2      },
                   1911: {"sdc1",    "T,A(b)",  0,    (int) M_SDC1_AB,  INSN_MACRO,             I2      },
                   1912: {"sdc1",    "E,A(b)",  0,    (int) M_SDC1_AB,  INSN_MACRO,             I2      },
                   1913: {"sdc2",    "E,o(b)",  0xf8000000, 0xfc000000, SM|RD_C2|RD_b,          I2      },
                   1914: {"sdc2",    "E,A(b)",  0,    (int) M_SDC2_AB,  INSN_MACRO,             I2      },
                   1915: {"sdc3",    "E,o(b)",  0xfc000000, 0xfc000000, SM|RD_C3|RD_b,          I2      },
                   1916: {"sdc3",    "E,A(b)",  0,    (int) M_SDC3_AB,  INSN_MACRO,             I2      },
                   1917: {"s.d",     "T,o(b)",  0xf4000000, 0xfc000000, SM|RD_T|RD_b|FP_D,      I2      },
                   1918: {"s.d",     "T,o(b)",  0,    (int) M_S_DOB,    INSN_MACRO,             I1      },
                   1919: {"s.d",     "T,A(b)",  0,    (int) M_S_DAB,    INSN_MACRO,             I1      },
                   1920: {"sdl",     "t,o(b)",  0xb0000000, 0xfc000000, SM|RD_t|RD_b,           I3      },
                   1921: {"sdl",     "t,A(b)",  0,    (int) M_SDL_AB,   INSN_MACRO,             I3      },
                   1922: {"sdr",     "t,o(b)",  0xb4000000, 0xfc000000, SM|RD_t|RD_b,           I3      },
                   1923: {"sdr",     "t,A(b)",  0,    (int) M_SDR_AB,   INSN_MACRO,             I3      },
                   1924: {"sdxc1",   "S,t(b)",   0x4c000009, 0xfc0007ff, SM|RD_S|RD_t|RD_b,     I4      },
                   1925: {"seb",     "d,w",     0x7c000420, 0xffe007ff, WR_d|RD_t,              I33     },
                   1926: {"seh",     "d,w",     0x7c000620, 0xffe007ff, WR_d|RD_t,              I33     },
                   1927: {"selsl",   "d,v,t",   0x00000005, 0xfc0007ff, WR_d|RD_s|RD_t,         L1      },
                   1928: {"selsr",   "d,v,t",   0x00000001, 0xfc0007ff, WR_d|RD_s|RD_t,         L1      },
                   1929: {"seq",     "d,v,t",   0,    (int) M_SEQ,      INSN_MACRO,             I1      },
                   1930: {"seq",     "d,v,I",   0,    (int) M_SEQ_I,    INSN_MACRO,             I1      },
                   1931: {"sge",     "d,v,t",   0,    (int) M_SGE,      INSN_MACRO,             I1      },
                   1932: {"sge",     "d,v,I",   0,    (int) M_SGE_I,    INSN_MACRO,             I1      },
                   1933: {"sgeu",    "d,v,t",   0,    (int) M_SGEU,     INSN_MACRO,             I1      },
                   1934: {"sgeu",    "d,v,I",   0,    (int) M_SGEU_I,   INSN_MACRO,             I1      },
                   1935: {"sgt",     "d,v,t",   0,    (int) M_SGT,      INSN_MACRO,             I1      },
                   1936: {"sgt",     "d,v,I",   0,    (int) M_SGT_I,    INSN_MACRO,             I1      },
                   1937: {"sgtu",    "d,v,t",   0,    (int) M_SGTU,     INSN_MACRO,             I1      },
                   1938: {"sgtu",    "d,v,I",   0,    (int) M_SGTU_I,   INSN_MACRO,             I1      },
                   1939: {"sh",      "t,o(b)",  0xa4000000, 0xfc000000, SM|RD_t|RD_b,           I1      },
                   1940: {"sh",      "t,A(b)",  0,    (int) M_SH_AB,    INSN_MACRO,             I1      },
                   1941: {"shfl.bfla.qh", "X,Y,Z", 0x7a20001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, MX      },
                   1942: {"shfl.mixh.ob", "X,Y,Z", 0x7980001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, MX|SB1  },
                   1943: {"shfl.mixh.ob", "D,S,T", 0x4980001f, 0xffe0003f, WR_D|RD_S|RD_T,      N54     },
                   1944: {"shfl.mixh.qh", "X,Y,Z", 0x7820001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, MX      },
                   1945: {"shfl.mixl.ob", "X,Y,Z", 0x79c0001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, MX|SB1  },
                   1946: {"shfl.mixl.ob", "D,S,T", 0x49c0001f, 0xffe0003f, WR_D|RD_S|RD_T,      N54     },
                   1947: {"shfl.mixl.qh", "X,Y,Z", 0x78a0001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, MX      },
                   1948: {"shfl.pach.ob", "X,Y,Z", 0x7900001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, MX|SB1  },
                   1949: {"shfl.pach.ob", "D,S,T", 0x4900001f, 0xffe0003f, WR_D|RD_S|RD_T,      N54     },
                   1950: {"shfl.pach.qh", "X,Y,Z", 0x7920001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, MX      },
                   1951: {"shfl.pacl.ob", "D,S,T", 0x4940001f, 0xffe0003f, WR_D|RD_S|RD_T,      N54     },
                   1952: {"shfl.repa.qh", "X,Y,Z", 0x7b20001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, MX      },
                   1953: {"shfl.repb.qh", "X,Y,Z", 0x7ba0001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, MX      },
                   1954: {"shfl.upsl.ob", "X,Y,Z", 0x78c0001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, MX|SB1  },
                   1955: {"sle",     "d,v,t",   0,    (int) M_SLE,      INSN_MACRO,             I1      },
                   1956: {"sle",     "d,v,I",   0,    (int) M_SLE_I,    INSN_MACRO,             I1      },
                   1957: {"sleu",    "d,v,t",   0,    (int) M_SLEU,     INSN_MACRO,             I1      },
                   1958: {"sleu",    "d,v,I",   0,    (int) M_SLEU_I,   INSN_MACRO,             I1      },
                   1959: {"sllv",    "d,t,s",   0x00000004, 0xfc0007ff, WR_d|RD_t|RD_s,         I1      },
                   1960: {"sll",     "d,w,s",   0x00000004, 0xfc0007ff, WR_d|RD_t|RD_s,         I1      }, /* sllv */
                   1961: {"sll",     "d,w,<",   0x00000000, 0xffe0003f, WR_d|RD_t,              I1      },
                   1962: {"sll.ob",  "X,Y,Q",   0x78000010, 0xfc20003f, WR_D|RD_S|RD_T|FP_D,    MX|SB1  },
                   1963: {"sll.ob",  "D,S,T[e]",        0x48000010, 0xfe20003f, WR_D|RD_S|RD_T,         N54     },
                   1964: {"sll.ob",  "D,S,k",   0x4bc00010, 0xffe0003f, WR_D|RD_S|RD_T,         N54     },
                   1965: {"sll.qh",  "X,Y,Q",   0x78200010, 0xfc20003f, WR_D|RD_S|RD_T|FP_D,    MX      },
                   1966: {"slt",     "d,v,t",   0x0000002a, 0xfc0007ff, WR_d|RD_s|RD_t,         I1      },
                   1967: {"slt",     "d,v,I",   0,    (int) M_SLT_I,    INSN_MACRO,             I1      },
                   1968: {"slti",    "t,r,j",   0x28000000, 0xfc000000, WR_t|RD_s,              I1      },
                   1969: {"sltiu",   "t,r,j",   0x2c000000, 0xfc000000, WR_t|RD_s,              I1      },
                   1970: {"sltu",    "d,v,t",   0x0000002b, 0xfc0007ff, WR_d|RD_s|RD_t,         I1      },
                   1971: {"sltu",    "d,v,I",   0,    (int) M_SLTU_I,   INSN_MACRO,             I1      },
                   1972: {"sne",     "d,v,t",   0,    (int) M_SNE,      INSN_MACRO,             I1      },
                   1973: {"sne",     "d,v,I",   0,    (int) M_SNE_I,    INSN_MACRO,             I1      },
                   1974: {"sqrt.d",  "D,S",     0x46200004, 0xffff003f, WR_D|RD_S|FP_D,         I2      },
                   1975: {"sqrt.s",  "D,S",     0x46000004, 0xffff003f, WR_D|RD_S|FP_S,         I2      },
                   1976: {"sqrt.ps", "D,S",     0x46c00004, 0xffff003f, WR_D|RD_S|FP_D,         SB1     },
                   1977: {"srav",    "d,t,s",   0x00000007, 0xfc0007ff, WR_d|RD_t|RD_s,         I1      },
                   1978: {"sra",     "d,w,s",   0x00000007, 0xfc0007ff, WR_d|RD_t|RD_s,         I1      }, /* srav */
                   1979: {"sra",     "d,w,<",   0x00000003, 0xffe0003f, WR_d|RD_t,              I1      },
                   1980: {"sra.qh",  "X,Y,Q",   0x78200013, 0xfc20003f, WR_D|RD_S|RD_T|FP_D,    MX      },
                   1981: {"srlv",    "d,t,s",   0x00000006, 0xfc0007ff, WR_d|RD_t|RD_s,         I1      },
                   1982: {"srl",     "d,w,s",   0x00000006, 0xfc0007ff, WR_d|RD_t|RD_s,         I1      }, /* srlv */
                   1983: {"srl",     "d,w,<",   0x00000002, 0xffe0003f, WR_d|RD_t,              I1      },
                   1984: {"srl.ob",  "X,Y,Q",   0x78000012, 0xfc20003f, WR_D|RD_S|RD_T|FP_D,    MX|SB1  },
                   1985: {"srl.ob",  "D,S,T[e]",        0x48000012, 0xfe20003f, WR_D|RD_S|RD_T,         N54     },
                   1986: {"srl.ob",  "D,S,k",   0x4bc00012, 0xffe0003f, WR_D|RD_S|RD_T,         N54     },
                   1987: {"srl.qh",  "X,Y,Q",   0x78200012, 0xfc20003f, WR_D|RD_S|RD_T|FP_D,    MX      },
                   1988: /* ssnop is at the start of the table.  */
                   1989: {"standby", "",         0x42000021, 0xffffffff,        0,                      V1      },
                   1990: {"sub",     "d,v,t",   0x00000022, 0xfc0007ff, WR_d|RD_s|RD_t,         I1      },
                   1991: {"sub",     "d,v,I",   0,    (int) M_SUB_I,    INSN_MACRO,             I1      },
                   1992: {"sub.d",   "D,V,T",   0x46200001, 0xffe0003f, WR_D|RD_S|RD_T|FP_D,    I1      },
                   1993: {"sub.s",   "D,V,T",   0x46000001, 0xffe0003f, WR_D|RD_S|RD_T|FP_S,    I1      },
                   1994: {"sub.ob",  "X,Y,Q",   0x7800000a, 0xfc20003f, WR_D|RD_S|RD_T|FP_D,    MX|SB1  },
                   1995: {"sub.ob",  "D,S,T",   0x4ac0000a, 0xffe0003f, WR_D|RD_S|RD_T,         N54     },
                   1996: {"sub.ob",  "D,S,T[e]",        0x4800000a, 0xfe20003f, WR_D|RD_S|RD_T,         N54     },
                   1997: {"sub.ob",  "D,S,k",   0x4bc0000a, 0xffe0003f, WR_D|RD_S|RD_T,         N54     },
                   1998: {"sub.ps",  "D,V,T",   0x46c00001, 0xffe0003f, WR_D|RD_S|RD_T|FP_D,    I5      },
                   1999: {"sub.qh",  "X,Y,Q",   0x7820000a, 0xfc20003f, WR_D|RD_S|RD_T|FP_D,    MX      },
                   2000: {"suba.ob", "Y,Q",     0x78000036, 0xfc2007ff, WR_MACC|RD_S|RD_T|FP_D, MX|SB1  },
                   2001: {"suba.qh", "Y,Q",     0x78200036, 0xfc2007ff, WR_MACC|RD_S|RD_T|FP_D, MX      },
                   2002: {"subl.ob", "Y,Q",     0x78000436, 0xfc2007ff, WR_MACC|RD_S|RD_T|FP_D, MX|SB1  },
                   2003: {"subl.qh", "Y,Q",     0x78200436, 0xfc2007ff, WR_MACC|RD_S|RD_T|FP_D, MX      },
                   2004: {"subu",    "d,v,t",   0x00000023, 0xfc0007ff, WR_d|RD_s|RD_t,         I1      },
                   2005: {"subu",    "d,v,I",   0,    (int) M_SUBU_I,   INSN_MACRO,             I1      },
                   2006: {"suspend", "",         0x42000022, 0xffffffff,        0,                      V1      },
                   2007: {"suxc1",   "S,t(b)",   0x4c00000d, 0xfc0007ff, SM|RD_S|RD_t|RD_b,     I5|N55  },
                   2008: {"sw",      "t,o(b)",  0xac000000, 0xfc000000, SM|RD_t|RD_b,           I1      },
                   2009: {"sw",      "t,A(b)",  0,    (int) M_SW_AB,    INSN_MACRO,             I1      },
                   2010: {"swc0",    "E,o(b)",  0xe0000000, 0xfc000000, SM|RD_C0|RD_b,          I1      },
                   2011: {"swc0",    "E,A(b)",  0,    (int) M_SWC0_AB,  INSN_MACRO,             I1      },
                   2012: {"swc1",    "T,o(b)",  0xe4000000, 0xfc000000, SM|RD_T|RD_b|FP_S,      I1      },
                   2013: {"swc1",    "E,o(b)",  0xe4000000, 0xfc000000, SM|RD_T|RD_b|FP_S,      I1      },
                   2014: {"swc1",    "T,A(b)",  0,    (int) M_SWC1_AB,  INSN_MACRO,             I1      },
                   2015: {"swc1",    "E,A(b)",  0,    (int) M_SWC1_AB,  INSN_MACRO,             I1      },
                   2016: {"s.s",     "T,o(b)",  0xe4000000, 0xfc000000, SM|RD_T|RD_b|FP_S,      I1      }, /* swc1 */
                   2017: {"s.s",     "T,A(b)",  0,    (int) M_SWC1_AB,  INSN_MACRO,             I1      },
                   2018: {"swc2",    "E,o(b)",  0xe8000000, 0xfc000000, SM|RD_C2|RD_b,          I1      },
                   2019: {"swc2",    "E,A(b)",  0,    (int) M_SWC2_AB,  INSN_MACRO,             I1      },
                   2020: {"swc3",    "E,o(b)",  0xec000000, 0xfc000000, SM|RD_C3|RD_b,          I1      },
                   2021: {"swc3",    "E,A(b)",  0,    (int) M_SWC3_AB,  INSN_MACRO,             I1      },
                   2022: {"swl",     "t,o(b)",  0xa8000000, 0xfc000000, SM|RD_t|RD_b,           I1      },
                   2023: {"swl",     "t,A(b)",  0,    (int) M_SWL_AB,   INSN_MACRO,             I1      },
                   2024: {"scache",  "t,o(b)",  0xa8000000, 0xfc000000, RD_t|RD_b,              I2      }, /* same */
                   2025: {"scache",  "t,A(b)",  0,    (int) M_SWL_AB,   INSN_MACRO,             I2      }, /* as swl */
                   2026: {"swr",     "t,o(b)",  0xb8000000, 0xfc000000, SM|RD_t|RD_b,           I1      },
                   2027: {"swr",     "t,A(b)",  0,    (int) M_SWR_AB,   INSN_MACRO,             I1      },
                   2028: {"invalidate", "t,o(b)",0xb8000000, 0xfc000000,        RD_t|RD_b,              I2      }, /* same */
                   2029: {"invalidate", "t,A(b)",0,    (int) M_SWR_AB,  INSN_MACRO,             I2      }, /* as swr */
                   2030: {"swxc1",   "S,t(b)",   0x4c000008, 0xfc0007ff, SM|RD_S|RD_t|RD_b,     I4      },
                   2031: {"sync",    "",                0x0000000f, 0xffffffff, INSN_SYNC,              I2|G1   },
                   2032: {"sync.p",  "",                0x0000040f, 0xffffffff, INSN_SYNC,              I2      },
                   2033: {"sync.l",  "",                0x0000000f, 0xffffffff, INSN_SYNC,              I2      },
                   2034: {"synci",   "o(b)",    0x041f0000, 0xfc1f0000, SM|RD_b,                I33     },
                   2035: {"syscall", "",                0x0000000c, 0xffffffff, TRAP,                   I1      },
                   2036: {"syscall", "B",       0x0000000c, 0xfc00003f, TRAP,                   I1      },
                   2037: {"teqi",    "s,j",     0x040c0000, 0xfc1f0000, RD_s|TRAP,              I2      },
                   2038: {"teq",            "s,t",      0x00000034, 0xfc00ffff, RD_s|RD_t|TRAP,         I2      },
                   2039: {"teq",            "s,t,q",    0x00000034, 0xfc00003f, RD_s|RD_t|TRAP,         I2      },
                   2040: {"teq",     "s,j",     0x040c0000, 0xfc1f0000, RD_s|TRAP,              I2      }, /* teqi */
                   2041: {"teq",     "s,I",     0,    (int) M_TEQ_I,    INSN_MACRO,             I2      },
                   2042: {"tgei",    "s,j",     0x04080000, 0xfc1f0000, RD_s|TRAP,              I2      },
                   2043: {"tge",            "s,t",      0x00000030, 0xfc00ffff, RD_s|RD_t|TRAP,         I2      },
                   2044: {"tge",            "s,t,q",    0x00000030, 0xfc00003f, RD_s|RD_t|TRAP,         I2      },
                   2045: {"tge",     "s,j",     0x04080000, 0xfc1f0000, RD_s|TRAP,              I2      }, /* tgei */
                   2046: {"tge",            "s,I",      0,    (int) M_TGE_I,    INSN_MACRO,             I2      },
                   2047: {"tgeiu",   "s,j",     0x04090000, 0xfc1f0000, RD_s|TRAP,              I2      },
                   2048: {"tgeu",    "s,t",     0x00000031, 0xfc00ffff, RD_s|RD_t|TRAP,         I2      },
                   2049: {"tgeu",    "s,t,q",   0x00000031, 0xfc00003f, RD_s|RD_t|TRAP,         I2      },
                   2050: {"tgeu",    "s,j",     0x04090000, 0xfc1f0000, RD_s|TRAP,              I2      }, /* tgeiu */
                   2051: {"tgeu",    "s,I",     0,    (int) M_TGEU_I,   INSN_MACRO,             I2      },
                   2052: {"tlbp",    "",         0x42000008, 0xffffffff, INSN_TLB,              I1      },
                   2053: {"tlbr",    "",         0x42000001, 0xffffffff, INSN_TLB,              I1      },
                   2054: {"tlbwi",   "",         0x42000002, 0xffffffff, INSN_TLB,              I1      },
                   2055: {"tlbwr",   "",         0x42000006, 0xffffffff, INSN_TLB,              I1      },
                   2056: {"tlti",    "s,j",     0x040a0000, 0xfc1f0000, RD_s|TRAP,              I2      },
                   2057: {"tlt",     "s,t",     0x00000032, 0xfc00ffff, RD_s|RD_t|TRAP,         I2      },
                   2058: {"tlt",     "s,t,q",   0x00000032, 0xfc00003f, RD_s|RD_t|TRAP,         I2      },
                   2059: {"tlt",     "s,j",     0x040a0000, 0xfc1f0000, RD_s|TRAP,              I2      }, /* tlti */
                   2060: {"tlt",     "s,I",     0,    (int) M_TLT_I,    INSN_MACRO,             I2      },
                   2061: {"tltiu",   "s,j",     0x040b0000, 0xfc1f0000, RD_s|TRAP,              I2      },
                   2062: {"tltu",    "s,t",     0x00000033, 0xfc00ffff, RD_s|RD_t|TRAP,         I2      },
                   2063: {"tltu",    "s,t,q",   0x00000033, 0xfc00003f, RD_s|RD_t|TRAP,         I2      },
                   2064: {"tltu",    "s,j",     0x040b0000, 0xfc1f0000, RD_s|TRAP,              I2      }, /* tltiu */
                   2065: {"tltu",    "s,I",     0,    (int) M_TLTU_I,   INSN_MACRO,             I2      },
                   2066: {"tnei",    "s,j",     0x040e0000, 0xfc1f0000, RD_s|TRAP,              I2      },
                   2067: {"tne",     "s,t",     0x00000036, 0xfc00ffff, RD_s|RD_t|TRAP,         I2      },
                   2068: {"tne",     "s,t,q",   0x00000036, 0xfc00003f, RD_s|RD_t|TRAP,         I2      },
                   2069: {"tne",     "s,j",     0x040e0000, 0xfc1f0000, RD_s|TRAP,              I2      }, /* tnei */
                   2070: {"tne",     "s,I",     0,    (int) M_TNE_I,    INSN_MACRO,             I2      },
                   2071: {"trunc.l.d", "D,S",   0x46200009, 0xffff003f, WR_D|RD_S|FP_D,         I3      },
                   2072: {"trunc.l.s", "D,S",   0x46000009, 0xffff003f, WR_D|RD_S|FP_S,         I3      },
                   2073: {"trunc.w.d", "D,S",   0x4620000d, 0xffff003f, WR_D|RD_S|FP_D,         I2      },
                   2074: {"trunc.w.d", "D,S,x", 0x4620000d, 0xffff003f, WR_D|RD_S|FP_D,         I2      },
                   2075: {"trunc.w.d", "D,S,t", 0,    (int) M_TRUNCWD,  INSN_MACRO,             I1      },
                   2076: {"trunc.w.s", "D,S",   0x4600000d, 0xffff003f, WR_D|RD_S|FP_S,         I2      },
                   2077: {"trunc.w.s", "D,S,x", 0x4600000d, 0xffff003f, WR_D|RD_S|FP_S,         I2      },
                   2078: {"trunc.w.s", "D,S,t", 0,    (int) M_TRUNCWS,  INSN_MACRO,             I1      },
                   2079: {"uld",     "t,o(b)",  0,    (int) M_ULD,      INSN_MACRO,             I3      },
                   2080: {"uld",     "t,A(b)",  0,    (int) M_ULD_A,    INSN_MACRO,             I3      },
                   2081: {"ulh",     "t,o(b)",  0,    (int) M_ULH,      INSN_MACRO,             I1      },
                   2082: {"ulh",     "t,A(b)",  0,    (int) M_ULH_A,    INSN_MACRO,             I1      },
                   2083: {"ulhu",    "t,o(b)",  0,    (int) M_ULHU,     INSN_MACRO,             I1      },
                   2084: {"ulhu",    "t,A(b)",  0,    (int) M_ULHU_A,   INSN_MACRO,             I1      },
                   2085: {"ulw",     "t,o(b)",  0,    (int) M_ULW,      INSN_MACRO,             I1      },
                   2086: {"ulw",     "t,A(b)",  0,    (int) M_ULW_A,    INSN_MACRO,             I1      },
                   2087: {"usd",     "t,o(b)",  0,    (int) M_USD,      INSN_MACRO,             I3      },
                   2088: {"usd",     "t,A(b)",  0,    (int) M_USD_A,    INSN_MACRO,             I3      },
                   2089: {"ush",     "t,o(b)",  0,    (int) M_USH,      INSN_MACRO,             I1      },
                   2090: {"ush",     "t,A(b)",  0,    (int) M_USH_A,    INSN_MACRO,             I1      },
                   2091: {"usw",     "t,o(b)",  0,    (int) M_USW,      INSN_MACRO,             I1      },
                   2092: {"usw",     "t,A(b)",  0,    (int) M_USW_A,    INSN_MACRO,             I1      },
                   2093: {"wach.ob", "Y",       0x7a00003e, 0xffff07ff, WR_MACC|RD_S|FP_D,      MX|SB1  },
                   2094: {"wach.ob", "S",       0x4a00003e, 0xffff07ff, RD_S,                   N54     },
                   2095: {"wach.qh", "Y",       0x7a20003e, 0xffff07ff, WR_MACC|RD_S|FP_D,      MX      },
                   2096: {"wacl.ob", "Y,Z",     0x7800003e, 0xffe007ff, WR_MACC|RD_S|RD_T|FP_D, MX|SB1  },
                   2097: {"wacl.ob", "S,T",     0x4800003e, 0xffe007ff, RD_S|RD_T,              N54     },
                   2098: {"wacl.qh", "Y,Z",     0x7820003e, 0xffe007ff, WR_MACC|RD_S|RD_T|FP_D, MX      },
                   2099: {"wait",    "",         0x42000020, 0xffffffff, TRAP,                  I3|I32  },
                   2100: {"wait",    "J",        0x42000020, 0xfe00003f, TRAP,                  I32|N55 },
                   2101: {"waiti",   "",                0x42000020, 0xffffffff, TRAP,                   L1      },
                   2102: {"wb",             "o(b)",     0xbc040000, 0xfc1f0000, SM|RD_b,                L1      },
                   2103: {"wrpgpr",  "d,w",     0x41c00000, 0xffe007ff, RD_t,                   I33     },
                   2104: {"wsbh",    "d,w",     0x7c0000a0, 0xffe007ff, WR_d|RD_t,              I33     },
                   2105: {"xor",     "d,v,t",   0x00000026, 0xfc0007ff, WR_d|RD_s|RD_t,         I1      },
                   2106: {"xor",     "t,r,I",   0,    (int) M_XOR_I,    INSN_MACRO,             I1      },
                   2107: {"xor.ob",  "X,Y,Q",   0x7800000d, 0xfc20003f, WR_D|RD_S|RD_T|FP_D,    MX|SB1  },
                   2108: {"xor.ob",  "D,S,T",   0x4ac0000d, 0xffe0003f, WR_D|RD_S|RD_T,         N54     },
                   2109: {"xor.ob",  "D,S,T[e]",        0x4800000d, 0xfe20003f, WR_D|RD_S|RD_T,         N54     },
                   2110: {"xor.ob",  "D,S,k",   0x4bc0000d, 0xffe0003f, WR_D|RD_S|RD_T,         N54     },
                   2111: {"xor.qh",  "X,Y,Q",   0x7820000d, 0xfc20003f, WR_D|RD_S|RD_T|FP_D,    MX      },
                   2112: {"xori",    "t,r,i",   0x38000000, 0xfc000000, WR_t|RD_s,              I1      },
                   2113: 
                   2114: /* Coprocessor 2 move/branch operations overlap with VR5400 .ob format
                   2115:    instructions so they are here for the latters to take precedence.  */
                   2116: {"bc2f",    "p",       0x49000000, 0xffff0000, CBD|RD_CC,              I1      },
                   2117: {"bc2fl",   "p",       0x49020000, 0xffff0000, CBL|RD_CC,              I2|T3   },
                   2118: {"bc2t",    "p",       0x49010000, 0xffff0000, CBD|RD_CC,              I1      },
                   2119: {"bc2tl",   "p",       0x49030000, 0xffff0000, CBL|RD_CC,              I2|T3   },
                   2120: {"cfc2",    "t,G",     0x48400000, 0xffe007ff, LCD|WR_t|RD_C2,         I1      },
                   2121: {"ctc2",    "t,G",     0x48c00000, 0xffe007ff, COD|RD_t|WR_CC,         I1      },
                   2122: {"dmfc2",   "t,G",     0x48200000, 0xffe007ff, LCD|WR_t|RD_C2,         I3      },
                   2123: {"dmfc2",   "t,G,H",   0x48200000, 0xffe007f8, LCD|WR_t|RD_C2,         I64     },
                   2124: {"dmtc2",   "t,G",     0x48a00000, 0xffe007ff, COD|RD_t|WR_C2|WR_CC,   I3      },
                   2125: {"dmtc2",   "t,G,H",   0x48a00000, 0xffe007f8, COD|RD_t|WR_C2|WR_CC,   I64     },
                   2126: {"mfc2",    "t,G",     0x48000000, 0xffe007ff, LCD|WR_t|RD_C2,         I1      },
                   2127: {"mfc2",    "t,G,H",   0x48000000, 0xffe007f8, LCD|WR_t|RD_C2,         I32     },
                   2128: {"mfhc2",   "t,i",     0x48600000, 0xffe00000, LCD|WR_t|RD_C2,         I33     },
                   2129: {"mtc2",    "t,G",     0x48800000, 0xffe007ff, COD|RD_t|WR_C2|WR_CC,   I1      },
                   2130: {"mtc2",    "t,G,H",   0x48800000, 0xffe007f8, COD|RD_t|WR_C2|WR_CC,   I32     },
                   2131: {"mthc2",   "t,i",     0x48e00000, 0xffe00000, COD|RD_t|WR_C2|WR_CC,   I33     },
                   2132: 
                   2133: /* No hazard protection on coprocessor instructions--they shouldn't
                   2134:    change the state of the processor and if they do it's up to the
                   2135:    user to put in nops as necessary.  These are at the end so that the
                   2136:    disassembler recognizes more specific versions first.  */
                   2137: {"c0",      "C",       0x42000000, 0xfe000000, 0,                      I1      },
                   2138: {"c1",      "C",       0x46000000, 0xfe000000, 0,                      I1      },
                   2139: {"c2",      "C",       0x4a000000, 0xfe000000, 0,                      I1      },
                   2140: {"c3",      "C",       0x4e000000, 0xfe000000, 0,                      I1      },
                   2141: {"cop0",     "C",      0,    (int) M_COP0,     INSN_MACRO,             I1      },
                   2142: {"cop1",     "C",      0,    (int) M_COP1,     INSN_MACRO,             I1      },
                   2143: {"cop2",     "C",      0,    (int) M_COP2,     INSN_MACRO,             I1      },
                   2144: {"cop3",     "C",      0,    (int) M_COP3,     INSN_MACRO,             I1      },
                   2145: 
                   2146:   /* Conflicts with the 4650's "mul" instruction.  Nobody's using the
                   2147:      4010 any more, so move this insn out of the way.  If the object
                   2148:      format gave us more info, we could do this right.  */
                   2149: {"addciu",  "t,r,j",   0x70000000, 0xfc000000, WR_t|RD_s,              L1      },
                   2150: };
                   2151: 
                   2152: #define MIPS_NUM_OPCODES \
                   2153:        ((sizeof mips_builtin_opcodes) / (sizeof (mips_builtin_opcodes[0])))
                   2154: const int bfd_mips_num_builtin_opcodes = MIPS_NUM_OPCODES;
                   2155: 
                   2156: /* const removed from the following to allow for dynamic extensions to the
                   2157:  * built-in instruction set. */
                   2158: struct mips_opcode *mips_opcodes =
                   2159:   (struct mips_opcode *) mips_builtin_opcodes;
                   2160: int bfd_mips_num_opcodes = MIPS_NUM_OPCODES;
                   2161: #undef MIPS_NUM_OPCODES
                   2162: 
                   2163: /* Mips instructions are at maximum this many bytes long.  */
                   2164: #define INSNLEN 4
                   2165: 
                   2166: static void set_default_mips_dis_options
                   2167:   PARAMS ((struct disassemble_info *));
                   2168: static void parse_mips_dis_option
                   2169:   PARAMS ((const char *, unsigned int));
                   2170: static void parse_mips_dis_options
                   2171:   PARAMS ((const char *));
                   2172: static int _print_insn_mips
                   2173:   PARAMS ((bfd_vma, struct disassemble_info *, enum bfd_endian));
                   2174: static int print_insn_mips
                   2175:   PARAMS ((bfd_vma, unsigned long int, struct disassemble_info *));
                   2176: static void print_insn_args
                   2177:   PARAMS ((const char *, unsigned long, bfd_vma, struct disassemble_info *));
                   2178: #if 0
                   2179: static int print_insn_mips16
                   2180:   PARAMS ((bfd_vma, struct disassemble_info *));
                   2181: #endif
                   2182: #if 0
                   2183: static int is_newabi
                   2184:   PARAMS ((Elf32_Ehdr *));
                   2185: #endif
                   2186: #if 0
                   2187: static void print_mips16_insn_arg
                   2188:   PARAMS ((int, const struct mips_opcode *, int, bfd_boolean, int, bfd_vma,
                   2189:           struct disassemble_info *));
                   2190: #endif
                   2191: 
                   2192: /* FIXME: These should be shared with gdb somehow.  */
                   2193: 
                   2194: struct mips_cp0sel_name {
                   2195:        unsigned int cp0reg;
                   2196:        unsigned int sel;
                   2197:        const char * const name;
                   2198: };
                   2199: 
                   2200: /* The mips16 register names.  */
                   2201: static const char * const mips16_reg_names[] = {
                   2202:   "s0", "s1", "v0", "v1", "a0", "a1", "a2", "a3"
                   2203: };
                   2204: 
                   2205: static const char * const mips_gpr_names_numeric[32] = {
                   2206:   "$0",   "$1",   "$2",   "$3",   "$4",   "$5",   "$6",   "$7",
                   2207:   "$8",   "$9",   "$10",  "$11",  "$12",  "$13",  "$14",  "$15",
                   2208:   "$16",  "$17",  "$18",  "$19",  "$20",  "$21",  "$22",  "$23",
                   2209:   "$24",  "$25",  "$26",  "$27",  "$28",  "$29",  "$30",  "$31"
                   2210: };
                   2211: 
                   2212: static const char * const mips_gpr_names_oldabi[32] = {
                   2213:   "zero", "at",   "v0",   "v1",   "a0",   "a1",   "a2",   "a3",
                   2214:   "t0",   "t1",   "t2",   "t3",   "t4",   "t5",   "t6",   "t7",
                   2215:   "s0",   "s1",   "s2",   "s3",   "s4",   "s5",   "s6",   "s7",
                   2216:   "t8",   "t9",   "k0",   "k1",   "gp",   "sp",   "s8",   "ra"
                   2217: };
                   2218: 
                   2219: static const char * const mips_gpr_names_newabi[32] = {
                   2220:   "zero", "at",   "v0",   "v1",   "a0",   "a1",   "a2",   "a3",
                   2221:   "a4",   "a5",   "a6",   "a7",   "t0",   "t1",   "t2",   "t3",
                   2222:   "s0",   "s1",   "s2",   "s3",   "s4",   "s5",   "s6",   "s7",
                   2223:   "t8",   "t9",   "k0",   "k1",   "gp",   "sp",   "s8",   "ra"
                   2224: };
                   2225: 
                   2226: static const char * const mips_fpr_names_numeric[32] = {
                   2227:   "$f0",  "$f1",  "$f2",  "$f3",  "$f4",  "$f5",  "$f6",  "$f7",
                   2228:   "$f8",  "$f9",  "$f10", "$f11", "$f12", "$f13", "$f14", "$f15",
                   2229:   "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23",
                   2230:   "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31"
                   2231: };
                   2232: 
                   2233: static const char * const mips_fpr_names_32[32] = {
                   2234:   "fv0",  "fv0f", "fv1",  "fv1f", "ft0",  "ft0f", "ft1",  "ft1f",
                   2235:   "ft2",  "ft2f", "ft3",  "ft3f", "fa0",  "fa0f", "fa1",  "fa1f",
                   2236:   "ft4",  "ft4f", "ft5",  "ft5f", "fs0",  "fs0f", "fs1",  "fs1f",
                   2237:   "fs2",  "fs2f", "fs3",  "fs3f", "fs4",  "fs4f", "fs5",  "fs5f"
                   2238: };
                   2239: 
                   2240: static const char * const mips_fpr_names_n32[32] = {
                   2241:   "fv0",  "ft14", "fv1",  "ft15", "ft0",  "ft1",  "ft2",  "ft3",
                   2242:   "ft4",  "ft5",  "ft6",  "ft7",  "fa0",  "fa1",  "fa2",  "fa3",
                   2243:   "fa4",  "fa5",  "fa6",  "fa7",  "fs0",  "ft8",  "fs1",  "ft9",
                   2244:   "fs2",  "ft10", "fs3",  "ft11", "fs4",  "ft12", "fs5",  "ft13"
                   2245: };
                   2246: 
                   2247: static const char * const mips_fpr_names_64[32] = {
                   2248:   "fv0",  "ft12", "fv1",  "ft13", "ft0",  "ft1",  "ft2",  "ft3",
                   2249:   "ft4",  "ft5",  "ft6",  "ft7",  "fa0",  "fa1",  "fa2",  "fa3",
                   2250:   "fa4",  "fa5",  "fa6",  "fa7",  "ft8",  "ft9",  "ft10", "ft11",
                   2251:   "fs0",  "fs1",  "fs2",  "fs3",  "fs4",  "fs5",  "fs6",  "fs7"
                   2252: };
                   2253: 
                   2254: static const char * const mips_cp0_names_numeric[32] = {
                   2255:   "$0",   "$1",   "$2",   "$3",   "$4",   "$5",   "$6",   "$7",
                   2256:   "$8",   "$9",   "$10",  "$11",  "$12",  "$13",  "$14",  "$15",
                   2257:   "$16",  "$17",  "$18",  "$19",  "$20",  "$21",  "$22",  "$23",
                   2258:   "$24",  "$25",  "$26",  "$27",  "$28",  "$29",  "$30",  "$31"
                   2259: };
                   2260: 
                   2261: static const char * const mips_cp0_names_mips3264[32] = {
                   2262:   "c0_index",     "c0_random",    "c0_entrylo0",  "c0_entrylo1",
                   2263:   "c0_context",   "c0_pagemask",  "c0_wired",     "$7",
                   2264:   "c0_badvaddr",  "c0_count",     "c0_entryhi",   "c0_compare",
                   2265:   "c0_status",    "c0_cause",     "c0_epc",       "c0_prid",
                   2266:   "c0_config",    "c0_lladdr",    "c0_watchlo",   "c0_watchhi",
                   2267:   "c0_xcontext",  "$21",          "$22",          "c0_debug",
                   2268:   "c0_depc",      "c0_perfcnt",   "c0_errctl",    "c0_cacheerr",
                   2269:   "c0_taglo",     "c0_taghi",     "c0_errorepc",  "c0_desave",
                   2270: };
                   2271: 
                   2272: static const struct mips_cp0sel_name mips_cp0sel_names_mips3264[] = {
                   2273:   { 16, 1, "c0_config1"                },
                   2274:   { 16, 2, "c0_config2"                },
                   2275:   { 16, 3, "c0_config3"                },
                   2276:   { 18, 1, "c0_watchlo,1"      },
                   2277:   { 18, 2, "c0_watchlo,2"      },
                   2278:   { 18, 3, "c0_watchlo,3"      },
                   2279:   { 18, 4, "c0_watchlo,4"      },
                   2280:   { 18, 5, "c0_watchlo,5"      },
                   2281:   { 18, 6, "c0_watchlo,6"      },
                   2282:   { 18, 7, "c0_watchlo,7"      },
                   2283:   { 19, 1, "c0_watchhi,1"      },
                   2284:   { 19, 2, "c0_watchhi,2"      },
                   2285:   { 19, 3, "c0_watchhi,3"      },
                   2286:   { 19, 4, "c0_watchhi,4"      },
                   2287:   { 19, 5, "c0_watchhi,5"      },
                   2288:   { 19, 6, "c0_watchhi,6"      },
                   2289:   { 19, 7, "c0_watchhi,7"      },
                   2290:   { 25, 1, "c0_perfcnt,1"      },
                   2291:   { 25, 2, "c0_perfcnt,2"      },
                   2292:   { 25, 3, "c0_perfcnt,3"      },
                   2293:   { 25, 4, "c0_perfcnt,4"      },
                   2294:   { 25, 5, "c0_perfcnt,5"      },
                   2295:   { 25, 6, "c0_perfcnt,6"      },
                   2296:   { 25, 7, "c0_perfcnt,7"      },
                   2297:   { 27, 1, "c0_cacheerr,1"     },
                   2298:   { 27, 2, "c0_cacheerr,2"     },
                   2299:   { 27, 3, "c0_cacheerr,3"     },
                   2300:   { 28, 1, "c0_datalo"         },
                   2301:   { 29, 1, "c0_datahi"         }
                   2302: };
                   2303: 
                   2304: static const char * const mips_cp0_names_mips3264r2[32] = {
                   2305:   "c0_index",     "c0_random",    "c0_entrylo0",  "c0_entrylo1",
                   2306:   "c0_context",   "c0_pagemask",  "c0_wired",     "c0_hwrena",
                   2307:   "c0_badvaddr",  "c0_count",     "c0_entryhi",   "c0_compare",
                   2308:   "c0_status",    "c0_cause",     "c0_epc",       "c0_prid",
                   2309:   "c0_config",    "c0_lladdr",    "c0_watchlo",   "c0_watchhi",
                   2310:   "c0_xcontext",  "$21",          "$22",          "c0_debug",
                   2311:   "c0_depc",      "c0_perfcnt",   "c0_errctl",    "c0_cacheerr",
                   2312:   "c0_taglo",     "c0_taghi",     "c0_errorepc",  "c0_desave",
                   2313: };
                   2314: 
                   2315: static const struct mips_cp0sel_name mips_cp0sel_names_mips3264r2[] = {
                   2316:   {  4, 1, "c0_contextconfig"  },
                   2317:   {  5, 1, "c0_pagegrain"      },
                   2318:   { 12, 1, "c0_intctl"         },
                   2319:   { 12, 2, "c0_srsctl"         },
                   2320:   { 12, 3, "c0_srsmap"         },
                   2321:   { 15, 1, "c0_ebase"          },
                   2322:   { 16, 1, "c0_config1"                },
                   2323:   { 16, 2, "c0_config2"                },
                   2324:   { 16, 3, "c0_config3"                },
                   2325:   { 18, 1, "c0_watchlo,1"      },
                   2326:   { 18, 2, "c0_watchlo,2"      },
                   2327:   { 18, 3, "c0_watchlo,3"      },
                   2328:   { 18, 4, "c0_watchlo,4"      },
                   2329:   { 18, 5, "c0_watchlo,5"      },
                   2330:   { 18, 6, "c0_watchlo,6"      },
                   2331:   { 18, 7, "c0_watchlo,7"      },
                   2332:   { 19, 1, "c0_watchhi,1"      },
                   2333:   { 19, 2, "c0_watchhi,2"      },
                   2334:   { 19, 3, "c0_watchhi,3"      },
                   2335:   { 19, 4, "c0_watchhi,4"      },
                   2336:   { 19, 5, "c0_watchhi,5"      },
                   2337:   { 19, 6, "c0_watchhi,6"      },
                   2338:   { 19, 7, "c0_watchhi,7"      },
                   2339:   { 23, 1, "c0_tracecontrol"   },
                   2340:   { 23, 2, "c0_tracecontrol2"  },
                   2341:   { 23, 3, "c0_usertracedata"  },
                   2342:   { 23, 4, "c0_tracebpc"       },
                   2343:   { 25, 1, "c0_perfcnt,1"      },
                   2344:   { 25, 2, "c0_perfcnt,2"      },
                   2345:   { 25, 3, "c0_perfcnt,3"      },
                   2346:   { 25, 4, "c0_perfcnt,4"      },
                   2347:   { 25, 5, "c0_perfcnt,5"      },
                   2348:   { 25, 6, "c0_perfcnt,6"      },
                   2349:   { 25, 7, "c0_perfcnt,7"      },
                   2350:   { 27, 1, "c0_cacheerr,1"     },
                   2351:   { 27, 2, "c0_cacheerr,2"     },
                   2352:   { 27, 3, "c0_cacheerr,3"     },
                   2353:   { 28, 1, "c0_datalo"         },
                   2354:   { 28, 2, "c0_taglo1"         },
                   2355:   { 28, 3, "c0_datalo1"                },
                   2356:   { 28, 4, "c0_taglo2"         },
                   2357:   { 28, 5, "c0_datalo2"                },
                   2358:   { 28, 6, "c0_taglo3"         },
                   2359:   { 28, 7, "c0_datalo3"                },
                   2360:   { 29, 1, "c0_datahi"         },
                   2361:   { 29, 2, "c0_taghi1"         },
                   2362:   { 29, 3, "c0_datahi1"                },
                   2363:   { 29, 4, "c0_taghi2"         },
                   2364:   { 29, 5, "c0_datahi2"                },
                   2365:   { 29, 6, "c0_taghi3"         },
                   2366:   { 29, 7, "c0_datahi3"                },
                   2367: };
                   2368: 
                   2369: /* SB-1: MIPS64 (mips_cp0_names_mips3264) with minor mods.  */
                   2370: static const char * const mips_cp0_names_sb1[32] = {
                   2371:   "c0_index",     "c0_random",    "c0_entrylo0",  "c0_entrylo1",
                   2372:   "c0_context",   "c0_pagemask",  "c0_wired",     "$7",
                   2373:   "c0_badvaddr",  "c0_count",     "c0_entryhi",   "c0_compare",
                   2374:   "c0_status",    "c0_cause",     "c0_epc",       "c0_prid",
                   2375:   "c0_config",    "c0_lladdr",    "c0_watchlo",   "c0_watchhi",
                   2376:   "c0_xcontext",  "$21",          "$22",          "c0_debug",
                   2377:   "c0_depc",      "c0_perfcnt",   "c0_errctl",    "c0_cacheerr_i",
                   2378:   "c0_taglo_i",   "c0_taghi_i",   "c0_errorepc",  "c0_desave",
                   2379: };
                   2380: 
                   2381: static const struct mips_cp0sel_name mips_cp0sel_names_sb1[] = {
                   2382:   { 16, 1, "c0_config1"                },
                   2383:   { 18, 1, "c0_watchlo,1"      },
                   2384:   { 19, 1, "c0_watchhi,1"      },
                   2385:   { 22, 0, "c0_perftrace"      },
                   2386:   { 23, 3, "c0_edebug"         },
                   2387:   { 25, 1, "c0_perfcnt,1"      },
                   2388:   { 25, 2, "c0_perfcnt,2"      },
                   2389:   { 25, 3, "c0_perfcnt,3"      },
                   2390:   { 25, 4, "c0_perfcnt,4"      },
                   2391:   { 25, 5, "c0_perfcnt,5"      },
                   2392:   { 25, 6, "c0_perfcnt,6"      },
                   2393:   { 25, 7, "c0_perfcnt,7"      },
                   2394:   { 26, 1, "c0_buserr_pa"      },
                   2395:   { 27, 1, "c0_cacheerr_d"     },
                   2396:   { 27, 3, "c0_cacheerr_d_pa"  },
                   2397:   { 28, 1, "c0_datalo_i"       },
                   2398:   { 28, 2, "c0_taglo_d"                },
                   2399:   { 28, 3, "c0_datalo_d"       },
                   2400:   { 29, 1, "c0_datahi_i"       },
                   2401:   { 29, 2, "c0_taghi_d"                },
                   2402:   { 29, 3, "c0_datahi_d"       },
                   2403: };
                   2404: 
                   2405: static const char * const mips_hwr_names_numeric[32] = {
                   2406:   "$0",   "$1",   "$2",   "$3",   "$4",   "$5",   "$6",   "$7",
                   2407:   "$8",   "$9",   "$10",  "$11",  "$12",  "$13",  "$14",  "$15",
                   2408:   "$16",  "$17",  "$18",  "$19",  "$20",  "$21",  "$22",  "$23",
                   2409:   "$24",  "$25",  "$26",  "$27",  "$28",  "$29",  "$30",  "$31"
                   2410: };
                   2411: 
                   2412: static const char * const mips_hwr_names_mips3264r2[32] = {
                   2413:   "hwr_cpunum",   "hwr_synci_step", "hwr_cc",     "hwr_ccres",
                   2414:   "$4",          "$5",            "$6",           "$7",
                   2415:   "$8",   "$9",   "$10",  "$11",  "$12",  "$13",  "$14",  "$15",
                   2416:   "$16",  "$17",  "$18",  "$19",  "$20",  "$21",  "$22",  "$23",
                   2417:   "$24",  "$25",  "$26",  "$27",  "$28",  "$29",  "$30",  "$31"
                   2418: };
                   2419: 
                   2420: struct mips_abi_choice {
                   2421:   const char *name;
                   2422:   const char * const *gpr_names;
                   2423:   const char * const *fpr_names;
                   2424: };
                   2425: 
                   2426: struct mips_abi_choice mips_abi_choices[] = {
                   2427:   { "numeric", mips_gpr_names_numeric, mips_fpr_names_numeric },
                   2428:   { "32", mips_gpr_names_oldabi, mips_fpr_names_32 },
                   2429:   { "n32", mips_gpr_names_newabi, mips_fpr_names_n32 },
                   2430:   { "64", mips_gpr_names_newabi, mips_fpr_names_64 },
                   2431: };
                   2432: 
                   2433: struct mips_arch_choice {
                   2434:   const char *name;
                   2435:   int bfd_mach_valid;
                   2436:   unsigned long bfd_mach;
                   2437:   int processor;
                   2438:   int isa;
                   2439:   const char * const *cp0_names;
                   2440:   const struct mips_cp0sel_name *cp0sel_names;
                   2441:   unsigned int cp0sel_names_len;
                   2442:   const char * const *hwr_names;
                   2443: };
                   2444: 
                   2445: #define bfd_mach_mips3000              3000
                   2446: #define bfd_mach_mips3900              3900
                   2447: #define bfd_mach_mips4000              4000
                   2448: #define bfd_mach_mips4010              4010
                   2449: #define bfd_mach_mips4100              4100
                   2450: #define bfd_mach_mips4111              4111
                   2451: #define bfd_mach_mips4120              4120
                   2452: #define bfd_mach_mips4300              4300
                   2453: #define bfd_mach_mips4400              4400
                   2454: #define bfd_mach_mips4600              4600
                   2455: #define bfd_mach_mips4650              4650
                   2456: #define bfd_mach_mips5000              5000
                   2457: #define bfd_mach_mips5400              5400
                   2458: #define bfd_mach_mips5500              5500
                   2459: #define bfd_mach_mips6000              6000
                   2460: #define bfd_mach_mips7000              7000
                   2461: #define bfd_mach_mips8000              8000
                   2462: #define bfd_mach_mips10000             10000
                   2463: #define bfd_mach_mips12000             12000
                   2464: #define bfd_mach_mips16                16
                   2465: #define bfd_mach_mips5                 5
                   2466: #define bfd_mach_mips_sb1              12310201 /* octal 'SB', 01 */
                   2467: #define bfd_mach_mipsisa32             32
                   2468: #define bfd_mach_mipsisa32r2           33
                   2469: #define bfd_mach_mipsisa64             64
                   2470: #define bfd_mach_mipsisa64r2           65
                   2471: 
                   2472: #define ARRAY_SIZE(a) (sizeof(a) / sizeof(a[0]))
                   2473: 
                   2474: const struct mips_arch_choice mips_arch_choices[] = {
                   2475:   { "numeric", 0, 0, 0, 0,
                   2476:     mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
                   2477: 
                   2478:   { "r3000",   1, bfd_mach_mips3000, CPU_R3000, ISA_MIPS1,
                   2479:     mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
                   2480:   { "r3900",   1, bfd_mach_mips3900, CPU_R3900, ISA_MIPS1,
                   2481:     mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
                   2482:   { "r4000",   1, bfd_mach_mips4000, CPU_R4000, ISA_MIPS3,
                   2483:     mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
                   2484:   { "r4010",   1, bfd_mach_mips4010, CPU_R4010, ISA_MIPS2,
                   2485:     mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
                   2486:   { "vr4100",  1, bfd_mach_mips4100, CPU_VR4100, ISA_MIPS3,
                   2487:     mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
                   2488:   { "vr4111",  1, bfd_mach_mips4111, CPU_R4111, ISA_MIPS3,
                   2489:     mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
                   2490:   { "vr4120",  1, bfd_mach_mips4120, CPU_VR4120, ISA_MIPS3,
                   2491:     mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
                   2492:   { "r4300",   1, bfd_mach_mips4300, CPU_R4300, ISA_MIPS3,
                   2493:     mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
                   2494:   { "r4400",   1, bfd_mach_mips4400, CPU_R4400, ISA_MIPS3,
                   2495:     mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
                   2496:   { "r4600",   1, bfd_mach_mips4600, CPU_R4600, ISA_MIPS3,
                   2497:     mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
                   2498:   { "r4650",   1, bfd_mach_mips4650, CPU_R4650, ISA_MIPS3,
                   2499:     mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
                   2500:   { "r5000",   1, bfd_mach_mips5000, CPU_R5000, ISA_MIPS4,
                   2501:     mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
                   2502:   { "vr5400",  1, bfd_mach_mips5400, CPU_VR5400, ISA_MIPS4,
                   2503:     mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
                   2504:   { "vr5500",  1, bfd_mach_mips5500, CPU_VR5500, ISA_MIPS4,
                   2505:     mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
                   2506:   { "r6000",   1, bfd_mach_mips6000, CPU_R6000, ISA_MIPS2,
                   2507:     mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
                   2508:   { "rm7000",  1, bfd_mach_mips7000, CPU_RM7000, ISA_MIPS4,
                   2509:     mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
                   2510:   { "rm9000",  1, bfd_mach_mips7000, CPU_RM7000, ISA_MIPS4,
                   2511:     mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
                   2512:   { "r8000",   1, bfd_mach_mips8000, CPU_R8000, ISA_MIPS4,
                   2513:     mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
                   2514:   { "r10000",  1, bfd_mach_mips10000, CPU_R10000, ISA_MIPS4,
                   2515:     mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
                   2516:   { "r12000",  1, bfd_mach_mips12000, CPU_R12000, ISA_MIPS4,
                   2517:     mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
                   2518:   { "mips5",   1, bfd_mach_mips5, CPU_MIPS5, ISA_MIPS5,
                   2519:     mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
                   2520: 
                   2521:   /* For stock MIPS32, disassemble all applicable MIPS-specified ASEs.
                   2522:      Note that MIPS-3D and MDMX are not applicable to MIPS32.  (See
                   2523:      _MIPS32 Architecture For Programmers Volume I: Introduction to the
                   2524:      MIPS32 Architecture_ (MIPS Document Number MD00082, Revision 0.95),
                   2525:      page 1.  */
                   2526:   { "mips32",  1, bfd_mach_mipsisa32, CPU_MIPS32,
                   2527:     ISA_MIPS32 | INSN_MIPS16,
                   2528:     mips_cp0_names_mips3264,
                   2529:     mips_cp0sel_names_mips3264, ARRAY_SIZE (mips_cp0sel_names_mips3264),
                   2530:     mips_hwr_names_numeric },
                   2531: 
                   2532:   { "mips32r2",        1, bfd_mach_mipsisa32r2, CPU_MIPS32R2,
                   2533:     ISA_MIPS32R2 | INSN_MIPS16,
                   2534:     mips_cp0_names_mips3264r2,
                   2535:     mips_cp0sel_names_mips3264r2, ARRAY_SIZE (mips_cp0sel_names_mips3264r2),
                   2536:     mips_hwr_names_mips3264r2 },
                   2537: 
                   2538:   /* For stock MIPS64, disassemble all applicable MIPS-specified ASEs.  */
                   2539:   { "mips64",  1, bfd_mach_mipsisa64, CPU_MIPS64,
                   2540:     ISA_MIPS64 | INSN_MIPS16 | INSN_MIPS3D | INSN_MDMX,
                   2541:     mips_cp0_names_mips3264,
                   2542:     mips_cp0sel_names_mips3264, ARRAY_SIZE (mips_cp0sel_names_mips3264),
                   2543:     mips_hwr_names_numeric },
                   2544: 
                   2545:   { "mips64r2",        1, bfd_mach_mipsisa64r2, CPU_MIPS64R2,
                   2546:     ISA_MIPS64R2 | INSN_MIPS16 | INSN_MIPS3D | INSN_MDMX,
                   2547:     mips_cp0_names_mips3264r2,
                   2548:     mips_cp0sel_names_mips3264r2, ARRAY_SIZE (mips_cp0sel_names_mips3264r2),
                   2549:     mips_hwr_names_mips3264r2 },
                   2550: 
                   2551:   { "sb1",     1, bfd_mach_mips_sb1, CPU_SB1,
                   2552:     ISA_MIPS64 | INSN_MIPS3D | INSN_SB1,
                   2553:     mips_cp0_names_sb1,
                   2554:     mips_cp0sel_names_sb1, ARRAY_SIZE (mips_cp0sel_names_sb1),
                   2555:     mips_hwr_names_numeric },
                   2556: 
                   2557:   /* This entry, mips16, is here only for ISA/processor selection; do
                   2558:      not print its name.  */
                   2559:   { "",                1, bfd_mach_mips16, CPU_MIPS16, ISA_MIPS3 | INSN_MIPS16,
                   2560:     mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
                   2561: };
                   2562: 
                   2563: /* ISA and processor type to disassemble for, and register names to use.
                   2564:    set_default_mips_dis_options and parse_mips_dis_options fill in these
                   2565:    values.  */
                   2566: static int mips_processor;
                   2567: static int mips_isa;
                   2568: static const char * const *mips_gpr_names;
                   2569: static const char * const *mips_fpr_names;
                   2570: static const char * const *mips_cp0_names;
                   2571: static const struct mips_cp0sel_name *mips_cp0sel_names;
                   2572: static int mips_cp0sel_names_len;
                   2573: static const char * const *mips_hwr_names;
                   2574: 
                   2575: static const struct mips_abi_choice *choose_abi_by_name
                   2576:   PARAMS ((const char *, unsigned int));
                   2577: static const struct mips_arch_choice *choose_arch_by_name
                   2578:   PARAMS ((const char *, unsigned int));
                   2579: static const struct mips_arch_choice *choose_arch_by_number
                   2580:   PARAMS ((unsigned long));
                   2581: static const struct mips_cp0sel_name *lookup_mips_cp0sel_name
                   2582:   PARAMS ((const struct mips_cp0sel_name *, unsigned int, unsigned int,
                   2583:           unsigned int));
                   2584: 
                   2585: static const struct mips_abi_choice *
                   2586: choose_abi_by_name (name, namelen)
                   2587:      const char *name;
                   2588:      unsigned int namelen;
                   2589: {
                   2590:   const struct mips_abi_choice *c;
                   2591:   unsigned int i;
                   2592: 
                   2593:   for (i = 0, c = NULL; i < ARRAY_SIZE (mips_abi_choices) && c == NULL; i++)
                   2594:     {
                   2595:       if (strncmp (mips_abi_choices[i].name, name, namelen) == 0
                   2596:          && strlen (mips_abi_choices[i].name) == namelen)
                   2597:        c = &mips_abi_choices[i];
                   2598:     }
                   2599:   return c;
                   2600: }
                   2601: 
                   2602: static const struct mips_arch_choice *
                   2603: choose_arch_by_name (name, namelen)
                   2604:      const char *name;
                   2605:      unsigned int namelen;
                   2606: {
                   2607:   const struct mips_arch_choice *c = NULL;
                   2608:   unsigned int i;
                   2609: 
                   2610:   for (i = 0, c = NULL; i < ARRAY_SIZE (mips_arch_choices) && c == NULL; i++)
                   2611:     {
                   2612:       if (strncmp (mips_arch_choices[i].name, name, namelen) == 0
                   2613:          && strlen (mips_arch_choices[i].name) == namelen)
                   2614:        c = &mips_arch_choices[i];
                   2615:     }
                   2616:   return c;
                   2617: }
                   2618: 
                   2619: static const struct mips_arch_choice *
                   2620: choose_arch_by_number (mach)
                   2621:      unsigned long mach;
                   2622: {
                   2623:   static unsigned long hint_bfd_mach;
                   2624:   static const struct mips_arch_choice *hint_arch_choice;
                   2625:   const struct mips_arch_choice *c;
                   2626:   unsigned int i;
                   2627: 
                   2628:   /* We optimize this because even if the user specifies no
                   2629:      flags, this will be done for every instruction!  */
                   2630:   if (hint_bfd_mach == mach
                   2631:       && hint_arch_choice != NULL
                   2632:       && hint_arch_choice->bfd_mach == hint_bfd_mach)
                   2633:     return hint_arch_choice;
                   2634: 
                   2635:   for (i = 0, c = NULL; i < ARRAY_SIZE (mips_arch_choices) && c == NULL; i++)
                   2636:     {
                   2637:       if (mips_arch_choices[i].bfd_mach_valid
                   2638:          && mips_arch_choices[i].bfd_mach == mach)
                   2639:        {
                   2640:          c = &mips_arch_choices[i];
                   2641:          hint_bfd_mach = mach;
                   2642:          hint_arch_choice = c;
                   2643:        }
                   2644:     }
                   2645:   return c;
                   2646: }
                   2647: 
                   2648: void
                   2649: set_default_mips_dis_options (info)
                   2650:      struct disassemble_info *info;
                   2651: {
                   2652:   const struct mips_arch_choice *chosen_arch;
                   2653: 
                   2654:   /* Defaults: mipsIII/r3000 (?!), (o)32-style ("oldabi") GPR names,
                   2655:      and numeric FPR, CP0 register, and HWR names.  */
                   2656:   mips_isa = ISA_MIPS3;
                   2657:   mips_processor =  CPU_R3000;
                   2658:   mips_gpr_names = mips_gpr_names_oldabi;
                   2659:   mips_fpr_names = mips_fpr_names_numeric;
                   2660:   mips_cp0_names = mips_cp0_names_numeric;
                   2661:   mips_cp0sel_names = NULL;
                   2662:   mips_cp0sel_names_len = 0;
                   2663:   mips_hwr_names = mips_hwr_names_numeric;
                   2664: 
                   2665:   /* If an ELF "newabi" binary, use the n32/(n)64 GPR names.  */
                   2666: #if 0
                   2667:   if (info->flavour == bfd_target_elf_flavour && info->section != NULL)
                   2668:     {
                   2669:       Elf_Internal_Ehdr *header;
                   2670: 
                   2671:       header = elf_elfheader (info->section->owner);
                   2672:       if (is_newabi (header))
                   2673:        mips_gpr_names = mips_gpr_names_newabi;
                   2674:     }
                   2675: #endif
                   2676: 
                   2677:   /* Set ISA, architecture, and cp0 register names as best we can.  */
                   2678: #if ! SYMTAB_AVAILABLE && 0
                   2679:   /* This is running out on a target machine, not in a host tool.
                   2680:      FIXME: Where does mips_target_info come from?  */
                   2681:   target_processor = mips_target_info.processor;
                   2682:   mips_isa = mips_target_info.isa;
                   2683: #else
                   2684:   chosen_arch = choose_arch_by_number (info->mach);
                   2685:   if (chosen_arch != NULL)
                   2686:     {
                   2687:       mips_processor = chosen_arch->processor;
                   2688:       mips_isa = chosen_arch->isa;
                   2689:       mips_cp0_names = chosen_arch->cp0_names;
                   2690:       mips_cp0sel_names = chosen_arch->cp0sel_names;
                   2691:       mips_cp0sel_names_len = chosen_arch->cp0sel_names_len;
                   2692:       mips_hwr_names = chosen_arch->hwr_names;
                   2693:     }
                   2694: #endif
                   2695: }
                   2696: 
                   2697: void
                   2698: parse_mips_dis_option (option, len)
                   2699:      const char *option;
                   2700:      unsigned int len;
                   2701: {
                   2702:   unsigned int i, optionlen, vallen;
                   2703:   const char *val;
                   2704:   const struct mips_abi_choice *chosen_abi;
                   2705:   const struct mips_arch_choice *chosen_arch;
                   2706: 
                   2707:   /* Look for the = that delimits the end of the option name.  */
                   2708:   for (i = 0; i < len; i++)
                   2709:     {
                   2710:       if (option[i] == '=')
                   2711:        break;
                   2712:     }
                   2713:   if (i == 0)          /* Invalid option: no name before '='.  */
                   2714:     return;
                   2715:   if (i == len)                /* Invalid option: no '='.  */
                   2716:     return;
                   2717:   if (i == (len - 1))  /* Invalid option: no value after '='.  */
                   2718:     return;
                   2719: 
                   2720:   optionlen = i;
                   2721:   val = option + (optionlen + 1);
                   2722:   vallen = len - (optionlen + 1);
                   2723: 
                   2724:   if (strncmp("gpr-names", option, optionlen) == 0
                   2725:       && strlen("gpr-names") == optionlen)
                   2726:     {
                   2727:       chosen_abi = choose_abi_by_name (val, vallen);
                   2728:       if (chosen_abi != NULL)
                   2729:        mips_gpr_names = chosen_abi->gpr_names;
                   2730:       return;
                   2731:     }
                   2732: 
                   2733:   if (strncmp("fpr-names", option, optionlen) == 0
                   2734:       && strlen("fpr-names") == optionlen)
                   2735:     {
                   2736:       chosen_abi = choose_abi_by_name (val, vallen);
                   2737:       if (chosen_abi != NULL)
                   2738:        mips_fpr_names = chosen_abi->fpr_names;
                   2739:       return;
                   2740:     }
                   2741: 
                   2742:   if (strncmp("cp0-names", option, optionlen) == 0
                   2743:       && strlen("cp0-names") == optionlen)
                   2744:     {
                   2745:       chosen_arch = choose_arch_by_name (val, vallen);
                   2746:       if (chosen_arch != NULL)
                   2747:        {
                   2748:          mips_cp0_names = chosen_arch->cp0_names;
                   2749:          mips_cp0sel_names = chosen_arch->cp0sel_names;
                   2750:          mips_cp0sel_names_len = chosen_arch->cp0sel_names_len;
                   2751:        }
                   2752:       return;
                   2753:     }
                   2754: 
                   2755:   if (strncmp("hwr-names", option, optionlen) == 0
                   2756:       && strlen("hwr-names") == optionlen)
                   2757:     {
                   2758:       chosen_arch = choose_arch_by_name (val, vallen);
                   2759:       if (chosen_arch != NULL)
                   2760:        mips_hwr_names = chosen_arch->hwr_names;
                   2761:       return;
                   2762:     }
                   2763: 
                   2764:   if (strncmp("reg-names", option, optionlen) == 0
                   2765:       && strlen("reg-names") == optionlen)
                   2766:     {
                   2767:       /* We check both ABI and ARCH here unconditionally, so
                   2768:         that "numeric" will do the desirable thing: select
                   2769:         numeric register names for all registers.  Other than
                   2770:         that, a given name probably won't match both.  */
                   2771:       chosen_abi = choose_abi_by_name (val, vallen);
                   2772:       if (chosen_abi != NULL)
                   2773:        {
                   2774:          mips_gpr_names = chosen_abi->gpr_names;
                   2775:          mips_fpr_names = chosen_abi->fpr_names;
                   2776:        }
                   2777:       chosen_arch = choose_arch_by_name (val, vallen);
                   2778:       if (chosen_arch != NULL)
                   2779:        {
                   2780:          mips_cp0_names = chosen_arch->cp0_names;
                   2781:          mips_cp0sel_names = chosen_arch->cp0sel_names;
                   2782:          mips_cp0sel_names_len = chosen_arch->cp0sel_names_len;
                   2783:          mips_hwr_names = chosen_arch->hwr_names;
                   2784:        }
                   2785:       return;
                   2786:     }
                   2787: 
                   2788:   /* Invalid option.  */
                   2789: }
                   2790: 
                   2791: void
                   2792: parse_mips_dis_options (options)
                   2793:      const char *options;
                   2794: {
                   2795:   const char *option_end;
                   2796: 
                   2797:   if (options == NULL)
                   2798:     return;
                   2799: 
                   2800:   while (*options != '\0')
                   2801:     {
                   2802:       /* Skip empty options.  */
                   2803:       if (*options == ',')
                   2804:        {
                   2805:          options++;
                   2806:          continue;
                   2807:        }
                   2808: 
                   2809:       /* We know that *options is neither NUL or a comma.  */
                   2810:       option_end = options + 1;
                   2811:       while (*option_end != ',' && *option_end != '\0')
                   2812:        option_end++;
                   2813: 
                   2814:       parse_mips_dis_option (options, option_end - options);
                   2815: 
                   2816:       /* Go on to the next one.  If option_end points to a comma, it
                   2817:         will be skipped above.  */
                   2818:       options = option_end;
                   2819:     }
                   2820: }
                   2821: 
                   2822: static const struct mips_cp0sel_name *
                   2823: lookup_mips_cp0sel_name(names, len, cp0reg, sel)
                   2824:        const struct mips_cp0sel_name *names;
                   2825:        unsigned int len, cp0reg, sel;
                   2826: {
                   2827:   unsigned int i;
                   2828: 
                   2829:   for (i = 0; i < len; i++)
                   2830:     if (names[i].cp0reg == cp0reg && names[i].sel == sel)
                   2831:       return &names[i];
                   2832:   return NULL;
                   2833: }
                   2834: 
                   2835: /* Print insn arguments for 32/64-bit code.  */
                   2836: 
                   2837: static void
                   2838: print_insn_args (d, l, pc, info)
                   2839:      const char *d;
                   2840:      register unsigned long int l;
                   2841:      bfd_vma pc;
                   2842:      struct disassemble_info *info;
                   2843: {
                   2844:   int op, delta;
                   2845:   unsigned int lsb, msb, msbd;
                   2846: 
                   2847:   lsb = 0;
                   2848: 
                   2849:   for (; *d != '\0'; d++)
                   2850:     {
                   2851:       switch (*d)
                   2852:        {
                   2853:        case ',':
                   2854:        case '(':
                   2855:        case ')':
                   2856:        case '[':
                   2857:        case ']':
                   2858:          (*info->fprintf_func) (info->stream, "%c", *d);
                   2859:          break;
                   2860: 
                   2861:        case '+':
                   2862:          /* Extension character; switch for second char.  */
                   2863:          d++;
                   2864:          switch (*d)
                   2865:            {
                   2866:            case '\0':
                   2867:              /* xgettext:c-format */
                   2868:              (*info->fprintf_func) (info->stream,
                   2869:                                     _("# internal error, incomplete extension sequence (+)"));
                   2870:              return;
                   2871: 
                   2872:            case 'A':
                   2873:              lsb = (l >> OP_SH_SHAMT) & OP_MASK_SHAMT;
                   2874:              (*info->fprintf_func) (info->stream, "0x%x", lsb);
                   2875:              break;
                   2876:        
                   2877:            case 'B':
                   2878:              msb = (l >> OP_SH_INSMSB) & OP_MASK_INSMSB;
                   2879:              (*info->fprintf_func) (info->stream, "0x%x", msb - lsb + 1);
                   2880:              break;
                   2881: 
                   2882:            case 'C':
                   2883:            case 'H':
                   2884:              msbd = (l >> OP_SH_EXTMSBD) & OP_MASK_EXTMSBD;
                   2885:              (*info->fprintf_func) (info->stream, "0x%x", msbd + 1);
                   2886:              break;
                   2887: 
                   2888:            case 'D':
                   2889:              {
                   2890:                const struct mips_cp0sel_name *n;
                   2891:                unsigned int cp0reg, sel;
                   2892: 
                   2893:                cp0reg = (l >> OP_SH_RD) & OP_MASK_RD;
                   2894:                sel = (l >> OP_SH_SEL) & OP_MASK_SEL;
                   2895: 
                   2896:                /* CP0 register including 'sel' code for mtcN (et al.), to be
                   2897:                   printed textually if known.  If not known, print both
                   2898:                   CP0 register name and sel numerically since CP0 register
                   2899:                   with sel 0 may have a name unrelated to register being
                   2900:                   printed.  */
                   2901:                n = lookup_mips_cp0sel_name(mips_cp0sel_names,
                   2902:                                            mips_cp0sel_names_len, cp0reg, sel);
                   2903:                if (n != NULL)
                   2904:                  (*info->fprintf_func) (info->stream, "%s", n->name);
                   2905:                else
                   2906:                  (*info->fprintf_func) (info->stream, "$%d,%d", cp0reg, sel);
                   2907:                break;
                   2908:              }
                   2909: 
                   2910:            case 'E':
                   2911:              lsb = ((l >> OP_SH_SHAMT) & OP_MASK_SHAMT) + 32;
                   2912:              (*info->fprintf_func) (info->stream, "0x%x", lsb);
                   2913:              break;
                   2914:        
                   2915:            case 'F':
                   2916:              msb = ((l >> OP_SH_INSMSB) & OP_MASK_INSMSB) + 32;
                   2917:              (*info->fprintf_func) (info->stream, "0x%x", msb - lsb + 1);
                   2918:              break;
                   2919: 
                   2920:            case 'G':
                   2921:              msbd = ((l >> OP_SH_EXTMSBD) & OP_MASK_EXTMSBD) + 32;
                   2922:              (*info->fprintf_func) (info->stream, "0x%x", msbd + 1);
                   2923:              break;
                   2924: 
                   2925:            default:
                   2926:              /* xgettext:c-format */
                   2927:              (*info->fprintf_func) (info->stream,
                   2928:                                     _("# internal error, undefined extension sequence (+%c)"),
                   2929:                                     *d);
                   2930:              return;
                   2931:            }
                   2932:          break;
                   2933: 
                   2934:        case 's':
                   2935:        case 'b':
                   2936:        case 'r':
                   2937:        case 'v':
                   2938:          (*info->fprintf_func) (info->stream, "%s",
                   2939:                                 mips_gpr_names[(l >> OP_SH_RS) & OP_MASK_RS]);
                   2940:          break;
                   2941: 
                   2942:        case 't':
                   2943:        case 'w':
                   2944:          (*info->fprintf_func) (info->stream, "%s",
                   2945:                                 mips_gpr_names[(l >> OP_SH_RT) & OP_MASK_RT]);
                   2946:          break;
                   2947: 
                   2948:        case 'i':
                   2949:        case 'u':
                   2950:          (*info->fprintf_func) (info->stream, "0x%x",
                   2951:                                 (l >> OP_SH_IMMEDIATE) & OP_MASK_IMMEDIATE);
                   2952:          break;
                   2953: 
                   2954:        case 'j': /* Same as i, but sign-extended.  */
                   2955:        case 'o':
                   2956:          delta = (l >> OP_SH_DELTA) & OP_MASK_DELTA;
                   2957:          if (delta & 0x8000)
                   2958:            delta |= ~0xffff;
                   2959:          (*info->fprintf_func) (info->stream, "%d",
                   2960:                                 delta);
                   2961:          break;
                   2962: 
                   2963:        case 'h':
                   2964:          (*info->fprintf_func) (info->stream, "0x%x",
                   2965:                                 (unsigned int) ((l >> OP_SH_PREFX)
                   2966:                                                 & OP_MASK_PREFX));
                   2967:          break;
                   2968: 
                   2969:        case 'k':
                   2970:          (*info->fprintf_func) (info->stream, "0x%x",
                   2971:                                 (unsigned int) ((l >> OP_SH_CACHE)
                   2972:                                                 & OP_MASK_CACHE));
                   2973:          break;
                   2974: 
                   2975:        case 'a':
                   2976:          info->target = (((pc + 4) & ~(bfd_vma) 0x0fffffff)
                   2977:                          | (((l >> OP_SH_TARGET) & OP_MASK_TARGET) << 2));
                   2978:          (*info->print_address_func) (info->target, info);
                   2979:          break;
                   2980: 
                   2981:        case 'p':
                   2982:          /* Sign extend the displacement.  */
                   2983:          delta = (l >> OP_SH_DELTA) & OP_MASK_DELTA;
                   2984:          if (delta & 0x8000)
                   2985:            delta |= ~0xffff;
                   2986:          info->target = (delta << 2) + pc + INSNLEN;
                   2987:          (*info->print_address_func) (info->target, info);
                   2988:          break;
                   2989: 
                   2990:        case 'd':
                   2991:          (*info->fprintf_func) (info->stream, "%s",
                   2992:                                 mips_gpr_names[(l >> OP_SH_RD) & OP_MASK_RD]);
                   2993:          break;
                   2994: 
                   2995:        case 'U':
                   2996:          {
                   2997:            /* First check for both rd and rt being equal.  */
                   2998:            unsigned int reg = (l >> OP_SH_RD) & OP_MASK_RD;
                   2999:            if (reg == ((l >> OP_SH_RT) & OP_MASK_RT))
                   3000:              (*info->fprintf_func) (info->stream, "%s",
                   3001:                                     mips_gpr_names[reg]);
                   3002:            else
                   3003:              {
                   3004:                /* If one is zero use the other.  */
                   3005:                if (reg == 0)
                   3006:                  (*info->fprintf_func) (info->stream, "%s",
                   3007:                                         mips_gpr_names[(l >> OP_SH_RT) & OP_MASK_RT]);
                   3008:                else if (((l >> OP_SH_RT) & OP_MASK_RT) == 0)
                   3009:                  (*info->fprintf_func) (info->stream, "%s",
                   3010:                                         mips_gpr_names[reg]);
                   3011:                else /* Bogus, result depends on processor.  */
                   3012:                  (*info->fprintf_func) (info->stream, "%s or %s",
                   3013:                                         mips_gpr_names[reg],
                   3014:                                         mips_gpr_names[(l >> OP_SH_RT) & OP_MASK_RT]);
                   3015:              }
                   3016:          }
                   3017:          break;
                   3018: 
                   3019:        case 'z':
                   3020:          (*info->fprintf_func) (info->stream, "%s", mips_gpr_names[0]);
                   3021:          break;
                   3022: 
                   3023:        case '<':
                   3024:          (*info->fprintf_func) (info->stream, "0x%x",
                   3025:                                 (l >> OP_SH_SHAMT) & OP_MASK_SHAMT);
                   3026:          break;
                   3027: 
                   3028:        case 'c':
                   3029:          (*info->fprintf_func) (info->stream, "0x%x",
                   3030:                                 (l >> OP_SH_CODE) & OP_MASK_CODE);
                   3031:          break;
                   3032: 
                   3033:        case 'q':
                   3034:          (*info->fprintf_func) (info->stream, "0x%x",
                   3035:                                 (l >> OP_SH_CODE2) & OP_MASK_CODE2);
                   3036:          break;
                   3037: 
                   3038:        case 'C':
                   3039:          (*info->fprintf_func) (info->stream, "0x%x",
                   3040:                                 (l >> OP_SH_COPZ) & OP_MASK_COPZ);
                   3041:          break;
                   3042: 
                   3043:        case 'B':
                   3044:          (*info->fprintf_func) (info->stream, "0x%x",
                   3045:                                 (l >> OP_SH_CODE20) & OP_MASK_CODE20);
                   3046:          break;
                   3047: 
                   3048:        case 'J':
                   3049:          (*info->fprintf_func) (info->stream, "0x%x",
                   3050:                                 (l >> OP_SH_CODE19) & OP_MASK_CODE19);
                   3051:          break;
                   3052: 
                   3053:        case 'S':
                   3054:        case 'V':
                   3055:          (*info->fprintf_func) (info->stream, "%s",
                   3056:                                 mips_fpr_names[(l >> OP_SH_FS) & OP_MASK_FS]);
                   3057:          break;
                   3058: 
                   3059:        case 'T':
                   3060:        case 'W':
                   3061:          (*info->fprintf_func) (info->stream, "%s",
                   3062:                                 mips_fpr_names[(l >> OP_SH_FT) & OP_MASK_FT]);
                   3063:          break;
                   3064: 
                   3065:        case 'D':
                   3066:          (*info->fprintf_func) (info->stream, "%s",
                   3067:                                 mips_fpr_names[(l >> OP_SH_FD) & OP_MASK_FD]);
                   3068:          break;
                   3069: 
                   3070:        case 'R':
                   3071:          (*info->fprintf_func) (info->stream, "%s",
                   3072:                                 mips_fpr_names[(l >> OP_SH_FR) & OP_MASK_FR]);
                   3073:          break;
                   3074: 
                   3075:        case 'E':
                   3076:          /* Coprocessor register for lwcN instructions, et al.
                   3077: 
                   3078:             Note that there is no load/store cp0 instructions, and
                   3079:             that FPU (cp1) instructions disassemble this field using
                   3080:             'T' format.  Therefore, until we gain understanding of
                   3081:             cp2 register names, we can simply print the register
                   3082:             numbers.  */
                   3083:          (*info->fprintf_func) (info->stream, "$%d",
                   3084:                                 (l >> OP_SH_RT) & OP_MASK_RT);
                   3085:          break;
                   3086: 
                   3087:        case 'G':
                   3088:          /* Coprocessor register for mtcN instructions, et al.  Note
                   3089:             that FPU (cp1) instructions disassemble this field using
                   3090:             'S' format.  Therefore, we only need to worry about cp0,
                   3091:             cp2, and cp3.  */
                   3092:          op = (l >> OP_SH_OP) & OP_MASK_OP;
                   3093:          if (op == OP_OP_COP0)
                   3094:            (*info->fprintf_func) (info->stream, "%s",
                   3095:                                   mips_cp0_names[(l >> OP_SH_RD) & OP_MASK_RD]);
                   3096:          else
                   3097:            (*info->fprintf_func) (info->stream, "$%d",
                   3098:                                   (l >> OP_SH_RD) & OP_MASK_RD);
                   3099:          break;
                   3100: 
                   3101:        case 'K':
                   3102:          (*info->fprintf_func) (info->stream, "%s",
                   3103:                                 mips_hwr_names[(l >> OP_SH_RD) & OP_MASK_RD]);
                   3104:          break;
                   3105: 
                   3106:        case 'N':
                   3107:          (*info->fprintf_func) (info->stream, "$fcc%d",
                   3108:                                 (l >> OP_SH_BCC) & OP_MASK_BCC);
                   3109:          break;
                   3110: 
                   3111:        case 'M':
                   3112:          (*info->fprintf_func) (info->stream, "$fcc%d",
                   3113:                                 (l >> OP_SH_CCC) & OP_MASK_CCC);
                   3114:          break;
                   3115: 
                   3116:        case 'P':
                   3117:          (*info->fprintf_func) (info->stream, "%d",
                   3118:                                 (l >> OP_SH_PERFREG) & OP_MASK_PERFREG);
                   3119:          break;
                   3120: 
                   3121:        case 'e':
                   3122:          (*info->fprintf_func) (info->stream, "%d",
                   3123:                                 (l >> OP_SH_VECBYTE) & OP_MASK_VECBYTE);
                   3124:          break;
                   3125: 
                   3126:        case '%':
                   3127:          (*info->fprintf_func) (info->stream, "%d",
                   3128:                                 (l >> OP_SH_VECALIGN) & OP_MASK_VECALIGN);
                   3129:          break;
                   3130: 
                   3131:        case 'H':
                   3132:          (*info->fprintf_func) (info->stream, "%d",
                   3133:                                 (l >> OP_SH_SEL) & OP_MASK_SEL);
                   3134:          break;
                   3135: 
                   3136:        case 'O':
                   3137:          (*info->fprintf_func) (info->stream, "%d",
                   3138:                                 (l >> OP_SH_ALN) & OP_MASK_ALN);
                   3139:          break;
                   3140: 
                   3141:        case 'Q':
                   3142:          {
                   3143:            unsigned int vsel = (l >> OP_SH_VSEL) & OP_MASK_VSEL;
                   3144:            if ((vsel & 0x10) == 0)
                   3145:              {
                   3146:                int fmt;
                   3147:                vsel &= 0x0f;
                   3148:                for (fmt = 0; fmt < 3; fmt++, vsel >>= 1)
                   3149:                  if ((vsel & 1) == 0)
                   3150:                    break;
                   3151:                (*info->fprintf_func) (info->stream, "$v%d[%d]",
                   3152:                                       (l >> OP_SH_FT) & OP_MASK_FT,
                   3153:                                       vsel >> 1);
                   3154:              }
                   3155:            else if ((vsel & 0x08) == 0)
                   3156:              {
                   3157:                (*info->fprintf_func) (info->stream, "$v%d",
                   3158:                                       (l >> OP_SH_FT) & OP_MASK_FT);
                   3159:              }
                   3160:            else
                   3161:              {
                   3162:                (*info->fprintf_func) (info->stream, "0x%x",
                   3163:                                       (l >> OP_SH_FT) & OP_MASK_FT);
                   3164:              }
                   3165:          }
                   3166:          break;
                   3167: 
                   3168:        case 'X':
                   3169:          (*info->fprintf_func) (info->stream, "$v%d",
                   3170:                                 (l >> OP_SH_FD) & OP_MASK_FD);
                   3171:          break;
                   3172: 
                   3173:        case 'Y':
                   3174:          (*info->fprintf_func) (info->stream, "$v%d",
                   3175:                                 (l >> OP_SH_FS) & OP_MASK_FS);
                   3176:          break;
                   3177: 
                   3178:        case 'Z':
                   3179:          (*info->fprintf_func) (info->stream, "$v%d",
                   3180:                                 (l >> OP_SH_FT) & OP_MASK_FT);
                   3181:          break;
                   3182: 
                   3183:        default:
                   3184:          /* xgettext:c-format */
                   3185:          (*info->fprintf_func) (info->stream,
                   3186:                                 _("# internal error, undefined modifier(%c)"),
                   3187:                                 *d);
                   3188:          return;
                   3189:        }
                   3190:     }
                   3191: }
                   3192: 
                   3193: /* Check if the object uses NewABI conventions.  */
                   3194: #if 0
                   3195: static int
                   3196: is_newabi (header)
                   3197:      Elf_Internal_Ehdr *header;
                   3198: {
                   3199:   /* There are no old-style ABIs which use 64-bit ELF.  */
                   3200:   if (header->e_ident[EI_CLASS] == ELFCLASS64)
                   3201:     return 1;
                   3202: 
                   3203:   /* If a 32-bit ELF file, n32 is a new-style ABI.  */
                   3204:   if ((header->e_flags & EF_MIPS_ABI2) != 0)
                   3205:     return 1;
                   3206: 
                   3207:   return 0;
                   3208: }
                   3209: #endif
                   3210: 
                   3211: /* Print the mips instruction at address MEMADDR in debugged memory,
                   3212:    on using INFO.  Returns length of the instruction, in bytes, which is
                   3213:    always INSNLEN.  BIGENDIAN must be 1 if this is big-endian code, 0 if
                   3214:    this is little-endian code.  */
                   3215: 
                   3216: static int
                   3217: print_insn_mips (memaddr, word, info)
                   3218:      bfd_vma memaddr;
                   3219:      unsigned long int word;
                   3220:      struct disassemble_info *info;
                   3221: {
                   3222:   register const struct mips_opcode *op;
                   3223:   static bfd_boolean init = 0;
                   3224:   static const struct mips_opcode *mips_hash[OP_MASK_OP + 1];
                   3225: 
                   3226:   /* Build a hash table to shorten the search time.  */
                   3227:   if (! init)
                   3228:     {
                   3229:       unsigned int i;
                   3230: 
                   3231:       for (i = 0; i <= OP_MASK_OP; i++)
                   3232:        {
                   3233:          for (op = mips_opcodes; op < &mips_opcodes[NUMOPCODES]; op++)
                   3234:            {
                   3235:              if (op->pinfo == INSN_MACRO)
                   3236:                continue;
                   3237:              if (i == ((op->match >> OP_SH_OP) & OP_MASK_OP))
                   3238:                {
                   3239:                  mips_hash[i] = op;
                   3240:                  break;
                   3241:                }
                   3242:            }
                   3243:        }
                   3244: 
                   3245:       init = 1;
                   3246:     }
                   3247: 
                   3248:   info->bytes_per_chunk = INSNLEN;
                   3249:   info->display_endian = info->endian;
                   3250:   info->insn_info_valid = 1;
                   3251:   info->branch_delay_insns = 0;
                   3252:   info->data_size = 0;
                   3253:   info->insn_type = dis_nonbranch;
                   3254:   info->target = 0;
                   3255:   info->target2 = 0;
                   3256: 
                   3257:   op = mips_hash[(word >> OP_SH_OP) & OP_MASK_OP];
                   3258:   if (op != NULL)
                   3259:     {
                   3260:       for (; op < &mips_opcodes[NUMOPCODES]; op++)
                   3261:        {
                   3262:          if (op->pinfo != INSN_MACRO && (word & op->mask) == op->match)
                   3263:            {
                   3264:              register const char *d;
                   3265: 
                   3266:              /* We always allow to disassemble the jalx instruction.  */
                   3267:              if (! OPCODE_IS_MEMBER (op, mips_isa, mips_processor)
                   3268:                  && strcmp (op->name, "jalx"))
                   3269:                continue;
                   3270: 
                   3271:              /* Figure out instruction type and branch delay information.  */
                   3272:              if ((op->pinfo & INSN_UNCOND_BRANCH_DELAY) != 0)
                   3273:                {
                   3274:                  if ((info->insn_type & INSN_WRITE_GPR_31) != 0)
                   3275:                    info->insn_type = dis_jsr;
                   3276:                  else
                   3277:                    info->insn_type = dis_branch;
                   3278:                  info->branch_delay_insns = 1;
                   3279:                }
                   3280:              else if ((op->pinfo & (INSN_COND_BRANCH_DELAY
                   3281:                                     | INSN_COND_BRANCH_LIKELY)) != 0)
                   3282:                {
                   3283:                  if ((info->insn_type & INSN_WRITE_GPR_31) != 0)
                   3284:                    info->insn_type = dis_condjsr;
                   3285:                  else
                   3286:                    info->insn_type = dis_condbranch;
                   3287:                  info->branch_delay_insns = 1;
                   3288:                }
                   3289:              else if ((op->pinfo & (INSN_STORE_MEMORY
                   3290:                                     | INSN_LOAD_MEMORY_DELAY)) != 0)
                   3291:                info->insn_type = dis_dref;
                   3292: 
                   3293:              (*info->fprintf_func) (info->stream, "%s", op->name);
                   3294: 
                   3295:              d = op->args;
                   3296:              if (d != NULL && *d != '\0')
                   3297:                {
                   3298:                  (*info->fprintf_func) (info->stream, "\t");
                   3299:                  print_insn_args (d, word, memaddr, info);
                   3300:                }
                   3301: 
                   3302:              return INSNLEN;
                   3303:            }
                   3304:        }
                   3305:     }
                   3306: 
                   3307:   /* Handle undefined instructions.  */
                   3308:   info->insn_type = dis_noninsn;
                   3309:   (*info->fprintf_func) (info->stream, "0x%x", word);
                   3310:   return INSNLEN;
                   3311: }
                   3312: 
                   3313: /* In an environment where we do not know the symbol type of the
                   3314:    instruction we are forced to assume that the low order bit of the
                   3315:    instructions' address may mark it as a mips16 instruction.  If we
                   3316:    are single stepping, or the pc is within the disassembled function,
                   3317:    this works.  Otherwise, we need a clue.  Sometimes.  */
                   3318: 
                   3319: static int
                   3320: _print_insn_mips (memaddr, info, endianness)
                   3321:      bfd_vma memaddr;
                   3322:      struct disassemble_info *info;
                   3323:      enum bfd_endian endianness;
                   3324: {
                   3325:   bfd_byte buffer[INSNLEN];
                   3326:   int status;
                   3327: 
                   3328:   set_default_mips_dis_options (info);
                   3329:   parse_mips_dis_options (info->disassembler_options);
                   3330: 
                   3331: #if 0
                   3332: #if 1
                   3333:   /* FIXME: If odd address, this is CLEARLY a mips 16 instruction.  */
                   3334:   /* Only a few tools will work this way.  */
                   3335:   if (memaddr & 0x01)
                   3336:     return print_insn_mips16 (memaddr, info);
                   3337: #endif
                   3338: 
                   3339: #if SYMTAB_AVAILABLE
                   3340:   if (info->mach == bfd_mach_mips16
                   3341:       || (info->flavour == bfd_target_elf_flavour
                   3342:          && info->symbols != NULL
                   3343:          && ((*(elf_symbol_type **) info->symbols)->internal_elf_sym.st_other
                   3344:              == STO_MIPS16)))
                   3345:     return print_insn_mips16 (memaddr, info);
                   3346: #endif
                   3347: #endif
                   3348: 
                   3349:   status = (*info->read_memory_func) (memaddr, buffer, INSNLEN, info);
                   3350:   if (status == 0)
                   3351:     {
                   3352:       unsigned long insn;
                   3353: 
                   3354:       if (endianness == BFD_ENDIAN_BIG)
                   3355:        insn = (unsigned long) bfd_getb32 (buffer);
                   3356:       else
                   3357:        insn = (unsigned long) bfd_getl32 (buffer);
                   3358: 
                   3359:       return print_insn_mips (memaddr, insn, info);
                   3360:     }
                   3361:   else
                   3362:     {
                   3363:       (*info->memory_error_func) (status, memaddr, info);
                   3364:       return -1;
                   3365:     }
                   3366: }
                   3367: 
                   3368: int
                   3369: print_insn_big_mips (memaddr, info)
                   3370:      bfd_vma memaddr;
                   3371:      struct disassemble_info *info;
                   3372: {
                   3373:   return _print_insn_mips (memaddr, info, BFD_ENDIAN_BIG);
                   3374: }
                   3375: 
                   3376: int
                   3377: print_insn_little_mips (memaddr, info)
                   3378:      bfd_vma memaddr;
                   3379:      struct disassemble_info *info;
                   3380: {
                   3381:   return _print_insn_mips (memaddr, info, BFD_ENDIAN_LITTLE);
                   3382: }
                   3383: 
                   3384: /* Disassemble mips16 instructions.  */
                   3385: #if 0
                   3386: static int
                   3387: print_insn_mips16 (memaddr, info)
                   3388:      bfd_vma memaddr;
                   3389:      struct disassemble_info *info;
                   3390: {
                   3391:   int status;
                   3392:   bfd_byte buffer[2];
                   3393:   int length;
                   3394:   int insn;
                   3395:   bfd_boolean use_extend;
                   3396:   int extend = 0;
                   3397:   const struct mips_opcode *op, *opend;
                   3398: 
                   3399:   info->bytes_per_chunk = 2;
                   3400:   info->display_endian = info->endian;
                   3401:   info->insn_info_valid = 1;
                   3402:   info->branch_delay_insns = 0;
                   3403:   info->data_size = 0;
                   3404:   info->insn_type = dis_nonbranch;
                   3405:   info->target = 0;
                   3406:   info->target2 = 0;
                   3407: 
                   3408:   status = (*info->read_memory_func) (memaddr, buffer, 2, info);
                   3409:   if (status != 0)
                   3410:     {
                   3411:       (*info->memory_error_func) (status, memaddr, info);
                   3412:       return -1;
                   3413:     }
                   3414: 
                   3415:   length = 2;
                   3416: 
                   3417:   if (info->endian == BFD_ENDIAN_BIG)
                   3418:     insn = bfd_getb16 (buffer);
                   3419:   else
                   3420:     insn = bfd_getl16 (buffer);
                   3421: 
                   3422:   /* Handle the extend opcode specially.  */
                   3423:   use_extend = FALSE;
                   3424:   if ((insn & 0xf800) == 0xf000)
                   3425:     {
                   3426:       use_extend = TRUE;
                   3427:       extend = insn & 0x7ff;
                   3428: 
                   3429:       memaddr += 2;
                   3430: 
                   3431:       status = (*info->read_memory_func) (memaddr, buffer, 2, info);
                   3432:       if (status != 0)
                   3433:        {
                   3434:          (*info->fprintf_func) (info->stream, "extend 0x%x",
                   3435:                                 (unsigned int) extend);
                   3436:          (*info->memory_error_func) (status, memaddr, info);
                   3437:          return -1;
                   3438:        }
                   3439: 
                   3440:       if (info->endian == BFD_ENDIAN_BIG)
                   3441:        insn = bfd_getb16 (buffer);
                   3442:       else
                   3443:        insn = bfd_getl16 (buffer);
                   3444: 
                   3445:       /* Check for an extend opcode followed by an extend opcode.  */
                   3446:       if ((insn & 0xf800) == 0xf000)
                   3447:        {
                   3448:          (*info->fprintf_func) (info->stream, "extend 0x%x",
                   3449:                                 (unsigned int) extend);
                   3450:          info->insn_type = dis_noninsn;
                   3451:          return length;
                   3452:        }
                   3453: 
                   3454:       length += 2;
                   3455:     }
                   3456: 
                   3457:   /* FIXME: Should probably use a hash table on the major opcode here.  */
                   3458: 
                   3459:   opend = mips16_opcodes + bfd_mips16_num_opcodes;
                   3460:   for (op = mips16_opcodes; op < opend; op++)
                   3461:     {
                   3462:       if (op->pinfo != INSN_MACRO && (insn & op->mask) == op->match)
                   3463:        {
                   3464:          const char *s;
                   3465: 
                   3466:          if (strchr (op->args, 'a') != NULL)
                   3467:            {
                   3468:              if (use_extend)
                   3469:                {
                   3470:                  (*info->fprintf_func) (info->stream, "extend 0x%x",
                   3471:                                         (unsigned int) extend);
                   3472:                  info->insn_type = dis_noninsn;
                   3473:                  return length - 2;
                   3474:                }
                   3475: 
                   3476:              use_extend = FALSE;
                   3477: 
                   3478:              memaddr += 2;
                   3479: 
                   3480:              status = (*info->read_memory_func) (memaddr, buffer, 2,
                   3481:                                                  info);
                   3482:              if (status == 0)
                   3483:                {
                   3484:                  use_extend = TRUE;
                   3485:                  if (info->endian == BFD_ENDIAN_BIG)
                   3486:                    extend = bfd_getb16 (buffer);
                   3487:                  else
                   3488:                    extend = bfd_getl16 (buffer);
                   3489:                  length += 2;
                   3490:                }
                   3491:            }
                   3492: 
                   3493:          (*info->fprintf_func) (info->stream, "%s", op->name);
                   3494:          if (op->args[0] != '\0')
                   3495:            (*info->fprintf_func) (info->stream, "\t");
                   3496: 
                   3497:          for (s = op->args; *s != '\0'; s++)
                   3498:            {
                   3499:              if (*s == ','
                   3500:                  && s[1] == 'w'
                   3501:                  && (((insn >> MIPS16OP_SH_RX) & MIPS16OP_MASK_RX)
                   3502:                      == ((insn >> MIPS16OP_SH_RY) & MIPS16OP_MASK_RY)))
                   3503:                {
                   3504:                  /* Skip the register and the comma.  */
                   3505:                  ++s;
                   3506:                  continue;
                   3507:                }
                   3508:              if (*s == ','
                   3509:                  && s[1] == 'v'
                   3510:                  && (((insn >> MIPS16OP_SH_RZ) & MIPS16OP_MASK_RZ)
                   3511:                      == ((insn >> MIPS16OP_SH_RX) & MIPS16OP_MASK_RX)))
                   3512:                {
                   3513:                  /* Skip the register and the comma.  */
                   3514:                  ++s;
                   3515:                  continue;
                   3516:                }
                   3517:              print_mips16_insn_arg (*s, op, insn, use_extend, extend, memaddr,
                   3518:                                     info);
                   3519:            }
                   3520: 
                   3521:          if ((op->pinfo & INSN_UNCOND_BRANCH_DELAY) != 0)
                   3522:            {
                   3523:              info->branch_delay_insns = 1;
                   3524:              if (info->insn_type != dis_jsr)
                   3525:                info->insn_type = dis_branch;
                   3526:            }
                   3527: 
                   3528:          return length;
                   3529:        }
                   3530:     }
                   3531: 
                   3532:   if (use_extend)
                   3533:     (*info->fprintf_func) (info->stream, "0x%x", extend | 0xf000);
                   3534:   (*info->fprintf_func) (info->stream, "0x%x", insn);
                   3535:   info->insn_type = dis_noninsn;
                   3536: 
                   3537:   return length;
                   3538: }
                   3539: 
                   3540: /* Disassemble an operand for a mips16 instruction.  */
                   3541: 
                   3542: static void
                   3543: print_mips16_insn_arg (type, op, l, use_extend, extend, memaddr, info)
                   3544:      char type;
                   3545:      const struct mips_opcode *op;
                   3546:      int l;
                   3547:      bfd_boolean use_extend;
                   3548:      int extend;
                   3549:      bfd_vma memaddr;
                   3550:      struct disassemble_info *info;
                   3551: {
                   3552:   switch (type)
                   3553:     {
                   3554:     case ',':
                   3555:     case '(':
                   3556:     case ')':
                   3557:       (*info->fprintf_func) (info->stream, "%c", type);
                   3558:       break;
                   3559: 
                   3560:     case 'y':
                   3561:     case 'w':
                   3562:       (*info->fprintf_func) (info->stream, "%s",
                   3563:                             mips16_reg_names[((l >> MIPS16OP_SH_RY)
                   3564:                                               & MIPS16OP_MASK_RY)]);
                   3565:       break;
                   3566: 
                   3567:     case 'x':
                   3568:     case 'v':
                   3569:       (*info->fprintf_func) (info->stream, "%s",
                   3570:                             mips16_reg_names[((l >> MIPS16OP_SH_RX)
                   3571:                                               & MIPS16OP_MASK_RX)]);
                   3572:       break;
                   3573: 
                   3574:     case 'z':
                   3575:       (*info->fprintf_func) (info->stream, "%s",
                   3576:                             mips16_reg_names[((l >> MIPS16OP_SH_RZ)
                   3577:                                               & MIPS16OP_MASK_RZ)]);
                   3578:       break;
                   3579: 
                   3580:     case 'Z':
                   3581:       (*info->fprintf_func) (info->stream, "%s",
                   3582:                             mips16_reg_names[((l >> MIPS16OP_SH_MOVE32Z)
                   3583:                                               & MIPS16OP_MASK_MOVE32Z)]);
                   3584:       break;
                   3585: 
                   3586:     case '0':
                   3587:       (*info->fprintf_func) (info->stream, "%s", mips_gpr_names[0]);
                   3588:       break;
                   3589: 
                   3590:     case 'S':
                   3591:       (*info->fprintf_func) (info->stream, "%s", mips_gpr_names[29]);
                   3592:       break;
                   3593: 
                   3594:     case 'P':
                   3595:       (*info->fprintf_func) (info->stream, "$pc");
                   3596:       break;
                   3597: 
                   3598:     case 'R':
                   3599:       (*info->fprintf_func) (info->stream, "%s", mips_gpr_names[31]);
                   3600:       break;
                   3601: 
                   3602:     case 'X':
                   3603:       (*info->fprintf_func) (info->stream, "%s",
                   3604:                             mips_gpr_names[((l >> MIPS16OP_SH_REGR32)
                   3605:                                            & MIPS16OP_MASK_REGR32)]);
                   3606:       break;
                   3607: 
                   3608:     case 'Y':
                   3609:       (*info->fprintf_func) (info->stream, "%s",
                   3610:                             mips_gpr_names[MIPS16OP_EXTRACT_REG32R (l)]);
                   3611:       break;
                   3612: 
                   3613:     case '<':
                   3614:     case '>':
                   3615:     case '[':
                   3616:     case ']':
                   3617:     case '4':
                   3618:     case '5':
                   3619:     case 'H':
                   3620:     case 'W':
                   3621:     case 'D':
                   3622:     case 'j':
                   3623:     case '6':
                   3624:     case '8':
                   3625:     case 'V':
                   3626:     case 'C':
                   3627:     case 'U':
                   3628:     case 'k':
                   3629:     case 'K':
                   3630:     case 'p':
                   3631:     case 'q':
                   3632:     case 'A':
                   3633:     case 'B':
                   3634:     case 'E':
                   3635:       {
                   3636:        int immed, nbits, shift, signedp, extbits, pcrel, extu, branch;
                   3637: 
                   3638:        shift = 0;
                   3639:        signedp = 0;
                   3640:        extbits = 16;
                   3641:        pcrel = 0;
                   3642:        extu = 0;
                   3643:        branch = 0;
                   3644:        switch (type)
                   3645:          {
                   3646:          case '<':
                   3647:            nbits = 3;
                   3648:            immed = (l >> MIPS16OP_SH_RZ) & MIPS16OP_MASK_RZ;
                   3649:            extbits = 5;
                   3650:            extu = 1;
                   3651:            break;
                   3652:          case '>':
                   3653:            nbits = 3;
                   3654:            immed = (l >> MIPS16OP_SH_RX) & MIPS16OP_MASK_RX;
                   3655:            extbits = 5;
                   3656:            extu = 1;
                   3657:            break;
                   3658:          case '[':
                   3659:            nbits = 3;
                   3660:            immed = (l >> MIPS16OP_SH_RZ) & MIPS16OP_MASK_RZ;
                   3661:            extbits = 6;
                   3662:            extu = 1;
                   3663:            break;
                   3664:          case ']':
                   3665:            nbits = 3;
                   3666:            immed = (l >> MIPS16OP_SH_RX) & MIPS16OP_MASK_RX;
                   3667:            extbits = 6;
                   3668:            extu = 1;
                   3669:            break;
                   3670:          case '4':
                   3671:            nbits = 4;
                   3672:            immed = (l >> MIPS16OP_SH_IMM4) & MIPS16OP_MASK_IMM4;
                   3673:            signedp = 1;
                   3674:            extbits = 15;
                   3675:            break;
                   3676:          case '5':
                   3677:            nbits = 5;
                   3678:            immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5;
                   3679:            info->insn_type = dis_dref;
                   3680:            info->data_size = 1;
                   3681:            break;
                   3682:          case 'H':
                   3683:            nbits = 5;
                   3684:            shift = 1;
                   3685:            immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5;
                   3686:            info->insn_type = dis_dref;
                   3687:            info->data_size = 2;
                   3688:            break;
                   3689:          case 'W':
                   3690:            nbits = 5;
                   3691:            shift = 2;
                   3692:            immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5;
                   3693:            if ((op->pinfo & MIPS16_INSN_READ_PC) == 0
                   3694:                && (op->pinfo & MIPS16_INSN_READ_SP) == 0)
                   3695:              {
                   3696:                info->insn_type = dis_dref;
                   3697:                info->data_size = 4;
                   3698:              }
                   3699:            break;
                   3700:          case 'D':
                   3701:            nbits = 5;
                   3702:            shift = 3;
                   3703:            immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5;
                   3704:            info->insn_type = dis_dref;
                   3705:            info->data_size = 8;
                   3706:            break;
                   3707:          case 'j':
                   3708:            nbits = 5;
                   3709:            immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5;
                   3710:            signedp = 1;
                   3711:            break;
                   3712:          case '6':
                   3713:            nbits = 6;
                   3714:            immed = (l >> MIPS16OP_SH_IMM6) & MIPS16OP_MASK_IMM6;
                   3715:            break;
                   3716:          case '8':
                   3717:            nbits = 8;
                   3718:            immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8;
                   3719:            break;
                   3720:          case 'V':
                   3721:            nbits = 8;
                   3722:            shift = 2;
                   3723:            immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8;
                   3724:            /* FIXME: This might be lw, or it might be addiu to $sp or
                   3725:                $pc.  We assume it's load.  */
                   3726:            info->insn_type = dis_dref;
                   3727:            info->data_size = 4;
                   3728:            break;
                   3729:          case 'C':
                   3730:            nbits = 8;
                   3731:            shift = 3;
                   3732:            immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8;
                   3733:            info->insn_type = dis_dref;
                   3734:            info->data_size = 8;
                   3735:            break;
                   3736:          case 'U':
                   3737:            nbits = 8;
                   3738:            immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8;
                   3739:            extu = 1;
                   3740:            break;
                   3741:          case 'k':
                   3742:            nbits = 8;
                   3743:            immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8;
                   3744:            signedp = 1;
                   3745:            break;
                   3746:          case 'K':
                   3747:            nbits = 8;
                   3748:            shift = 3;
                   3749:            immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8;
                   3750:            signedp = 1;
                   3751:            break;
                   3752:          case 'p':
                   3753:            nbits = 8;
                   3754:            immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8;
                   3755:            signedp = 1;
                   3756:            pcrel = 1;
                   3757:            branch = 1;
                   3758:            info->insn_type = dis_condbranch;
                   3759:            break;
                   3760:          case 'q':
                   3761:            nbits = 11;
                   3762:            immed = (l >> MIPS16OP_SH_IMM11) & MIPS16OP_MASK_IMM11;
                   3763:            signedp = 1;
                   3764:            pcrel = 1;
                   3765:            branch = 1;
                   3766:            info->insn_type = dis_branch;
                   3767:            break;
                   3768:          case 'A':
                   3769:            nbits = 8;
                   3770:            shift = 2;
                   3771:            immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8;
                   3772:            pcrel = 1;
                   3773:            /* FIXME: This can be lw or la.  We assume it is lw.  */
                   3774:            info->insn_type = dis_dref;
                   3775:            info->data_size = 4;
                   3776:            break;
                   3777:          case 'B':
                   3778:            nbits = 5;
                   3779:            shift = 3;
                   3780:            immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5;
                   3781:            pcrel = 1;
                   3782:            info->insn_type = dis_dref;
                   3783:            info->data_size = 8;
                   3784:            break;
                   3785:          case 'E':
                   3786:            nbits = 5;
                   3787:            shift = 2;
                   3788:            immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5;
                   3789:            pcrel = 1;
                   3790:            break;
                   3791:          default:
                   3792:            abort ();
                   3793:          }
                   3794: 
                   3795:        if (! use_extend)
                   3796:          {
                   3797:            if (signedp && immed >= (1 << (nbits - 1)))
                   3798:              immed -= 1 << nbits;
                   3799:            immed <<= shift;
                   3800:            if ((type == '<' || type == '>' || type == '[' || type == ']')
                   3801:                && immed == 0)
                   3802:              immed = 8;
                   3803:          }
                   3804:        else
                   3805:          {
                   3806:            if (extbits == 16)
                   3807:              immed |= ((extend & 0x1f) << 11) | (extend & 0x7e0);
                   3808:            else if (extbits == 15)
                   3809:              immed |= ((extend & 0xf) << 11) | (extend & 0x7f0);
                   3810:            else
                   3811:              immed = ((extend >> 6) & 0x1f) | (extend & 0x20);
                   3812:            immed &= (1 << extbits) - 1;
                   3813:            if (! extu && immed >= (1 << (extbits - 1)))
                   3814:              immed -= 1 << extbits;
                   3815:          }
                   3816: 
                   3817:        if (! pcrel)
                   3818:          (*info->fprintf_func) (info->stream, "%d", immed);
                   3819:        else
                   3820:          {
                   3821:            bfd_vma baseaddr;
                   3822: 
                   3823:            if (branch)
                   3824:              {
                   3825:                immed *= 2;
                   3826:                baseaddr = memaddr + 2;
                   3827:              }
                   3828:            else if (use_extend)
                   3829:              baseaddr = memaddr - 2;
                   3830:            else
                   3831:              {
                   3832:                int status;
                   3833:                bfd_byte buffer[2];
                   3834: 
                   3835:                baseaddr = memaddr;
                   3836: 
                   3837:                /* If this instruction is in the delay slot of a jr
                   3838:                    instruction, the base address is the address of the
                   3839:                    jr instruction.  If it is in the delay slot of jalr
                   3840:                    instruction, the base address is the address of the
                   3841:                    jalr instruction.  This test is unreliable: we have
                   3842:                    no way of knowing whether the previous word is
                   3843:                    instruction or data.  */
                   3844:                status = (*info->read_memory_func) (memaddr - 4, buffer, 2,
                   3845:                                                    info);
                   3846:                if (status == 0
                   3847:                    && (((info->endian == BFD_ENDIAN_BIG
                   3848:                          ? bfd_getb16 (buffer)
                   3849:                          : bfd_getl16 (buffer))
                   3850:                         & 0xf800) == 0x1800))
                   3851:                  baseaddr = memaddr - 4;
                   3852:                else
                   3853:                  {
                   3854:                    status = (*info->read_memory_func) (memaddr - 2, buffer,
                   3855:                                                        2, info);
                   3856:                    if (status == 0
                   3857:                        && (((info->endian == BFD_ENDIAN_BIG
                   3858:                              ? bfd_getb16 (buffer)
                   3859:                              : bfd_getl16 (buffer))
                   3860:                             & 0xf81f) == 0xe800))
                   3861:                      baseaddr = memaddr - 2;
                   3862:                  }
                   3863:              }
                   3864:            info->target = (baseaddr & ~((1 << shift) - 1)) + immed;
                   3865:            (*info->print_address_func) (info->target, info);
                   3866:          }
                   3867:       }
                   3868:       break;
                   3869: 
                   3870:     case 'a':
                   3871:       if (! use_extend)
                   3872:        extend = 0;
                   3873:       l = ((l & 0x1f) << 23) | ((l & 0x3e0) << 13) | (extend << 2);
                   3874:       info->target = ((memaddr + 4) & ~(bfd_vma) 0x0fffffff) | l;
                   3875:       (*info->print_address_func) (info->target, info);
                   3876:       info->insn_type = dis_jsr;
                   3877:       info->branch_delay_insns = 1;
                   3878:       break;
                   3879: 
                   3880:     case 'l':
                   3881:     case 'L':
                   3882:       {
                   3883:        int need_comma, amask, smask;
                   3884: 
                   3885:        need_comma = 0;
                   3886: 
                   3887:        l = (l >> MIPS16OP_SH_IMM6) & MIPS16OP_MASK_IMM6;
                   3888: 
                   3889:        amask = (l >> 3) & 7;
                   3890: 
                   3891:        if (amask > 0 && amask < 5)
                   3892:          {
                   3893:            (*info->fprintf_func) (info->stream, "%s", mips_gpr_names[4]);
                   3894:            if (amask > 1)
                   3895:              (*info->fprintf_func) (info->stream, "-%s",
                   3896:                                     mips_gpr_names[amask + 3]);
                   3897:            need_comma = 1;
                   3898:          }
                   3899: 
                   3900:        smask = (l >> 1) & 3;
                   3901:        if (smask == 3)
                   3902:          {
                   3903:            (*info->fprintf_func) (info->stream, "%s??",
                   3904:                                   need_comma ? "," : "");
                   3905:            need_comma = 1;
                   3906:          }
                   3907:        else if (smask > 0)
                   3908:          {
                   3909:            (*info->fprintf_func) (info->stream, "%s%s",
                   3910:                                   need_comma ? "," : "",
                   3911:                                   mips_gpr_names[16]);
                   3912:            if (smask > 1)
                   3913:              (*info->fprintf_func) (info->stream, "-%s",
                   3914:                                     mips_gpr_names[smask + 15]);
                   3915:            need_comma = 1;
                   3916:          }
                   3917: 
                   3918:        if (l & 1)
                   3919:          {
                   3920:            (*info->fprintf_func) (info->stream, "%s%s",
                   3921:                                   need_comma ? "," : "",
                   3922:                                   mips_gpr_names[31]);
                   3923:            need_comma = 1;
                   3924:          }
                   3925: 
                   3926:        if (amask == 5 || amask == 6)
                   3927:          {
                   3928:            (*info->fprintf_func) (info->stream, "%s$f0",
                   3929:                                   need_comma ? "," : "");
                   3930:            if (amask == 6)
                   3931:              (*info->fprintf_func) (info->stream, "-$f1");
                   3932:          }
                   3933:       }
                   3934:       break;
                   3935: 
                   3936:     default:
                   3937:       /* xgettext:c-format */
                   3938:       (*info->fprintf_func)
                   3939:        (info->stream,
                   3940:         _("# internal disassembler error, unrecognised modifier (%c)"),
                   3941:         type);
                   3942:       abort ();
                   3943:     }
                   3944: }
                   3945: #endif
                   3946: 
                   3947: void
                   3948: print_mips_disassembler_options (stream)
                   3949:      FILE *stream;
                   3950: {
                   3951:   unsigned int i;
                   3952: 
                   3953:   fprintf (stream, _("\n\
                   3954: The following MIPS specific disassembler options are supported for use\n\
                   3955: with the -M switch (multiple options should be separated by commas):\n"));
                   3956: 
                   3957:   fprintf (stream, _("\n\
                   3958:   gpr-names=ABI            Print GPR names according to  specified ABI.\n\
                   3959:                            Default: based on binary being disassembled.\n"));
                   3960: 
                   3961:   fprintf (stream, _("\n\
                   3962:   fpr-names=ABI            Print FPR names according to specified ABI.\n\
                   3963:                            Default: numeric.\n"));
                   3964: 
                   3965:   fprintf (stream, _("\n\
                   3966:   cp0-names=ARCH           Print CP0 register names according to\n\
                   3967:                            specified architecture.\n\
                   3968:                            Default: based on binary being disassembled.\n"));
                   3969: 
                   3970:   fprintf (stream, _("\n\
                   3971:   hwr-names=ARCH           Print HWR names according to specified \n\
                   3972:                           architecture.\n\
                   3973:                            Default: based on binary being disassembled.\n"));
                   3974: 
                   3975:   fprintf (stream, _("\n\
                   3976:   reg-names=ABI            Print GPR and FPR names according to\n\
                   3977:                            specified ABI.\n"));
                   3978: 
                   3979:   fprintf (stream, _("\n\
                   3980:   reg-names=ARCH           Print CP0 register and HWR names according to\n\
                   3981:                            specified architecture.\n"));
                   3982: 
                   3983:   fprintf (stream, _("\n\
                   3984:   For the options above, the following values are supported for \"ABI\":\n\
                   3985:    "));
                   3986:   for (i = 0; i < ARRAY_SIZE (mips_abi_choices); i++)
                   3987:     fprintf (stream, " %s", mips_abi_choices[i].name);
                   3988:   fprintf (stream, _("\n"));
                   3989: 
                   3990:   fprintf (stream, _("\n\
                   3991:   For the options above, The following values are supported for \"ARCH\":\n\
                   3992:    "));
                   3993:   for (i = 0; i < ARRAY_SIZE (mips_arch_choices); i++)
                   3994:     if (*mips_arch_choices[i].name != '\0')
                   3995:       fprintf (stream, " %s", mips_arch_choices[i].name);
                   3996:   fprintf (stream, _("\n"));
                   3997: 
                   3998:   fprintf (stream, _("\n"));
                   3999: }

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