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Up to [Qemu by Fabrice Bellard] / qemu / roms / SLOF / board-qemu / llfw|
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1.1 root 1: /******************************************************************************
2: * Copyright (c) 2004, 2011 IBM Corporation
3: * All rights reserved.
4: * This program and the accompanying materials
5: * are made available under the terms of the BSD License
6: * which accompanies this distribution, and is available at
7: * http://www.opensource.org/licenses/bsd-license.php
8: *
9: * Contributors:
10: * IBM Corporation - initial implementation
11: *****************************************************************************/
12:
13: /* SLOF for QEMU -- boot code.
14: * Initial entry point
15: */
16:
17: #include "termctrl.h"
18: #include <product.h>
19: #include <xvect.h>
20: #include <cpu.h>
21: #include <macros.h>
22:
23: /* qemu entry:
24: *
25: * __start loaded at 0x100
26: *
27: * CPU 0 starts at 0 with GPR3 pointing to the flat devtree
28: *
29: * All other CPUs are held in stopped state by qemu and are
30: * started via RTAS
31: */
32: .text
33: .globl __start
34: __start:
35: b _start
36: .long 0xDEADBEE0
37: .long 0x0 /* size */
38: .long 0x0 /* crc */
39: .long relTag - __start
40:
41: /* Some exception vectors
42: *
43: * FIXME: Also need 0280, 0380, 0f20, etc.
44: */
45:
46: .irp i, 0x0100,0x0180,0x0200,0x0280,0x0300,0x0380,0x0400,0x0500, \
47: 0x0600,0x0700,0x0800,0x0900,0x0a00,0x0b00,0x0c00,0x0d00, \
48: 0x0e00,0x0f00,0x1000,0x1100,0x1200,0x1300,0x1400,0x1500, \
49: 0x1600,0x1700, \
50: 0x1800,0x1900,0x1a00,0x1b00,0x1c00,0x1d00,0x1e00,0x1f00, \
51: 0x2000,0x2100,0x2200,0x2300,0x2400,0x2500,0x2600,0x2700, \
52: 0x2800,0x2900,0x2a00,0x2b00,0x2c00,0x2d00,0x2e00
53: . = \i
54:
55: /* enable this if you get exceptions before the console works */
56: /* this will allow using the hardware debugger to see where */
57: /* it traps, and with what register values etc. */
58: // b $
59:
60: mtsprg 0,r0
61: mfctr r0
62: mtsprg 2,r0
63: mflr r0
64: // 10
65: mtsprg 3,r0
66: ld r0, (\i + 0x160)(0)
67: mtctr r0
68: li r0, \i + 0x100
69: // 20
70: bctr
71:
72: . = \i + 0x60
73: .quad intHandler2C
74: .endr
75:
76: . = XVECT_M_HANDLER - 0x100
77: .quad 0x00
78: .text
79:
80: /* Here's the startup code for the master CPU */
81: .org 0x4000 - 0x100
82: _start:
83: /* Save device-tree pointer */
84: mr r31,r3
85:
86: /* Switch to 64-bit mode with 64-bit exceptions */
87: #define MSR_SF_LG 63 /* Enable 64 bit mode */
88: #define MSR_ISF_LG 61 /* Interrupt 64b mode valid on 630 */
89: #define __MASK(X) (1<<(X))
90: #define MSR_SF __MASK(MSR_SF_LG) /* Enable 64 bit mode */
91: #define MSR_ISF __MASK(MSR_ISF_LG) /* Interrupt 64b mode */
92: mfmsr r11 /* grab the current MSR */
93: li r12,(MSR_SF | MSR_ISF)@highest
94: sldi r12,r12,48
95: or r11,r11,r12
96: mtmsrd r11
97: isync
98:
99: /* Early greet */
100: li r3,10
101: bl putc
102: li r3,13
103: bl putc
104: li r3,10
105: bl putc
106: li r3,'S'
107: bl putc
108:
109: li r3,'L'
110: bl putc
111: li r3,'O'
112: bl putc
113: li r3,'F'
114: bl putc
115:
116: /* give live sign *****************************/
117: bl 0f
118: .ascii TERM_CTRL_RESET
119: .ascii TERM_CTRL_CRSOFF
120: .ascii " **********************************************************************"
121: .ascii "\r\n"
122: .ascii TERM_CTRL_BRIGHT
123: .ascii PRODUCT_NAME
124: .ascii " Starting\r\n"
125: .ascii TERM_CTRL_RESET
126: .ascii " Build Date = ", __DATE__, " ", __TIME__
127: .ascii "\r\n"
128: .ascii " FW Version = " , RELEASE
129: .ascii "\r\n\0"
130: .align 2
131: 0: mflr r3
132: bl io_print
133:
134: /* go! */
135: li r3,__startC@l
136: mtctr r3
137: bctrl
138:
139: /* write a character to the HV console */
140: putc: sldi r6,r3,(24+32)
141: li r3,0x58
142: li r4,0
143: li r5,1
144: .long 0x44000022
145: blr
146:
147: relTag:
148: .ascii RELEASE
149: .ascii "\0"
150: .align 2
151:
152: C_ENTRY(proceedInterrupt)
153:
154: ld r3,exception_stack_frame@got(r2)
155: ld r1,0(r3)
156:
157: .irp i, 2,3,4,5,6,7,8,9,10,11,12,13,14,15,16, \
158: 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, \
159: 27, 28, 29, 30, 31
160: ld r\i, 0x30+\i*8 (r1)
161: .endr
162:
163: ld r14,0x138(r1);
164: mtsrr0 r14
165:
166: ld r14,0x140(r1);
167: mtsrr1 r14
168:
169: ld r14,0x148(r1);
170: mtcr r14
171:
172: ld 0,XVECT_M_HANDLER(0)
173: mtctr 0
174:
175: ld r0,0x30(r1); # restore vector number
176: ld r1,0x38(r1);
177:
178: bctr
179:
180: intHandler2C:
181: mtctr r1 # save old stack pointer
182: lis r1,0x4
183: stdu r1, -0x160(r1)
184: .irp i, 2,3,4,5,6,7,8,9,10,11,12,13,14,15,16, \
185: 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, \
186: 27, 28, 29, 30, 31
187: std r\i, 0x30+\i*8 (r1)
188: .endr
189:
190: std r0,0x30(r1); # save vector number
191:
192: mfctr r14
193: std r14,0x38(r1); # save old r1
194:
195: mfsrr0 r14
196: std r14,0x138(r1);
197:
198: mfsrr1 r14
199: std r14,0x140(r1);
200:
201: mfcr r14
202: std r14,0x148(r1);
203:
204: mfxer r14
205: std r14,0x150(r1);
206:
207: bl toc_init
208:
209: ld r3,exception_stack_frame@got(r2)
210: std r1,0(r3)
211:
212:
213: mr r3,r0
214: bl .c_interrupt
215:
216: ld r14,0x138(r1);
217: mtsrr0 r14
218:
219: ld r14,0x140(r1);
220: mtsrr1 r14
221:
222: ld r14,0x148(r1);
223: mtcr r14
224:
225: ld r14,0x150(r1);
226: mtxer r14
227:
228:
229: .irp i, 2,3,4,5,6,7,8,9,10,11,12,13,14,15,16, \
230: 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, \
231: 27, 28, 29, 30, 31
232: ld r\i, 0x30+\i*8 (r1)
233: .endr
234:
235: ld r1,0x38(r1);
236:
237: mfsprg r0,2
238: mtctr r0
239: mfsprg r0,3
240: mtlr r0
241: mfsprg r0,0
242: rfid
243:
244: /* Set exception handler for given exception vector.
245: r3: exception vector offset
246: r4: exception handler
247: */
248: .globl .set_exception
249: .set_exception:
250: .globl set_exception
251: set_exception:
252: ld r4,0x0(r4)
253: .globl .set_exception_asm
254: .set_exception_asm:
255: .globl set_exception_asm
256: set_exception_asm:
257: std r4, 0x60(r3) # fixme diff 1f - 0b
258: blr
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