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1.1 root 1: /******************************************************************************
2: * Copyright (c) 2004, 2008 IBM Corporation
3: * All rights reserved.
4: * This program and the accompanying materials
5: * are made available under the terms of the BSD License
6: * which accompanies this distribution, and is available at
7: * http://www.opensource.org/licenses/bsd-license.php
8: *
9: * Contributors:
10: * IBM Corporation - initial implementation
11: *****************************************************************************/
12:
13: #include "netdriver_int.h"
14: #include "types.h"
15:
16: // compiler switches
17:
18: // Debug switches
19: //#define BCM_DEBUG // main debug switch, w/o it the other ones don't work
20: //#define BCM_SHOW_RCV
21: //#define BCM_SHOW_RCV_DATA
22: //#define BCM_SHOW_XMIT
23: //#define BCM_SHOW_XMIT_DATA
24: //#define BCM_SHOW_XMIT_STATS
25: //#define BCM_SHOW_IDX
26: //#define BCM_SHOW_STATS
27: //#define BCM_SHOW_ASF_REGS
28:
29: // Switch to enable SW AUTO-NEG
30: // don't try, it's still incomplete
31: //#define BCM_SW_AUTONEG
32:
33: /*
34: * used register offsets
35: */
36: // PCI command register
37: #define PCI_COM_R ( (u16_t) 0x0004 )
38: // PCI Cache Line Size register
39: #define PCI_CACHELS_R ( (u16_t) 0x000c )
40: // PCI bar1 register
41: #define PCI_BAR1_R ( (u16_t) 0x0010 )
42: // PCI bar2 register
43: #define PCI_BAR2_R ( (u16_t) 0x0014 )
44: // PCI bar1 register
45: #define PCI_SUBID_R ( (u16_t) 0x002e )
46: // PCI-X Comand register
47: #define PCI_X_COM_R ( (u16_t) 0x0042 )
48: // Message Data Register
49: #define MSG_DATA_R ( (u16_t) 0x0064 )
50: // PCI misc host contrl register
51: #define PCI_MISC_HCTRL_R ( (u16_t) 0x0068 )
52: // DMA Read/Write Control register
53: #define DMA_RW_CTRL_R ( (u16_t) 0x006c )
54: // PCI State register
55: #define PCI_STATE_R ( (u16_t) 0x0070 )
56: // PCI_Clock Control register
57: #define PCI_CLK_CTRL_R ( (u16_t) 0x0074 )
58: // Register Base Address Register
59: #define REG_BASE_ADDR_REG ( (u16_t) 0x0078 )
60: // Memory Window Base Address Register
61: #define MEM_BASE_ADDR_REG ( (u16_t) 0x007c )
62: // Register Data Register
63: #define REG_DATA_REG ( (u16_t) 0x0080 )
64: // Memory Window Data Register
65: #define MEM_DATA_REG ( (u16_t) 0x0084 )
66: // MAC Function register
67: #define MAC_FUNC_R ( (u16_t) 0x00b8 )
68: // Interrupt Mailbox 0 register
69: #define INT_MBX0_R ( (u16_t) 0x0204 )
70: // Ethernet MAC Mode register
71: #define ETH_MAC_MODE_R ( (u16_t) 0x0400 )
72: // Ethernet MAC Addresses registers
73: #define MAC_ADDR_OFFS_HI( idx ) ( (u16_t) ( (idx*2 + 0)*sizeof( u32_t ) + 0x0410 ) )
74: #define MAC_ADDR_OFFS_LO( idx ) ( (u16_t) ( (idx*2 + 1)*sizeof( u32_t ) + 0x0410 ) )
75: // Ethernet MAC Status register
76: #define ETH_MAC_STAT_R ( (u16_t) 0x0404 )
77: // Ethernet MAC Event Enable register
78: #define ETH_MAC_EVT_EN_R ( (u16_t) 0x0408 )
79: // Ethernet Transmit Random Backoff register
80: #define ETH_TX_RND_BO_R ( (u16_t) 0x0438 )
81: // Receive MTU Size register
82: #define RX_MTU_SIZE_R ( (u16_t) 0x043c )
83: // Transmit 1000BASE-X Auto Negotiation register
84: #define TX_1000BX_AUTONEG_R ( (u16_t) 0x0444 )
85: // Receive 1000BASE-X Auto Negotiation register
86: #define RX_1000BX_AUTONEG_R ( (u16_t) 0x0448 )
87: // MI Communication register
88: #define MI_COM_R ( (u16_t) 0x044c )
89: // MI Status Register
90: #define MI_STATUS_R ( (u16_t) 0x0450 )
91: // MI Mode register
92: #define MI_MODE_R ( (u16_t) 0x0454 )
93: // Transmit MAC Mode register
94: #define TX_MAC_MODE_R ( (u16_t) 0x045c )
95: // Transmit MAC Length register
96: #define TX_MAC_LEN_R ( (u16_t) 0x0464 )
97: // Receive MAC Mode register
98: #define RX_MAC_MODE_R ( (u16_t) 0x0468 )
99: // MAC Hash 0 register* VPD Config:
100: #define MAC_HASH0_R ( (u16_t) 0x0470 )
101: // MAC Hash 1 register
102: #define MAC_HASH1_R ( (u16_t) 0x0474 )
103: // MAC Hash 2 register
104: #define MAC_HASH2_R ( (u16_t) 0x0478 )
105: // MAC Hash 3 register
106: #define MAC_HASH3_R ( (u16_t) 0x047c )
107: // Receive Rules Control register
108: #define RX_RULE_CTRL_R( idx ) ( (u16_t) ( idx*8 + 0x0480 ) )
109: // Receive Rules Value register
110: #define RX_RULE_VAL_R( idx ) ( (u16_t) ( idx*8 + 0x0484 ) )
111: // Receive Rules Configuration register
112: #define RX_RULE_CFG_R ( (u16_t) 0x0500 )
113: // Low Watermark Max Receive Frames register
114: #define LOW_WMARK_MAX_RXFRAM_R ( (u16_t) 0x0504 )
115: // SerDes Control Register
116: #define SERDES_CTRL_R ( (u16_t) 0x0590 )
117: // Hardware Auto Negotiation Control Register
118: #define HW_AUTONEG_CTRL_R ( (u16_t) 0x05B0 )
119: // Hardware Auto Negotiation Status Register
120: #define HW_AUTONEG_STAT_R ( (u16_t) 0x05B4 )
121: // Send Data Initiator Mode register
122: #define TX_DAT_INIT_MODE_R ( (u16_t) 0x0c00 )
123: // Send Data Completion Mode register
124: #define TX_DAT_COMPL_MODE_R ( (u16_t) 0x1000 )
125: // Send BD Ring Selector Mode register
126: #define TX_BD_RING_SEL_MODE_R ( (u16_t) 0x1400 )
127: // Send BD Initiator Mode register
128: #define TX_BD_INIT_MODE_R ( (u16_t) 0x1800 )
129: // Send BD Completion Mode register
130: #define TX_BD_COMPL_MODE_R ( (u16_t) 0x1c00 )
131: // Receive List Placement Mode register
132: #define RX_LST_PLACE_MODE_R ( (u16_t) 0x2000 )
133: // Receive List Placement Configuration register
134: #define RX_LST_PLACE_CFG_R ( (u16_t) 0x2010 )
135: // Receive List Placement Statistics Enable Mask register
136: #define RX_LST_PLACE_STAT_EN_R ( (u16_t) 0x2018 )
137: // Receive Data & Receive BD Initiator Mode register
138: #define RX_DAT_BD_INIT_MODE_R ( (u16_t) 0x2400 )
139: // Receive Data Completion Mode register
140: #define RX_DAT_COMPL_MODE_R ( (u16_t) 0x2800 )
141: // Receive BD Initiator Mode register
142: #define RX_BD_INIT_MODE_R ( (u16_t) 0x2c00 )
143: // Standard Receive Producer Ring Replenish Threshhold register
144: #define STD_RXPR_REP_THR_R ( (u16_t) 0x2c18 )
145: // Receive BD Completion Mode register
146: #define RX_BD_COMPL_MODE_R ( (u16_t) 0x3000 )
147: // Receive List Selector Mode register
148: #define RX_LST_SEL_MODE_R ( (u16_t) 0x3400 )
149: // MBUF Cluster Free Mode register
150: #define MBUF_CLSTR_FREE_MODE_R ( (u16_t) 0x3800 )
151: // Host Coalescing Mode register
152: #define HOST_COAL_MODE_R ( (u16_t) 0x3c00 )
153: // Receive Coalescing Ticks register
154: #define RX_COAL_TICKS_R ( (u16_t) 0x3c08 )
155: // Send Coalescing Ticks register
156: #define TX_COAL_TICKS_R ( (u16_t) 0x3c0c )
157: // Receive Max Coalesced BD Count register
158: #define RX_COAL_MAX_BD_R ( (u16_t) 0x3c10 )
159: // Send Max Coalesced BD Count register
160: #define TX_COAL_MAX_BD_R ( (u16_t) 0x3c14 )
161: // Receive Coalescing Ticks During Int register
162: #define RX_COAL_TICKS_INT_R ( (u16_t) 0x3c18 )
163: // Send Coalescing Ticks During Int register
164: #define TX_COAL_TICKS_INT_R ( (u16_t) 0x3c1c )
165: // Receive Max Coalesced BD Count During Int register
166: #define RX_COAL_MAX_BD_INT_R ( (u16_t) 0x3c18 )
167: // Send Max Coalesced BD Count During Int register
168: #define TX_COAL_MAX_BD_INT_R ( (u16_t) 0x3c1c )
169: // Statistics Ticks Counter register
170: #define STAT_TICK_CNT_R ( (u16_t) 0x3c28 )
171: // Status Block Host Address Low register
172: #define STB_HOST_ADDR_HI_R ( (u16_t) 0x3c38 )
173: // Status Block Host Address High register
174: #define STB_HOST_ADDR_LO_R ( (u16_t) 0x3c3c )
175: // Statistsics Base Adress register
176: #define STAT_NIC_ADDR_R ( (u16_t) 0x3c40 )
177: // Status Block Base Address register
178: #define STB_NIC_ADDR_R ( (u16_t) 0x3c44 )
179: // Memory Arbiter Mode register
180: #define MEMARB_MODE_R ( (u16_t) 0x4000 )
181: // Buffer Manager Mode register
182: #define BUF_MAN_MODE_R ( (u16_t) 0x4400 )
183: // MBuf Pool Address register
184: #define MBUF_POOL_ADDR_R ( (u16_t) 0x4408 )
185: // MBuf Pool Length register
186: #define MBUF_POOL_LEN_R ( (u16_t) 0x440c )
187: // Read DMA Mbuf Low Watermark register
188: #define DMA_RMBUF_LOW_WMARK_R ( (u16_t) 0x4410 )
189: // MAC Rx Mbuf Low Watermark register
190: #define MAC_RXMBUF_LOW_WMARK_R ( (u16_t) 0x4414 )
191: // Mbuf High Watermark register
192: #define MBUF_HIGH_WMARK_R ( (u16_t) 0x4418 )
193: // DMA Descriptor Pool Address register
194: #define DMA_DESC_POOL_ADDR_R ( (u16_t) 0x442c )
195: // DMA Descriptor Pool Length register
196: #define DMA_DESC_POOL_LEN_R ( (u16_t) 0x4430 )
197: // DMA Descriptor Low Watermark register
198: #define DMA_DESC_LOW_WM_R ( (u16_t) 0x4434 )
199: // DMA Descriptor HIGH Watermark register
200: #define DMA_DESC_HIGH_WM_R ( (u16_t) 0x4438 )
201: // Read DMA Mode register
202: #define RD_DMA_MODE_R ( (u16_t) 0x4800 )
203: // Write DMA Mode register
204: #define WR_DMA_MODE_R ( (u16_t) 0x4c00 )
205: // FTQ Reset register
206: #define FTQ_RES_R ( (u16_t) 0x5c00 )
207: // MSI Mode register
208: #define MSI_MODE_R ( (u16_t) 0x6000 )
209: // DMA completion Mode register
210: #define DMA_COMPL_MODE_R ( (u16_t) 0x6400 )
211: // Mode Control register
212: #define MODE_CTRL_R ( (u16_t) 0x6800 )
213: // Misc Configuration register
214: #define MISC_CFG_R ( (u16_t) 0x6804 )
215: // Misc Local Control register
216: #define MISC_LOCAL_CTRL_R ( (u16_t) 0x6808 )
217: // RX-Risc Mode Register
218: #define RX_CPU_MODE_R ( (u16_t) 0x5000 )
219: // RX-Risc State Register
220: #define RX_CPU_STATE_R ( (u16_t) 0x5004 )
221: // RX-Risc Program Counter
222: #define RX_CPU_PC_R ( (u16_t) 0x501c )
223: // RX-Risc Event Register
224: #define RX_CPU_EVENT_R ( (u16_t) 0x6810 )
225: // MDI Control register
226: #define MDI_CTRL_R ( (u16_t) 0x6844 )
227: // WOL Mode register
228: #define WOL_MODE_R ( (u16_t) 0x6880 )
229: // WOL Config register
230: #define WOL_CFG_R ( (u16_t) 0x6884 )
231: // WOL Status register
232: #define WOL_STATUS_R ( (u16_t) 0x6888 )
233:
234: // ASF Control register
235: #define ASF_CTRL_R ( (u16_t) 0x6c00 )
236: // ASF Watchdog Timer register
237: #define ASF_WATCHDOG_TIMER_R ( (u16_t) 0x6c0c )
238: // ASF Heartbeat Timer register
239: #define ASF_HEARTBEAT_TIMER_R ( (u16_t) 0x6c10 )
240: // Poll ASF Timer register
241: #define ASF_POLL_TIMER_R ( (u16_t) 0x6c14 )
242: // Poll Legacy Timer register
243: #define POLL_LEGACY_TIMER_R ( (u16_t) 0x6c18 )
244: // Retransmission Timer register
245: #define RETRANSMISSION_TIMER_R ( (u16_t) 0x6c1c )
246: // Time Stamp Counter register
247: #define TIME_STAMP_COUNTER_R ( (u16_t) 0x6c20 )
248:
249: // NVM Command register
250: #define NVM_COM_R ( (u16_t) 0x7000 )
251: // NVM Write register
252: #define NVM_WRITE_R ( (u16_t) 0x7008 )
253: // NVM Address register
254: #define NVM_ADDR_R ( (u16_t) 0x700c )
255: // NVM Read registertg3_phy_copper_begin
256: #define NVM_READ_R ( (u16_t) 0x7010 )
257: // NVM Access register
258: #define NVM_ACC_R ( (u16_t) 0x7024 )
259: // NVM Config 1 register
260: #define NVM_CFG1_R ( (u16_t) 0x7014 )
261: // Software arbitration register
262: #define SW_ARB_R ( (u16_t) 0x7020 )
263:
264: /*
265: * useful def's
266: */
267: #define rd08(a) (u08_t) snk_kernel_interface->io_read((void*)(a),1)
268: #define rd16(a) (u16_t) snk_kernel_interface->io_read((void*)(a),2)
269: #define rd32(a) (u32_t) snk_kernel_interface->io_read((void*)(a),4)
270: #define wr08(a,v) snk_kernel_interface->io_write((void*)(a),(u32_t)(v),1)
271: #define wr16(a,v) snk_kernel_interface->io_write((void*)(a),(u32_t)(v),2)
272: #define wr32(a,v) snk_kernel_interface->io_write((void*)(a),(u32_t)(v),4)
273: #define printk snk_kernel_interface->print
274: #define us_delay snk_kernel_interface->us_delay
275: #define ms_delay snk_kernel_interface->ms_delay
276:
277: #define BIT08( bit ) ( (u08_t) 0x1 << (bit) )
278: #define BIT16( bit ) ( (u16_t) 0x1 << (bit) )
279: #define BIT32( bit ) ( (u32_t) 0x1 << (bit) )
280:
281: /*
282: * type definition
283: */
284:
285: extern snk_kernel_t *snk_kernel_interface;
286:
287:
288: /*
289: * inline functions
290: */
291: // memory barrier function implementation
292: static inline void
293: mb()
294: {
295: asm volatile( "sync;" );
296: }
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