--- qemu/roms/SLOF/include/ppcp7/cache.h	2018/04/24 18:59:09	1.1.1.1
+++ qemu/roms/SLOF/include/ppcp7/cache.h	2018/04/24 19:45:28	1.1.1.2
@@ -17,16 +17,45 @@
 #include <stdint.h>
 
 // XXX FIXME: Use proper CI load/store */
-#define cache_inhibited_access(type,name) 			\
-	static inline type ci_read_##name(type * addr)		\
-	{							\
-		type val;					\
-		val = *addr;					\
-		return val;					\
-	}							\
-	static inline void ci_write_##name(type * addr, type data)	\
-	{							\
-		*addr = data;					\
+#define cache_inhibited_access(type,size) 				\
+	static inline type ci_read_##size(type * addr)			\
+	{								\
+		register uint64_t arg0 asm ("r3");			\
+		register uint64_t arg1 asm ("r4");			\
+		register uint64_t arg2 asm ("r5");			\
+									\
+		arg0 = 0x3c; /* H_LOGICAL_CI_LOAD*/			\
+		arg1 = size / 8;					\
+		arg2 = (uint64_t)addr;					\
+									\
+		asm volatile(						\
+			".long	0x44000022 \n"  /* HVCALL */		\
+			: "=&r" (arg0), "=&r"(arg1), "=&r"(arg2)	\
+			: "0"(arg0), "1"(arg1), "2"(arg2)		\
+			: "r0", "r6", "r7", "r8", "r9", "r10", "r11",	\
+			  "r12", "memory", "cr0", "cr1", "cr5",		\
+			  "cr6", "cr7", "ctr", "xer");			\
+		return arg0 ? -1 : arg1;				\
+	}								\
+	static inline void ci_write_##size(type * addr, type data)	\
+	{								\
+		register uint64_t arg0 asm ("r3");			\
+		register uint64_t arg1 asm ("r4");			\
+		register uint64_t arg2 asm ("r5");			\
+		register uint64_t arg3 asm ("r6");			\
+									\
+		arg0 = 0x40; /* H_LOGICAL_CI_STORE*/			\
+		arg1 = size / 8;					\
+		arg2 = (uint64_t)addr;					\
+		arg3 = (uint64_t)data;					\
+									\
+		asm volatile(						\
+			".long	0x44000022 \n"  /* HVCALL */		\
+			: "=&r"(arg0),"=&r"(arg1),"=&r"(arg2),"=&r"(arg3) \
+			: "0"(arg0),"1"(arg1),"2"(arg2),"3"(arg3)	\
+			: "r0", "r7", "r8", "r9", "r10", "r11",		\
+			  "r12", "memory", "cr0", "cr1", "cr5",		\
+			  "cr6", "cr7", "ctr", "xer");			\
 	}
 
 cache_inhibited_access(uint8_t,  8)