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Annotation of qemu/roms/SLOF/include/ppcp7/cache.h, revision 1.1

1.1     ! root        1: /******************************************************************************
        !             2:  * Copyright (c) 2004, 2008 IBM Corporation
        !             3:  * All rights reserved.
        !             4:  * This program and the accompanying materials
        !             5:  * are made available under the terms of the BSD License
        !             6:  * which accompanies this distribution, and is available at
        !             7:  * http://www.opensource.org/licenses/bsd-license.php
        !             8:  *
        !             9:  * Contributors:
        !            10:  *     IBM Corporation - initial implementation
        !            11:  *****************************************************************************/
        !            12: 
        !            13: #ifndef __CACHE_H
        !            14: #define __CACHE_H
        !            15: 
        !            16: #include <cpu.h>
        !            17: #include <stdint.h>
        !            18: 
        !            19: // XXX FIXME: Use proper CI load/store */
        !            20: #define cache_inhibited_access(type,name)                      \
        !            21:        static inline type ci_read_##name(type * addr)          \
        !            22:        {                                                       \
        !            23:                type val;                                       \
        !            24:                val = *addr;                                    \
        !            25:                return val;                                     \
        !            26:        }                                                       \
        !            27:        static inline void ci_write_##name(type * addr, type data)      \
        !            28:        {                                                       \
        !            29:                *addr = data;                                   \
        !            30:        }
        !            31: 
        !            32: cache_inhibited_access(uint8_t,  8)
        !            33: cache_inhibited_access(uint16_t, 16)
        !            34: cache_inhibited_access(uint32_t, 32)
        !            35: cache_inhibited_access(uint64_t, 64)
        !            36: 
        !            37: static inline uint16_t bswap16_load(uint64_t addr)
        !            38: {
        !            39:        unsigned int val;
        !            40:        asm volatile ("lhbrx %0, 0, %1":"=r" (val):"r"(addr));
        !            41:        return val;
        !            42: }
        !            43: 
        !            44: static inline uint32_t bswap32_load(uint64_t addr)
        !            45: {
        !            46:        unsigned int val;
        !            47:        asm volatile ("lwbrx %0, 0, %1":"=r" (val):"r"(addr));
        !            48:        return val;
        !            49: }
        !            50: 
        !            51: static inline void bswap16_store(uint64_t addr, uint16_t val)
        !            52: {
        !            53:        asm volatile ("sthbrx %0, 0, %1"::"r" (val), "r"(addr));
        !            54: }
        !            55: 
        !            56: static inline void bswap32_store(uint64_t addr, uint32_t val)
        !            57: {
        !            58:        asm volatile ("stwbrx %0, 0, %1"::"r" (val), "r"(addr));
        !            59: }
        !            60: 
        !            61: #endif /* __CACHE_H */
        !            62: 

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