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1.1 root 1: /******************************************************************************
2: * Copyright (c) 2004, 2008 IBM Corporation
3: * All rights reserved.
4: * This program and the accompanying materials
5: * are made available under the terms of the BSD License
6: * which accompanies this distribution, and is available at
7: * http://www.opensource.org/licenses/bsd-license.php
8: *
9: * Contributors:
10: * IBM Corporation - initial implementation
11: *****************************************************************************/
12:
13: #ifndef __CACHE_H
14: #define __CACHE_H
15:
16: #include <cpu.h>
17: #include <stdint.h>
18:
19: // XXX FIXME: Use proper CI load/store */
1.1.1.2 ! root 20: #define cache_inhibited_access(type,size) \
! 21: static inline type ci_read_##size(type * addr) \
! 22: { \
! 23: register uint64_t arg0 asm ("r3"); \
! 24: register uint64_t arg1 asm ("r4"); \
! 25: register uint64_t arg2 asm ("r5"); \
! 26: \
! 27: arg0 = 0x3c; /* H_LOGICAL_CI_LOAD*/ \
! 28: arg1 = size / 8; \
! 29: arg2 = (uint64_t)addr; \
! 30: \
! 31: asm volatile( \
! 32: ".long 0x44000022 \n" /* HVCALL */ \
! 33: : "=&r" (arg0), "=&r"(arg1), "=&r"(arg2) \
! 34: : "0"(arg0), "1"(arg1), "2"(arg2) \
! 35: : "r0", "r6", "r7", "r8", "r9", "r10", "r11", \
! 36: "r12", "memory", "cr0", "cr1", "cr5", \
! 37: "cr6", "cr7", "ctr", "xer"); \
! 38: return arg0 ? -1 : arg1; \
! 39: } \
! 40: static inline void ci_write_##size(type * addr, type data) \
! 41: { \
! 42: register uint64_t arg0 asm ("r3"); \
! 43: register uint64_t arg1 asm ("r4"); \
! 44: register uint64_t arg2 asm ("r5"); \
! 45: register uint64_t arg3 asm ("r6"); \
! 46: \
! 47: arg0 = 0x40; /* H_LOGICAL_CI_STORE*/ \
! 48: arg1 = size / 8; \
! 49: arg2 = (uint64_t)addr; \
! 50: arg3 = (uint64_t)data; \
! 51: \
! 52: asm volatile( \
! 53: ".long 0x44000022 \n" /* HVCALL */ \
! 54: : "=&r"(arg0),"=&r"(arg1),"=&r"(arg2),"=&r"(arg3) \
! 55: : "0"(arg0),"1"(arg1),"2"(arg2),"3"(arg3) \
! 56: : "r0", "r7", "r8", "r9", "r10", "r11", \
! 57: "r12", "memory", "cr0", "cr1", "cr5", \
! 58: "cr6", "cr7", "ctr", "xer"); \
1.1 root 59: }
60:
61: cache_inhibited_access(uint8_t, 8)
62: cache_inhibited_access(uint16_t, 16)
63: cache_inhibited_access(uint32_t, 32)
64: cache_inhibited_access(uint64_t, 64)
65:
66: static inline uint16_t bswap16_load(uint64_t addr)
67: {
68: unsigned int val;
69: asm volatile ("lhbrx %0, 0, %1":"=r" (val):"r"(addr));
70: return val;
71: }
72:
73: static inline uint32_t bswap32_load(uint64_t addr)
74: {
75: unsigned int val;
76: asm volatile ("lwbrx %0, 0, %1":"=r" (val):"r"(addr));
77: return val;
78: }
79:
80: static inline void bswap16_store(uint64_t addr, uint16_t val)
81: {
82: asm volatile ("sthbrx %0, 0, %1"::"r" (val), "r"(addr));
83: }
84:
85: static inline void bswap32_store(uint64_t addr, uint32_t val)
86: {
87: asm volatile ("stwbrx %0, 0, %1"::"r" (val), "r"(addr));
88: }
89:
90: #endif /* __CACHE_H */
91:
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