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1.1 root 1: #ifndef _QIB7322_H
2: #define _QIB7322_H
3:
4: /*
5: * Copyright (C) 2009 Michael Brown <[email protected]>.
6: *
7: * This program is free software; you can redistribute it and/or
8: * modify it under the terms of the GNU General Public License as
9: * published by the Free Software Foundation; either version 2 of the
10: * License, or any later version.
11: *
12: * This program is distributed in the hope that it will be useful, but
13: * WITHOUT ANY WARRANTY; without even the implied warranty of
14: * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15: * General Public License for more details.
16: *
17: * You should have received a copy of the GNU General Public License
18: * along with this program; if not, write to the Free Software
19: * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
20: */
21:
22: FILE_LICENCE ( GPL2_OR_LATER );
23:
24: /**
25: * @file
26: *
27: * QLogic QIB7322 Infiniband HCA
28: *
29: */
30:
31: #define BITOPS_LITTLE_ENDIAN
32: #include <ipxe/bitops.h>
33: #include "qib_7322_regs.h"
34:
35: /** A QIB7322 GPIO register */
36: struct QIB_7322_GPIO_pb {
37: pseudo_bit_t GPIO[16];
38: pseudo_bit_t Reserved[48];
39: };
40: struct QIB_7322_GPIO {
41: PSEUDO_BIT_STRUCT ( struct QIB_7322_GPIO_pb );
42: };
43:
44: /** A QIB7322 general scalar register */
45: struct QIB_7322_scalar_pb {
46: pseudo_bit_t Value[64];
47: };
48: struct QIB_7322_scalar {
49: PSEUDO_BIT_STRUCT ( struct QIB_7322_scalar_pb );
50: };
51:
52: /** QIB7322 feature mask */
53: struct QIB_7322_feature_mask_pb {
54: pseudo_bit_t Port0_Link_Speed_Supported[3];
55: pseudo_bit_t Port1_Link_Speed_Supported[3];
56: pseudo_bit_t _unused_0[58];
57: };
58: struct QIB_7322_feature_mask {
59: PSEUDO_BIT_STRUCT ( struct QIB_7322_feature_mask_pb );
60: };
61:
62: /** QIB7322 send per-buffer control word */
63: struct QIB_7322_SendPbc_pb {
64: pseudo_bit_t LengthP1_toibc[11];
65: pseudo_bit_t Reserved1[4];
66: pseudo_bit_t LengthP1_trigger[11];
67: pseudo_bit_t Reserved2[3];
68: pseudo_bit_t TestEbp[1];
69: pseudo_bit_t Test[1];
70: pseudo_bit_t Intr[1];
71: pseudo_bit_t StaticRateControlCnt[14];
72: pseudo_bit_t Reserved3[12];
73: pseudo_bit_t Port[1];
74: pseudo_bit_t VLane[3];
75: pseudo_bit_t Reserved4[1];
76: pseudo_bit_t VL15[1];
77: };
78: struct QIB_7322_SendPbc {
79: PSEUDO_BIT_STRUCT ( struct QIB_7322_SendPbc_pb );
80: };
81:
82: /** QIB7322 send buffer availability */
83: struct QIB_7322_SendBufAvail_pb {
84: pseudo_bit_t InUseCheck[162][2];
85: pseudo_bit_t Reserved[60];
86: };
87: struct QIB_7322_SendBufAvail {
88: PSEUDO_BIT_STRUCT ( struct QIB_7322_SendBufAvail_pb );
89: };
90:
91: /** DMA alignment for send buffer availability */
92: #define QIB7322_SENDBUFAVAIL_ALIGN 64
93:
94: /** QIB7322 port-specific receive control */
95: struct QIB_7322_RcvCtrl_P_pb {
96: pseudo_bit_t ContextEnable[18];
97: pseudo_bit_t _unused_1[21];
98: pseudo_bit_t RcvIBPortEnable[1];
99: pseudo_bit_t RcvQPMapEnable[1];
100: pseudo_bit_t RcvPartitionKeyDisable[1];
101: pseudo_bit_t RcvResetCredit[1];
102: pseudo_bit_t _unused_2[21];
103: };
104: struct QIB_7322_RcvCtrl_P {
105: PSEUDO_BIT_STRUCT ( struct QIB_7322_RcvCtrl_P_pb );
106: };
107:
108: /** A QIB7322 eager receive descriptor */
109: struct QIB_7322_RcvEgr_pb {
110: pseudo_bit_t Addr[37];
111: pseudo_bit_t BufSize[3];
112: pseudo_bit_t Reserved[24];
113: };
114: struct QIB_7322_RcvEgr {
115: PSEUDO_BIT_STRUCT ( struct QIB_7322_RcvEgr_pb );
116: };
117:
118: /** QIB7322 receive header flags */
119: struct QIB_7322_RcvHdrFlags_pb {
120: pseudo_bit_t PktLen[11];
121: pseudo_bit_t RcvType[3];
122: pseudo_bit_t SoftB[1];
123: pseudo_bit_t SoftA[1];
124: pseudo_bit_t EgrIndex[12];
125: pseudo_bit_t Reserved1[3];
126: pseudo_bit_t UseEgrBfr[1];
127: pseudo_bit_t RcvSeq[4];
128: pseudo_bit_t HdrqOffset[11];
129: pseudo_bit_t Reserved2[8];
130: pseudo_bit_t IBErr[1];
131: pseudo_bit_t MKErr[1];
132: pseudo_bit_t TIDErr[1];
133: pseudo_bit_t KHdrErr[1];
134: pseudo_bit_t MTUErr[1];
135: pseudo_bit_t LenErr[1];
136: pseudo_bit_t ParityErr[1];
137: pseudo_bit_t VCRCErr[1];
138: pseudo_bit_t ICRCErr[1];
139: };
140: struct QIB_7322_RcvHdrFlags {
141: PSEUDO_BIT_STRUCT ( struct QIB_7322_RcvHdrFlags_pb );
142: };
143:
144: /** QIB7322 DDS tuning parameters */
145: struct QIB_7322_IBSD_DDS_MAP_TABLE_pb {
146: pseudo_bit_t Pre[3];
147: pseudo_bit_t PreXtra[2];
148: pseudo_bit_t Post[4];
149: pseudo_bit_t Main[5];
150: pseudo_bit_t Amp[4];
151: pseudo_bit_t _unused_0[46];
152: };
153: struct QIB_7322_IBSD_DDS_MAP_TABLE {
154: PSEUDO_BIT_STRUCT ( struct QIB_7322_IBSD_DDS_MAP_TABLE_pb );
155: };
156:
157: /** QIB7322 memory BAR size */
158: #define QIB7322_BAR0_SIZE 0x400000
159:
160: /** QIB7322 base port number */
161: #define QIB7322_PORT_BASE 1
162:
163: /** QIB7322 maximum number of ports */
164: #define QIB7322_MAX_PORTS 2
165:
166: /** QIB7322 maximum width */
167: #define QIB7322_MAX_WIDTH 4
168:
169: /** QIB7322 board identifiers */
170: enum qib7322_board_id {
171: QIB7322_BOARD_QLE7342_EMULATION = 0,
172: QIB7322_BOARD_QLE7340 = 1,
173: QIB7322_BOARD_QLE7342 = 2,
174: QIB7322_BOARD_QMI7342 = 3,
175: QIB7322_BOARD_QMH7342_UNSUPPORTED = 4,
176: QIB7322_BOARD_QME7342 = 5,
177: QIB7322_BOARD_QMH7342 = 6,
178: QIB7322_BOARD_QLE7342_TEST = 15,
179: };
180:
181: /** QIB7322 I2C SCL line GPIO number */
182: #define QIB7322_GPIO_SCL 0
183:
184: /** QIB7322 I2C SDA line GPIO number */
185: #define QIB7322_GPIO_SDA 1
186:
187: /** GUID offset within EEPROM */
188: #define QIB7322_EEPROM_GUID_OFFSET 3
189:
190: /** GUID size within EEPROM */
191: #define QIB7322_EEPROM_GUID_SIZE 8
192:
193: /** Board serial number offset within EEPROM */
194: #define QIB7322_EEPROM_SERIAL_OFFSET 12
195:
196: /** Board serial number size within EEPROM */
197: #define QIB7322_EEPROM_SERIAL_SIZE 12
198:
199: /** QIB7322 small send buffer size */
200: #define QIB7322_SMALL_SEND_BUF_SIZE 4096
201:
202: /** QIB7322 small send buffer starting index */
203: #define QIB7322_SMALL_SEND_BUF_START 0
204:
205: /** QIB7322 small send buffer count */
206: #define QIB7322_SMALL_SEND_BUF_COUNT 128
207:
208: /** QIB7322 large send buffer size */
209: #define QIB7322_LARGE_SEND_BUF_SIZE 8192
210:
211: /** QIB7322 large send buffer starting index */
212: #define QIB7322_LARGE_SEND_BUF_START 128
213:
214: /** QIB7322 large send buffer count */
215: #define QIB7322_LARGE_SEND_BUF_COUNT 32
216:
217: /** QIB7322 VL15 port 0 send buffer starting index */
218: #define QIB7322_VL15_PORT0_SEND_BUF_START 160
219:
220: /** QIB7322 VL15 port 0 send buffer count */
221: #define QIB7322_VL15_PORT0_SEND_BUF_COUNT 1
222:
223: /** QIB7322 VL15 port 0 send buffer size */
224: #define QIB7322_VL15_PORT0_SEND_BUF_SIZE 8192
225:
226: /** QIB7322 VL15 port 0 send buffer starting index */
227: #define QIB7322_VL15_PORT1_SEND_BUF_START 161
228:
229: /** QIB7322 VL15 port 0 send buffer count */
230: #define QIB7322_VL15_PORT1_SEND_BUF_COUNT 1
231:
232: /** QIB7322 VL15 port 0 send buffer size */
233: #define QIB7322_VL15_PORT1_SEND_BUF_SIZE 8192
234:
235: /** Number of small send buffers used
236: *
237: * This is a policy decision. Must be less than or equal to the total
238: * number of small send buffers supported by the hardware
239: * (QIB7322_SMALL_SEND_BUF_COUNT).
240: */
241: #define QIB7322_SMALL_SEND_BUF_USED 32
242:
243: /** Number of contexts (including kernel context)
244: *
245: * This is a policy decision. Must be 6, 10 or 18.
246: */
247: #define QIB7322_NUM_CONTEXTS 6
248:
249: /** ContextCfg values for different numbers of contexts */
250: enum qib7322_contextcfg {
251: QIB7322_CONTEXTCFG_6CTX = 0,
252: QIB7322_CONTEXTCFG_10CTX = 1,
253: QIB7322_CONTEXTCFG_18CTX = 2,
254: };
255:
256: /** ContextCfg values for different numbers of contexts */
257: #define QIB7322_EAGER_ARRAY_SIZE_6CTX_KERNEL 1024
258: #define QIB7322_EAGER_ARRAY_SIZE_6CTX_USER 4096
259: #define QIB7322_EAGER_ARRAY_SIZE_10CTX_KERNEL 1024
260: #define QIB7322_EAGER_ARRAY_SIZE_10CTX_USER 2048
261: #define QIB7322_EAGER_ARRAY_SIZE_18CTX_KERNEL 1024
262: #define QIB7322_EAGER_ARRAY_SIZE_18CTX_USER 1024
263:
264: /** Eager buffer required alignment */
265: #define QIB7322_EAGER_BUFFER_ALIGN 2048
266:
267: /** Eager buffer size encodings */
268: enum qib7322_eager_buffer_size {
269: QIB7322_EAGER_BUFFER_NONE = 0,
270: QIB7322_EAGER_BUFFER_2K = 1,
271: QIB7322_EAGER_BUFFER_4K = 2,
272: QIB7322_EAGER_BUFFER_8K = 3,
273: QIB7322_EAGER_BUFFER_16K = 4,
274: QIB7322_EAGER_BUFFER_32K = 5,
275: QIB7322_EAGER_BUFFER_64K = 6,
276: };
277:
278: /** Number of RX headers per context
279: *
280: * This is a policy decision.
281: */
282: #define QIB7322_RECV_HEADER_COUNT 8
283:
284: /** Maximum size of each RX header
285: *
286: * This is a policy decision. Must be divisible by 4.
287: */
288: #define QIB7322_RECV_HEADER_SIZE 96
289:
290: /** Total size of an RX header ring */
291: #define QIB7322_RECV_HEADERS_SIZE \
292: ( QIB7322_RECV_HEADER_SIZE * QIB7322_RECV_HEADER_COUNT )
293:
294: /** RX header alignment */
295: #define QIB7322_RECV_HEADERS_ALIGN 64
296:
297: /** RX payload size
298: *
299: * This is a policy decision. Must be a valid eager buffer size.
300: */
301: #define QIB7322_RECV_PAYLOAD_SIZE 2048
302:
303: /** Maximum number of credits per port
304: *
305: * 64kB of internal RX buffer space, in units of 64 bytes, split
306: * between two ports.
307: */
308: #define QIB7322_MAX_CREDITS ( ( 65536 / 64 ) / QIB7322_MAX_PORTS )
309:
310: /** Number of credits to advertise for VL15
311: *
312: * This is a policy decision. Using 9 credits allows for 9*64=576
313: * bytes, which is enough for two MADs.
314: */
315: #define QIB7322_MAX_CREDITS_VL15 9
316:
317: /** Number of credits to advertise for VL0
318: *
319: * This is a policy decision.
320: */
321: #define QIB7322_MAX_CREDITS_VL0 \
322: ( QIB7322_MAX_CREDITS - QIB7322_MAX_CREDITS_VL15 )
323:
324: /** QPN used for Infinipath Packets
325: *
326: * This is a policy decision. Must have bit 0 clear. Must not be a
327: * QPN that we will use.
328: */
329: #define QIB7322_QP_IDETH 0xdead0
330:
331: /** Maximum time for wait for AHB, in us */
332: #define QIB7322_AHB_MAX_WAIT_US 500
333:
334: /** QIB7322 AHB locations */
335: #define QIB7322_AHB_LOC_ADDRESS( _location ) ( (_location) & 0xffff )
336: #define QIB7322_AHB_LOC_TARGET( _location ) ( (_location) >> 16 )
337: #define QIB7322_AHB_CHAN_0 0
338: #define QIB7322_AHB_CHAN_1 1
339: #define QIB7322_AHB_PLL 2
340: #define QIB7322_AHB_CHAN_2 3
341: #define QIB7322_AHB_CHAN_3 4
342: #define QIB7322_AHB_SUBSYS 5
343: #define QIB7322_AHB_CHAN( _channel ) ( (_channel) + ( (_channel) >> 1 ) )
344: #define QIB7322_AHB_TARGET_0 2
345: #define QIB7322_AHB_TARGET_1 3
346: #define QIB7322_AHB_TARGET( _port ) ( (_port) + 2 )
347: #define QIB7322_AHB_LOCATION( _port, _channel, _register ) \
348: ( ( QIB7322_AHB_TARGET(_port) << 16 ) | \
349: ( QIB7322_AHB_CHAN(_channel) << 7 ) | \
350: ( (_register) << 1 ) )
351:
352: /** QIB7322 link states */
353: enum qib7322_link_state {
354: QIB7322_LINK_STATE_DOWN = 0,
355: QIB7322_LINK_STATE_INIT = 1,
356: QIB7322_LINK_STATE_ARM = 2,
357: QIB7322_LINK_STATE_ACTIVE = 3,
358: QIB7322_LINK_STATE_ACT_DEFER = 4,
359: };
360:
361: /** Maximum time to wait for link state changes, in us */
362: #define QIB7322_LINK_STATE_MAX_WAIT_US 20
363:
364: #endif /* _QIB7322_H */
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