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Annotation of qemu/roms/ipxe/src/drivers/net/ath5k/desc.h, revision 1.1

1.1     ! root        1: /*
        !             2:  * Copyright (c) 2004-2008 Reyk Floeter <[email protected]>
        !             3:  * Copyright (c) 2006-2008 Nick Kossifidis <[email protected]>
        !             4:  *
        !             5:  * Permission to use, copy, modify, and distribute this software for any
        !             6:  * purpose with or without fee is hereby granted, provided that the above
        !             7:  * copyright notice and this permission notice appear in all copies.
        !             8:  *
        !             9:  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
        !            10:  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
        !            11:  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
        !            12:  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
        !            13:  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
        !            14:  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
        !            15:  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
        !            16:  *
        !            17:  */
        !            18: 
        !            19: /*
        !            20:  * Internal RX/TX descriptor structures
        !            21:  * (rX: reserved fields possibily used by future versions of the ar5k chipset)
        !            22:  */
        !            23: 
        !            24: /*
        !            25:  * common hardware RX control descriptor
        !            26:  */
        !            27: struct ath5k_hw_rx_ctl {
        !            28:        u32     rx_control_0; /* RX control word 0 */
        !            29:        u32     rx_control_1; /* RX control word 1 */
        !            30: } __attribute__ ((packed));
        !            31: 
        !            32: /* RX control word 0 field/sflags */
        !            33: #define AR5K_DESC_RX_CTL0                      0x00000000
        !            34: 
        !            35: /* RX control word 1 fields/flags */
        !            36: #define AR5K_DESC_RX_CTL1_BUF_LEN              0x00000fff
        !            37: #define AR5K_DESC_RX_CTL1_INTREQ               0x00002000
        !            38: 
        !            39: /*
        !            40:  * common hardware RX status descriptor
        !            41:  * 5210/11 and 5212 differ only in the flags defined below
        !            42:  */
        !            43: struct ath5k_hw_rx_status {
        !            44:        u32     rx_status_0; /* RX status word 0 */
        !            45:        u32     rx_status_1; /* RX status word 1 */
        !            46: } __attribute__ ((packed));
        !            47: 
        !            48: /* 5210/5211 */
        !            49: /* RX status word 0 fields/flags */
        !            50: #define AR5K_5210_RX_DESC_STATUS0_DATA_LEN             0x00000fff
        !            51: #define AR5K_5210_RX_DESC_STATUS0_MORE                 0x00001000
        !            52: #define AR5K_5210_RX_DESC_STATUS0_RECEIVE_RATE         0x00078000
        !            53: #define AR5K_5210_RX_DESC_STATUS0_RECEIVE_RATE_S       15
        !            54: #define AR5K_5210_RX_DESC_STATUS0_RECEIVE_SIGNAL       0x07f80000
        !            55: #define AR5K_5210_RX_DESC_STATUS0_RECEIVE_SIGNAL_S     19
        !            56: #define AR5K_5210_RX_DESC_STATUS0_RECEIVE_ANTENNA      0x38000000
        !            57: #define AR5K_5210_RX_DESC_STATUS0_RECEIVE_ANTENNA_S    27
        !            58: 
        !            59: /* RX status word 1 fields/flags */
        !            60: #define AR5K_5210_RX_DESC_STATUS1_DONE                 0x00000001
        !            61: #define AR5K_5210_RX_DESC_STATUS1_FRAME_RECEIVE_OK     0x00000002
        !            62: #define AR5K_5210_RX_DESC_STATUS1_CRC_ERROR            0x00000004
        !            63: #define AR5K_5210_RX_DESC_STATUS1_FIFO_OVERRUN         0x00000008
        !            64: #define AR5K_5210_RX_DESC_STATUS1_DECRYPT_CRC_ERROR    0x00000010
        !            65: #define AR5K_5210_RX_DESC_STATUS1_PHY_ERROR            0x000000e0
        !            66: #define AR5K_5210_RX_DESC_STATUS1_PHY_ERROR_S          5
        !            67: #define AR5K_5210_RX_DESC_STATUS1_KEY_INDEX_VALID      0x00000100
        !            68: #define AR5K_5210_RX_DESC_STATUS1_KEY_INDEX            0x00007e00
        !            69: #define AR5K_5210_RX_DESC_STATUS1_KEY_INDEX_S          9
        !            70: #define AR5K_5210_RX_DESC_STATUS1_RECEIVE_TIMESTAMP    0x0fff8000
        !            71: #define AR5K_5210_RX_DESC_STATUS1_RECEIVE_TIMESTAMP_S  15
        !            72: #define AR5K_5210_RX_DESC_STATUS1_KEY_CACHE_MISS       0x10000000
        !            73: 
        !            74: /* 5212 */
        !            75: /* RX status word 0 fields/flags */
        !            76: #define AR5K_5212_RX_DESC_STATUS0_DATA_LEN             0x00000fff
        !            77: #define AR5K_5212_RX_DESC_STATUS0_MORE                 0x00001000
        !            78: #define AR5K_5212_RX_DESC_STATUS0_DECOMP_CRC_ERROR     0x00002000
        !            79: #define AR5K_5212_RX_DESC_STATUS0_RECEIVE_RATE         0x000f8000
        !            80: #define AR5K_5212_RX_DESC_STATUS0_RECEIVE_RATE_S       15
        !            81: #define AR5K_5212_RX_DESC_STATUS0_RECEIVE_SIGNAL       0x0ff00000
        !            82: #define AR5K_5212_RX_DESC_STATUS0_RECEIVE_SIGNAL_S     20
        !            83: #define AR5K_5212_RX_DESC_STATUS0_RECEIVE_ANTENNA      0xf0000000
        !            84: #define AR5K_5212_RX_DESC_STATUS0_RECEIVE_ANTENNA_S    28
        !            85: 
        !            86: /* RX status word 1 fields/flags */
        !            87: #define AR5K_5212_RX_DESC_STATUS1_DONE                 0x00000001
        !            88: #define AR5K_5212_RX_DESC_STATUS1_FRAME_RECEIVE_OK     0x00000002
        !            89: #define AR5K_5212_RX_DESC_STATUS1_CRC_ERROR            0x00000004
        !            90: #define AR5K_5212_RX_DESC_STATUS1_DECRYPT_CRC_ERROR    0x00000008
        !            91: #define AR5K_5212_RX_DESC_STATUS1_PHY_ERROR            0x00000010
        !            92: #define AR5K_5212_RX_DESC_STATUS1_MIC_ERROR            0x00000020
        !            93: #define AR5K_5212_RX_DESC_STATUS1_KEY_INDEX_VALID      0x00000100
        !            94: #define AR5K_5212_RX_DESC_STATUS1_KEY_INDEX            0x0000fe00
        !            95: #define AR5K_5212_RX_DESC_STATUS1_KEY_INDEX_S          9
        !            96: #define AR5K_5212_RX_DESC_STATUS1_RECEIVE_TIMESTAMP    0x7fff0000
        !            97: #define AR5K_5212_RX_DESC_STATUS1_RECEIVE_TIMESTAMP_S  16
        !            98: #define AR5K_5212_RX_DESC_STATUS1_KEY_CACHE_MISS       0x80000000
        !            99: 
        !           100: /*
        !           101:  * common hardware RX error descriptor
        !           102:  */
        !           103: struct ath5k_hw_rx_error {
        !           104:        u32     rx_error_0; /* RX status word 0 */
        !           105:        u32     rx_error_1; /* RX status word 1 */
        !           106: } __attribute__ ((packed));
        !           107: 
        !           108: /* RX error word 0 fields/flags */
        !           109: #define AR5K_RX_DESC_ERROR0                    0x00000000
        !           110: 
        !           111: /* RX error word 1 fields/flags */
        !           112: #define AR5K_RX_DESC_ERROR1_PHY_ERROR_CODE     0x0000ff00
        !           113: #define AR5K_RX_DESC_ERROR1_PHY_ERROR_CODE_S   8
        !           114: 
        !           115: /* PHY Error codes */
        !           116: #define AR5K_DESC_RX_PHY_ERROR_NONE            0x00
        !           117: #define AR5K_DESC_RX_PHY_ERROR_TIMING          0x20
        !           118: #define AR5K_DESC_RX_PHY_ERROR_PARITY          0x40
        !           119: #define AR5K_DESC_RX_PHY_ERROR_RATE            0x60
        !           120: #define AR5K_DESC_RX_PHY_ERROR_LENGTH          0x80
        !           121: #define AR5K_DESC_RX_PHY_ERROR_64QAM           0xa0
        !           122: #define AR5K_DESC_RX_PHY_ERROR_SERVICE         0xc0
        !           123: #define AR5K_DESC_RX_PHY_ERROR_TRANSMITOVR     0xe0
        !           124: 
        !           125: /*
        !           126:  * 5210/5211 hardware 2-word TX control descriptor
        !           127:  */
        !           128: struct ath5k_hw_2w_tx_ctl {
        !           129:        u32     tx_control_0; /* TX control word 0 */
        !           130:        u32     tx_control_1; /* TX control word 1 */
        !           131: } __attribute__ ((packed));
        !           132: 
        !           133: /* TX control word 0 fields/flags */
        !           134: #define AR5K_2W_TX_DESC_CTL0_FRAME_LEN         0x00000fff
        !           135: #define AR5K_2W_TX_DESC_CTL0_HEADER_LEN                0x0003f000 /*[5210 ?]*/
        !           136: #define AR5K_2W_TX_DESC_CTL0_HEADER_LEN_S      12
        !           137: #define AR5K_2W_TX_DESC_CTL0_XMIT_RATE         0x003c0000
        !           138: #define AR5K_2W_TX_DESC_CTL0_XMIT_RATE_S       18
        !           139: #define AR5K_2W_TX_DESC_CTL0_RTSENA            0x00400000
        !           140: #define AR5K_2W_TX_DESC_CTL0_CLRDMASK          0x01000000
        !           141: #define AR5K_2W_TX_DESC_CTL0_LONG_PACKET       0x00800000 /*[5210]*/
        !           142: #define AR5K_2W_TX_DESC_CTL0_VEOL              0x00800000 /*[5211]*/
        !           143: #define AR5K_2W_TX_DESC_CTL0_FRAME_TYPE                0x1c000000 /*[5210]*/
        !           144: #define AR5K_2W_TX_DESC_CTL0_FRAME_TYPE_S      26
        !           145: #define AR5K_2W_TX_DESC_CTL0_ANT_MODE_XMIT_5210        0x02000000
        !           146: #define AR5K_2W_TX_DESC_CTL0_ANT_MODE_XMIT_5211        0x1e000000
        !           147: 
        !           148: #define AR5K_2W_TX_DESC_CTL0_ANT_MODE_XMIT                     \
        !           149:                (ah->ah_version == AR5K_AR5210 ?                \
        !           150:                AR5K_2W_TX_DESC_CTL0_ANT_MODE_XMIT_5210 :       \
        !           151:                AR5K_2W_TX_DESC_CTL0_ANT_MODE_XMIT_5211)
        !           152: 
        !           153: #define AR5K_2W_TX_DESC_CTL0_ANT_MODE_XMIT_S   25
        !           154: #define AR5K_2W_TX_DESC_CTL0_INTREQ            0x20000000
        !           155: #define AR5K_2W_TX_DESC_CTL0_ENCRYPT_KEY_VALID 0x40000000
        !           156: 
        !           157: /* TX control word 1 fields/flags */
        !           158: #define AR5K_2W_TX_DESC_CTL1_BUF_LEN           0x00000fff
        !           159: #define AR5K_2W_TX_DESC_CTL1_MORE              0x00001000
        !           160: #define AR5K_2W_TX_DESC_CTL1_ENCRYPT_KEY_INDEX_5210    0x0007e000
        !           161: #define AR5K_2W_TX_DESC_CTL1_ENCRYPT_KEY_INDEX_5211    0x000fe000
        !           162: 
        !           163: #define AR5K_2W_TX_DESC_CTL1_ENCRYPT_KEY_INDEX                         \
        !           164:                        (ah->ah_version == AR5K_AR5210 ?                \
        !           165:                        AR5K_2W_TX_DESC_CTL1_ENCRYPT_KEY_INDEX_5210 :   \
        !           166:                        AR5K_2W_TX_DESC_CTL1_ENCRYPT_KEY_INDEX_5211)
        !           167: 
        !           168: #define AR5K_2W_TX_DESC_CTL1_ENCRYPT_KEY_INDEX_S       13
        !           169: #define AR5K_2W_TX_DESC_CTL1_FRAME_TYPE                0x00700000 /*[5211]*/
        !           170: #define AR5K_2W_TX_DESC_CTL1_FRAME_TYPE_S      20
        !           171: #define AR5K_2W_TX_DESC_CTL1_NOACK             0x00800000 /*[5211]*/
        !           172: #define AR5K_2W_TX_DESC_CTL1_RTS_DURATION      0xfff80000 /*[5210 ?]*/
        !           173: 
        !           174: /* Frame types */
        !           175: #define AR5K_AR5210_TX_DESC_FRAME_TYPE_NORMAL   0x00
        !           176: #define AR5K_AR5210_TX_DESC_FRAME_TYPE_ATIM     0x04
        !           177: #define AR5K_AR5210_TX_DESC_FRAME_TYPE_PSPOLL   0x08
        !           178: #define AR5K_AR5210_TX_DESC_FRAME_TYPE_NO_DELAY 0x0c
        !           179: #define AR5K_AR5210_TX_DESC_FRAME_TYPE_PIFS     0x10
        !           180: 
        !           181: /*
        !           182:  * 5212 hardware 4-word TX control descriptor
        !           183:  */
        !           184: struct ath5k_hw_4w_tx_ctl {
        !           185:        u32     tx_control_0; /* TX control word 0 */
        !           186: 
        !           187: #define AR5K_4W_TX_DESC_CTL0_FRAME_LEN         0x00000fff
        !           188: #define AR5K_4W_TX_DESC_CTL0_XMIT_POWER                0x003f0000
        !           189: #define AR5K_4W_TX_DESC_CTL0_XMIT_POWER_S      16
        !           190: #define AR5K_4W_TX_DESC_CTL0_RTSENA            0x00400000
        !           191: #define AR5K_4W_TX_DESC_CTL0_VEOL              0x00800000
        !           192: #define AR5K_4W_TX_DESC_CTL0_CLRDMASK          0x01000000
        !           193: #define AR5K_4W_TX_DESC_CTL0_ANT_MODE_XMIT     0x1e000000
        !           194: #define AR5K_4W_TX_DESC_CTL0_ANT_MODE_XMIT_S   25
        !           195: #define AR5K_4W_TX_DESC_CTL0_INTREQ            0x20000000
        !           196: #define AR5K_4W_TX_DESC_CTL0_ENCRYPT_KEY_VALID 0x40000000
        !           197: #define AR5K_4W_TX_DESC_CTL0_CTSENA            0x80000000
        !           198: 
        !           199:        u32     tx_control_1; /* TX control word 1 */
        !           200: 
        !           201: #define AR5K_4W_TX_DESC_CTL1_BUF_LEN           0x00000fff
        !           202: #define AR5K_4W_TX_DESC_CTL1_MORE              0x00001000
        !           203: #define AR5K_4W_TX_DESC_CTL1_ENCRYPT_KEY_INDEX 0x000fe000
        !           204: #define AR5K_4W_TX_DESC_CTL1_ENCRYPT_KEY_INDEX_S       13
        !           205: #define AR5K_4W_TX_DESC_CTL1_FRAME_TYPE                0x00f00000
        !           206: #define AR5K_4W_TX_DESC_CTL1_FRAME_TYPE_S      20
        !           207: #define AR5K_4W_TX_DESC_CTL1_NOACK             0x01000000
        !           208: #define AR5K_4W_TX_DESC_CTL1_COMP_PROC         0x06000000
        !           209: #define AR5K_4W_TX_DESC_CTL1_COMP_PROC_S       25
        !           210: #define AR5K_4W_TX_DESC_CTL1_COMP_IV_LEN       0x18000000
        !           211: #define AR5K_4W_TX_DESC_CTL1_COMP_IV_LEN_S     27
        !           212: #define AR5K_4W_TX_DESC_CTL1_COMP_ICV_LEN      0x60000000
        !           213: #define AR5K_4W_TX_DESC_CTL1_COMP_ICV_LEN_S    29
        !           214: 
        !           215:        u32     tx_control_2; /* TX control word 2 */
        !           216: 
        !           217: #define AR5K_4W_TX_DESC_CTL2_RTS_DURATION              0x00007fff
        !           218: #define AR5K_4W_TX_DESC_CTL2_DURATION_UPDATE_ENABLE    0x00008000
        !           219: #define AR5K_4W_TX_DESC_CTL2_XMIT_TRIES0               0x000f0000
        !           220: #define AR5K_4W_TX_DESC_CTL2_XMIT_TRIES0_S             16
        !           221: #define AR5K_4W_TX_DESC_CTL2_XMIT_TRIES1               0x00f00000
        !           222: #define AR5K_4W_TX_DESC_CTL2_XMIT_TRIES1_S             20
        !           223: #define AR5K_4W_TX_DESC_CTL2_XMIT_TRIES2               0x0f000000
        !           224: #define AR5K_4W_TX_DESC_CTL2_XMIT_TRIES2_S             24
        !           225: #define AR5K_4W_TX_DESC_CTL2_XMIT_TRIES3               0xf0000000
        !           226: #define AR5K_4W_TX_DESC_CTL2_XMIT_TRIES3_S             28
        !           227: 
        !           228:        u32     tx_control_3; /* TX control word 3 */
        !           229: 
        !           230: #define AR5K_4W_TX_DESC_CTL3_XMIT_RATE0                0x0000001f
        !           231: #define AR5K_4W_TX_DESC_CTL3_XMIT_RATE1                0x000003e0
        !           232: #define AR5K_4W_TX_DESC_CTL3_XMIT_RATE1_S      5
        !           233: #define AR5K_4W_TX_DESC_CTL3_XMIT_RATE2                0x00007c00
        !           234: #define AR5K_4W_TX_DESC_CTL3_XMIT_RATE2_S      10
        !           235: #define AR5K_4W_TX_DESC_CTL3_XMIT_RATE3                0x000f8000
        !           236: #define AR5K_4W_TX_DESC_CTL3_XMIT_RATE3_S      15
        !           237: #define AR5K_4W_TX_DESC_CTL3_RTS_CTS_RATE      0x01f00000
        !           238: #define AR5K_4W_TX_DESC_CTL3_RTS_CTS_RATE_S    20
        !           239: } __attribute__ ((packed));
        !           240: 
        !           241: /*
        !           242:  * Common TX status descriptor
        !           243:  */
        !           244: struct ath5k_hw_tx_status {
        !           245:        u32     tx_status_0; /* TX status word 0 */
        !           246:        u32     tx_status_1; /* TX status word 1 */
        !           247: } __attribute__ ((packed));
        !           248: 
        !           249: /* TX status word 0 fields/flags */
        !           250: #define AR5K_DESC_TX_STATUS0_FRAME_XMIT_OK     0x00000001
        !           251: #define AR5K_DESC_TX_STATUS0_EXCESSIVE_RETRIES 0x00000002
        !           252: #define AR5K_DESC_TX_STATUS0_FIFO_UNDERRUN     0x00000004
        !           253: #define AR5K_DESC_TX_STATUS0_FILTERED          0x00000008
        !           254: /*???
        !           255: #define AR5K_DESC_TX_STATUS0_RTS_FAIL_COUNT    0x000000f0
        !           256: #define AR5K_DESC_TX_STATUS0_RTS_FAIL_COUNT_S  4
        !           257: */
        !           258: #define AR5K_DESC_TX_STATUS0_SHORT_RETRY_COUNT 0x000000f0
        !           259: #define AR5K_DESC_TX_STATUS0_SHORT_RETRY_COUNT_S       4
        !           260: /*???
        !           261: #define AR5K_DESC_TX_STATUS0_DATA_FAIL_COUNT   0x00000f00
        !           262: #define AR5K_DESC_TX_STATUS0_DATA_FAIL_COUNT_S 8
        !           263: */
        !           264: #define AR5K_DESC_TX_STATUS0_LONG_RETRY_COUNT  0x00000f00
        !           265: #define AR5K_DESC_TX_STATUS0_LONG_RETRY_COUNT_S        8
        !           266: #define AR5K_DESC_TX_STATUS0_VIRT_COLL_COUNT   0x0000f000
        !           267: #define AR5K_DESC_TX_STATUS0_VIRT_COLL_COUNT_S 12
        !           268: #define AR5K_DESC_TX_STATUS0_SEND_TIMESTAMP    0xffff0000
        !           269: #define AR5K_DESC_TX_STATUS0_SEND_TIMESTAMP_S  16
        !           270: 
        !           271: /* TX status word 1 fields/flags */
        !           272: #define AR5K_DESC_TX_STATUS1_DONE              0x00000001
        !           273: #define AR5K_DESC_TX_STATUS1_SEQ_NUM           0x00001ffe
        !           274: #define AR5K_DESC_TX_STATUS1_SEQ_NUM_S         1
        !           275: #define AR5K_DESC_TX_STATUS1_ACK_SIG_STRENGTH  0x001fe000
        !           276: #define AR5K_DESC_TX_STATUS1_ACK_SIG_STRENGTH_S        13
        !           277: #define AR5K_DESC_TX_STATUS1_FINAL_TS_INDEX    0x00600000
        !           278: #define AR5K_DESC_TX_STATUS1_FINAL_TS_INDEX_S  21
        !           279: #define AR5K_DESC_TX_STATUS1_COMP_SUCCESS      0x00800000
        !           280: #define AR5K_DESC_TX_STATUS1_XMIT_ANTENNA      0x01000000
        !           281: 
        !           282: /*
        !           283:  * 5210/5211 hardware TX descriptor
        !           284:  */
        !           285: struct ath5k_hw_5210_tx_desc {
        !           286:        struct ath5k_hw_2w_tx_ctl       tx_ctl;
        !           287:        struct ath5k_hw_tx_status       tx_stat;
        !           288: } __attribute__ ((packed));
        !           289: 
        !           290: /*
        !           291:  * 5212 hardware TX descriptor
        !           292:  */
        !           293: struct ath5k_hw_5212_tx_desc {
        !           294:        struct ath5k_hw_4w_tx_ctl       tx_ctl;
        !           295:        struct ath5k_hw_tx_status       tx_stat;
        !           296: } __attribute__ ((packed));
        !           297: 
        !           298: /*
        !           299:  * common hardware RX descriptor
        !           300:  */
        !           301: struct ath5k_hw_all_rx_desc {
        !           302:        struct ath5k_hw_rx_ctl                  rx_ctl;
        !           303:        union {
        !           304:                struct ath5k_hw_rx_status       rx_stat;
        !           305:                struct ath5k_hw_rx_error        rx_err;
        !           306:        } u;
        !           307: } __attribute__ ((packed));
        !           308: 
        !           309: /*
        !           310:  * Atheros hardware descriptor
        !           311:  * This is read and written to by the hardware
        !           312:  */
        !           313: struct ath5k_desc {
        !           314:        u32     ds_link;        /* physical address of the next descriptor */
        !           315:        u32     ds_data;        /* physical address of data buffer (skb) */
        !           316: 
        !           317:        union {
        !           318:                struct ath5k_hw_5210_tx_desc    ds_tx5210;
        !           319:                struct ath5k_hw_5212_tx_desc    ds_tx5212;
        !           320:                struct ath5k_hw_all_rx_desc     ds_rx;
        !           321:        } ud;
        !           322: } __attribute__ ((packed));
        !           323: 
        !           324: #define AR5K_RXDESC_INTREQ     0x0020
        !           325: 
        !           326: #define AR5K_TXDESC_CLRDMASK   0x0001
        !           327: #define AR5K_TXDESC_NOACK      0x0002  /*[5211+]*/
        !           328: #define AR5K_TXDESC_RTSENA     0x0004
        !           329: #define AR5K_TXDESC_CTSENA     0x0008
        !           330: #define AR5K_TXDESC_INTREQ     0x0010
        !           331: #define AR5K_TXDESC_VEOL       0x0020  /*[5211+]*/
        !           332: 

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