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1.1 root 1: /*
2: * Copyright (c) 2004-2008 Reyk Floeter <[email protected]>
3: * Copyright (c) 2006-2008 Nick Kossifidis <[email protected]>
4: *
5: * Permission to use, copy, modify, and distribute this software for any
6: * purpose with or without fee is hereby granted, provided that the above
7: * copyright notice and this permission notice appear in all copies.
8: *
9: * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
10: * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
11: * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
12: * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
13: * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
14: * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
15: * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
16: *
17: */
18:
19: /*
20: * Common ar5xxx EEPROM data offsets (set these on AR5K_EEPROM_BASE)
21: */
22: #define AR5K_EEPROM_MAGIC 0x003d /* EEPROM Magic number */
23: #define AR5K_EEPROM_MAGIC_VALUE 0x5aa5 /* Default - found on EEPROM */
24: #define AR5K_EEPROM_MAGIC_5212 0x0000145c /* 5212 */
25: #define AR5K_EEPROM_MAGIC_5211 0x0000145b /* 5211 */
26: #define AR5K_EEPROM_MAGIC_5210 0x0000145a /* 5210 */
27:
28: #define AR5K_EEPROM_IS_HB63 0x000b /* Talon detect */
29:
30: #define AR5K_EEPROM_RFKILL 0x0f
31: #define AR5K_EEPROM_RFKILL_GPIO_SEL 0x0000001c
32: #define AR5K_EEPROM_RFKILL_GPIO_SEL_S 2
33: #define AR5K_EEPROM_RFKILL_POLARITY 0x00000002
34: #define AR5K_EEPROM_RFKILL_POLARITY_S 1
35:
36: #define AR5K_EEPROM_REG_DOMAIN 0x00bf /* EEPROM regdom */
37: #define AR5K_EEPROM_CHECKSUM 0x00c0 /* EEPROM checksum */
38: #define AR5K_EEPROM_INFO_BASE 0x00c0 /* EEPROM header */
39: #define AR5K_EEPROM_INFO_MAX (0x400 - AR5K_EEPROM_INFO_BASE)
40: #define AR5K_EEPROM_INFO_CKSUM 0xffff
41: #define AR5K_EEPROM_INFO(_n) (AR5K_EEPROM_INFO_BASE + (_n))
42:
43: #define AR5K_EEPROM_VERSION AR5K_EEPROM_INFO(1) /* EEPROM Version */
44: #define AR5K_EEPROM_VERSION_3_0 0x3000 /* No idea what's going on before this version */
45: #define AR5K_EEPROM_VERSION_3_1 0x3001 /* ob/db values for 2Ghz (ar5211_rfregs) */
46: #define AR5K_EEPROM_VERSION_3_2 0x3002 /* different frequency representation (eeprom_bin2freq) */
47: #define AR5K_EEPROM_VERSION_3_3 0x3003 /* offsets changed, has 32 CTLs (see below) and ee_false_detect (eeprom_read_modes) */
48: #define AR5K_EEPROM_VERSION_3_4 0x3004 /* has ee_i_gain, ee_cck_ofdm_power_delta (eeprom_read_modes) */
49: #define AR5K_EEPROM_VERSION_4_0 0x4000 /* has ee_misc, ee_cal_pier, ee_turbo_max_power and ee_xr_power (eeprom_init) */
50: #define AR5K_EEPROM_VERSION_4_1 0x4001 /* has ee_margin_tx_rx (eeprom_init) */
51: #define AR5K_EEPROM_VERSION_4_2 0x4002 /* has ee_cck_ofdm_gain_delta (eeprom_init) */
52: #define AR5K_EEPROM_VERSION_4_3 0x4003 /* power calibration changes */
53: #define AR5K_EEPROM_VERSION_4_4 0x4004
54: #define AR5K_EEPROM_VERSION_4_5 0x4005
55: #define AR5K_EEPROM_VERSION_4_6 0x4006 /* has ee_scaled_cck_delta */
56: #define AR5K_EEPROM_VERSION_4_7 0x3007 /* 4007 ? */
57: #define AR5K_EEPROM_VERSION_4_9 0x4009 /* EAR futureproofing */
58: #define AR5K_EEPROM_VERSION_5_0 0x5000 /* Has 2413 PDADC calibration etc */
59: #define AR5K_EEPROM_VERSION_5_1 0x5001 /* Has capability values */
60: #define AR5K_EEPROM_VERSION_5_3 0x5003 /* Has spur mitigation tables */
61:
62: #define AR5K_EEPROM_MODE_11A 0
63: #define AR5K_EEPROM_MODE_11B 1
64: #define AR5K_EEPROM_MODE_11G 2
65:
66: #define AR5K_EEPROM_HDR AR5K_EEPROM_INFO(2) /* Header that contains the device caps */
67: #define AR5K_EEPROM_HDR_11A(_v) (((_v) >> AR5K_EEPROM_MODE_11A) & 0x1)
68: #define AR5K_EEPROM_HDR_11B(_v) (((_v) >> AR5K_EEPROM_MODE_11B) & 0x1)
69: #define AR5K_EEPROM_HDR_11G(_v) (((_v) >> AR5K_EEPROM_MODE_11G) & 0x1)
70: #define AR5K_EEPROM_HDR_T_2GHZ_DIS(_v) (((_v) >> 3) & 0x1) /* Disable turbo for 2Ghz (?) */
71: #define AR5K_EEPROM_HDR_T_5GHZ_DBM(_v) (((_v) >> 4) & 0x7f) /* Max turbo power for a/XR mode (eeprom_init) */
72: #define AR5K_EEPROM_HDR_DEVICE(_v) (((_v) >> 11) & 0x7)
73: #define AR5K_EEPROM_HDR_RFKILL(_v) (((_v) >> 14) & 0x1) /* Device has RFKill support */
74: #define AR5K_EEPROM_HDR_T_5GHZ_DIS(_v) (((_v) >> 15) & 0x1) /* Disable turbo for 5Ghz */
75:
76: #define AR5K_EEPROM_RFKILL_GPIO_SEL 0x0000001c
77: #define AR5K_EEPROM_RFKILL_GPIO_SEL_S 2
78: #define AR5K_EEPROM_RFKILL_POLARITY 0x00000002
79: #define AR5K_EEPROM_RFKILL_POLARITY_S 1
80:
81: /* Newer EEPROMs are using a different offset */
82: #define AR5K_EEPROM_OFF(_v, _v3_0, _v3_3) \
83: (((_v) >= AR5K_EEPROM_VERSION_3_3) ? _v3_3 : _v3_0)
84:
85: #define AR5K_EEPROM_ANT_GAIN(_v) AR5K_EEPROM_OFF(_v, 0x00c4, 0x00c3)
86: #define AR5K_EEPROM_ANT_GAIN_5GHZ(_v) ((s8)(((_v) >> 8) & 0xff))
87: #define AR5K_EEPROM_ANT_GAIN_2GHZ(_v) ((s8)((_v) & 0xff))
88:
89: /* Misc values available since EEPROM 4.0 */
90: #define AR5K_EEPROM_MISC0 AR5K_EEPROM_INFO(4)
91: #define AR5K_EEPROM_EARSTART(_v) ((_v) & 0xfff)
92: #define AR5K_EEPROM_HDR_XR2_DIS(_v) (((_v) >> 12) & 0x1)
93: #define AR5K_EEPROM_HDR_XR5_DIS(_v) (((_v) >> 13) & 0x1)
94: #define AR5K_EEPROM_EEMAP(_v) (((_v) >> 14) & 0x3)
95:
96: #define AR5K_EEPROM_MISC1 AR5K_EEPROM_INFO(5)
97: #define AR5K_EEPROM_TARGET_PWRSTART(_v) ((_v) & 0xfff)
98: #define AR5K_EEPROM_HAS32KHZCRYSTAL(_v) (((_v) >> 14) & 0x1)
99: #define AR5K_EEPROM_HAS32KHZCRYSTAL_OLD(_v) (((_v) >> 15) & 0x1)
100:
101: #define AR5K_EEPROM_MISC2 AR5K_EEPROM_INFO(6)
102: #define AR5K_EEPROM_EEP_FILE_VERSION(_v) (((_v) >> 8) & 0xff)
103: #define AR5K_EEPROM_EAR_FILE_VERSION(_v) ((_v) & 0xff)
104:
105: #define AR5K_EEPROM_MISC3 AR5K_EEPROM_INFO(7)
106: #define AR5K_EEPROM_ART_BUILD_NUM(_v) (((_v) >> 10) & 0x3f)
107: #define AR5K_EEPROM_EAR_FILE_ID(_v) ((_v) & 0xff)
108:
109: #define AR5K_EEPROM_MISC4 AR5K_EEPROM_INFO(8)
110: #define AR5K_EEPROM_CAL_DATA_START(_v) (((_v) >> 4) & 0xfff)
111: #define AR5K_EEPROM_MASK_R0(_v) (((_v) >> 2) & 0x3)
112: #define AR5K_EEPROM_MASK_R1(_v) ((_v) & 0x3)
113:
114: #define AR5K_EEPROM_MISC5 AR5K_EEPROM_INFO(9)
115: #define AR5K_EEPROM_COMP_DIS(_v) ((_v) & 0x1)
116: #define AR5K_EEPROM_AES_DIS(_v) (((_v) >> 1) & 0x1)
117: #define AR5K_EEPROM_FF_DIS(_v) (((_v) >> 2) & 0x1)
118: #define AR5K_EEPROM_BURST_DIS(_v) (((_v) >> 3) & 0x1)
119: #define AR5K_EEPROM_MAX_QCU(_v) (((_v) >> 4) & 0xf)
120: #define AR5K_EEPROM_HEAVY_CLIP_EN(_v) (((_v) >> 8) & 0x1)
121: #define AR5K_EEPROM_KEY_CACHE_SIZE(_v) (((_v) >> 12) & 0xf)
122:
123: #define AR5K_EEPROM_MISC6 AR5K_EEPROM_INFO(10)
124: #define AR5K_EEPROM_TX_CHAIN_DIS ((_v) & 0x8)
125: #define AR5K_EEPROM_RX_CHAIN_DIS (((_v) >> 3) & 0x8)
126: #define AR5K_EEPROM_FCC_MID_EN (((_v) >> 6) & 0x1)
127: #define AR5K_EEPROM_JAP_U1EVEN_EN (((_v) >> 7) & 0x1)
128: #define AR5K_EEPROM_JAP_U2_EN (((_v) >> 8) & 0x1)
129: #define AR5K_EEPROM_JAP_U1ODD_EN (((_v) >> 9) & 0x1)
130: #define AR5K_EEPROM_JAP_11A_NEW_EN (((_v) >> 10) & 0x1)
131:
132: /* calibration settings */
133: #define AR5K_EEPROM_MODES_11A(_v) AR5K_EEPROM_OFF(_v, 0x00c5, 0x00d4)
134: #define AR5K_EEPROM_MODES_11B(_v) AR5K_EEPROM_OFF(_v, 0x00d0, 0x00f2)
135: #define AR5K_EEPROM_MODES_11G(_v) AR5K_EEPROM_OFF(_v, 0x00da, 0x010d)
136: #define AR5K_EEPROM_CTL(_v) AR5K_EEPROM_OFF(_v, 0x00e4, 0x0128) /* Conformance test limits */
137: #define AR5K_EEPROM_GROUPS_START(_v) AR5K_EEPROM_OFF(_v, 0x0100, 0x0150) /* Start of Groups */
138: #define AR5K_EEPROM_GROUP1_OFFSET 0x0
139: #define AR5K_EEPROM_GROUP2_OFFSET 0x5
140: #define AR5K_EEPROM_GROUP3_OFFSET 0x37
141: #define AR5K_EEPROM_GROUP4_OFFSET 0x46
142: #define AR5K_EEPROM_GROUP5_OFFSET 0x55
143: #define AR5K_EEPROM_GROUP6_OFFSET 0x65
144: #define AR5K_EEPROM_GROUP7_OFFSET 0x69
145: #define AR5K_EEPROM_GROUP8_OFFSET 0x6f
146:
147: #define AR5K_EEPROM_TARGET_PWR_OFF_11A(_v) AR5K_EEPROM_OFF(_v, AR5K_EEPROM_GROUPS_START(_v) + \
148: AR5K_EEPROM_GROUP5_OFFSET, 0x0000)
149: #define AR5K_EEPROM_TARGET_PWR_OFF_11B(_v) AR5K_EEPROM_OFF(_v, AR5K_EEPROM_GROUPS_START(_v) + \
150: AR5K_EEPROM_GROUP6_OFFSET, 0x0010)
151: #define AR5K_EEPROM_TARGET_PWR_OFF_11G(_v) AR5K_EEPROM_OFF(_v, AR5K_EEPROM_GROUPS_START(_v) + \
152: AR5K_EEPROM_GROUP7_OFFSET, 0x0014)
153:
154: /* [3.1 - 3.3] */
155: #define AR5K_EEPROM_OBDB0_2GHZ 0x00ec
156: #define AR5K_EEPROM_OBDB1_2GHZ 0x00ed
157:
158: #define AR5K_EEPROM_PROTECT 0x003f /* EEPROM protect status */
159: #define AR5K_EEPROM_PROTECT_RD_0_31 0x0001 /* Read protection bit for offsets 0x0 - 0x1f */
160: #define AR5K_EEPROM_PROTECT_WR_0_31 0x0002 /* Write protection bit for offsets 0x0 - 0x1f */
161: #define AR5K_EEPROM_PROTECT_RD_32_63 0x0004 /* 0x20 - 0x3f */
162: #define AR5K_EEPROM_PROTECT_WR_32_63 0x0008
163: #define AR5K_EEPROM_PROTECT_RD_64_127 0x0010 /* 0x40 - 0x7f */
164: #define AR5K_EEPROM_PROTECT_WR_64_127 0x0020
165: #define AR5K_EEPROM_PROTECT_RD_128_191 0x0040 /* 0x80 - 0xbf (regdom) */
166: #define AR5K_EEPROM_PROTECT_WR_128_191 0x0080
167: #define AR5K_EEPROM_PROTECT_RD_192_207 0x0100 /* 0xc0 - 0xcf */
168: #define AR5K_EEPROM_PROTECT_WR_192_207 0x0200
169: #define AR5K_EEPROM_PROTECT_RD_208_223 0x0400 /* 0xd0 - 0xdf */
170: #define AR5K_EEPROM_PROTECT_WR_208_223 0x0800
171: #define AR5K_EEPROM_PROTECT_RD_224_239 0x1000 /* 0xe0 - 0xef */
172: #define AR5K_EEPROM_PROTECT_WR_224_239 0x2000
173: #define AR5K_EEPROM_PROTECT_RD_240_255 0x4000 /* 0xf0 - 0xff */
174: #define AR5K_EEPROM_PROTECT_WR_240_255 0x8000
175:
176: /* Some EEPROM defines */
177: #define AR5K_EEPROM_EEP_SCALE 100
178: #define AR5K_EEPROM_EEP_DELTA 10
179: #define AR5K_EEPROM_N_MODES 3
180: #define AR5K_EEPROM_N_5GHZ_CHAN 10
181: #define AR5K_EEPROM_N_2GHZ_CHAN 3
182: #define AR5K_EEPROM_N_2GHZ_CHAN_2413 4
183: #define AR5K_EEPROM_N_2GHZ_CHAN_MAX 4
184: #define AR5K_EEPROM_MAX_CHAN 10
185: #define AR5K_EEPROM_N_PWR_POINTS_5111 11
186: #define AR5K_EEPROM_N_PCDAC 11
187: #define AR5K_EEPROM_N_PHASE_CAL 5
188: #define AR5K_EEPROM_N_TEST_FREQ 8
189: #define AR5K_EEPROM_N_EDGES 8
190: #define AR5K_EEPROM_N_INTERCEPTS 11
191: #define AR5K_EEPROM_FREQ_M(_v) AR5K_EEPROM_OFF(_v, 0x7f, 0xff)
192: #define AR5K_EEPROM_PCDAC_M 0x3f
193: #define AR5K_EEPROM_PCDAC_START 1
194: #define AR5K_EEPROM_PCDAC_STOP 63
195: #define AR5K_EEPROM_PCDAC_STEP 1
196: #define AR5K_EEPROM_NON_EDGE_M 0x40
197: #define AR5K_EEPROM_CHANNEL_POWER 8
198: #define AR5K_EEPROM_N_OBDB 4
199: #define AR5K_EEPROM_OBDB_DIS 0xffff
200: #define AR5K_EEPROM_CHANNEL_DIS 0xff
201: #define AR5K_EEPROM_SCALE_OC_DELTA(_x) (((_x) * 2) / 10)
202: #define AR5K_EEPROM_N_CTLS(_v) AR5K_EEPROM_OFF(_v, 16, 32)
203: #define AR5K_EEPROM_MAX_CTLS 32
204: #define AR5K_EEPROM_N_PD_CURVES 4
205: #define AR5K_EEPROM_N_XPD0_POINTS 4
206: #define AR5K_EEPROM_N_XPD3_POINTS 3
207: #define AR5K_EEPROM_N_PD_GAINS 4
208: #define AR5K_EEPROM_N_PD_POINTS 5
209: #define AR5K_EEPROM_N_INTERCEPT_10_2GHZ 35
210: #define AR5K_EEPROM_N_INTERCEPT_10_5GHZ 55
211: #define AR5K_EEPROM_POWER_M 0x3f
212: #define AR5K_EEPROM_POWER_MIN 0
213: #define AR5K_EEPROM_POWER_MAX 3150
214: #define AR5K_EEPROM_POWER_STEP 50
215: #define AR5K_EEPROM_POWER_TABLE_SIZE 64
216: #define AR5K_EEPROM_N_POWER_LOC_11B 4
217: #define AR5K_EEPROM_N_POWER_LOC_11G 6
218: #define AR5K_EEPROM_I_GAIN 10
219: #define AR5K_EEPROM_CCK_OFDM_DELTA 15
220: #define AR5K_EEPROM_N_IQ_CAL 2
221:
222: #define AR5K_EEPROM_READ(_o, _v) do { \
223: ret = ath5k_hw_eeprom_read(ah, (_o), &(_v)); \
224: if (ret) \
225: return ret; \
226: } while (0)
227:
228: #define AR5K_EEPROM_READ_HDR(_o, _v) \
229: AR5K_EEPROM_READ(_o, ah->ah_capabilities.cap_eeprom._v); \
230:
231: enum ath5k_ant_setting {
232: AR5K_ANT_VARIABLE = 0, /* variable by programming */
233: AR5K_ANT_FIXED_A = 1, /* fixed to 11a frequencies */
234: AR5K_ANT_FIXED_B = 2, /* fixed to 11b frequencies */
235: AR5K_ANT_MAX = 3,
236: };
237:
238: enum ath5k_ctl_mode {
239: AR5K_CTL_11A = 0,
240: AR5K_CTL_11B = 1,
241: AR5K_CTL_11G = 2,
242: AR5K_CTL_TURBO = 3,
243: AR5K_CTL_TURBOG = 4,
244: AR5K_CTL_2GHT20 = 5,
245: AR5K_CTL_5GHT20 = 6,
246: AR5K_CTL_2GHT40 = 7,
247: AR5K_CTL_5GHT40 = 8,
248: AR5K_CTL_MODE_M = 15,
249: };
250:
251: /* Default CTL ids for the 3 main reg domains.
252: * Atheros only uses these by default but vendors
253: * can have up to 32 different CTLs for different
254: * scenarios. Note that theese values are ORed with
255: * the mode id (above) so we can have up to 24 CTL
256: * datasets out of these 3 main regdomains. That leaves
257: * 8 ids that can be used by vendors and since 0x20 is
258: * missing from HAL sources i guess this is the set of
259: * custom CTLs vendors can use. */
260: #define AR5K_CTL_FCC 0x10
261: #define AR5K_CTL_CUSTOM 0x20
262: #define AR5K_CTL_ETSI 0x30
263: #define AR5K_CTL_MKK 0x40
264:
265: /* Indicates a CTL with only mode set and
266: * no reg domain mapping, such CTLs are used
267: * for world roaming domains or simply when
268: * a reg domain is not set */
269: #define AR5K_CTL_NO_REGDOMAIN 0xf0
270:
271: /* Indicates an empty (invalid) CTL */
272: #define AR5K_CTL_NO_CTL 0xff
273:
274: /* Per channel calibration data, used for power table setup */
275: struct ath5k_chan_pcal_info_rf5111 {
276: /* Power levels in half dbm units
277: * for one power curve. */
278: u8 pwr[AR5K_EEPROM_N_PWR_POINTS_5111];
279: /* PCDAC table steps
280: * for the above values */
281: u8 pcdac[AR5K_EEPROM_N_PWR_POINTS_5111];
282: /* Starting PCDAC step */
283: u8 pcdac_min;
284: /* Final PCDAC step */
285: u8 pcdac_max;
286: };
287:
288: struct ath5k_chan_pcal_info_rf5112 {
289: /* Power levels in quarter dBm units
290: * for lower (0) and higher (3)
291: * level curves in 0.25dB units */
292: s8 pwr_x0[AR5K_EEPROM_N_XPD0_POINTS];
293: s8 pwr_x3[AR5K_EEPROM_N_XPD3_POINTS];
294: /* PCDAC table steps
295: * for the above values */
296: u8 pcdac_x0[AR5K_EEPROM_N_XPD0_POINTS];
297: u8 pcdac_x3[AR5K_EEPROM_N_XPD3_POINTS];
298: };
299:
300: struct ath5k_chan_pcal_info_rf2413 {
301: /* Starting pwr/pddac values */
302: s8 pwr_i[AR5K_EEPROM_N_PD_GAINS];
303: u8 pddac_i[AR5K_EEPROM_N_PD_GAINS];
304: /* (pwr,pddac) points
305: * power levels in 0.5dB units */
306: s8 pwr[AR5K_EEPROM_N_PD_GAINS]
307: [AR5K_EEPROM_N_PD_POINTS];
308: u8 pddac[AR5K_EEPROM_N_PD_GAINS]
309: [AR5K_EEPROM_N_PD_POINTS];
310: };
311:
312: enum ath5k_powertable_type {
313: AR5K_PWRTABLE_PWR_TO_PCDAC = 0,
314: AR5K_PWRTABLE_LINEAR_PCDAC = 1,
315: AR5K_PWRTABLE_PWR_TO_PDADC = 2,
316: };
317:
318: struct ath5k_pdgain_info {
319: u8 pd_points;
320: u8 *pd_step;
321: /* Power values are in
322: * 0.25dB units */
323: s16 *pd_pwr;
324: };
325:
326: struct ath5k_chan_pcal_info {
327: /* Frequency */
328: u16 freq;
329: /* Tx power boundaries */
330: s16 max_pwr;
331: s16 min_pwr;
332: union {
333: struct ath5k_chan_pcal_info_rf5111 rf5111_info;
334: struct ath5k_chan_pcal_info_rf5112 rf5112_info;
335: struct ath5k_chan_pcal_info_rf2413 rf2413_info;
336: };
337: /* Raw values used by phy code
338: * Curves are stored in order from lower
339: * gain to higher gain (max txpower -> min txpower) */
340: struct ath5k_pdgain_info *pd_curves;
341: };
342:
343: /* Per rate calibration data for each mode,
344: * used for rate power table setup.
345: * Note: Values in 0.5dB units */
346: struct ath5k_rate_pcal_info {
347: u16 freq; /* Frequency */
348: /* Power level for 6-24Mbit/s rates or
349: * 1Mb rate */
350: u16 target_power_6to24;
351: /* Power level for 36Mbit rate or
352: * 2Mb rate */
353: u16 target_power_36;
354: /* Power level for 48Mbit rate or
355: * 5.5Mbit rate */
356: u16 target_power_48;
357: /* Power level for 54Mbit rate or
358: * 11Mbit rate */
359: u16 target_power_54;
360: };
361:
362: /* Power edges for conformance test limits */
363: struct ath5k_edge_power {
364: u16 freq;
365: u16 edge; /* in half dBm */
366: int flag;
367: };
368:
369: /* EEPROM calibration data */
370: struct ath5k_eeprom_info {
371:
372: /* Header information */
373: u16 ee_magic;
374: u16 ee_protect;
375: u16 ee_regdomain;
376: u16 ee_version;
377: u16 ee_header;
378: u16 ee_ant_gain;
379: u8 ee_rfkill_pin;
380: int ee_rfkill_pol;
381: int ee_is_hb63;
382: u16 ee_misc0;
383: u16 ee_misc1;
384: u16 ee_misc2;
385: u16 ee_misc3;
386: u16 ee_misc4;
387: u16 ee_misc5;
388: u16 ee_misc6;
389: u16 ee_cck_ofdm_gain_delta;
390: u16 ee_cck_ofdm_power_delta;
391: u16 ee_scaled_cck_delta;
392:
393: /* RF Calibration settings (reset, rfregs) */
394: u16 ee_i_cal[AR5K_EEPROM_N_MODES];
395: u16 ee_q_cal[AR5K_EEPROM_N_MODES];
396: u16 ee_fixed_bias[AR5K_EEPROM_N_MODES];
397: u16 ee_turbo_max_power[AR5K_EEPROM_N_MODES];
398: u16 ee_xr_power[AR5K_EEPROM_N_MODES];
399: u16 ee_switch_settling[AR5K_EEPROM_N_MODES];
400: u16 ee_atn_tx_rx[AR5K_EEPROM_N_MODES];
401: u16 ee_ant_control[AR5K_EEPROM_N_MODES][AR5K_EEPROM_N_PCDAC];
402: u16 ee_ob[AR5K_EEPROM_N_MODES][AR5K_EEPROM_N_OBDB];
403: u16 ee_db[AR5K_EEPROM_N_MODES][AR5K_EEPROM_N_OBDB];
404: u16 ee_tx_end2xlna_enable[AR5K_EEPROM_N_MODES];
405: u16 ee_tx_end2xpa_disable[AR5K_EEPROM_N_MODES];
406: u16 ee_tx_frm2xpa_enable[AR5K_EEPROM_N_MODES];
407: u16 ee_thr_62[AR5K_EEPROM_N_MODES];
408: u16 ee_xlna_gain[AR5K_EEPROM_N_MODES];
409: u16 ee_xpd[AR5K_EEPROM_N_MODES];
410: u16 ee_x_gain[AR5K_EEPROM_N_MODES];
411: u16 ee_i_gain[AR5K_EEPROM_N_MODES];
412: u16 ee_margin_tx_rx[AR5K_EEPROM_N_MODES];
413: u16 ee_switch_settling_turbo[AR5K_EEPROM_N_MODES];
414: u16 ee_margin_tx_rx_turbo[AR5K_EEPROM_N_MODES];
415: u16 ee_atn_tx_rx_turbo[AR5K_EEPROM_N_MODES];
416:
417: /* Power calibration data */
418: u16 ee_false_detect[AR5K_EEPROM_N_MODES];
419:
420: /* Number of pd gain curves per mode */
421: u8 ee_pd_gains[AR5K_EEPROM_N_MODES];
422: /* Back mapping pdcurve number -> pdcurve index in pd->pd_curves */
423: u8 ee_pdc_to_idx[AR5K_EEPROM_N_MODES][AR5K_EEPROM_N_PD_GAINS];
424:
425: u8 ee_n_piers[AR5K_EEPROM_N_MODES];
426: struct ath5k_chan_pcal_info ee_pwr_cal_a[AR5K_EEPROM_N_5GHZ_CHAN];
427: struct ath5k_chan_pcal_info ee_pwr_cal_b[AR5K_EEPROM_N_2GHZ_CHAN_MAX];
428: struct ath5k_chan_pcal_info ee_pwr_cal_g[AR5K_EEPROM_N_2GHZ_CHAN_MAX];
429:
430: /* Per rate target power levels */
431: u8 ee_rate_target_pwr_num[AR5K_EEPROM_N_MODES];
432: struct ath5k_rate_pcal_info ee_rate_tpwr_a[AR5K_EEPROM_N_5GHZ_CHAN];
433: struct ath5k_rate_pcal_info ee_rate_tpwr_b[AR5K_EEPROM_N_2GHZ_CHAN_MAX];
434: struct ath5k_rate_pcal_info ee_rate_tpwr_g[AR5K_EEPROM_N_2GHZ_CHAN_MAX];
435:
436: /* Conformance test limits (Unused) */
437: u8 ee_ctls;
438: u8 ee_ctl[AR5K_EEPROM_MAX_CTLS];
439: struct ath5k_edge_power ee_ctl_pwr[AR5K_EEPROM_N_EDGES * AR5K_EEPROM_MAX_CTLS];
440:
441: /* Noise Floor Calibration settings */
442: s16 ee_noise_floor_thr[AR5K_EEPROM_N_MODES];
443: s8 ee_adc_desired_size[AR5K_EEPROM_N_MODES];
444: s8 ee_pga_desired_size[AR5K_EEPROM_N_MODES];
445: s8 ee_adc_desired_size_turbo[AR5K_EEPROM_N_MODES];
446: s8 ee_pga_desired_size_turbo[AR5K_EEPROM_N_MODES];
447: s8 ee_pd_gain_overlap;
448:
449: u32 ee_antenna[AR5K_EEPROM_N_MODES][AR5K_ANT_MAX];
450: };
451:
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