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1.1 root 1: /*
2: * Copyright (c) 2008 Stefan Hajnoczi <[email protected]>
3: * Copyright (c) 2008 Pantelis Koukousoulas <[email protected]>
4: *
5: * This program is free software; you can redistribute it and/or
6: * modify it under the terms of the GNU General Public License as
7: * published by the Free Software Foundation; either version 2 of the
8: * License, or any later version.
9: *
10: * This program is distributed in the hope that it will be useful, but
11: * WITHOUT ANY WARRANTY; without even the implied warranty of
12: * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
13: * General Public License for more details.
14: *
15: * You should have received a copy of the GNU General Public License
16: * along with this program; if not, write to the Free Software
17: * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
18: *
19: * This driver is a port of the b44 linux driver version 1.01
20: *
21: * Copyright (c) 2002 David S. Miller <[email protected]>
22: * Copyright (c) Pekka Pietikainen <[email protected]>
23: * Copyright (C) 2006 Broadcom Corporation.
24: *
25: * Some ssb bits copied from version 2.0 of the b44 driver
26: * Copyright (c) Michael Buesch
27: *
28: * Copyright (c) a lot of people too. Please respect their work.
29: */
30:
31: FILE_LICENCE ( GPL2_OR_LATER );
32:
33: #ifndef _B44_H
34: #define _B44_H
35:
36: /* BCM44xx Register layout */
37: #define B44_DEVCTRL 0x0000UL /* Device Control */
38: #define DEVCTRL_MPM 0x00000040 /* MP PME Enable (B0 only) */
39: #define DEVCTRL_PFE 0x00000080 /* Pattern Filtering Enable */
40: #define DEVCTRL_IPP 0x00000400 /* Internal EPHY Present */
41: #define DEVCTRL_EPR 0x00008000 /* EPHY Reset */
42: #define DEVCTRL_PME 0x00001000 /* PHY Mode Enable */
43: #define DEVCTRL_PMCE 0x00002000 /* PHY Mode Clocks Enable */
44: #define DEVCTRL_PADDR 0x0007c000 /* PHY Address */
45: #define DEVCTRL_PADDR_SHIFT 18
46: #define B44_BIST_STAT 0x000CUL /* Built-In Self-Test Status */
47: #define B44_WKUP_LEN 0x0010UL /* Wakeup Length */
48: #define WKUP_LEN_P0_MASK 0x0000007f /* Pattern 0 */
49: #define WKUP_LEN_D0 0x00000080
50: #define WKUP_LEN_P1_MASK 0x00007f00 /* Pattern 1 */
51: #define WKUP_LEN_P1_SHIFT 8
52: #define WKUP_LEN_D1 0x00008000
53: #define WKUP_LEN_P2_MASK 0x007f0000 /* Pattern 2 */
54: #define WKUP_LEN_P2_SHIFT 16
55: #define WKUP_LEN_D2 0x00000000
56: #define WKUP_LEN_P3_MASK 0x7f000000 /* Pattern 3 */
57: #define WKUP_LEN_P3_SHIFT 24
58: #define WKUP_LEN_D3 0x80000000
59: #define WKUP_LEN_DISABLE 0x80808080
60: #define WKUP_LEN_ENABLE_TWO 0x80800000
61: #define WKUP_LEN_ENABLE_THREE 0x80000000
62: #define B44_ISTAT 0x0020UL /* Interrupt Status */
63: #define ISTAT_LS 0x00000020 /* Link Change (B0 only) */
64: #define ISTAT_PME 0x00000040 /* Power Management Event */
65: #define ISTAT_TO 0x00000080 /* General Purpose Timeout */
66: #define ISTAT_DSCE 0x00000400 /* Descriptor Error */
67: #define ISTAT_DATAE 0x00000800 /* Data Error */
68: #define ISTAT_DPE 0x00001000 /* Descr. Protocol Error */
69: #define ISTAT_RDU 0x00002000 /* Receive Descr. Underflow */
70: #define ISTAT_RFO 0x00004000 /* Receive FIFO Overflow */
71: #define ISTAT_TFU 0x00008000 /* Transmit FIFO Underflow */
72: #define ISTAT_RX 0x00010000 /* RX Interrupt */
73: #define ISTAT_TX 0x01000000 /* TX Interrupt */
74: #define ISTAT_EMAC 0x04000000 /* EMAC Interrupt */
75: #define ISTAT_MII_WRITE 0x08000000 /* MII Write Interrupt */
76: #define ISTAT_MII_READ 0x10000000 /* MII Read Interrupt */
77: #define ISTAT_ERRORS (ISTAT_DSCE|ISTAT_DATAE|ISTAT_DPE|\
78: ISTAT_RDU|ISTAT_RFO|ISTAT_TFU)
79: #define B44_IMASK 0x0024UL /* Interrupt Mask */
80: #define IMASK_DEF (ISTAT_ERRORS | ISTAT_RX | ISTAT_TX)
81: #define IMASK_DISABLE 0
82: #define B44_GPTIMER 0x0028UL /* General Purpose Timer */
83: #define B44_ADDR_LO 0x0088UL /* ENET Address Lo (B0 only) */
84: #define B44_ADDR_HI 0x008CUL /* ENET Address Hi (B0 only) */
85: #define B44_FILT_ADDR 0x0090UL /* ENET Filter Address */
86: #define B44_FILT_DATA 0x0094UL /* ENET Filter Data */
87: #define B44_TXBURST 0x00A0UL /* TX Max Burst Length */
88: #define B44_RXBURST 0x00A4UL /* RX Max Burst Length */
89: #define B44_MAC_CTRL 0x00A8UL /* MAC Control */
90: #define MAC_CTRL_CRC32_ENAB 0x00000001 /* CRC32 Generation Enable */
91: #define MAC_CTRL_PHY_PDOWN 0x00000004 /* Onchip EPHY Powerdown */
92: #define MAC_CTRL_PHY_EDET 0x00000008 /* Onchip EPHY Energy Detected*/
93: #define MAC_CTRL_PHY_LEDCTRL 0x000000e0 /* Onchip EPHY LED Control */
94: #define MAC_CTRL_PHY_LEDCTRL_SHIFT 5
95: #define B44_MAC_FLOW 0x00ACUL /* MAC Flow Control */
96: #define MAC_FLOW_RX_HI_WATER 0x000000ff /* Receive FIFO HI Water Mark */
97: #define MAC_FLOW_PAUSE_ENAB 0x00008000 /* Enbl Pause Frm Generation */
98: #define B44_RCV_LAZY 0x0100UL /* Lazy Interrupt Control */
99: #define RCV_LAZY_TO_MASK 0x00ffffff /* Timeout */
100: #define RCV_LAZY_FC_MASK 0xff000000 /* Frame Count */
101: #define RCV_LAZY_FC_SHIFT 24
102: #define B44_DMATX_CTRL 0x0200UL /* DMA TX Control */
103: #define DMATX_CTRL_ENABLE 0x00000001 /* Enable */
104: #define DMATX_CTRL_SUSPEND 0x00000002 /* Suepend Request */
105: #define DMATX_CTRL_LPBACK 0x00000004 /* Loopback Enable */
106: #define DMATX_CTRL_FAIRPRIOR 0x00000008 /* Fair Priority */
107: #define DMATX_CTRL_FLUSH 0x00000010 /* Flush Request */
108: #define B44_DMATX_ADDR 0x0204UL /* DMA TX Descriptor Ring Addr */
109: #define B44_DMATX_PTR 0x0208UL /* DMA TX Last Posted Desc. */
110: #define B44_DMATX_STAT 0x020CUL /* DMA TX Cur Actve Desc. + Sts */
111: #define DMATX_STAT_CDMASK 0x00000fff /* Current Descriptor Mask */
112: #define DMATX_STAT_SMASK 0x0000f000 /* State Mask */
113: #define DMATX_STAT_SDISABLED 0x00000000 /* State Disabled */
114: #define DMATX_STAT_SACTIVE 0x00001000 /* State Active */
115: #define DMATX_STAT_SIDLE 0x00002000 /* State Idle Wait */
116: #define DMATX_STAT_SSTOPPED 0x00003000 /* State Stopped */
117: #define DMATX_STAT_SSUSP 0x00004000 /* State Suspend Pending */
118: #define DMATX_STAT_EMASK 0x000f0000 /* Error Mask */
119: #define DMATX_STAT_ENONE 0x00000000 /* Error None */
120: #define DMATX_STAT_EDPE 0x00010000 /* Error Desc. Protocol Error */
121: #define DMATX_STAT_EDFU 0x00020000 /* Error Data FIFO Underrun */
122: #define DMATX_STAT_EBEBR 0x00030000 /* Bus Error on Buffer Read */
123: #define DMATX_STAT_EBEDA 0x00040000 /* Bus Error on Desc. Access */
124: #define DMATX_STAT_FLUSHED 0x00100000 /* Flushed */
125: #define B44_DMARX_CTRL 0x0210UL /* DMA RX Control */
126: #define DMARX_CTRL_ENABLE 0x00000001 /* Enable */
127: #define DMARX_CTRL_ROMASK 0x000000fe /* Receive Offset Mask */
128: #define DMARX_CTRL_ROSHIFT 1 /* Receive Offset Shift */
129: #define B44_DMARX_ADDR 0x0214UL /* DMA RX Descriptor Ring Addr */
130: #define B44_DMARX_PTR 0x0218UL /* DMA RX Last Posted Desc */
131: #define B44_DMARX_STAT 0x021CUL /* Cur Active Desc. + Status */
132: #define DMARX_STAT_CDMASK 0x00000fff /* Current Descriptor Mask */
133: #define DMARX_STAT_SMASK 0x0000f000 /* State Mask */
134: #define DMARX_STAT_SDISABLED 0x00000000 /* State Disbaled */
135: #define DMARX_STAT_SACTIVE 0x00001000 /* State Active */
136: #define DMARX_STAT_SIDLE 0x00002000 /* State Idle Wait */
137: #define DMARX_STAT_SSTOPPED 0x00003000 /* State Stopped */
138: #define DMARX_STAT_EMASK 0x000f0000 /* Error Mask */
139: #define DMARX_STAT_ENONE 0x00000000 /* Error None */
140: #define DMARX_STAT_EDPE 0x00010000 /* Error Desc. Protocol Error */
141: #define DMARX_STAT_EDFO 0x00020000 /* Error Data FIFO Overflow */
142: #define DMARX_STAT_EBEBW 0x00030000 /* Error on Buffer Write */
143: #define DMARX_STAT_EBEDA 0x00040000 /* Bus Error on Desc. Access */
144: #define B44_DMAFIFO_AD 0x0220UL /* DMA FIFO Diag Address */
145: #define DMAFIFO_AD_OMASK 0x0000ffff /* Offset Mask */
146: #define DMAFIFO_AD_SMASK 0x000f0000 /* Select Mask */
147: #define DMAFIFO_AD_SXDD 0x00000000 /* Select Transmit DMA Data */
148: #define DMAFIFO_AD_SXDP 0x00010000 /* Sel Transmit DMA Pointers */
149: #define DMAFIFO_AD_SRDD 0x00040000 /* Select Receive DMA Data */
150: #define DMAFIFO_AD_SRDP 0x00050000 /* Sel Receive DMA Pointers */
151: #define DMAFIFO_AD_SXFD 0x00080000 /* Select Transmit FIFO Data */
152: #define DMAFIFO_AD_SXFP 0x00090000 /* Sel Transmit FIFO Pointers */
153: #define DMAFIFO_AD_SRFD 0x000c0000 /* Select Receive FIFO Data */
154: #define DMAFIFO_AD_SRFP 0x000c0000 /* Sel Receive FIFO Pointers */
155: #define B44_DMAFIFO_LO 0x0224UL /* DMA FIFO Diag Low Data */
156: #define B44_DMAFIFO_HI 0x0228UL /* DMA FIFO Diag High Data */
157: #define B44_RXCONFIG 0x0400UL /* EMAC RX Config */
158: #define RXCONFIG_DBCAST 0x00000001 /* Disable Broadcast */
159: #define RXCONFIG_ALLMULTI 0x00000002 /* Accept All Multicast */
160: #define RXCONFIG_NORX_WHILE_TX 0x00000004 /* Rcv Disble While TX */
161: #define RXCONFIG_PROMISC 0x00000008 /* Promiscuous Enable */
162: #define RXCONFIG_LPBACK 0x00000010 /* Loopback Enable */
163: #define RXCONFIG_FLOW 0x00000020 /* Flow Control Enable */
164: #define RXCONFIG_FLOW_ACCEPT 0x00000040 /* Accept UFC Frame */
165: #define RXCONFIG_RFILT 0x00000080 /* Reject Filter */
166: #define B44_RXMAXLEN 0x0404UL /* EMAC RX Max Packet Length */
167: #define B44_TXMAXLEN 0x0408UL /* EMAC TX Max Packet Length */
168: #define B44_MDIO_CTRL 0x0410UL /* EMAC MDIO Control */
169: #define MDIO_CTRL_MAXF_MASK 0x0000007f /* MDC Frequency */
170: #define MDIO_CTRL_PREAMBLE 0x00000080 /* MII Preamble Enable */
171: #define B44_MDIO_DATA 0x0414UL /* EMAC MDIO Data */
172: #define MDIO_DATA_DATA 0x0000ffff /* R/W Data */
173: #define MDIO_DATA_TA_MASK 0x00030000 /* Turnaround Value */
174: #define MDIO_DATA_TA_SHIFT 16
175: #define MDIO_TA_VALID 2
176: #define MDIO_DATA_RA_MASK 0x007c0000 /* Register Address */
177: #define MDIO_DATA_RA_SHIFT 18
178: #define MDIO_DATA_PMD_MASK 0x0f800000 /* Physical Media Device */
179: #define MDIO_DATA_PMD_SHIFT 23
180: #define MDIO_DATA_OP_MASK 0x30000000 /* Opcode */
181: #define MDIO_DATA_OP_SHIFT 28
182: #define MDIO_OP_WRITE 1
183: #define MDIO_OP_READ 2
184: #define MDIO_DATA_SB_MASK 0xc0000000 /* Start Bits */
185: #define MDIO_DATA_SB_SHIFT 30
186: #define MDIO_DATA_SB_START 0x40000000 /* Start Of Frame */
187: #define B44_EMAC_IMASK 0x0418UL /* EMAC Interrupt Mask */
188: #define B44_EMAC_ISTAT 0x041CUL /* EMAC Interrupt Status */
189: #define EMAC_INT_MII 0x00000001 /* MII MDIO Interrupt */
190: #define EMAC_INT_MIB 0x00000002 /* MIB Interrupt */
191: #define EMAC_INT_FLOW 0x00000003 /* Flow Control Interrupt */
192: #define B44_CAM_DATA_LO 0x0420UL /* EMAC CAM Data Low */
193: #define B44_CAM_DATA_HI 0x0424UL /* EMAC CAM Data High */
194: #define CAM_DATA_HI_VALID 0x00010000 /* Valid Bit */
195: #define B44_CAM_CTRL 0x0428UL /* EMAC CAM Control */
196: #define CAM_CTRL_ENABLE 0x00000001 /* CAM Enable */
197: #define CAM_CTRL_MSEL 0x00000002 /* Mask Select */
198: #define CAM_CTRL_READ 0x00000004 /* Read */
199: #define CAM_CTRL_WRITE 0x00000008 /* Read */
200: #define CAM_CTRL_INDEX_MASK 0x003f0000 /* Index Mask */
201: #define CAM_CTRL_INDEX_SHIFT 16
202: #define CAM_CTRL_BUSY 0x80000000 /* CAM Busy */
203: #define B44_ENET_CTRL 0x042CUL /* EMAC ENET Control */
204: #define ENET_CTRL_ENABLE 0x00000001 /* EMAC Enable */
205: #define ENET_CTRL_DISABLE 0x00000002 /* EMAC Disable */
206: #define ENET_CTRL_SRST 0x00000004 /* EMAC Soft Reset */
207: #define ENET_CTRL_EPSEL 0x00000008 /* External PHY Select */
208: #define B44_TX_CTRL 0x0430UL /* EMAC TX Control */
209: #define TX_CTRL_DUPLEX 0x00000001 /* Full Duplex */
210: #define TX_CTRL_FMODE 0x00000002 /* Flow Mode */
211: #define TX_CTRL_SBENAB 0x00000004 /* Single Backoff Enable */
212: #define TX_CTRL_SMALL_SLOT 0x00000008 /* Small Slottime */
213: #define B44_TX_HIWMARK 0x0434UL /* EMAC TX High Watermark */
214: #define TX_HIWMARK_DEFLT 56 /* Default used in all drivers */
215: #define B44_MIB_CTRL 0x0438UL /* EMAC MIB Control */
216: #define MIB_CTRL_CLR_ON_READ 0x00000001 /* Autoclear on Read */
217: #define B44_TX_GOOD_O 0x0500UL /* MIB TX Good Octets */
218: #define B44_TX_GOOD_P 0x0504UL /* MIB TX Good Packets */
219: #define B44_TX_O 0x0508UL /* MIB TX Octets */
220: #define B44_TX_P 0x050CUL /* MIB TX Packets */
221: #define B44_TX_BCAST 0x0510UL /* MIB TX Broadcast Packets */
222: #define B44_TX_MCAST 0x0514UL /* MIB TX Multicast Packets */
223: #define B44_TX_64 0x0518UL /* MIB TX <= 64 byte Packets */
224: #define B44_TX_65_127 0x051CUL /* MIB TX 65 to 127 byte Pkts */
225: #define B44_TX_128_255 0x0520UL /* MIB TX 128 to 255 byte Pkts */
226: #define B44_TX_256_511 0x0524UL /* MIB TX 256 to 511 byte Pkts */
227: #define B44_TX_512_1023 0x0528UL /* MIB TX 512 to 1023 byte Pkts */
228: #define B44_TX_1024_MAX 0x052CUL /* MIB TX 1024 to max byte Pkts */
229: #define B44_TX_JABBER 0x0530UL /* MIB TX Jabber Packets */
230: #define B44_TX_OSIZE 0x0534UL /* MIB TX Oversize Packets */
231: #define B44_TX_FRAG 0x0538UL /* MIB TX Fragment Packets */
232: #define B44_TX_URUNS 0x053CUL /* MIB TX Underruns */
233: #define B44_TX_TCOLS 0x0540UL /* MIB TX Total Collisions */
234: #define B44_TX_SCOLS 0x0544UL /* MIB TX Single Collisions */
235: #define B44_TX_MCOLS 0x0548UL /* MIB TX Multiple Collisions */
236: #define B44_TX_ECOLS 0x054CUL /* MIB TX Excessive Collisions */
237: #define B44_TX_LCOLS 0x0550UL /* MIB TX Late Collisions */
238: #define B44_TX_DEFERED 0x0554UL /* MIB TX Defered Packets */
239: #define B44_TX_CLOST 0x0558UL /* MIB TX Carrier Lost */
240: #define B44_TX_PAUSE 0x055CUL /* MIB TX Pause Packets */
241: #define B44_RX_GOOD_O 0x0580UL /* MIB RX Good Octets */
242: #define B44_RX_GOOD_P 0x0584UL /* MIB RX Good Packets */
243: #define B44_RX_O 0x0588UL /* MIB RX Octets */
244: #define B44_RX_P 0x058CUL /* MIB RX Packets */
245: #define B44_RX_BCAST 0x0590UL /* MIB RX Broadcast Packets */
246: #define B44_RX_MCAST 0x0594UL /* MIB RX Multicast Packets */
247: #define B44_RX_64 0x0598UL /* MIB RX <= 64 byte Packets */
248: #define B44_RX_65_127 0x059CUL /* MIB RX 65 to 127 byte Pkts */
249: #define B44_RX_128_255 0x05A0UL /* MIB RX 128 to 255 byte Pkts */
250: #define B44_RX_256_511 0x05A4UL /* MIB RX 256 to 511 byte Pkts */
251: #define B44_RX_512_1023 0x05A8UL /* MIB RX 512 to 1023 byte Pkts */
252: #define B44_RX_1024_MAX 0x05ACUL /* MIB RX 1024 to max byte Pkts */
253: #define B44_RX_JABBER 0x05B0UL /* MIB RX Jabber Packets */
254: #define B44_RX_OSIZE 0x05B4UL /* MIB RX Oversize Packets */
255: #define B44_RX_FRAG 0x05B8UL /* MIB RX Fragment Packets */
256: #define B44_RX_MISS 0x05BCUL /* MIB RX Missed Packets */
257: #define B44_RX_CRCA 0x05C0UL /* MIB RX CRC Align Errors */
258: #define B44_RX_USIZE 0x05C4UL /* MIB RX Undersize Packets */
259: #define B44_RX_CRC 0x05C8UL /* MIB RX CRC Errors */
260: #define B44_RX_ALIGN 0x05CCUL /* MIB RX Align Errors */
261: #define B44_RX_SYM 0x05D0UL /* MIB RX Symbol Errors */
262: #define B44_RX_PAUSE 0x05D4UL /* MIB RX Pause Packets */
263: #define B44_RX_NPAUSE 0x05D8UL /* MIB RX Non-Pause Packets */
264:
265: /* Sonics Silicon backplane register definitions */
266: #define B44_SBIMSTATE 0x0F90UL /* SB Initiator Agent State */
267: #define SBIMSTATE_PC 0x0000000f /* Pipe Count */
268: #define SBIMSTATE_AP_MASK 0x00000030 /* Arbitration Priority */
269: #define SBIMSTATE_AP_BOTH 0x00000000 /* both timeslices and token */
270: #define SBIMSTATE_AP_TS 0x00000010 /* Use timeslices only */
271: #define SBIMSTATE_AP_TK 0x00000020 /* Use token only */
272: #define SBIMSTATE_AP_RSV 0x00000030 /* Reserved */
273: #define SBIMSTATE_IBE 0x00020000 /* In Band Error */
274: #define SBIMSTATE_TO 0x00040000 /* Timeout */
275: #define SBIMSTATE_BAD ( SBIMSTATE_IBE | SBIMSTATE_TO )
276: #define B44_SBINTVEC 0x0F94UL /* SB Interrupt Mask */
277: #define SBINTVEC_PCI 0x00000001 /* Enable interrupts for PCI */
278: #define SBINTVEC_ENET0 0x00000002 /* Enable ints for enet 0 */
279: #define SBINTVEC_ILINE20 0x00000004 /* Enable ints for iline20 */
280: #define SBINTVEC_CODEC 0x00000008 /* Enable ints for v90 codec */
281: #define SBINTVEC_USB 0x00000010 /* Enable intts for usb */
282: #define SBINTVEC_EXTIF 0x00000020 /* Enable ints for ext i/f */
283: #define SBINTVEC_ENET1 0x00000040 /* Enable ints for enet 1 */
284: #define B44_SBTMSLOW 0x0F98UL /* SB Target State Low */
285: #define SBTMSLOW_RESET 0x00000001 /* Reset */
286: #define SBTMSLOW_REJECT 0x00000002 /* Reject */
287: #define SBTMSLOW_CLOCK 0x00010000 /* Clock Enable */
288: #define SBTMSLOW_FGC 0x00020000 /* Force Gated Clocks On */
289: #define SBTMSLOW_PE 0x40000000 /* Power Management Enable */
290: #define SBTMSLOW_BE 0x80000000 /* BIST Enable */
291: #define B44_SBTMSHIGH 0x0F9CUL /* SB Target State High */
292: #define SBTMSHIGH_SERR 0x00000001 /* S-error */
293: #define SBTMSHIGH_INT 0x00000002 /* Interrupt */
294: #define SBTMSHIGH_BUSY 0x00000004 /* Busy */
295: #define SBTMSHIGH_GCR 0x20000000 /* Gated Clock Request */
296: #define SBTMSHIGH_BISTF 0x40000000 /* BIST Failed */
297: #define SBTMSHIGH_BISTD 0x80000000 /* BIST Done */
298: #define B44_SBIDHIGH 0x0FFCUL /* SB Identification High */
299: #define SBIDHIGH_RC_MASK 0x0000000f /* Revision Code */
300: #define SBIDHIGH_CC_MASK 0x0000fff0 /* Core Code */
301: #define SBIDHIGH_CC_SHIFT 4
302: #define SBIDHIGH_VC_MASK 0xffff0000 /* Vendor Code */
303: #define SBIDHIGH_VC_SHIFT 16
304:
305: /* SSB PCI config space registers. */
306: #define SSB_PMCSR 0x44
307: #define SSB_PE 0x100
308: #define SSB_BAR0_WIN 0x80
309: #define SSB_BAR1_WIN 0x84
310: #define SSB_SPROM_CONTROL 0x88
311: #define SSB_BAR1_CONTROL 0x8c
312:
313: /* SSB core and host control registers. */
314: #define SSB_CONTROL 0x0000UL
315: #define SSB_ARBCONTROL 0x0010UL
316: #define SSB_ISTAT 0x0020UL
317: #define SSB_IMASK 0x0024UL
318: #define SSB_MBOX 0x0028UL
319: #define SSB_BCAST_ADDR 0x0050UL
320: #define SSB_BCAST_DATA 0x0054UL
321: #define SSB_PCI_TRANS_0 0x0100UL
322: #define SSB_PCI_TRANS_1 0x0104UL
323: #define SSB_PCI_TRANS_2 0x0108UL
324: #define SSB_SPROM 0x0800UL
325:
326: #define SSB_PCI_MEM 0x00000000
327: #define SSB_PCI_IO 0x00000001
328: #define SSB_PCI_CFG0 0x00000002
329: #define SSB_PCI_CFG1 0x00000003
330: #define SSB_PCI_PREF 0x00000004
331: #define SSB_PCI_BURST 0x00000008
332: #define SSB_PCI_MASK0 0xfc000000
333: #define SSB_PCI_MASK1 0xfc000000
334: #define SSB_PCI_MASK2 0xc0000000
335:
336: /* 4400 PHY registers */
337: #define B44_MII_AUXCTRL 24 /* Auxiliary Control */
338: #define MII_AUXCTRL_DUPLEX 0x0001 /* Full Duplex */
339: #define MII_AUXCTRL_SPEED 0x0002 /* 1=100Mbps, 0=10Mbps */
340: #define MII_AUXCTRL_FORCED 0x0004 /* Forced 10/100 */
341: #define B44_MII_ALEDCTRL 26 /* Activity LED */
342: #define MII_ALEDCTRL_ALLMSK 0x7fff
343: #define B44_MII_TLEDCTRL 27 /* Traffic Meter LED */
344: #define MII_TLEDCTRL_ENABLE 0x0040
345:
346: /* RX/TX descriptor */
347: struct dma_desc {
348: u32 ctrl; /* length of data and flags */
349: u32 addr; /* address of data */
350: };
351:
352: /* There are only 12 bits in the DMA engine for descriptor offsetting
353: * so the table must be aligned on a boundary of this.
354: */
355: #define B44_DMA_ALIGNMENT 4096
356:
357: /* The DMA engine can only address the first gigabyte of address space
358: */
359: #define B44_30BIT_DMA_MASK 0x3fffffff
360:
361: #define DESC_CTRL_LEN 0x00001fff
362: #define DESC_CTRL_CMASK 0x0ff00000 /* Core specific bits */
363: #define DESC_CTRL_EOT 0x10000000 /* End of Table */
364: #define DESC_CTRL_IOC 0x20000000 /* Interrupt On Completion */
365: #define DESC_CTRL_EOF 0x40000000 /* End of Frame */
366: #define DESC_CTRL_SOF 0x80000000 /* Start of Frame */
367:
368: struct rx_header {
369: u16 len;
370: u16 flags;
371: u16 pad[12];
372: };
373: #define RX_HEADER_LEN 28
374:
375: #define RX_FLAG_OFIFO 0x00000001 /* FIFO Overflow */
376: #define RX_FLAG_CRCERR 0x00000002 /* CRC Error */
377: #define RX_FLAG_SERR 0x00000004 /* Receive Symbol Error */
378: #define RX_FLAG_ODD 0x00000008 /* Frame has odd number of nibbles */
379: #define RX_FLAG_LARGE 0x00000010 /* Frame is > RX MAX Length */
380: #define RX_FLAG_MCAST 0x00000020 /* Dest is Multicast Address */
381: #define RX_FLAG_BCAST 0x00000040 /* Dest is Broadcast Address */
382: #define RX_FLAG_MISS 0x00000080 /* Received due to promisc mode */
383: #define RX_FLAG_LAST 0x00000800 /* Last buffer in frame */
384: #define RX_FLAG_ERRORS (RX_FLAG_ODD | RX_FLAG_SERR |\
385: RX_FLAG_CRCERR | RX_FLAG_OFIFO)
386:
387: /* Client Mode PCI memory access space (1 GB) */
388: #define SB_PCI_DMA 0x40000000
389:
390: /* Address of PCI core on BCM4400 cards */
391: #define BCM4400_PCI_CORE_ADDR 0x18002000
392:
393: /* Hardware minimum and maximum for a single frame's data payload */
394: #define B44_MIN_MTU 60
395: #define B44_MAX_MTU 1500
396:
397: #define B44_RING_SIZE 8
398: #define B44_RING_LAST ( B44_RING_SIZE - 1 )
399:
400: #define B44_RX_RING_LEN_BYTES ( sizeof bp->rx[0] * B44_RING_SIZE )
401: #define B44_TX_RING_LEN_BYTES ( sizeof bp->tx[0] * B44_RING_SIZE )
402:
403: #define RX_PKT_OFFSET 30
404: #define RX_PKT_BUF_SZ (1536 + RX_PKT_OFFSET + 64)
405:
406: #define B44_FULL_RESET 1
407: #define B44_FULL_RESET_SKIP_PHY 2
408: #define B44_PARTIAL_RESET 3
409: #define B44_CHIP_RESET_FULL 4
410: #define B44_CHIP_RESET_PARTIAL 5
411:
412: #define SSB_CORE_DOWN ( SBTMSLOW_RESET | SBTMSLOW_REJECT )
413:
414: #define B44_REGS_SIZE 8192
415:
416: /** Driver private state */
417: struct b44_private {
418: struct net_device *netdev;
419: struct pci_device *pci;
420: u8 *regs; /* memory-mapped registers */
421: u8 phy_addr;
422:
423: struct dma_desc *tx;
424: struct io_buffer *tx_iobuf[B44_RING_SIZE];
425: u32 tx_cur; /* next available descriptor */
426: u32 tx_dirty; /* oldest pending descriptor */
427:
428: struct dma_desc *rx;
429: struct io_buffer *rx_iobuf[B44_RING_SIZE];
430: u32 rx_cur; /* next descriptor to read */
431: };
432:
433:
434: static void ssb_core_reset ( struct b44_private *bp );
435: static void ssb_core_disable ( struct b44_private *bp );
436: static u32 ssb_pci_setup ( struct b44_private *bp, u32 cores );
437:
438: static void b44_chip_reset ( struct b44_private *bp, int reset_kind );
439: static void b44_init_hw ( struct b44_private *bp, int reset_kind );
440: static void b44_cam_write ( struct b44_private *bp, u8 *data, int index );
441: static void b44_set_mac_addr ( struct b44_private *bp );
442: static void b44_set_rx_mode ( struct net_device *netdev );
443: static void b44_halt(struct b44_private *);
444:
445: static int b44_phy_reset ( struct b44_private *bp );
446: static int b44_phy_write ( struct b44_private *bp, int reg, u32 val );
447: static int b44_phy_read ( struct b44_private *bp, int reg, u32 *val );
448:
449: static int b44_init_tx_ring ( struct b44_private *bp );
450: static void b44_free_tx_ring ( struct b44_private *bp );
451: static int b44_init_rx_ring ( struct b44_private *bp );
452: static void b44_free_rx_ring ( struct b44_private *bp );
453: static void b44_rx_refill ( struct b44_private *bp, u32 pending );
454: static void b44_populate_rx_descriptor (struct b44_private *bp, u32 index);
455:
456: static int b44_probe ( struct pci_device *pci );
457: static void b44_remove ( struct pci_device *pci );
458:
459: static int b44_open ( struct net_device *netdev );
460: static void b44_close ( struct net_device *netdev );
461: static void b44_irq ( struct net_device *netdev, int enable );
462: static void b44_poll ( struct net_device *netdev );
463: static void b44_process_rx_packets ( struct b44_private *bp );
464: static int b44_transmit ( struct net_device *netdev,
465: struct io_buffer *iobuf );
466:
467: static struct net_device_operations b44_operations;
468:
469: #endif /* _B44_H */
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