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Annotation of qemu/roms/ipxe/src/drivers/net/cs89x0.h, revision 1.1

1.1     ! root        1: /**
        !             2:    Per an email message from Russ Nelson <[email protected]> on
        !             3:    18 March 2008 this file is now licensed under GPL Version 2.
        !             4: 
        !             5:    From: Russ Nelson <[email protected]>
        !             6:    Date: Tue, 18 Mar 2008 12:42:00 -0400
        !             7:    Subject: Re: [Etherboot-developers] cs89x0 driver in etherboot
        !             8:    -- quote from email 
        !             9:    As copyright holder, if I say it doesn't conflict with the GPL,
        !            10:    then it doesn't conflict with the GPL.
        !            11: 
        !            12:    However, there's no point in causing people's brains to overheat,
        !            13:    so yes, I grant permission for the code to be relicensed under the
        !            14:    GPLv2.  Please make sure that this change in licensing makes its
        !            15:    way upstream.  -russ 
        !            16:    -- quote from email
        !            17: **/
        !            18: 
        !            19: FILE_LICENCE ( GPL2_ONLY );
        !            20: 
        !            21: /*  Copyright, 1988-1992, Russell Nelson, Crynwr Software
        !            22: 
        !            23:    This program is free software; you can redistribute it and/or modify
        !            24:    it under the terms of the GNU General Public License as published by
        !            25:    the Free Software Foundation, version 1.
        !            26: 
        !            27:    This program is distributed in the hope that it will be useful,
        !            28:    but WITHOUT ANY WARRANTY; without even the implied warranty of
        !            29:    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
        !            30:    GNU General Public License for more details.
        !            31: 
        !            32:    You should have received a copy of the GNU General Public License
        !            33:    along with this program; if not, write to the Free Software
        !            34:    Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.  */
        !            35: 
        !            36: #define PP_ChipID 0x0000       /* offset   0h -> Corp -ID              */
        !            37:                                /* offset   2h -> Model/Product Number  */
        !            38:                                /* offset   3h -> Chip Revision Number  */
        !            39: 
        !            40: #define PP_ISAIOB 0x0020       /*  IO base address */
        !            41: #define PP_CS8900_ISAINT 0x0022        /*  ISA interrupt select */
        !            42: #define PP_CS8920_ISAINT 0x0370        /*  ISA interrupt select */
        !            43: #define PP_CS8900_ISADMA 0x0024        /*  ISA Rec DMA channel */
        !            44: #define PP_CS8920_ISADMA 0x0374        /*  ISA Rec DMA channel */
        !            45: #define PP_ISASOF 0x0026       /*  ISA DMA offset */
        !            46: #define PP_DmaFrameCnt 0x0028  /*  ISA DMA Frame count */
        !            47: #define PP_DmaByteCnt 0x002A   /*  ISA DMA Byte count */
        !            48: #define PP_CS8900_ISAMemB 0x002C       /*  Memory base */
        !            49: #define PP_CS8920_ISAMemB 0x0348 /*  */
        !            50: 
        !            51: #define PP_ISABootBase 0x0030  /*  Boot Prom base  */
        !            52: #define PP_ISABootMask 0x0034  /*  Boot Prom Mask */
        !            53: 
        !            54: /* EEPROM data and command registers */
        !            55: #define PP_EECMD 0x0040                /*  NVR Interface Command register */
        !            56: #define PP_EEData 0x0042       /*  NVR Interface Data Register */
        !            57: #define PP_DebugReg 0x0044     /*  Debug Register */
        !            58: 
        !            59: #define PP_RxCFG 0x0102                /*  Rx Bus config */
        !            60: #define PP_RxCTL 0x0104                /*  Receive Control Register */
        !            61: #define PP_TxCFG 0x0106                /*  Transmit Config Register */
        !            62: #define PP_TxCMD 0x0108                /*  Transmit Command Register */
        !            63: #define PP_BufCFG 0x010A       /*  Bus configuration Register */
        !            64: #define PP_LineCTL 0x0112      /*  Line Config Register */
        !            65: #define PP_SelfCTL 0x0114      /*  Self Command Register */
        !            66: #define PP_BusCTL 0x0116       /*  ISA bus control Register */
        !            67: #define PP_TestCTL 0x0118      /*  Test Register */
        !            68: #define PP_AutoNegCTL 0x011C   /*  Auto Negotiation Ctrl */
        !            69: 
        !            70: #define PP_ISQ 0x0120          /*  Interrupt Status */
        !            71: #define PP_RxEvent 0x0124      /*  Rx Event Register */
        !            72: #define PP_TxEvent 0x0128      /*  Tx Event Register */
        !            73: #define PP_BufEvent 0x012C     /*  Bus Event Register */
        !            74: #define PP_RxMiss 0x0130       /*  Receive Miss Count */
        !            75: #define PP_TxCol 0x0132                /*  Transmit Collision Count */
        !            76: #define PP_LineST 0x0134       /*  Line State Register */
        !            77: #define PP_SelfST 0x0136       /*  Self State register */
        !            78: #define PP_BusST 0x0138                /*  Bus Status */
        !            79: #define PP_TDR 0x013C          /*  Time Domain Reflectometry */
        !            80: #define PP_AutoNegST 0x013E    /*  Auto Neg Status */
        !            81: #define PP_TxCommand 0x0144    /*  Tx Command */
        !            82: #define PP_TxLength 0x0146     /*  Tx Length */
        !            83: #define PP_LAF 0x0150          /*  Hash Table */
        !            84: #define PP_IA 0x0158           /*  Physical Address Register */
        !            85: 
        !            86: #define PP_RxStatus 0x0400     /*  Receive start of frame */
        !            87: #define PP_RxLength 0x0402     /*  Receive Length of frame */
        !            88: #define PP_RxFrame 0x0404      /*  Receive frame pointer */
        !            89: #define PP_TxFrame 0x0A00      /*  Transmit frame pointer */
        !            90: 
        !            91: /*  Primary I/O Base Address. If no I/O base is supplied by the user, then this */
        !            92: /*  can be used as the default I/O base to access the PacketPage Area. */
        !            93: #define DEFAULTIOBASE 0x0300
        !            94: #define FIRST_IO 0x020C                /*  First I/O port to check */
        !            95: #define LAST_IO 0x037C         /*  Last I/O port to check (+10h) */
        !            96: #define ADD_MASK 0x3000                /*  Mask it use of the ADD_PORT register */
        !            97: #define ADD_SIG 0x3000         /*  Expected ID signature */
        !            98: 
        !            99: #define CHIP_EISA_ID_SIG 0x630E   /*  Product ID Code for Crystal Chip (CS8900 spec 4.3) */
        !           100: 
        !           101: #ifdef IBMEIPKT
        !           102: #define EISA_ID_SIG 0x4D24     /*  IBM */
        !           103: #define PART_NO_SIG 0x1010     /*  IBM */
        !           104: #define MONGOOSE_BIT 0x0000    /*  IBM */
        !           105: #else
        !           106: #define EISA_ID_SIG 0x630E     /*  PnP Vendor ID (same as chip id for Crystal board) */
        !           107: #define PART_NO_SIG 0x4000     /*  ID code CS8920 board (PnP Vendor Product code) */
        !           108: #define MONGOOSE_BIT 0x2000    /*  PART_NO_SIG + MONGOOSE_BUT => ID of mongoose */
        !           109: #endif
        !           110: 
        !           111: #define PRODUCT_ID_ADD 0x0002   /*  Address of product ID */
        !           112: 
        !           113: /*  Mask to find out the types of  registers */
        !           114: #define REG_TYPE_MASK 0x001F
        !           115: 
        !           116: /*  Eeprom Commands */
        !           117: #define ERSE_WR_ENBL 0x00F0
        !           118: #define ERSE_WR_DISABLE 0x0000
        !           119: 
        !           120: /*  Defines Control/Config register quintuplet numbers */
        !           121: #define RX_BUF_CFG 0x0003
        !           122: #define RX_CONTROL 0x0005
        !           123: #define TX_CFG 0x0007
        !           124: #define TX_COMMAND 0x0009
        !           125: #define BUF_CFG 0x000B
        !           126: #define LINE_CONTROL 0x0013
        !           127: #define SELF_CONTROL 0x0015
        !           128: #define BUS_CONTROL 0x0017
        !           129: #define TEST_CONTROL 0x0019
        !           130: 
        !           131: /*  Defines Status/Count registers quintuplet numbers */
        !           132: #define RX_EVENT 0x0004
        !           133: #define TX_EVENT 0x0008
        !           134: #define BUF_EVENT 0x000C
        !           135: #define RX_MISS_COUNT 0x0010
        !           136: #define TX_COL_COUNT 0x0012
        !           137: #define LINE_STATUS 0x0014
        !           138: #define SELF_STATUS 0x0016
        !           139: #define BUS_STATUS 0x0018
        !           140: #define TDR 0x001C
        !           141: 
        !           142: /* PP_RxCFG - Receive  Configuration and Interrupt Mask bit definition -  Read/write */
        !           143: #define SKIP_1 0x0040
        !           144: #define RX_STREAM_ENBL 0x0080
        !           145: #define RX_OK_ENBL 0x0100
        !           146: #define RX_DMA_ONLY 0x0200
        !           147: #define AUTO_RX_DMA 0x0400
        !           148: #define BUFFER_CRC 0x0800
        !           149: #define RX_CRC_ERROR_ENBL 0x1000
        !           150: #define RX_RUNT_ENBL 0x2000
        !           151: #define RX_EXTRA_DATA_ENBL 0x4000
        !           152: 
        !           153: /* PP_RxCTL - Receive Control bit definition - Read/write */
        !           154: #define RX_IA_HASH_ACCEPT 0x0040
        !           155: #define RX_PROM_ACCEPT 0x0080
        !           156: #define RX_OK_ACCEPT 0x0100
        !           157: #define RX_MULTCAST_ACCEPT 0x0200
        !           158: #define RX_IA_ACCEPT 0x0400
        !           159: #define RX_BROADCAST_ACCEPT 0x0800
        !           160: #define RX_BAD_CRC_ACCEPT 0x1000
        !           161: #define RX_RUNT_ACCEPT 0x2000
        !           162: #define RX_EXTRA_DATA_ACCEPT 0x4000
        !           163: #define RX_ALL_ACCEPT (RX_PROM_ACCEPT|RX_BAD_CRC_ACCEPT|RX_RUNT_ACCEPT|RX_EXTRA_DATA_ACCEPT)
        !           164: /*  Default receive mode - individually addressed, broadcast, and error free */
        !           165: #define DEF_RX_ACCEPT (RX_IA_ACCEPT | RX_BROADCAST_ACCEPT | RX_OK_ACCEPT)
        !           166: 
        !           167: /* PP_TxCFG - Transmit Configuration Interrupt Mask bit definition - Read/write */
        !           168: #define TX_LOST_CRS_ENBL 0x0040
        !           169: #define TX_SQE_ERROR_ENBL 0x0080
        !           170: #define TX_OK_ENBL 0x0100
        !           171: #define TX_LATE_COL_ENBL 0x0200
        !           172: #define TX_JBR_ENBL 0x0400
        !           173: #define TX_ANY_COL_ENBL 0x0800
        !           174: #define TX_16_COL_ENBL 0x8000
        !           175: 
        !           176: /* PP_TxCMD - Transmit Command bit definition - Read-only */
        !           177: #define TX_START_4_BYTES 0x0000
        !           178: #define TX_START_64_BYTES 0x0040
        !           179: #define TX_START_128_BYTES 0x0080
        !           180: #define TX_START_ALL_BYTES 0x00C0
        !           181: #define TX_FORCE 0x0100
        !           182: #define TX_ONE_COL 0x0200
        !           183: #define TX_TWO_PART_DEFF_DISABLE 0x0400
        !           184: #define TX_NO_CRC 0x1000
        !           185: #define TX_RUNT 0x2000
        !           186: 
        !           187: /* PP_BufCFG - Buffer Configuration Interrupt Mask bit definition - Read/write */
        !           188: #define GENERATE_SW_INTERRUPT 0x0040
        !           189: #define RX_DMA_ENBL 0x0080
        !           190: #define READY_FOR_TX_ENBL 0x0100
        !           191: #define TX_UNDERRUN_ENBL 0x0200
        !           192: #define RX_MISS_ENBL 0x0400
        !           193: #define RX_128_BYTE_ENBL 0x0800
        !           194: #define TX_COL_COUNT_OVRFLOW_ENBL 0x1000
        !           195: #define RX_MISS_COUNT_OVRFLOW_ENBL 0x2000
        !           196: #define RX_DEST_MATCH_ENBL 0x8000
        !           197: 
        !           198: /* PP_LineCTL - Line Control bit definition - Read/write */
        !           199: #define SERIAL_RX_ON 0x0040
        !           200: #define SERIAL_TX_ON 0x0080
        !           201: #define AUI_ONLY 0x0100
        !           202: #define AUTO_AUI_10BASET 0x0200
        !           203: #define MODIFIED_BACKOFF 0x0800
        !           204: #define NO_AUTO_POLARITY 0x1000
        !           205: #define TWO_PART_DEFDIS 0x2000
        !           206: #define LOW_RX_SQUELCH 0x4000
        !           207: 
        !           208: /* PP_SelfCTL - Software Self Control bit definition - Read/write */
        !           209: #define POWER_ON_RESET 0x0040
        !           210: #define SW_STOP 0x0100
        !           211: #define SLEEP_ON 0x0200
        !           212: #define AUTO_WAKEUP 0x0400
        !           213: #define HCB0_ENBL 0x1000
        !           214: #define HCB1_ENBL 0x2000
        !           215: #define HCB0 0x4000
        !           216: #define HCB1 0x8000
        !           217: 
        !           218: /* PP_BusCTL - ISA Bus Control bit definition - Read/write */
        !           219: #define RESET_RX_DMA 0x0040
        !           220: #define MEMORY_ON 0x0400
        !           221: #define DMA_BURST_MODE 0x0800
        !           222: #define IO_CHANNEL_READY_ON 0x1000
        !           223: #define RX_DMA_SIZE_64K 0x2000
        !           224: #define ENABLE_IRQ 0x8000
        !           225: 
        !           226: /* PP_TestCTL - Test Control bit definition - Read/write */
        !           227: #define LINK_OFF 0x0080
        !           228: #define ENDEC_LOOPBACK 0x0200
        !           229: #define AUI_LOOPBACK 0x0400
        !           230: #define BACKOFF_OFF 0x0800
        !           231: #define FAST_TEST 0x8000
        !           232: 
        !           233: /* PP_RxEvent - Receive Event Bit definition - Read-only */
        !           234: #define RX_IA_HASHED 0x0040
        !           235: #define RX_DRIBBLE 0x0080
        !           236: #define RX_OK 0x0100
        !           237: #define RX_HASHED 0x0200
        !           238: #define RX_IA 0x0400
        !           239: #define RX_BROADCAST 0x0800
        !           240: #define RX_CRC_ERROR 0x1000
        !           241: #define RX_RUNT 0x2000
        !           242: #define RX_EXTRA_DATA 0x4000
        !           243: 
        !           244: #define HASH_INDEX_MASK 0x0FC00
        !           245: 
        !           246: /* PP_TxEvent - Transmit Event Bit definition - Read-only */
        !           247: #define TX_LOST_CRS 0x0040
        !           248: #define TX_SQE_ERROR 0x0080
        !           249: #define TX_OK 0x0100
        !           250: #define TX_LATE_COL 0x0200
        !           251: #define TX_JBR 0x0400
        !           252: #define TX_16_COL 0x8000
        !           253: #define TX_SEND_OK_BITS (TX_OK|TX_LOST_CRS)
        !           254: #define TX_COL_COUNT_MASK 0x7800
        !           255: 
        !           256: /* PP_BufEvent - Buffer Event Bit definition - Read-only */
        !           257: #define SW_INTERRUPT 0x0040
        !           258: #define RX_DMA 0x0080
        !           259: #define READY_FOR_TX 0x0100
        !           260: #define TX_UNDERRUN 0x0200
        !           261: #define RX_MISS 0x0400
        !           262: #define RX_128_BYTE 0x0800
        !           263: #define TX_COL_OVRFLW 0x1000
        !           264: #define RX_MISS_OVRFLW 0x2000
        !           265: #define RX_DEST_MATCH 0x8000
        !           266: 
        !           267: /* PP_LineST - Ethernet Line Status bit definition - Read-only */
        !           268: #define LINK_OK 0x0080
        !           269: #define AUI_ON 0x0100
        !           270: #define TENBASET_ON 0x0200
        !           271: #define POLARITY_OK 0x1000
        !           272: #define CRS_OK 0x4000
        !           273: 
        !           274: /* PP_SelfST - Chip Software Status bit definition */
        !           275: #define ACTIVE_33V 0x0040
        !           276: #define INIT_DONE 0x0080
        !           277: #define SI_BUSY 0x0100
        !           278: #define EEPROM_PRESENT 0x0200
        !           279: #define EEPROM_OK 0x0400
        !           280: #define EL_PRESENT 0x0800
        !           281: #define EE_SIZE_64 0x1000
        !           282: 
        !           283: /* PP_BusST - ISA Bus Status bit definition */
        !           284: #define TX_BID_ERROR 0x0080
        !           285: #define READY_FOR_TX_NOW 0x0100
        !           286: 
        !           287: /* PP_AutoNegCTL - Auto Negotiation Control bit definition */
        !           288: #define RE_NEG_NOW 0x0040
        !           289: #define ALLOW_FDX 0x0080
        !           290: #define AUTO_NEG_ENABLE 0x0100
        !           291: #define NLP_ENABLE 0x0200
        !           292: #define FORCE_FDX 0x8000
        !           293: #define AUTO_NEG_BITS (FORCE_FDX|NLP_ENABLE|AUTO_NEG_ENABLE)
        !           294: #define AUTO_NEG_MASK (FORCE_FDX|NLP_ENABLE|AUTO_NEG_ENABLE|ALLOW_FDX|RE_NEG_NOW)
        !           295: 
        !           296: /* PP_AutoNegST - Auto Negotiation Status bit definition */
        !           297: #define AUTO_NEG_BUSY 0x0080
        !           298: #define FLP_LINK 0x0100
        !           299: #define FLP_LINK_GOOD 0x0800
        !           300: #define LINK_FAULT 0x1000
        !           301: #define HDX_ACTIVE 0x4000
        !           302: #define FDX_ACTIVE 0x8000
        !           303: 
        !           304: /*  The following block defines the ISQ event types */
        !           305: #define ISQ_RECEIVER_EVENT 0x04
        !           306: #define ISQ_TRANSMITTER_EVENT 0x08
        !           307: #define ISQ_BUFFER_EVENT 0x0c
        !           308: #define ISQ_RX_MISS_EVENT 0x10
        !           309: #define ISQ_TX_COL_EVENT 0x12
        !           310: 
        !           311: #define ISQ_EVENT_MASK 0x003F   /*  ISQ mask to find out type of event */
        !           312: #define ISQ_HIST 16            /*  small history buffer */
        !           313: #define AUTOINCREMENT 0x8000   /*  Bit mask to set bit-15 for autoincrement */
        !           314: 
        !           315: #define TXRXBUFSIZE 0x0600
        !           316: #define RXDMABUFSIZE 0x8000
        !           317: #define RXDMASIZE 0x4000
        !           318: #define TXRX_LENGTH_MASK 0x07FF
        !           319: 
        !           320: /*  rx options bits */
        !           321: #define RCV_WITH_RXON  1       /*  Set SerRx ON */
        !           322: #define RCV_COUNTS     2       /*  Use Framecnt1 */
        !           323: #define RCV_PONG       4       /*  Pong respondent */
        !           324: #define RCV_DONG       8       /*  Dong operation */
        !           325: #define RCV_POLLING    0x10    /*  Poll RxEvent */
        !           326: #define RCV_ISQ                0x20    /*  Use ISQ, int */
        !           327: #define RCV_AUTO_DMA   0x100   /*  Set AutoRxDMAE */
        !           328: #define RCV_DMA                0x200   /*  Set RxDMA only */
        !           329: #define RCV_DMA_ALL    0x400   /*  Copy all DMA'ed */
        !           330: #define RCV_FIXED_DATA 0x800   /*  Every frame same */
        !           331: #define RCV_IO         0x1000  /*  Use ISA IO only */
        !           332: #define RCV_MEMORY     0x2000  /*  Use ISA Memory */
        !           333: 
        !           334: #define RAM_SIZE       0x1000       /*  The card has 4k bytes or RAM */
        !           335: #define PKT_START PP_TxFrame  /*  Start of packet RAM */
        !           336: 
        !           337: #define RX_FRAME_PORT  0x0000
        !           338: #define TX_FRAME_PORT RX_FRAME_PORT
        !           339: #define TX_CMD_PORT    0x0004
        !           340: #define TX_NOW         0x0000       /*  Tx packet after   5 bytes copied */
        !           341: #define TX_AFTER_381   0x0020       /*  Tx packet after 381 bytes copied */
        !           342: #define TX_AFTER_ALL   0x00C0       /*  Tx packet after all bytes copied */
        !           343: #define TX_LEN_PORT    0x0006
        !           344: #define ISQ_PORT       0x0008
        !           345: #define ADD_PORT       0x000A
        !           346: #define DATA_PORT      0x000C
        !           347: 
        !           348: #define EEPROM_WRITE_EN                0x00F0
        !           349: #define EEPROM_WRITE_DIS       0x0000
        !           350: #define EEPROM_WRITE_CMD       0x0100
        !           351: #define EEPROM_READ_CMD                0x0200
        !           352: 
        !           353: /*  Receive Header */
        !           354: /*  Description of header of each packet in receive area of memory */
        !           355: #define RBUF_EVENT_LOW 0   /*  Low byte of RxEvent - status of received frame */
        !           356: #define RBUF_EVENT_HIGH        1   /*  High byte of RxEvent - status of received frame */
        !           357: #define RBUF_LEN_LOW   2   /*  Length of received data - low byte */
        !           358: #define RBUF_LEN_HI    3   /*  Length of received data - high byte */
        !           359: #define RBUF_HEAD_LEN  4   /*  Length of this header */
        !           360: 
        !           361: #define CHIP_READ 0x1   /*  Used to mark state of the repins code (chip or dma) */
        !           362: #define DMA_READ 0x2   /*  Used to mark state of the repins code (chip or dma) */
        !           363: 
        !           364: /*  for bios scan */
        !           365: /*  */
        !           366: #ifdef CSDEBUG
        !           367: /*  use these values for debugging bios scan */
        !           368: #define BIOS_START_SEG 0x00000
        !           369: #define BIOS_OFFSET_INC 0x0010
        !           370: #else
        !           371: #define BIOS_START_SEG 0x0c000
        !           372: #define BIOS_OFFSET_INC 0x0200
        !           373: #endif
        !           374: 
        !           375: #define BIOS_LAST_OFFSET 0x0fc00
        !           376: 
        !           377: /*  Byte offsets into the EEPROM configuration buffer */
        !           378: #define ISA_CNF_OFFSET 0x6
        !           379: #define TX_CTL_OFFSET (ISA_CNF_OFFSET + 8)                     /*  8900 eeprom */
        !           380: #define AUTO_NEG_CNF_OFFSET (ISA_CNF_OFFSET + 8)               /*  8920 eeprom */
        !           381: 
        !           382:   /*  the assumption here is that the bits in the eeprom are generally  */
        !           383:   /*  in the same position as those in the autonegctl register. */
        !           384:   /*  Of course the IMM bit is not in that register so it must be  */
        !           385:   /*  masked out */
        !           386: #define EE_FORCE_FDX  0x8000
        !           387: #define EE_NLP_ENABLE 0x0200
        !           388: #define EE_AUTO_NEG_ENABLE 0x0100
        !           389: #define EE_ALLOW_FDX 0x0080
        !           390: #define EE_AUTO_NEG_CNF_MASK (EE_FORCE_FDX|EE_NLP_ENABLE|EE_AUTO_NEG_ENABLE|EE_ALLOW_FDX)
        !           391: 
        !           392: #define IMM_BIT 0x0040         /*  ignore missing media */
        !           393: 
        !           394: #define ADAPTER_CNF_OFFSET (AUTO_NEG_CNF_OFFSET + 2)
        !           395: #define A_CNF_10B_T 0x0001
        !           396: #define A_CNF_AUI 0x0002
        !           397: #define A_CNF_10B_2 0x0004
        !           398: #define A_CNF_MEDIA_TYPE 0x0060
        !           399: #define A_CNF_MEDIA_AUTO 0x0000
        !           400: #define A_CNF_MEDIA_10B_T 0x0020
        !           401: #define A_CNF_MEDIA_AUI 0x0040
        !           402: #define A_CNF_MEDIA_10B_2 0x0060
        !           403: #define A_CNF_DC_DC_POLARITY 0x0080
        !           404: #define A_CNF_NO_AUTO_POLARITY 0x2000
        !           405: #define A_CNF_LOW_RX_SQUELCH 0x4000
        !           406: #define A_CNF_EXTND_10B_2 0x8000
        !           407: 
        !           408: #define PACKET_PAGE_OFFSET 0x8
        !           409: 
        !           410: /*  Bit definitions for the ISA configuration word from the EEPROM */
        !           411: #define INT_NO_MASK 0x000F
        !           412: #define DMA_NO_MASK 0x0070
        !           413: #define ISA_DMA_SIZE 0x0200
        !           414: #define ISA_AUTO_RxDMA 0x0400
        !           415: #define ISA_RxDMA 0x0800
        !           416: #define DMA_BURST 0x1000
        !           417: #define STREAM_TRANSFER 0x2000
        !           418: #define ANY_ISA_DMA (ISA_AUTO_RxDMA | ISA_RxDMA)
        !           419: 
        !           420: /*  DMA controller registers */
        !           421: #define DMA_BASE 0x00     /*  DMA controller base */
        !           422: #define DMA_BASE_2 0x0C0    /*  DMA controller base */
        !           423: 
        !           424: #define DMA_STAT 0x0D0    /*  DMA controller status register */
        !           425: #define DMA_MASK 0x0D4    /*  DMA controller mask register */
        !           426: #define DMA_MODE 0x0D6    /*  DMA controller mode register */
        !           427: #define DMA_RESETFF 0x0D8    /*  DMA controller first/last flip flop */
        !           428: 
        !           429: /*  DMA data */
        !           430: #define DMA_DISABLE 0x04     /*  Disable channel n */
        !           431: #define DMA_ENABLE 0x00     /*  Enable channel n */
        !           432: /*  Demand transfers, incr. address, auto init, writes, ch. n */
        !           433: #define DMA_RX_MODE 0x14
        !           434: /*  Demand transfers, incr. address, auto init, reads, ch. n */
        !           435: #define DMA_TX_MODE 0x18
        !           436: 
        !           437: #define DMA_SIZE (16*1024) /*  Size of dma buffer - 16k */
        !           438: 
        !           439: #define CS8900 0x0000
        !           440: #define CS8920 0x4000
        !           441: #define CS8920M 0x6000
        !           442: #define REVISON_BITS 0x1F00
        !           443: #define EEVER_NUMBER 0x12
        !           444: #define CHKSUM_LEN 0x14
        !           445: #define CHKSUM_VAL 0x0000
        !           446: #define START_EEPROM_DATA 0x001c /*  Offset into eeprom for start of data */
        !           447: #define IRQ_MAP_EEPROM_DATA 0x0046 /*  Offset into eeprom for the IRQ map */
        !           448: #define IRQ_MAP_LEN 0x0004 /*  No of bytes to read for the IRQ map */
        !           449: #define PNP_IRQ_FRMT 0x0022 /*  PNP small item IRQ format */
        !           450: #define CS8900_IRQ_MAP 0x1c20 /*  This IRQ map is fixed */
        !           451: 
        !           452: #define CS8920_NO_INTS 0x0F   /*  Max CS8920 interrupt select # */
        !           453: 
        !           454: #define PNP_ADD_PORT 0x0279
        !           455: #define PNP_WRITE_PORT 0x0A79
        !           456: 
        !           457: #define GET_PNP_ISA_STRUCT 0x40
        !           458: #define PNP_ISA_STRUCT_LEN 0x06
        !           459: #define PNP_CSN_CNT_OFF 0x01
        !           460: #define PNP_RD_PORT_OFF 0x02
        !           461: #define PNP_FUNCTION_OK 0x00
        !           462: #define PNP_WAKE 0x03
        !           463: #define PNP_RSRC_DATA 0x04
        !           464: #define PNP_RSRC_READY 0x01
        !           465: #define PNP_STATUS 0x05
        !           466: #define PNP_ACTIVATE 0x30
        !           467: #define PNP_CNF_IO_H 0x60
        !           468: #define PNP_CNF_IO_L 0x61
        !           469: #define PNP_CNF_INT 0x70
        !           470: #define PNP_CNF_DMA 0x74
        !           471: #define PNP_CNF_MEM 0x48
        !           472: 
        !           473: #define BIT0 1
        !           474: #define BIT15 0x8000
        !           475: 
        !           476: /*
        !           477:  * Local variables:
        !           478:  *  c-basic-offset: 8
        !           479:  * End:
        !           480:  */
        !           481: 

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