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1.1 root 1: #ifdef ALLMULTI
2: #error multicast support is not yet implemented
3: #endif
4: /*
5: DAVICOM DM9009/DM9102/DM9102A Etherboot Driver V1.00
6:
7: This driver was ported from Marty Connor's Tulip Etherboot driver.
8: Thanks Marty Connor ([email protected])
9:
10: This davicom etherboot driver supports DM9009/DM9102/DM9102A/
11: DM9102A+DM9801/DM9102A+DM9802 NICs.
12:
13: This software may be used and distributed according to the terms
14: of the GNU Public License, incorporated herein by reference.
15:
16: */
17:
18: FILE_LICENCE ( GPL_ANY );
19:
20: /*********************************************************************/
21: /* Revision History */
22: /*********************************************************************/
23:
24: /*
25: 19 OCT 2000 Sten 1.00
26: Different half and full duplex mode
27: Do the different programming for DM9801/DM9802
28:
29: 12 OCT 2000 Sten 0.90
30: This driver was ported from tulip driver and it
31: has the following difference.
32: Changed symbol tulip/TULIP to davicom/DAVICOM
33: Deleted some code that did not use in this driver.
34: Used chain-strcture to replace ring structure
35: for both TX/RX descriptor.
36: Allocated two tx descriptor.
37: According current media mode to set operating
38: register(CR6)
39: */
40:
41:
42: /*********************************************************************/
43: /* Declarations */
44: /*********************************************************************/
45:
46: #include "etherboot.h"
47: #include "nic.h"
48: #include <ipxe/pci.h>
49: #include <ipxe/ethernet.h>
50:
51: #define TX_TIME_OUT 2*TICKS_PER_SEC
52:
53: /* Register offsets for davicom device */
54: enum davicom_offsets {
55: CSR0=0, CSR1=0x08, CSR2=0x10, CSR3=0x18, CSR4=0x20, CSR5=0x28,
56: CSR6=0x30, CSR7=0x38, CSR8=0x40, CSR9=0x48, CSR10=0x50, CSR11=0x58,
57: CSR12=0x60, CSR13=0x68, CSR14=0x70, CSR15=0x78, CSR16=0x80, CSR20=0xA0
58: };
59:
60: /* EEPROM Address width definitions */
61: #define EEPROM_ADDRLEN 6
62: #define EEPROM_SIZE 32 /* 1 << EEPROM_ADDRLEN */
63: /* Used to be 128, but we only need to read enough to get the MAC
64: address at bytes 20..25 */
65:
66: /* Data Read from the EEPROM */
67: static unsigned char ee_data[EEPROM_SIZE];
68:
69: /* The EEPROM commands include the alway-set leading bit. */
70: #define EE_WRITE_CMD (5 << addr_len)
71: #define EE_READ_CMD (6 << addr_len)
72: #define EE_ERASE_CMD (7 << addr_len)
73:
74: /* EEPROM_Ctrl bits. */
75: #define EE_SHIFT_CLK 0x02 /* EEPROM shift clock. */
76: #define EE_CS 0x01 /* EEPROM chip select. */
77: #define EE_DATA_WRITE 0x04 /* EEPROM chip data in. */
78: #define EE_WRITE_0 0x01
79: #define EE_WRITE_1 0x05
80: #define EE_DATA_READ 0x08 /* EEPROM chip data out. */
81: #define EE_ENB (0x4800 | EE_CS)
82:
83: /* Sten 10/11 for phyxcer */
84: #define PHY_DATA_0 0x0
85: #define PHY_DATA_1 0x20000
86: #define MDCLKH 0x10000
87:
88: /* Delay between EEPROM clock transitions. Even at 33Mhz current PCI
89: implementations don't overrun the EEPROM clock. We add a bus
90: turn-around to insure that this remains true. */
91: #define eeprom_delay() inl(ee_addr)
92:
93: /* helpful macro if on a big_endian machine for changing byte order.
94: not strictly needed on Intel
95: Already defined in Etherboot includes
96: #define le16_to_cpu(val) (val)
97: */
98:
99: /* transmit and receive descriptor format */
100: struct txdesc {
101: volatile unsigned long status; /* owner, status */
102: unsigned long buf1sz:11, /* size of buffer 1 */
103: buf2sz:11, /* size of buffer 2 */
104: control:10; /* control bits */
105: const unsigned char *buf1addr; /* buffer 1 address */
106: const unsigned char *buf2addr; /* buffer 2 address */
107: };
108:
109: struct rxdesc {
110: volatile unsigned long status; /* owner, status */
111: unsigned long buf1sz:11, /* size of buffer 1 */
112: buf2sz:11, /* size of buffer 2 */
113: control:10; /* control bits */
114: unsigned char *buf1addr; /* buffer 1 address */
115: unsigned char *buf2addr; /* buffer 2 address */
116: };
117:
118: /* Size of transmit and receive buffers */
119: #define BUFLEN 1536
120:
121: /*********************************************************************/
122: /* Global Storage */
123: /*********************************************************************/
124:
125: static struct nic_operations davicom_operations;
126:
127: /* PCI Bus parameters */
128: static unsigned short vendor, dev_id;
129: static unsigned long ioaddr;
130:
131: /* Note: transmit and receive buffers must be longword aligned and
132: longword divisable */
133:
134: /* transmit descriptor and buffer */
135: #define NTXD 2
136: #define NRXD 4
137: struct {
138: struct txdesc txd[NTXD] __attribute__ ((aligned(4)));
139: unsigned char txb[BUFLEN] __attribute__ ((aligned(4)));
140: struct rxdesc rxd[NRXD] __attribute__ ((aligned(4)));
141: unsigned char rxb[NRXD * BUFLEN] __attribute__ ((aligned(4)));
142: } davicom_bufs __shared;
143: #define txd davicom_bufs.txd
144: #define txb davicom_bufs.txb
145: #define rxd davicom_bufs.rxd
146: #define rxb davicom_bufs.rxb
147: static int rxd_tail;
148: static int TxPtr;
149:
150:
151: /*********************************************************************/
152: /* Function Prototypes */
153: /*********************************************************************/
154: static void whereami(const char *str);
155: static int read_eeprom(unsigned long ioaddr, int location, int addr_len);
156: static int davicom_probe(struct nic *nic,struct pci_device *pci);
157: static void davicom_init_chain(struct nic *nic); /* Sten 10/9 */
158: static void davicom_reset(struct nic *nic);
159: static void davicom_transmit(struct nic *nic, const char *d, unsigned int t,
160: unsigned int s, const char *p);
161: static int davicom_poll(struct nic *nic, int retrieve);
162: static void davicom_disable(struct nic *nic);
163: static void davicom_wait(unsigned int nticks);
164: static int phy_read(int);
165: static void phy_write(int, u16);
166: static void phy_write_1bit(u32, u32);
167: static int phy_read_1bit(u32);
168: static void davicom_media_chk(struct nic *);
169:
170:
171: /*********************************************************************/
172: /* Utility Routines */
173: /*********************************************************************/
174: static inline void whereami(const char *str)
175: {
176: DBGP("%s\n", str);
177: /* sleep(2); */
178: }
179:
180: static void davicom_wait(unsigned int nticks)
181: {
182: unsigned int to = currticks() + nticks;
183: while (currticks() < to)
184: /* wait */ ;
185: }
186:
187:
188: /*********************************************************************/
189: /* For DAVICOM phyxcer register by MII interface */
190: /*********************************************************************/
191: /*
192: Read a word data from phy register
193: */
194: static int phy_read(int location)
195: {
196: int i, phy_addr=1;
197: u16 phy_data;
198: u32 io_dcr9;
199:
200: whereami("phy_read\n");
201:
202: io_dcr9 = ioaddr + CSR9;
203:
204: /* Send 33 synchronization clock to Phy controller */
205: for (i=0; i<34; i++)
206: phy_write_1bit(io_dcr9, PHY_DATA_1);
207:
208: /* Send start command(01) to Phy */
209: phy_write_1bit(io_dcr9, PHY_DATA_0);
210: phy_write_1bit(io_dcr9, PHY_DATA_1);
211:
212: /* Send read command(10) to Phy */
213: phy_write_1bit(io_dcr9, PHY_DATA_1);
214: phy_write_1bit(io_dcr9, PHY_DATA_0);
215:
216: /* Send Phy addres */
217: for (i=0x10; i>0; i=i>>1)
218: phy_write_1bit(io_dcr9, phy_addr&i ? PHY_DATA_1: PHY_DATA_0);
219:
220: /* Send register addres */
221: for (i=0x10; i>0; i=i>>1)
222: phy_write_1bit(io_dcr9, location&i ? PHY_DATA_1: PHY_DATA_0);
223:
224: /* Skip transition state */
225: phy_read_1bit(io_dcr9);
226:
227: /* read 16bit data */
228: for (phy_data=0, i=0; i<16; i++) {
229: phy_data<<=1;
230: phy_data|=phy_read_1bit(io_dcr9);
231: }
232:
233: return phy_data;
234: }
235:
236: /*
237: Write a word to Phy register
238: */
239: static void phy_write(int location, u16 phy_data)
240: {
241: u16 i, phy_addr=1;
242: u32 io_dcr9;
243:
244: whereami("phy_write\n");
245:
246: io_dcr9 = ioaddr + CSR9;
247:
248: /* Send 33 synchronization clock to Phy controller */
249: for (i=0; i<34; i++)
250: phy_write_1bit(io_dcr9, PHY_DATA_1);
251:
252: /* Send start command(01) to Phy */
253: phy_write_1bit(io_dcr9, PHY_DATA_0);
254: phy_write_1bit(io_dcr9, PHY_DATA_1);
255:
256: /* Send write command(01) to Phy */
257: phy_write_1bit(io_dcr9, PHY_DATA_0);
258: phy_write_1bit(io_dcr9, PHY_DATA_1);
259:
260: /* Send Phy addres */
261: for (i=0x10; i>0; i=i>>1)
262: phy_write_1bit(io_dcr9, phy_addr&i ? PHY_DATA_1: PHY_DATA_0);
263:
264: /* Send register addres */
265: for (i=0x10; i>0; i=i>>1)
266: phy_write_1bit(io_dcr9, location&i ? PHY_DATA_1: PHY_DATA_0);
267:
268: /* written trasnition */
269: phy_write_1bit(io_dcr9, PHY_DATA_1);
270: phy_write_1bit(io_dcr9, PHY_DATA_0);
271:
272: /* Write a word data to PHY controller */
273: for (i=0x8000; i>0; i>>=1)
274: phy_write_1bit(io_dcr9, phy_data&i ? PHY_DATA_1: PHY_DATA_0);
275: }
276:
277: /*
278: Write one bit data to Phy Controller
279: */
280: static void phy_write_1bit(u32 ee_addr, u32 phy_data)
281: {
282: whereami("phy_write_1bit\n");
283: outl(phy_data, ee_addr); /* MII Clock Low */
284: eeprom_delay();
285: outl(phy_data|MDCLKH, ee_addr); /* MII Clock High */
286: eeprom_delay();
287: outl(phy_data, ee_addr); /* MII Clock Low */
288: eeprom_delay();
289: }
290:
291: /*
292: Read one bit phy data from PHY controller
293: */
294: static int phy_read_1bit(u32 ee_addr)
295: {
296: int phy_data;
297:
298: whereami("phy_read_1bit\n");
299:
300: outl(0x50000, ee_addr);
301: eeprom_delay();
302:
303: phy_data=(inl(ee_addr)>>19) & 0x1;
304:
305: outl(0x40000, ee_addr);
306: eeprom_delay();
307:
308: return phy_data;
309: }
310:
311: /*
312: DM9801/DM9802 present check and program
313: */
314: static void HPNA_process(void)
315: {
316:
317: if ( (phy_read(3) & 0xfff0) == 0xb900 ) {
318: if ( phy_read(31) == 0x4404 ) {
319: /* DM9801 present */
320: if (phy_read(3) == 0xb901)
321: phy_write(16, 0x5); /* DM9801 E4 */
322: else
323: phy_write(16, 0x1005); /* DM9801 E3 and others */
324: phy_write(25, ((phy_read(24) + 3) & 0xff) | 0xf000);
325: } else {
326: /* DM9802 present */
327: phy_write(16, 0x5);
328: phy_write(25, (phy_read(25) & 0xff00) + 2);
329: }
330: }
331: }
332:
333: /*
334: Sense media mode and set CR6
335: */
336: static void davicom_media_chk(struct nic * nic __unused)
337: {
338: unsigned long to, csr6;
339:
340: csr6 = 0x00200000; /* SF */
341: outl(csr6, ioaddr + CSR6);
342:
343: #define PCI_DEVICE_ID_DM9009 0x9009
344: if (vendor == PCI_VENDOR_ID_DAVICOM && dev_id == PCI_DEVICE_ID_DM9009) {
345: /* Set to 10BaseT mode for DM9009 */
346: phy_write(0, 0);
347: } else {
348: /* For DM9102/DM9102A */
349: to = currticks() + 2 * TICKS_PER_SEC;
350: while ( ((phy_read(1) & 0x24)!=0x24) && (currticks() < to))
351: /* wait */ ;
352:
353: if ( (phy_read(1) & 0x24) == 0x24 ) {
354: if (phy_read(17) & 0xa000)
355: csr6 |= 0x00000200; /* Full Duplex mode */
356: } else
357: csr6 |= 0x00040000; /* Select DM9801/DM9802 when Ethernet link failed */
358: }
359:
360: /* set the chip's operating mode */
361: outl(csr6, ioaddr + CSR6);
362:
363: /* DM9801/DM9802 present check & program */
364: if (csr6 & 0x40000)
365: HPNA_process();
366: }
367:
368:
369: /*********************************************************************/
370: /* EEPROM Reading Code */
371: /*********************************************************************/
372: /* EEPROM routines adapted from the Linux Tulip Code */
373: /* Reading a serial EEPROM is a "bit" grungy, but we work our way
374: through:->.
375: */
376: static int read_eeprom(unsigned long ioaddr, int location, int addr_len)
377: {
378: int i;
379: unsigned short retval = 0;
380: long ee_addr = ioaddr + CSR9;
381: int read_cmd = location | EE_READ_CMD;
382:
383: whereami("read_eeprom\n");
384:
385: outl(EE_ENB & ~EE_CS, ee_addr);
386: outl(EE_ENB, ee_addr);
387:
388: /* Shift the read command bits out. */
389: for (i = 4 + addr_len; i >= 0; i--) {
390: short dataval = (read_cmd & (1 << i)) ? EE_DATA_WRITE : 0;
391: outl(EE_ENB | dataval, ee_addr);
392: eeprom_delay();
393: outl(EE_ENB | dataval | EE_SHIFT_CLK, ee_addr);
394: eeprom_delay();
395: }
396: outl(EE_ENB, ee_addr);
397:
398: for (i = 16; i > 0; i--) {
399: outl(EE_ENB | EE_SHIFT_CLK, ee_addr);
400: eeprom_delay();
401: retval = (retval << 1) | ((inl(ee_addr) & EE_DATA_READ) ? 1 : 0);
402: outl(EE_ENB, ee_addr);
403: eeprom_delay();
404: }
405:
406: /* Terminate the EEPROM access. */
407: outl(EE_ENB & ~EE_CS, ee_addr);
408: return retval;
409: }
410:
411: /*********************************************************************/
412: /* davicom_init_chain - setup the tx and rx descriptors */
413: /* Sten 10/9 */
414: /*********************************************************************/
415: static void davicom_init_chain(struct nic *nic)
416: {
417: int i;
418:
419: /* setup the transmit descriptor */
420: /* Sten: Set 2 TX descriptor but use one TX buffer because
421: it transmit a packet and wait complete every time. */
422: for (i=0; i<NTXD; i++) {
423: txd[i].buf1addr = (void *)virt_to_bus(&txb[0]); /* Used same TX buffer */
424: txd[i].buf2addr = (void *)virt_to_bus(&txd[i+1]); /* Point to Next TX desc */
425: txd[i].buf1sz = 0;
426: txd[i].buf2sz = 0;
427: txd[i].control = 0x184; /* Begin/End/Chain */
428: txd[i].status = 0x00000000; /* give ownership to Host */
429: }
430:
431: /* construct perfect filter frame with mac address as first match
432: and broadcast address for all others */
433: for (i=0; i<192; i++) txb[i] = 0xFF;
434: txb[0] = nic->node_addr[0];
435: txb[1] = nic->node_addr[1];
436: txb[4] = nic->node_addr[2];
437: txb[5] = nic->node_addr[3];
438: txb[8] = nic->node_addr[4];
439: txb[9] = nic->node_addr[5];
440:
441: /* setup receive descriptor */
442: for (i=0; i<NRXD; i++) {
443: rxd[i].buf1addr = (void *)virt_to_bus(&rxb[i * BUFLEN]);
444: rxd[i].buf2addr = (void *)virt_to_bus(&rxd[i+1]); /* Point to Next RX desc */
445: rxd[i].buf1sz = BUFLEN;
446: rxd[i].buf2sz = 0; /* not used */
447: rxd[i].control = 0x4; /* Chain Structure */
448: rxd[i].status = 0x80000000; /* give ownership to device */
449: }
450:
451: /* Chain the last descriptor to first */
452: txd[NTXD - 1].buf2addr = (void *)virt_to_bus(&txd[0]);
453: rxd[NRXD - 1].buf2addr = (void *)virt_to_bus(&rxd[0]);
454: TxPtr = 0;
455: rxd_tail = 0;
456: }
457:
458:
459: /*********************************************************************/
460: /* davicom_reset - Reset adapter */
461: /*********************************************************************/
462: static void davicom_reset(struct nic *nic)
463: {
464: unsigned long to;
465:
466: whereami("davicom_reset\n");
467:
468: /* Stop Tx and RX */
469: outl(inl(ioaddr + CSR6) & ~0x00002002, ioaddr + CSR6);
470:
471: /* Reset the chip, holding bit 0 set at least 50 PCI cycles. */
472: outl(0x00000001, ioaddr + CSR0);
473:
474: davicom_wait(TICKS_PER_SEC);
475:
476: /* TX/RX descriptor burst */
477: outl(0x0C00000, ioaddr + CSR0); /* Sten 10/9 */
478:
479: /* set up transmit and receive descriptors */
480: davicom_init_chain(nic); /* Sten 10/9 */
481:
482: /* Point to receive descriptor */
483: outl(virt_to_bus(&rxd[0]), ioaddr + CSR3);
484: outl(virt_to_bus(&txd[0]), ioaddr + CSR4); /* Sten 10/9 */
485:
486: /* According phyxcer media mode to set CR6,
487: DM9102/A phyxcer can auto-detect media mode */
488: davicom_media_chk(nic);
489:
490: /* Prepare Setup Frame Sten 10/9 */
491: txd[TxPtr].buf1sz = 192;
492: txd[TxPtr].control = 0x024; /* SF/CE */
493: txd[TxPtr].status = 0x80000000; /* Give ownership to device */
494:
495: /* Start Tx */
496: outl(inl(ioaddr + CSR6) | 0x00002000, ioaddr + CSR6);
497: /* immediate transmit demand */
498: outl(0, ioaddr + CSR1);
499:
500: to = currticks() + TX_TIME_OUT;
501: while ((txd[TxPtr].status & 0x80000000) && (currticks() < to)) /* Sten 10/9 */
502: /* wait */ ;
503:
504: if (currticks() >= to) {
505: DBG ("TX Setup Timeout!\n");
506: }
507: /* Point to next TX descriptor */
508: TxPtr = (++TxPtr >= NTXD) ? 0:TxPtr; /* Sten 10/9 */
509:
510: DBG("txd.status = %lX\n", txd[TxPtr].status);
511: DBG("ticks = %ld\n", currticks() - (to - TX_TIME_OUT));
512: DBG_MORE();
513:
514: /* enable RX */
515: outl(inl(ioaddr + CSR6) | 0x00000002, ioaddr + CSR6);
516: /* immediate poll demand */
517: outl(0, ioaddr + CSR2);
518: }
519:
520:
521: /*********************************************************************/
522: /* eth_transmit - Transmit a frame */
523: /*********************************************************************/
524: static void davicom_transmit(struct nic *nic, const char *d, unsigned int t,
525: unsigned int s, const char *p)
526: {
527: unsigned long to;
528:
529: whereami("davicom_transmit\n");
530:
531: /* Stop Tx */
532: /* outl(inl(ioaddr + CSR6) & ~0x00002000, ioaddr + CSR6); */
533:
534: /* setup ethernet header */
535: memcpy(&txb[0], d, ETH_ALEN); /* DA 6byte */
536: memcpy(&txb[ETH_ALEN], nic->node_addr, ETH_ALEN); /* SA 6byte*/
537: txb[ETH_ALEN*2] = (t >> 8) & 0xFF; /* Frame type: 2byte */
538: txb[ETH_ALEN*2+1] = t & 0xFF;
539: memcpy(&txb[ETH_HLEN], p, s); /* Frame data */
540:
541: /* setup the transmit descriptor */
542: txd[TxPtr].buf1sz = ETH_HLEN+s;
543: txd[TxPtr].control = 0x00000184; /* LS+FS+CE */
544: txd[TxPtr].status = 0x80000000; /* give ownership to device */
545:
546: /* immediate transmit demand */
547: outl(0, ioaddr + CSR1);
548:
549: to = currticks() + TX_TIME_OUT;
550: while ((txd[TxPtr].status & 0x80000000) && (currticks() < to))
551: /* wait */ ;
552:
553: if (currticks() >= to) {
554: DBG ("TX Timeout!\n");
555: }
556:
557: /* Point to next TX descriptor */
558: TxPtr = (++TxPtr >= NTXD) ? 0:TxPtr; /* Sten 10/9 */
559:
560: }
561:
562: /*********************************************************************/
563: /* eth_poll - Wait for a frame */
564: /*********************************************************************/
565: static int davicom_poll(struct nic *nic, int retrieve)
566: {
567: whereami("davicom_poll\n");
568:
569: if (rxd[rxd_tail].status & 0x80000000)
570: return 0;
571:
572: if ( ! retrieve ) return 1;
573:
574: whereami("davicom_poll got one\n");
575:
576: nic->packetlen = (rxd[rxd_tail].status & 0x3FFF0000) >> 16;
577:
578: if( rxd[rxd_tail].status & 0x00008000){
579: rxd[rxd_tail].status = 0x80000000;
580: rxd_tail++;
581: if (rxd_tail == NRXD) rxd_tail = 0;
582: return 0;
583: }
584:
585: /* copy packet to working buffer */
586: /* XXX - this copy could be avoided with a little more work
587: but for now we are content with it because the optimised
588: memcpy is quite fast */
589:
590: memcpy(nic->packet, rxb + rxd_tail * BUFLEN, nic->packetlen);
591:
592: /* return the descriptor and buffer to receive ring */
593: rxd[rxd_tail].status = 0x80000000;
594: rxd_tail++;
595: if (rxd_tail == NRXD) rxd_tail = 0;
596:
597: return 1;
598: }
599:
600: /*********************************************************************/
601: /* eth_disable - Disable the interface */
602: /*********************************************************************/
603: static void davicom_disable ( struct nic *nic ) {
604:
605: whereami("davicom_disable\n");
606:
607: davicom_reset(nic);
608:
609: /* disable interrupts */
610: outl(0x00000000, ioaddr + CSR7);
611:
612: /* Stop the chip's Tx and Rx processes. */
613: outl(inl(ioaddr + CSR6) & ~0x00002002, ioaddr + CSR6);
614:
615: /* Clear the missed-packet counter. */
616: inl(ioaddr + CSR8);
617: }
618:
619:
620: /*********************************************************************/
621: /* eth_irq - enable, disable and force interrupts */
622: /*********************************************************************/
623: static void davicom_irq(struct nic *nic __unused, irq_action_t action __unused)
624: {
625: switch ( action ) {
626: case DISABLE :
627: break;
628: case ENABLE :
629: break;
630: case FORCE :
631: break;
632: }
633: }
634:
635:
636: /*********************************************************************/
637: /* eth_probe - Look for an adapter */
638: /*********************************************************************/
639: static int davicom_probe ( struct nic *nic, struct pci_device *pci ) {
640:
641: unsigned int i;
642:
643: whereami("davicom_probe\n");
644:
645: if (pci->ioaddr == 0)
646: return 0;
647:
648: vendor = pci->vendor;
649: dev_id = pci->device;
650: ioaddr = pci->ioaddr;
651:
652: nic->ioaddr = pci->ioaddr;
653: nic->irqno = 0;
654:
655: /* wakeup chip */
656: pci_write_config_dword(pci, 0x40, 0x00000000);
657:
658: /* Stop the chip's Tx and Rx processes. */
659: outl(inl(ioaddr + CSR6) & ~0x00002002, ioaddr + CSR6);
660:
661: /* Clear the missed-packet counter. */
662: inl(ioaddr + CSR8);
663:
664: /* Get MAC Address */
665: /* read EEPROM data */
666: for (i = 0; i < sizeof(ee_data)/2; i++)
667: ((unsigned short *)ee_data)[i] =
668: le16_to_cpu(read_eeprom(ioaddr, i, EEPROM_ADDRLEN));
669:
670: /* extract MAC address from EEPROM buffer */
671: for (i=0; i<ETH_ALEN; i++)
672: nic->node_addr[i] = ee_data[20+i];
673:
674: DBG ( "Davicom %s at IOADDR %4.4lx\n", eth_ntoa ( nic->node_addr ), ioaddr );
675:
676: /* initialize device */
677: davicom_reset(nic);
678: nic->nic_op = &davicom_operations;
679: return 1;
680: }
681:
682: static struct nic_operations davicom_operations = {
683: .connect = dummy_connect,
684: .poll = davicom_poll,
685: .transmit = davicom_transmit,
686: .irq = davicom_irq,
687:
688: };
689:
690: static struct pci_device_id davicom_nics[] = {
691: PCI_ROM(0x1282, 0x9100, "davicom9100", "Davicom 9100", 0),
692: PCI_ROM(0x1282, 0x9102, "davicom9102", "Davicom 9102", 0),
693: PCI_ROM(0x1282, 0x9009, "davicom9009", "Davicom 9009", 0),
694: PCI_ROM(0x1282, 0x9132, "davicom9132", "Davicom 9132", 0), /* Needs probably some fixing */
695: };
696:
697: PCI_DRIVER ( davicom_driver, davicom_nics, PCI_NO_CLASS );
698:
699: DRIVER ( "DAVICOM", nic_driver, pci_driver, davicom_driver,
700: davicom_probe, davicom_disable );
701:
702: /*
703: * Local variables:
704: * c-basic-offset: 8
705: * c-indent-level: 8
706: * tab-width: 8
707: * End:
708: */
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