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1.1 root 1: /* #warning "depca.c: FIXME: fix relocation" */
2:
3: FILE_LICENCE ( GPL_ANY );
4:
5: #if 0
6: /* Not fixed for relocation yet. Probably won't work relocated above 16MB */
7: #ifdef ALLMULTI
8: #error multicast support is not yet implemented
9: #endif
10: /* Etherboot: depca.h merged, comments from Linux driver retained */
11: /* depca.c: A DIGITAL DEPCA & EtherWORKS ethernet driver for linux.
12:
13: Written 1994, 1995 by David C. Davies.
14:
15:
16: Copyright 1994 David C. Davies
17: and
18: United States Government
19: (as represented by the Director, National Security Agency).
20:
21: Copyright 1995 Digital Equipment Corporation.
22:
23:
24: This software may be used and distributed according to the terms of
25: the GNU Public License, incorporated herein by reference.
26:
27: This driver is written for the Digital Equipment Corporation series
28: of DEPCA and EtherWORKS ethernet cards:
29:
30: DEPCA (the original)
31: DE100
32: DE101
33: DE200 Turbo
34: DE201 Turbo
35: DE202 Turbo (TP BNC)
36: DE210
37: DE422 (EISA)
38:
39: The driver has been tested on DE100, DE200 and DE202 cards in a
40: relatively busy network. The DE422 has been tested a little.
41:
42: This driver will NOT work for the DE203, DE204 and DE205 series of
43: cards, since they have a new custom ASIC in place of the AMD LANCE
44: chip. See the 'ewrk3.c' driver in the Linux source tree for running
45: those cards.
46:
47: I have benchmarked the driver with a DE100 at 595kB/s to (542kB/s from)
48: a DECstation 5000/200.
49:
50: The author may be reached at [email protected]
51:
52: =========================================================================
53:
54: The driver was originally based on the 'lance.c' driver from Donald
55: Becker which is included with the standard driver distribution for
56: linux. V0.4 is a complete re-write with only the kernel interface
57: remaining from the original code.
58:
59: 1) Lance.c code in /linux/drivers/net/
60: 2) "Ethernet/IEEE 802.3 Family. 1992 World Network Data Book/Handbook",
61: AMD, 1992 [(800) 222-9323].
62: 3) "Am79C90 CMOS Local Area Network Controller for Ethernet (C-LANCE)",
63: AMD, Pub. #17881, May 1993.
64: 4) "Am79C960 PCnet-ISA(tm), Single-Chip Ethernet Controller for ISA",
65: AMD, Pub. #16907, May 1992
66: 5) "DEC EtherWORKS LC Ethernet Controller Owners Manual",
67: Digital Equipment corporation, 1990, Pub. #EK-DE100-OM.003
68: 6) "DEC EtherWORKS Turbo Ethernet Controller Owners Manual",
69: Digital Equipment corporation, 1990, Pub. #EK-DE200-OM.003
70: 7) "DEPCA Hardware Reference Manual", Pub. #EK-DEPCA-PR
71: Digital Equipment Corporation, 1989
72: 8) "DEC EtherWORKS Turbo_(TP BNC) Ethernet Controller Owners Manual",
73: Digital Equipment corporation, 1991, Pub. #EK-DE202-OM.001
74:
75:
76: Peter Bauer's depca.c (V0.5) was referred to when debugging V0.1 of this
77: driver.
78:
79: The original DEPCA card requires that the ethernet ROM address counter
80: be enabled to count and has an 8 bit NICSR. The ROM counter enabling is
81: only done when a 0x08 is read as the first address octet (to minimise
82: the chances of writing over some other hardware's I/O register). The
83: NICSR accesses have been changed to byte accesses for all the cards
84: supported by this driver, since there is only one useful bit in the MSB
85: (remote boot timeout) and it is not used. Also, there is a maximum of
86: only 48kB network RAM for this card. My thanks to Torbjorn Lindh for
87: help debugging all this (and holding my feet to the fire until I got it
88: right).
89:
90: The DE200 series boards have on-board 64kB RAM for use as a shared
91: memory network buffer. Only the DE100 cards make use of a 2kB buffer
92: mode which has not been implemented in this driver (only the 32kB and
93: 64kB modes are supported [16kB/48kB for the original DEPCA]).
94:
95: At the most only 2 DEPCA cards can be supported on the ISA bus because
96: there is only provision for two I/O base addresses on each card (0x300
97: and 0x200). The I/O address is detected by searching for a byte sequence
98: in the Ethernet station address PROM at the expected I/O address for the
99: Ethernet PROM. The shared memory base address is 'autoprobed' by
100: looking for the self test PROM and detecting the card name. When a
101: second DEPCA is detected, information is placed in the base_addr
102: variable of the next device structure (which is created if necessary),
103: thus enabling ethif_probe initialization for the device. More than 2
104: EISA cards can be supported, but care will be needed assigning the
105: shared memory to ensure that each slot has the correct IRQ, I/O address
106: and shared memory address assigned.
107:
108: ************************************************************************
109:
110: NOTE: If you are using two ISA DEPCAs, it is important that you assign
111: the base memory addresses correctly. The driver autoprobes I/O 0x300
112: then 0x200. The base memory address for the first device must be less
113: than that of the second so that the auto probe will correctly assign the
114: I/O and memory addresses on the same card. I can't think of a way to do
115: this unambiguously at the moment, since there is nothing on the cards to
116: tie I/O and memory information together.
117:
118: I am unable to test 2 cards together for now, so this code is
119: unchecked. All reports, good or bad, are welcome.
120:
121: ************************************************************************
122:
123: The board IRQ setting must be at an unused IRQ which is auto-probed
124: using Donald Becker's autoprobe routines. DEPCA and DE100 board IRQs are
125: {2,3,4,5,7}, whereas the DE200 is at {5,9,10,11,15}. Note that IRQ2 is
126: really IRQ9 in machines with 16 IRQ lines.
127:
128: No 16MB memory limitation should exist with this driver as DMA is not
129: used and the common memory area is in low memory on the network card (my
130: current system has 20MB and I've not had problems yet).
131:
132: The ability to load this driver as a loadable module has been added. To
133: utilise this ability, you have to do <8 things:
134:
135: 0) have a copy of the loadable modules code installed on your system.
136: 1) copy depca.c from the /linux/drivers/net directory to your favourite
137: temporary directory.
138: 2) if you wish, edit the source code near line 1530 to reflect the I/O
139: address and IRQ you're using (see also 5).
140: 3) compile depca.c, but include -DMODULE in the command line to ensure
141: that the correct bits are compiled (see end of source code).
142: 4) if you are wanting to add a new card, goto 5. Otherwise, recompile a
143: kernel with the depca configuration turned off and reboot.
144: 5) insmod depca.o [irq=7] [io=0x200] [mem=0xd0000] [adapter_name=DE100]
145: [Alan Cox: Changed the code to allow command line irq/io assignments]
146: [Dave Davies: Changed the code to allow command line mem/name
147: assignments]
148: 6) run the net startup bits for your eth?? interface manually
149: (usually /etc/rc.inet[12] at boot time).
150: 7) enjoy!
151:
152: Note that autoprobing is not allowed in loadable modules - the system is
153: already up and running and you're messing with interrupts.
154:
155: To unload a module, turn off the associated interface
156: 'ifconfig eth?? down' then 'rmmod depca'.
157:
158: To assign a base memory address for the shared memory when running as a
159: loadable module, see 5 above. To include the adapter name (if you have
160: no PROM but know the card name) also see 5 above. Note that this last
161: option will not work with kernel built-in depca's.
162:
163: The shared memory assignment for a loadable module makes sense to avoid
164: the 'memory autoprobe' picking the wrong shared memory (for the case of
165: 2 depca's in a PC).
166:
167: ************************************************************************
168: Support for MCA EtherWORKS cards added 11-3-98.
169: Verified to work with up to 2 DE212 cards in a system (although not
170: fully stress-tested).
171:
172: Currently known bugs/limitations:
173:
174: Note: with the MCA stuff as a module, it trusts the MCA configuration,
175: not the command line for IRQ and memory address. You can
176: specify them if you want, but it will throw your values out.
177: You still have to pass the IO address it was configured as
178: though.
179:
180: ************************************************************************
181: TO DO:
182: ------
183:
184:
185: Revision History
186: ----------------
187:
188: Version Date Description
189:
190: 0.1 25-jan-94 Initial writing.
191: 0.2 27-jan-94 Added LANCE TX hardware buffer chaining.
192: 0.3 1-feb-94 Added multiple DEPCA support.
193: 0.31 4-feb-94 Added DE202 recognition.
194: 0.32 19-feb-94 Tidy up. Improve multi-DEPCA support.
195: 0.33 25-feb-94 Fix DEPCA ethernet ROM counter enable.
196: Add jabber packet fix from [email protected]
197: and [email protected]
198: 0.34 7-mar-94 Fix DEPCA max network memory RAM & NICSR access.
199: 0.35 8-mar-94 Added DE201 recognition. Tidied up.
200: 0.351 30-apr-94 Added EISA support. Added DE422 recognition.
201: 0.36 16-may-94 DE422 fix released.
202: 0.37 22-jul-94 Added MODULE support
203: 0.38 15-aug-94 Added DBR ROM switch in depca_close().
204: Multi DEPCA bug fix.
205: 0.38axp 15-sep-94 Special version for Alpha AXP Linux V1.0.
206: 0.381 12-dec-94 Added DE101 recognition, fix multicast bug.
207: 0.382 9-feb-95 Fix recognition bug reported by <[email protected]>.
208: 0.383 22-feb-95 Fix for conflict with VESA SCSI reported by
209: <[email protected]>
210: 0.384 17-mar-95 Fix a ring full bug reported by <[email protected]>
211: 0.385 3-apr-95 Fix a recognition bug reported by
212: <[email protected]>
213: 0.386 21-apr-95 Fix the last fix...sorry, must be galloping senility
214: 0.40 25-May-95 Rewrite for portability & updated.
215: ALPHA support from <[email protected]>
216: 0.41 26-Jun-95 Added verify_area() calls in depca_ioctl() from
217: suggestion by <[email protected]>
218: 0.42 27-Dec-95 Add 'mem' shared memory assignment for loadable
219: modules.
220: Add 'adapter_name' for loadable modules when no PROM.
221: Both above from a suggestion by
222: <[email protected]>.
223: Add new multicasting code.
224: 0.421 22-Apr-96 Fix alloc_device() bug <[email protected]>
225: 0.422 29-Apr-96 Fix depca_hw_init() bug <[email protected]>
226: 0.423 7-Jun-96 Fix module load bug <[email protected]>
227: 0.43 16-Aug-96 Update alloc_device() to conform to de4x5.c
228: 0.44 1-Sep-97 Fix *_probe() to test check_region() first - bug
229: reported by <[email protected]>
230: 0.45 3-Nov-98 Added support for MCA EtherWORKS (DE210/DE212) cards
231: by <[email protected]>
232: 0.451 5-Nov-98 Fixed mca stuff cuz I'm a dummy. <[email protected]>
233: 0.5 14-Nov-98 Re-spin for 2.1.x kernels.
234: 0.51 27-Jun-99 Correct received packet length for CRC from
235: report by <[email protected]>
236:
237: =========================================================================
238: */
239:
240: #include "etherboot.h"
241: #include "nic.h"
242: #include <ipxe/isa.h>
243: #include <ipxe/console.h>
244: #include <ipxe/ethernet.h>
245:
246: /*
247: ** I/O addresses. Note that the 2k buffer option is not supported in
248: ** this driver.
249: */
250: #define DEPCA_NICSR 0x00 /* Network interface CSR */
251: #define DEPCA_RBI 0x02 /* RAM buffer index (2k buffer mode) */
252: #define DEPCA_DATA 0x04 /* LANCE registers' data port */
253: #define DEPCA_ADDR 0x06 /* LANCE registers' address port */
254: #define DEPCA_HBASE 0x08 /* EISA high memory base address reg. */
255: #define DEPCA_PROM 0x0c /* Ethernet address ROM data port */
256: #define DEPCA_CNFG 0x0c /* EISA Configuration port */
257: #define DEPCA_RBSA 0x0e /* RAM buffer starting address (2k buff.) */
258:
259: /*
260: ** These are LANCE registers addressable through nic->ioaddr + DEPCA_ADDR
261: */
262: #define CSR0 0
263: #define CSR1 1
264: #define CSR2 2
265: #define CSR3 3
266:
267: /*
268: ** NETWORK INTERFACE CSR (NI_CSR) bit definitions
269: */
270:
271: #define TO 0x0100 /* Time Out for remote boot */
272: #define SHE 0x0080 /* SHadow memory Enable */
273: #define BS 0x0040 /* Bank Select */
274: #define BUF 0x0020 /* BUFfer size (1->32k, 0->64k) */
275: #define RBE 0x0010 /* Remote Boot Enable (1->net boot) */
276: #define AAC 0x0008 /* Address ROM Address Counter (1->enable) */
277: #define _128KB 0x0008 /* 128kB Network RAM (1->enable) */
278: #define IM 0x0004 /* Interrupt Mask (1->mask) */
279: #define IEN 0x0002 /* Interrupt tristate ENable (1->enable) */
280: #define LED 0x0001 /* LED control */
281:
282: /*
283: ** Control and Status Register 0 (CSR0) bit definitions
284: */
285:
286: #define ERR 0x8000 /* Error summary */
287: #define BABL 0x4000 /* Babble transmitter timeout error */
288: #define CERR 0x2000 /* Collision Error */
289: #define MISS 0x1000 /* Missed packet */
290: #define MERR 0x0800 /* Memory Error */
291: #define RINT 0x0400 /* Receiver Interrupt */
292: #define TINT 0x0200 /* Transmit Interrupt */
293: #define IDON 0x0100 /* Initialization Done */
294: #define INTR 0x0080 /* Interrupt Flag */
295: #define INEA 0x0040 /* Interrupt Enable */
296: #define RXON 0x0020 /* Receiver on */
297: #define TXON 0x0010 /* Transmitter on */
298: #define TDMD 0x0008 /* Transmit Demand */
299: #define STOP 0x0004 /* Stop */
300: #define STRT 0x0002 /* Start */
301: #define INIT 0x0001 /* Initialize */
302: #define INTM 0xff00 /* Interrupt Mask */
303: #define INTE 0xfff0 /* Interrupt Enable */
304:
305: /*
306: ** CONTROL AND STATUS REGISTER 3 (CSR3)
307: */
308:
309: #define BSWP 0x0004 /* Byte SWaP */
310: #define ACON 0x0002 /* ALE control */
311: #define BCON 0x0001 /* Byte CONtrol */
312:
313: /*
314: ** Initialization Block Mode Register
315: */
316:
317: #define PROM 0x8000 /* Promiscuous Mode */
318: #define EMBA 0x0080 /* Enable Modified Back-off Algorithm */
319: #define INTL 0x0040 /* Internal Loopback */
320: #define DRTY 0x0020 /* Disable Retry */
321: #define COLL 0x0010 /* Force Collision */
322: #define DTCR 0x0008 /* Disable Transmit CRC */
323: #define LOOP 0x0004 /* Loopback */
324: #define DTX 0x0002 /* Disable the Transmitter */
325: #define DRX 0x0001 /* Disable the Receiver */
326:
327: /*
328: ** Receive Message Descriptor 1 (RMD1) bit definitions.
329: */
330:
331: #define R_OWN 0x80000000 /* Owner bit 0 = host, 1 = lance */
332: #define R_ERR 0x4000 /* Error Summary */
333: #define R_FRAM 0x2000 /* Framing Error */
334: #define R_OFLO 0x1000 /* Overflow Error */
335: #define R_CRC 0x0800 /* CRC Error */
336: #define R_BUFF 0x0400 /* Buffer Error */
337: #define R_STP 0x0200 /* Start of Packet */
338: #define R_ENP 0x0100 /* End of Packet */
339:
340: /*
341: ** Transmit Message Descriptor 1 (TMD1) bit definitions.
342: */
343:
344: #define T_OWN 0x80000000 /* Owner bit 0 = host, 1 = lance */
345: #define T_ERR 0x4000 /* Error Summary */
346: #define T_ADD_FCS 0x2000 /* More the 1 retry needed to Xmit */
347: #define T_MORE 0x1000 /* >1 retry to transmit packet */
348: #define T_ONE 0x0800 /* 1 try needed to transmit the packet */
349: #define T_DEF 0x0400 /* Deferred */
350: #define T_STP 0x02000000 /* Start of Packet */
351: #define T_ENP 0x01000000 /* End of Packet */
352: #define T_FLAGS 0xff000000 /* TX Flags Field */
353:
354: /*
355: ** Transmit Message Descriptor 3 (TMD3) bit definitions.
356: */
357:
358: #define TMD3_BUFF 0x8000 /* BUFFer error */
359: #define TMD3_UFLO 0x4000 /* UnderFLOw error */
360: #define TMD3_RES 0x2000 /* REServed */
361: #define TMD3_LCOL 0x1000 /* Late COLlision */
362: #define TMD3_LCAR 0x0800 /* Loss of CARrier */
363: #define TMD3_RTRY 0x0400 /* ReTRY error */
364:
365: /*
366: ** Ethernet PROM defines
367: */
368: #define PROBE_LENGTH 32
369:
370: /*
371: ** Set the number of Tx and Rx buffers. Ensure that the memory requested
372: ** here is <= to the amount of shared memory set up by the board switches.
373: ** The number of descriptors MUST BE A POWER OF 2.
374: **
375: ** total_memory = NUM_RX_DESC*(8+RX_BUFF_SZ) + NUM_TX_DESC*(8+TX_BUFF_SZ)
376: */
377: #define NUM_RX_DESC 2 /* Number of RX descriptors */
378: #define NUM_TX_DESC 2 /* Number of TX descriptors */
379: #define RX_BUFF_SZ 1536 /* Buffer size for each Rx buffer */
380: #define TX_BUFF_SZ 1536 /* Buffer size for each Tx buffer */
381:
382: /*
383: ** ISA Bus defines
384: */
385: #ifndef DEPCA_MODEL
386: #define DEPCA_MODEL DEPCA
387: #endif
388:
389: static enum {
390: DEPCA, DE100, DE101, DE200, DE201, DE202, DE210, DE212, DE422, unknown
391: } adapter = DEPCA_MODEL;
392:
393: /*
394: ** Name <-> Adapter mapping
395: */
396:
397: static char *adapter_name[] = {
398: "DEPCA",
399: "DE100","DE101",
400: "DE200","DE201","DE202",
401: "DE210","DE212",
402: "DE422",
403: ""
404: };
405:
406: #ifndef DEPCA_RAM_BASE
407: #define DEPCA_RAM_BASE 0xd0000
408: #endif
409:
410: /*
411: ** Memory Alignment. Each descriptor is 4 longwords long. To force a
412: ** particular alignment on the TX descriptor, adjust DESC_SKIP_LEN and
413: ** DESC_ALIGN. ALIGN aligns the start address of the private memory area
414: ** and hence the RX descriptor ring's first entry.
415: */
416: #define ALIGN4 ((u32)4 - 1) /* 1 longword align */
417: #define ALIGN8 ((u32)8 - 1) /* 2 longword (quadword) align */
418: #define ALIGN ALIGN8 /* Keep the LANCE happy... */
419:
420: /*
421: ** The DEPCA Rx and Tx ring descriptors.
422: */
423: struct depca_rx_desc {
424: volatile s32 base;
425: s16 buf_length; /* This length is negative 2's complement! */
426: s16 msg_length; /* This length is "normal". */
427: };
428:
429: struct depca_tx_desc {
430: volatile s32 base;
431: s16 length; /* This length is negative 2's complement! */
432: s16 misc; /* Errors and TDR info */
433: };
434:
435: #define LA_MASK 0x0000ffff /* LANCE address mask for mapping network RAM
436: to LANCE memory address space */
437:
438: /*
439: ** The Lance initialization block, described in databook, in common memory.
440: */
441: struct depca_init {
442: u16 mode; /* Mode register */
443: u8 phys_addr[ETH_ALEN]; /* Physical ethernet address */
444: u8 mcast_table[8]; /* Multicast Hash Table. */
445: u32 rx_ring; /* Rx ring base pointer & ring length */
446: u32 tx_ring; /* Tx ring base pointer & ring length */
447: };
448:
449: struct depca_private {
450: struct depca_rx_desc *rx_ring;
451: struct depca_tx_desc *tx_ring;
452: struct depca_init init_block; /* Shadow init block */
453: char *rx_memcpy[NUM_RX_DESC];
454: char *tx_memcpy[NUM_TX_DESC];
455: u32 bus_offset; /* ISA bus address offset */
456: u32 sh_mem; /* address of shared mem */
457: u32 dma_buffs; /* Rx & Tx buffer start */
458: int rx_cur, tx_cur; /* Next free ring entry */
459: int txRingMask, rxRingMask;
460: s32 rx_rlen, tx_rlen;
461: /* log2([rt]xRingMask+1) for the descriptors */
462: };
463:
464: static Address mem_start = DEPCA_RAM_BASE;
465: static Address mem_len, offset;
466: static struct depca_private lp;
467:
468: /*
469: ** Miscellaneous defines...
470: */
471: #define STOP_DEPCA(ioaddr) \
472: outw(CSR0, ioaddr + DEPCA_ADDR);\
473: outw(STOP, ioaddr + DEPCA_DATA)
474:
475: /* Initialize the lance Rx and Tx descriptor rings. */
476: static void depca_init_ring(struct nic *nic)
477: {
478: int i;
479: u32 p;
480:
481: lp.rx_cur = lp.tx_cur = 0;
482: /* Initialize the base addresses and length of each buffer in the ring */
483: for (i = 0; i <= lp.rxRingMask; i++) {
484: writel((p = lp.dma_buffs + i * RX_BUFF_SZ) | R_OWN, &lp.rx_ring[i].base);
485: writew(-RX_BUFF_SZ, &lp.rx_ring[i].buf_length);
486: lp.rx_memcpy[i] = (char *) (p + lp.bus_offset);
487: }
488: for (i = 0; i <= lp.txRingMask; i++) {
489: writel((p = lp.dma_buffs + (i + lp.txRingMask + 1) * TX_BUFF_SZ) & 0x00ffffff, &lp.tx_ring[i].base);
490: lp.tx_memcpy[i] = (char *) (p + lp.bus_offset);
491: }
492:
493: /* Set up the initialization block */
494: lp.init_block.rx_ring = ((u32) ((u32) lp.rx_ring) & LA_MASK) | lp.rx_rlen;
495: lp.init_block.tx_ring = ((u32) ((u32) lp.tx_ring) & LA_MASK) | lp.tx_rlen;
496: for (i = 0; i < ETH_ALEN; i++)
497: lp.init_block.phys_addr[i] = nic->node_addr[i];
498: lp.init_block.mode = 0x0000; /* Enable the Tx and Rx */
499: memset(lp.init_block.mcast_table, 0, sizeof(lp.init_block.mcast_table));
500: }
501:
502: static inline void LoadCSRs(struct nic *nic)
503: {
504: outw(CSR1, nic->ioaddr + DEPCA_ADDR); /* initialisation block address LSW */
505: outw((u16) (lp.sh_mem & LA_MASK), nic->ioaddr + DEPCA_DATA);
506: outw(CSR2, nic->ioaddr + DEPCA_ADDR); /* initialisation block address MSW */
507: outw((u16) ((lp.sh_mem & LA_MASK) >> 16), nic->ioaddr + DEPCA_DATA);
508: outw(CSR3, nic->ioaddr + DEPCA_ADDR); /* ALE control */
509: outw(ACON, nic->ioaddr + DEPCA_DATA);
510: outw(CSR0, nic->ioaddr + DEPCA_ADDR); /* Point back to CSR0 */
511: }
512:
513: static inline int InitRestartDepca(struct nic *nic)
514: {
515: int i;
516:
517: /* Copy the shadow init_block to shared memory */
518: memcpy_toio((char *)lp.sh_mem, &lp.init_block, sizeof(struct depca_init));
519: outw(CSR0, nic->ioaddr + DEPCA_ADDR); /* point back to CSR0 */
520: outw(INIT, nic->ioaddr + DEPCA_DATA); /* initialise DEPCA */
521:
522: for (i = 0; i < 100 && !(inw(nic->ioaddr + DEPCA_DATA) & IDON); i++)
523: ;
524: if (i < 100) {
525: /* clear IDON by writing a 1, and start LANCE */
526: outw(IDON | STRT, nic->ioaddr + DEPCA_DATA);
527: } else {
528: printf("DEPCA not initialised\n");
529: return (1);
530: }
531: return (0);
532: }
533:
534: /**************************************************************************
535: RESET - Reset adapter
536: ***************************************************************************/
537: static void depca_reset(struct nic *nic)
538: {
539: s16 nicsr;
540: int i, j;
541:
542: STOP_DEPCA(nic->ioaddr);
543: nicsr = inb(nic->ioaddr + DEPCA_NICSR);
544: nicsr = ((nicsr & ~SHE & ~RBE & ~IEN) | IM);
545: outb(nicsr, nic->ioaddr + DEPCA_NICSR);
546: if (inw(nic->ioaddr + DEPCA_DATA) != STOP)
547: {
548: printf("depca: Cannot stop NIC\n");
549: return;
550: }
551:
552: /* Initialisation block */
553: lp.sh_mem = mem_start;
554: mem_start += sizeof(struct depca_init);
555: /* Tx & Rx descriptors (aligned to a quadword boundary) */
556: mem_start = (mem_start + ALIGN) & ~ALIGN;
557: lp.rx_ring = (struct depca_rx_desc *) mem_start;
558: mem_start += (sizeof(struct depca_rx_desc) * NUM_RX_DESC);
559: lp.tx_ring = (struct depca_tx_desc *) mem_start;
560: mem_start += (sizeof(struct depca_tx_desc) * NUM_TX_DESC);
561:
562: lp.bus_offset = mem_start & 0x00ff0000;
563: /* LANCE re-mapped start address */
564: lp.dma_buffs = mem_start & LA_MASK;
565:
566: /* Finish initialising the ring information. */
567: lp.rxRingMask = NUM_RX_DESC - 1;
568: lp.txRingMask = NUM_TX_DESC - 1;
569:
570: /* Calculate Tx/Rx RLEN size for the descriptors. */
571: for (i = 0, j = lp.rxRingMask; j > 0; i++) {
572: j >>= 1;
573: }
574: lp.rx_rlen = (s32) (i << 29);
575: for (i = 0, j = lp.txRingMask; j > 0; i++) {
576: j >>= 1;
577: }
578: lp.tx_rlen = (s32) (i << 29);
579:
580: /* Load the initialisation block */
581: depca_init_ring(nic);
582: LoadCSRs(nic);
583: InitRestartDepca(nic);
584: }
585:
586: /**************************************************************************
587: POLL - Wait for a frame
588: ***************************************************************************/
589: static int depca_poll(struct nic *nic, int retrieve)
590: {
591: int entry;
592: u32 status;
593:
594: entry = lp.rx_cur;
595: if ((status = readl(&lp.rx_ring[entry].base) & R_OWN))
596: return (0);
597:
598: if ( ! retrieve ) return 1;
599:
600: memcpy(nic->packet, lp.rx_memcpy[entry], nic->packetlen = lp.rx_ring[entry].msg_length);
601: lp.rx_ring[entry].base |= R_OWN;
602: lp.rx_cur = (++lp.rx_cur) & lp.rxRingMask;
603: return (1);
604: }
605:
606: /**************************************************************************
607: TRANSMIT - Transmit a frame
608: ***************************************************************************/
609: static void depca_transmit(
610: struct nic *nic,
611: const char *d, /* Destination */
612: unsigned int t, /* Type */
613: unsigned int s, /* size */
614: const char *p) /* Packet */
615: {
616: int entry, len;
617: char *mem;
618:
619: /* send the packet to destination */
620: /*
621: ** Caution: the right order is important here... dont
622: ** setup the ownership rights until all the other
623: ** information is in place
624: */
625: mem = lp.tx_memcpy[entry = lp.tx_cur];
626: memcpy_toio(mem, d, ETH_ALEN);
627: memcpy_toio(mem + ETH_ALEN, nic->node_addr, ETH_ALEN);
628: mem[ETH_ALEN * 2] = t >> 8;
629: mem[ETH_ALEN * 2 + 1] = t;
630: memcpy_toio(mem + ETH_HLEN, p, s);
631: s += ETH_HLEN;
632: len = (s < ETH_ZLEN ? ETH_ZLEN : s);
633: /* clean out flags */
634: writel(readl(&lp.tx_ring[entry].base) & ~T_FLAGS, &lp.tx_ring[entry].base);
635: /* clears other error flags */
636: writew(0x0000, &lp.tx_ring[entry].misc);
637: /* packet length in buffer */
638: writew(-len, &lp.tx_ring[entry].length);
639: /* start and end of packet, ownership */
640: writel(readl(&lp.tx_ring[entry].base) | (T_STP|T_ENP|T_OWN), &lp.tx_ring[entry].base);
641: /* update current pointers */
642: lp.tx_cur = (++lp.tx_cur) & lp.txRingMask;
643: }
644:
645: /**************************************************************************
646: DISABLE - Turn off ethernet interface
647: ***************************************************************************/
648: static void depca_disable ( struct nic *nic ) {
649: depca_reset(nic);
650:
651: STOP_DEPCA(nic->ioaddr);
652: }
653:
654: /**************************************************************************
655: IRQ - Interrupt Control
656: ***************************************************************************/
657: static void depca_irq(struct nic *nic __unused, irq_action_t action __unused)
658: {
659: switch ( action ) {
660: case DISABLE :
661: break;
662: case ENABLE :
663: break;
664: case FORCE :
665: break;
666: }
667: }
668:
669: /*
670: ** Look for a special sequence in the Ethernet station address PROM that
671: ** is common across all DEPCA products. Note that the original DEPCA needs
672: ** its ROM address counter to be initialized and enabled. Only enable
673: ** if the first address octet is a 0x08 - this minimises the chances of
674: ** messing around with some other hardware, but it assumes that this DEPCA
675: ** card initialized itself correctly.
676: **
677: ** Search the Ethernet address ROM for the signature. Since the ROM address
678: ** counter can start at an arbitrary point, the search must include the entire
679: ** probe sequence length plus the (length_of_the_signature - 1).
680: ** Stop the search IMMEDIATELY after the signature is found so that the
681: ** PROM address counter is correctly positioned at the start of the
682: ** ethernet address for later read out.
683: */
684:
685:
686: /*
687: * Ugly, ugly, ugly. I can't quite make out where the split should be
688: * between probe1 and probe()...
689: *
690: */
691: static u8 nicsr;
692:
693:
694: static int depca_probe1 ( isa_probe_addr_t ioaddr ) {
695: u8 data;
696: /* This is only correct for little endian machines, but then
697: Etherboot doesn't work on anything but a PC */
698: u8 sig[] = { 0xFF, 0x00, 0x55, 0xAA, 0xFF, 0x00, 0x55, 0xAA };
699: int i, j;
700:
701: data = inb(ioaddr + DEPCA_PROM); /* clear counter on DEPCA */
702: data = inb(ioaddr + DEPCA_PROM); /* read data */
703: if (data == 0x8) {
704: nicsr = inb(ioaddr + DEPCA_NICSR);
705: nicsr |= AAC;
706: outb(nicsr, ioaddr + DEPCA_NICSR);
707: }
708: for (i = 0, j = 0; j < (int)sizeof(sig) && i < PROBE_LENGTH+((int)sizeof(sig))-1; ++i) {
709: data = inb(ioaddr + DEPCA_PROM);
710: if (data == sig[j]) /* track signature */
711: ++j;
712: else
713: j = (data == sig[0]) ? 1 : 0;
714: }
715: if (j != sizeof(sig))
716: return (0);
717: /* put the card in its initial state */
718: STOP_DEPCA(ioaddr);
719: nicsr = ((inb(ioaddr + DEPCA_NICSR) & ~SHE & ~RBE & ~IEN) | IM);
720: outb(nicsr, ioaddr + DEPCA_NICSR);
721: if (inw(ioaddr + DEPCA_DATA) != STOP)
722: return (0);
723: memcpy((char *)mem_start, sig, sizeof(sig));
724: if (memcmp((char *)mem_start, sig, sizeof(sig)) != 0)
725: return (0);
726:
727: return 1;
728: }
729:
730: static struct nic_operations depca_operations = {
731: .connect = dummy_connect,
732: .poll = depca_poll,
733: .transmit = depca_transmit,
734: .irq = depca_irq,
735:
736: };
737:
738: /**************************************************************************
739: PROBE - Look for an adapter, this routine's visible to the outside
740: ***************************************************************************/
741: static int depca_probe ( struct nic *nic, struct isa_device *isa ) {
742:
743: int i, j;
744: long sum, chksum;
745:
746: nic->irqno = 0;
747: nic->ioaddr = isa->ioaddr;
748:
749: for (i = 0, j = 0, sum = 0; j < 3; j++) {
750: sum <<= 1;
751: if (sum > 0xFFFF)
752: sum -= 0xFFFF;
753: sum += (u8)(nic->node_addr[i++] = inb(nic->ioaddr + DEPCA_PROM));
754: sum += (u16)((nic->node_addr[i++] = inb(nic->ioaddr + DEPCA_PROM)) << 8);
755: if (sum > 0xFFFF)
756: sum -= 0xFFFF;
757: }
758: if (sum == 0xFFFF)
759: sum = 0;
760: chksum = (u8)inb(nic->ioaddr + DEPCA_PROM);
761: chksum |= (u16)(inb(nic->ioaddr + DEPCA_PROM) << 8);
762: mem_len = (adapter == DEPCA) ? (48 << 10) : (64 << 10);
763: offset = 0;
764: if (nicsr & BUF) {
765: offset = 0x8000;
766: nicsr &= ~BS;
767: mem_len -= (32 << 10);
768: }
769: if (adapter != DEPCA) /* enable shadow RAM */
770: outb(nicsr |= SHE, nic->ioaddr + DEPCA_NICSR);
771: DBG ( "%s base %4.4x, memory [%4.4lx-%4.4lx] addr %s",
772: adapter_name[adapter], nic->ioaddr, mem_start,
773: mem_start + mem_len, eth_ntoa ( nic->node_addr ) );
774: if (sum != chksum)
775: printf(" (bad checksum)");
776: putchar('\n');
777:
778: depca_reset(nic);
779:
780: /* point to NIC specific routines */
781: nic->nic_op = &depca_operations;
782: return 1;
783: }
784:
785: static isa_probe_addr_t depca_probe_addrs[] = {
786: 0x300, 0x200,
787: };
788:
789: ISA_DRIVER ( depca_driver, depca_probe_addrs, depca_probe1,
790: GENERIC_ISAPNP_VENDOR, 0x80f7 );
791:
792: DRIVER ( "depce", nic_driver, isa_driver, depca_driver,
793: depca_probe, depca_disable );
794:
795: ISA_ROM ( "depca", "Digital DE100 and DE200" );
796:
797: #endif
798:
799: /*
800: * Local variables:
801: * c-basic-offset: 8
802: * c-indent-level: 8
803: * tab-width: 8
804: * End:
805: */
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