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Annotation of qemu/roms/ipxe/src/drivers/net/epic100.h, revision 1.1

1.1     ! root        1: #ifndef        _EPIC100_H_
        !             2: # define _EPIC100_H_
        !             3: 
        !             4: FILE_LICENCE ( GPL2_OR_LATER );
        !             5: 
        !             6: #ifndef        PCI_VENDOR_SMC
        !             7: # define PCI_VENDOR_SMC                0x10B8
        !             8: #endif
        !             9: 
        !            10: #ifndef        PCI_DEVICE_SMC_EPIC100
        !            11: # define PCI_DEVICE_SMC_EPIC100        0x0005
        !            12: #endif
        !            13: 
        !            14: #define PCI_DEVICE_ID_NONE     0xFFFF
        !            15: 
        !            16: /* Offsets to registers (using SMC names). */
        !            17: enum epic100_registers {
        !            18:     COMMAND= 0,                /* Control Register */
        !            19:     INTSTAT= 4,                /* Interrupt Status */
        !            20:     INTMASK= 8,                /* Interrupt Mask */
        !            21:     GENCTL = 0x0C,     /* General Control */
        !            22:     NVCTL  = 0x10,     /* Non Volatile Control */
        !            23:     EECTL  = 0x14,     /* EEPROM Control  */
        !            24:     TEST   = 0x1C,     /* Test register: marked as reserved (see in source code) */
        !            25:     CRCCNT = 0x20,     /* CRC Error Counter */
        !            26:     ALICNT = 0x24,     /* Frame Alignment Error Counter */
        !            27:     MPCNT  = 0x28,     /* Missed Packet Counter */
        !            28:     MMCTL  = 0x30,     /* MII Management Interface Control */
        !            29:     MMDATA = 0x34,     /* MII Management Interface Data */
        !            30:     MIICFG = 0x38,     /* MII Configuration */
        !            31:     IPG    = 0x3C,     /* InterPacket Gap */
        !            32:     LAN0   = 0x40,     /* MAC address. (0x40-0x48) */
        !            33:     IDCHK  = 0x4C,     /* BoardID/ Checksum */
        !            34:     MC0    = 0x50,     /* Multicast filter table. (0x50-0x5c) */
        !            35:     RXCON  = 0x60,     /* Receive Control */
        !            36:     TXCON  = 0x70,     /* Transmit Control */
        !            37:     TXSTAT = 0x74,     /* Transmit Status */
        !            38:     PRCDAR = 0x84,     /* PCI Receive Current Descriptor Address */
        !            39:     PRSTAT = 0xA4,     /* PCI Receive DMA Status */
        !            40:     PRCPTHR= 0xB0,     /* PCI Receive Copy Threshold */
        !            41:     PTCDAR = 0xC4,     /* PCI Transmit Current Descriptor Address */
        !            42:     ETHTHR = 0xDC      /* Early Transmit Threshold */
        !            43: };
        !            44: 
        !            45: /* Command register (CR_) bits */
        !            46: #define CR_STOP_RX             (0x00000001)
        !            47: #define CR_START_RX            (0x00000002)
        !            48: #define CR_QUEUE_TX            (0x00000004)
        !            49: #define CR_QUEUE_RX            (0x00000008)
        !            50: #define CR_NEXTFRAME           (0x00000010)
        !            51: #define CR_STOP_TX_DMA         (0x00000020)
        !            52: #define CR_STOP_RX_DMA         (0x00000040)
        !            53: #define CR_TX_UGO              (0x00000080)
        !            54: 
        !            55: /* Interrupt register bits. NI means No Interrupt generated */
        !            56: 
        !            57: #define        INTR_RX_THR_STA         (0x00400000)    /* rx copy threshold status NI */
        !            58: #define        INTR_RX_BUFF_EMPTY      (0x00200000)    /* rx buffers empty. NI */
        !            59: #define        INTR_TX_IN_PROG         (0x00100000)    /* tx copy in progess. NI */
        !            60: #define        INTR_RX_IN_PROG         (0x00080000)    /* rx copy in progress. NI */
        !            61: #define        INTR_TXIDLE             (0x00040000)    /* tx idle. NI */
        !            62: #define INTR_RXIDLE            (0x00020000)    /* rx idle. NI */
        !            63: #define INTR_INTR_ACTIVE       (0x00010000)    /* Interrupt active. NI */
        !            64: #define INTR_RX_STATUS_OK      (0x00008000)    /* rx status valid. NI */
        !            65: #define INTR_PCI_TGT_ABT       (0x00004000)    /* PCI Target abort */
        !            66: #define INTR_PCI_MASTER_ABT    (0x00002000)    /* PCI Master abort */
        !            67: #define INTR_PCI_PARITY_ERR    (0x00001000)    /* PCI adress parity error */
        !            68: #define INTR_PCI_DATA_ERR      (0x00000800)    /* PCI data parity error */
        !            69: #define INTR_RX_THR_CROSSED    (0x00000400)    /* rx copy threshold crossed */
        !            70: #define INTR_CNTFULL           (0x00000200)    /* Counter overflow */
        !            71: #define INTR_TXUNDERRUN                (0x00000100)    /* tx underrun. */
        !            72: #define INTR_TXEMPTY           (0x00000080)    /* tx queue empty */
        !            73: #define INTR_TX_CH_COMPLETE    (0x00000040)    /* tx chain complete */
        !            74: #define INTR_TXDONE            (0x00000020)    /* tx complete (w or w/o err) */
        !            75: #define INTR_RXERROR           (0x00000010)    /* rx error (CRC) */
        !            76: #define INTR_RXOVERFLOW                (0x00000008)    /* rx buffer overflow */
        !            77: #define INTR_RX_QUEUE_EMPTY    (0x00000004)    /* rx queue empty. */
        !            78: #define INTR_RXHEADER          (0x00000002)    /* header copy complete */
        !            79: #define INTR_RXDONE            (0x00000001)    /* Receive copy complete */
        !            80: 
        !            81: #define INTR_CLEARINTR         (0x00007FFF)
        !            82: #define INTR_VALIDBITS         (0x007FFFFF)
        !            83: #define INTR_DISABLE           (0x00000000)
        !            84: #define INTR_CLEARERRS         (0x00007F18)
        !            85: #define INTR_ABNINTR           (INTR_CNTFULL | INTR_TXUNDERRUN | INTR_RXOVERFLOW)
        !            86: 
        !            87: /* General Control (GC_) bits */
        !            88: 
        !            89: #define GC_SOFT_RESET          (0x00000001)
        !            90: #define GC_INTR_ENABLE         (0x00000002)
        !            91: #define GC_SOFT_INTR           (0x00000004)
        !            92: #define GC_POWER_DOWN          (0x00000008)
        !            93: #define GC_ONE_COPY            (0x00000010)
        !            94: #define GC_BIG_ENDIAN          (0x00000020)
        !            95: #define GC_RX_PREEMPT_TX       (0x00000040)
        !            96: #define GC_TX_PREEMPT_RX       (0x00000080)
        !            97: 
        !            98: /*
        !            99:  * Receive FIFO Threshold values
        !           100:  * Control the level at which the  PCI burst state machine
        !           101:  * begins to empty the receive FIFO. Possible values: 0-3
        !           102:  *
        !           103:  * 0 => 32, 1 => 64, 2 => 96 3 => 128 bytes.
        !           104:  */
        !           105: #define GC_RX_FIFO_THR_32      (0x00000000)
        !           106: #define GC_RX_FIFO_THR_64      (0x00000100)
        !           107: #define GC_RX_FIFO_THR_96      (0x00000200)
        !           108: #define GC_RX_FIFO_THR_128     (0x00000300)
        !           109: 
        !           110: /* Memory Read Control (MRC_) values */
        !           111: #define GC_MRC_MEM_READ                (0x00000000)
        !           112: #define GC_MRC_READ_MULT       (0x00000400)
        !           113: #define GC_MRC_READ_LINE       (0x00000800)
        !           114: 
        !           115: #define GC_SOFTBIT0            (0x00001000)
        !           116: #define GC_SOFTBIT1            (0x00002000)
        !           117: #define GC_RESET_PHY           (0x00004000)
        !           118: 
        !           119: /* Definitions of the Receive Control (RC_) register bits */
        !           120: 
        !           121: #define RC_SAVE_ERRORED_PKT    (0x00000001)
        !           122: #define RC_SAVE_RUNT_FRAMES    (0x00000002)
        !           123: #define RC_RCV_BROADCAST       (0x00000004)
        !           124: #define RC_RCV_MULTICAST       (0x00000008)
        !           125: #define RC_RCV_INVERSE_PKT     (0x00000010)
        !           126: #define RC_PROMISCUOUS_MODE    (0x00000020)
        !           127: #define RC_MONITOR_MODE                (0x00000040)
        !           128: #define RC_EARLY_RCV_ENABLE    (0x00000080)
        !           129: 
        !           130: /* description of the rx descriptors control bits */
        !           131: #define RD_FRAGLIST            (0x0001)        /* Desc points to a fragment list */
        !           132: #define RD_LLFORM              (0x0002)        /* Frag list format */
        !           133: #define RD_HDR_CPY             (0x0004)        /* Desc used for header copy */
        !           134: 
        !           135: /* Definition of the Transmit CONTROL (TC) register bits */
        !           136: 
        !           137: #define TC_EARLY_TX_ENABLE     (0x00000001)
        !           138: 
        !           139: /* Loopback Mode (LM_) Select valuesbits */
        !           140: #define TC_LM_NORMAL           (0x00000000)
        !           141: #define TC_LM_INTERNAL         (0x00000002)
        !           142: #define TC_LM_EXTERNAL         (0x00000004)
        !           143: #define TC_LM_FULL_DPX         (0x00000006)
        !           144: 
        !           145: #define TX_SLOT_TIME           (0x00000078)
        !           146: 
        !           147: /* Bytes transferred to chip before transmission starts. */
        !           148: #define TX_FIFO_THRESH         128     /* Rounded down to 4 byte units. */
        !           149: 
        !           150: /* description of rx descriptors status bits */
        !           151: #define RRING_PKT_INTACT       (0x0001)
        !           152: #define RRING_ALIGN_ERR                (0x0002)
        !           153: #define RRING_CRC_ERR          (0x0004)
        !           154: #define RRING_MISSED_PKT       (0x0008)
        !           155: #define RRING_MULTICAST                (0x0010)
        !           156: #define RRING_BROADCAST                (0x0020)
        !           157: #define RRING_RECEIVER_DISABLE (0x0040)
        !           158: #define RRING_STATUS_VALID     (0x1000)
        !           159: #define RRING_FRAGLIST_ERR     (0x2000)
        !           160: #define RRING_HDR_COPIED       (0x4000)
        !           161: #define RRING_OWN              (0x8000)
        !           162: 
        !           163: /* error summary */
        !           164: #define RRING_ERROR            (RRING_ALIGN_ERR|RRING_CRC_ERR)
        !           165: 
        !           166: /* description of tx descriptors status bits */
        !           167: #define TRING_PKT_INTACT       (0x0001)        /* pkt transmitted. */
        !           168: #define TRING_PKT_NONDEFER     (0x0002)        /* pkt xmitted w/o deferring */
        !           169: #define TRING_COLL             (0x0004)        /* pkt xmitted w collisions */
        !           170: #define TRING_CARR             (0x0008)        /* carrier sense lost */
        !           171: #define TRING_UNDERRUN         (0x0010)        /* DMA underrun */
        !           172: #define TRING_HB_COLL          (0x0020)        /* Collision detect Heartbeat */
        !           173: #define TRING_WIN_COLL         (0x0040)        /* out of window collision */
        !           174: #define TRING_DEFERRED         (0x0080)        /* Deferring */
        !           175: #define TRING_COLL_COUNT       (0x0F00)        /* collision counter (mask) */
        !           176: #define TRING_COLL_EXCESS      (0x1000)        /* tx aborted: excessive colls */
        !           177: #define TRING_OWN              (0x8000)        /* desc ownership bit */
        !           178: 
        !           179: /* error summary */
        !           180: #define TRING_ABORT    (TRING_COLL_EXCESS|TRING_WIN_COLL|TRING_UNDERRUN)
        !           181: #define TRING_ERROR    (TRING_DEFERRED|TRING_WIN_COLL|TRING_UNDERRUN|TRING_CARR/*|TRING_COLL*/ )
        !           182: 
        !           183: /* description of the tx descriptors control bits */
        !           184: #define TD_FRAGLIST            (0x0001)        /* Desc points to a fragment list */
        !           185: #define TD_LLFORM              (0x0002)        /* Frag list format */
        !           186: #define TD_IAF                 (0x0004)        /* Generate Interrupt after tx */
        !           187: #define TD_NOCRC               (0x0008)        /* No CRC generated */
        !           188: #define TD_LASTDESC            (0x0010)        /* Last desc for this frame */
        !           189: 
        !           190: #endif /* _EPIC100_H_ */

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