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Annotation of qemu/roms/ipxe/src/drivers/net/etherfabric.c, revision 1.1

1.1     ! root        1: /**************************************************************************
        !             2:  *
        !             3:  * Etherboot driver for Level 5 Etherfabric network cards
        !             4:  *
        !             5:  * Written by Michael Brown <[email protected]>
        !             6:  *
        !             7:  * Copyright Fen Systems Ltd. 2005
        !             8:  * Copyright Level 5 Networks Inc. 2005
        !             9:  *
        !            10:  * This software may be used and distributed according to the terms of
        !            11:  * the GNU General Public License (GPL), incorporated herein by
        !            12:  * reference.  Drivers based on or derived from this code fall under
        !            13:  * the GPL and must retain the authorship, copyright and license
        !            14:  * notice.
        !            15:  *
        !            16:  **************************************************************************
        !            17:  */
        !            18: 
        !            19: FILE_LICENCE ( GPL_ANY );
        !            20: 
        !            21: #include <stdint.h>
        !            22: #include <stdlib.h>
        !            23: #include <unistd.h>
        !            24: #include <errno.h>
        !            25: #include <assert.h>
        !            26: #include <byteswap.h>
        !            27: #include <ipxe/console.h>
        !            28: #include <ipxe/io.h>
        !            29: #include <ipxe/pci.h>
        !            30: #include <ipxe/malloc.h>
        !            31: #include <ipxe/ethernet.h>
        !            32: #include <ipxe/iobuf.h>
        !            33: #include <ipxe/netdevice.h>
        !            34: #include <ipxe/timer.h>
        !            35: #include <mii.h>
        !            36: #include "etherfabric.h"
        !            37: #include "etherfabric_nic.h"
        !            38: 
        !            39: /**************************************************************************
        !            40:  *
        !            41:  * Constants and macros
        !            42:  *
        !            43:  **************************************************************************
        !            44:  */
        !            45: 
        !            46: #define EFAB_REGDUMP(...)
        !            47: #define EFAB_TRACE(...) DBGP(__VA_ARGS__)
        !            48: 
        !            49: // printf() is not allowed within drivers.  Use DBG() instead.
        !            50: #define EFAB_LOG(...) DBG(__VA_ARGS__)
        !            51: #define EFAB_ERR(...) DBG(__VA_ARGS__)
        !            52: 
        !            53: #define FALCON_USE_IO_BAR 0
        !            54: 
        !            55: #define HZ 100
        !            56: #define EFAB_BYTE 1
        !            57: 
        !            58: /**************************************************************************
        !            59:  *
        !            60:  * Hardware data structures and sizing
        !            61:  *
        !            62:  **************************************************************************
        !            63:  */
        !            64: extern int __invalid_queue_size;
        !            65: #define FQS(_prefix, _x)                                       \
        !            66:        ( ( (_x) == 512 ) ? _prefix ## _SIZE_512 :              \
        !            67:          ( ( (_x) == 1024 ) ? _prefix ## _SIZE_1K :            \
        !            68:            ( ( (_x) == 2048 ) ? _prefix ## _SIZE_2K :          \
        !            69:              ( ( (_x) == 4096) ? _prefix ## _SIZE_4K :         \
        !            70:                __invalid_queue_size ) ) ) )
        !            71: 
        !            72: 
        !            73: #define EFAB_MAX_FRAME_LEN(mtu)                                \
        !            74:        ( ( ( ( mtu ) + 4/* FCS */ ) + 7 ) & ~7 )
        !            75: 
        !            76: /**************************************************************************
        !            77:  *
        !            78:  * GMII routines
        !            79:  *
        !            80:  **************************************************************************
        !            81:  */
        !            82: 
        !            83: static void falcon_mdio_write (struct efab_nic *efab, int device,
        !            84:                               int location, int value );
        !            85: static int falcon_mdio_read ( struct efab_nic *efab, int device, int location );
        !            86: 
        !            87: /* GMII registers */
        !            88: #define GMII_PSSR              0x11    /* PHY-specific status register */
        !            89: 
        !            90: /* Pseudo extensions to the link partner ability register */
        !            91: #define LPA_EF_1000FULL                0x00020000
        !            92: #define LPA_EF_1000HALF                0x00010000
        !            93: #define LPA_EF_10000FULL               0x00040000
        !            94: #define LPA_EF_10000HALF               0x00080000
        !            95: 
        !            96: #define LPA_100                        (LPA_100FULL | LPA_100HALF | LPA_100BASE4)
        !            97: #define LPA_EF_1000            ( LPA_EF_1000FULL | LPA_EF_1000HALF )
        !            98: #define LPA_EF_10000               ( LPA_EF_10000FULL | LPA_EF_10000HALF )
        !            99: #define LPA_EF_DUPLEX          ( LPA_10FULL | LPA_100FULL | LPA_EF_1000FULL | \
        !           100:                                  LPA_EF_10000FULL )
        !           101: 
        !           102: /* Mask of bits not associated with speed or duplexity. */
        !           103: #define LPA_OTHER              ~( LPA_10FULL | LPA_10HALF | LPA_100FULL | \
        !           104:                                   LPA_100HALF | LPA_EF_1000FULL | LPA_EF_1000HALF )
        !           105: 
        !           106: /* PHY-specific status register */
        !           107: #define PSSR_LSTATUS           0x0400  /* Bit 10 - link status */
        !           108: 
        !           109: /**
        !           110:  * Retrieve GMII autonegotiation advertised abilities
        !           111:  *
        !           112:  */
        !           113: static unsigned int
        !           114: gmii_autoneg_advertised ( struct efab_nic *efab )
        !           115: {
        !           116:        unsigned int mii_advertise;
        !           117:        unsigned int gmii_advertise;
        !           118: 
        !           119:        /* Extended bits are in bits 8 and 9 of MII_CTRL1000 */
        !           120:        mii_advertise = falcon_mdio_read ( efab, 0, MII_ADVERTISE );
        !           121:        gmii_advertise = ( ( falcon_mdio_read ( efab, 0, MII_CTRL1000 ) >> 8 )
        !           122:                           & 0x03 );
        !           123:        return ( ( gmii_advertise << 16 ) | mii_advertise );
        !           124: }
        !           125: 
        !           126: /**
        !           127:  * Retrieve GMII autonegotiation link partner abilities
        !           128:  *
        !           129:  */
        !           130: static unsigned int
        !           131: gmii_autoneg_lpa ( struct efab_nic *efab )
        !           132: {
        !           133:        unsigned int mii_lpa;
        !           134:        unsigned int gmii_lpa;
        !           135: 
        !           136:        /* Extended bits are in bits 10 and 11 of MII_STAT1000 */
        !           137:        mii_lpa = falcon_mdio_read ( efab, 0, MII_LPA );
        !           138:        gmii_lpa = ( falcon_mdio_read ( efab, 0, MII_STAT1000 ) >> 10 ) & 0x03;
        !           139:        return ( ( gmii_lpa << 16 ) | mii_lpa );
        !           140: }
        !           141: 
        !           142: /**
        !           143:  * Calculate GMII autonegotiated link technology
        !           144:  *
        !           145:  */
        !           146: static unsigned int
        !           147: gmii_nway_result ( unsigned int negotiated )
        !           148: {
        !           149:        unsigned int other_bits;
        !           150: 
        !           151:        /* Mask out the speed and duplexity bits */
        !           152:        other_bits = negotiated & LPA_OTHER;
        !           153: 
        !           154:        if ( negotiated & LPA_EF_1000FULL )
        !           155:                return ( other_bits | LPA_EF_1000FULL );
        !           156:        else if ( negotiated & LPA_EF_1000HALF )
        !           157:                return ( other_bits | LPA_EF_1000HALF );
        !           158:        else if ( negotiated & LPA_100FULL )
        !           159:                return ( other_bits | LPA_100FULL );
        !           160:        else if ( negotiated & LPA_100BASE4 )
        !           161:                return ( other_bits | LPA_100BASE4 );
        !           162:        else if ( negotiated & LPA_100HALF )
        !           163:                return ( other_bits | LPA_100HALF );
        !           164:        else if ( negotiated & LPA_10FULL )
        !           165:                return ( other_bits | LPA_10FULL );
        !           166:        else return ( other_bits | LPA_10HALF );
        !           167: }
        !           168: 
        !           169: /**
        !           170:  * Check GMII PHY link status
        !           171:  *
        !           172:  */
        !           173: static int
        !           174: gmii_link_ok ( struct efab_nic *efab )
        !           175: {
        !           176:        int status;
        !           177:        int phy_status;
        !           178: 
        !           179:        /* BMSR is latching - it returns "link down" if the link has
        !           180:         * been down at any point since the last read.  To get a
        !           181:         * real-time status, we therefore read the register twice and
        !           182:         * use the result of the second read.
        !           183:         */
        !           184:        (void) falcon_mdio_read ( efab, 0, MII_BMSR );
        !           185:        status = falcon_mdio_read ( efab, 0, MII_BMSR );
        !           186: 
        !           187:        /* Read the PHY-specific Status Register.  This is
        !           188:         * non-latching, so we need do only a single read.
        !           189:         */
        !           190:        phy_status = falcon_mdio_read ( efab, 0, GMII_PSSR );
        !           191: 
        !           192:        return ( ( status & BMSR_LSTATUS ) && ( phy_status & PSSR_LSTATUS ) );
        !           193: }
        !           194: 
        !           195: /**************************************************************************
        !           196:  *
        !           197:  * MDIO routines
        !           198:  *
        !           199:  **************************************************************************
        !           200:  */
        !           201: 
        !           202: /* Numbering of the MDIO Manageable Devices (MMDs) */
        !           203: /* Physical Medium Attachment/ Physical Medium Dependent sublayer */
        !           204: #define MDIO_MMD_PMAPMD        (1)
        !           205: /* WAN Interface Sublayer */
        !           206: #define MDIO_MMD_WIS   (2)
        !           207: /* Physical Coding Sublayer */
        !           208: #define MDIO_MMD_PCS   (3)
        !           209: /* PHY Extender Sublayer */
        !           210: #define MDIO_MMD_PHYXS (4)
        !           211: /* Extender Sublayer */
        !           212: #define MDIO_MMD_DTEXS (5)
        !           213: /* Transmission convergence */
        !           214: #define MDIO_MMD_TC    (6)
        !           215: /* Auto negotiation */
        !           216: #define MDIO_MMD_AN    (7)
        !           217: 
        !           218: /* Generic register locations */
        !           219: #define MDIO_MMDREG_CTRL1      (0)
        !           220: #define MDIO_MMDREG_STAT1      (1)
        !           221: #define MDIO_MMDREG_DEVS0      (5)
        !           222: #define MDIO_MMDREG_STAT2      (8)
        !           223: 
        !           224: /* Bits in MMDREG_CTRL1 */
        !           225: /* Reset */
        !           226: #define MDIO_MMDREG_CTRL1_RESET_LBN    (15)
        !           227: #define MDIO_MMDREG_CTRL1_RESET_WIDTH  (1)
        !           228: 
        !           229: /* Bits in MMDREG_STAT1 */
        !           230: #define MDIO_MMDREG_STAT1_FAULT_LBN    (7)
        !           231: #define MDIO_MMDREG_STAT1_FAULT_WIDTH  (1)
        !           232: 
        !           233: /* Link state */
        !           234: #define MDIO_MMDREG_STAT1_LINK_LBN     (2)
        !           235: #define MDIO_MMDREG_STAT1_LINK_WIDTH   (1)
        !           236: 
        !           237: /* Bits in MMDREG_DEVS0. */
        !           238: #define DEV_PRESENT_BIT(_b) (1 << _b)
        !           239: 
        !           240: #define MDIO_MMDREG_DEVS0_DTEXS         DEV_PRESENT_BIT(MDIO_MMD_DTEXS)
        !           241: #define MDIO_MMDREG_DEVS0_PHYXS         DEV_PRESENT_BIT(MDIO_MMD_PHYXS)
        !           242: #define MDIO_MMDREG_DEVS0_PCS   DEV_PRESENT_BIT(MDIO_MMD_PCS)
        !           243: #define MDIO_MMDREG_DEVS0_WIS   DEV_PRESENT_BIT(MDIO_MMD_WIS)
        !           244: #define MDIO_MMDREG_DEVS0_PMAPMD DEV_PRESENT_BIT(MDIO_MMD_PMAPMD)
        !           245: 
        !           246: #define MDIO_MMDREG_DEVS0_AN     DEV_PRESENT_BIT(MDIO_MMD_AN)
        !           247: 
        !           248: /* Bits in MMDREG_STAT2 */
        !           249: #define MDIO_MMDREG_STAT2_PRESENT_VAL  (2)
        !           250: #define MDIO_MMDREG_STAT2_PRESENT_LBN  (14)
        !           251: #define MDIO_MMDREG_STAT2_PRESENT_WIDTH (2)
        !           252: 
        !           253: /* PHY XGXS lane state */
        !           254: #define MDIO_PHYXS_LANE_STATE          (0x18) 
        !           255: #define MDIO_PHYXS_LANE_ALIGNED_LBN    (12)
        !           256: #define MDIO_PHYXS_LANE_SYNC0_LBN      (0)
        !           257: #define MDIO_PHYXS_LANE_SYNC1_LBN      (1)
        !           258: #define MDIO_PHYXS_LANE_SYNC2_LBN      (2)
        !           259: #define MDIO_PHYXS_LANE_SYNC3_LBN      (3)
        !           260: 
        !           261: /* This ought to be ridiculous overkill. We expect it to fail rarely */
        !           262: #define MDIO45_RESET_TRIES      100
        !           263: #define MDIO45_RESET_SPINTIME   10
        !           264: 
        !           265: static int
        !           266: mdio_clause45_wait_reset_mmds ( struct efab_nic* efab )
        !           267: {
        !           268:        int tries = MDIO45_RESET_TRIES;
        !           269:        int in_reset;
        !           270: 
        !           271:        while(tries) {
        !           272:                int mask = efab->phy_op->mmds;
        !           273:                int mmd = 0;
        !           274:                in_reset = 0;
        !           275:                while(mask) {
        !           276:                        if (mask & 1) {
        !           277:                                int stat = falcon_mdio_read ( efab,  mmd,
        !           278:                                                              MDIO_MMDREG_CTRL1 );
        !           279:                                if (stat < 0) {
        !           280:                                        EFAB_ERR("Failed to read status of MMD %d\n",
        !           281:                                                 mmd );
        !           282:                                        in_reset = 1;
        !           283:                                        break;
        !           284:                                }
        !           285:                                if (stat & (1 << MDIO_MMDREG_CTRL1_RESET_LBN))
        !           286:                                        in_reset |= (1 << mmd);
        !           287:                        }
        !           288:                        mask = mask >> 1;
        !           289:                        mmd++;
        !           290:                }
        !           291:                if (!in_reset)
        !           292:                        break;
        !           293:                tries--;
        !           294:                mdelay ( MDIO45_RESET_SPINTIME );
        !           295:        }
        !           296:        if (in_reset != 0) {
        !           297:                EFAB_ERR("Not all MMDs came out of reset in time. MMDs "
        !           298:                         "still in reset: %x\n", in_reset);
        !           299:                return -ETIMEDOUT;
        !           300:        }
        !           301:        return 0;
        !           302: }
        !           303: 
        !           304: static int
        !           305: mdio_clause45_reset_mmd ( struct efab_nic *efab, int mmd )
        !           306: {
        !           307:        int tries = MDIO45_RESET_TRIES;
        !           308:        int ctrl;
        !           309: 
        !           310:        falcon_mdio_write ( efab, mmd, MDIO_MMDREG_CTRL1,
        !           311:                            ( 1 << MDIO_MMDREG_CTRL1_RESET_LBN ) );
        !           312: 
        !           313:        /* Wait for the reset bit to clear. */
        !           314:        do {
        !           315:                mdelay ( MDIO45_RESET_SPINTIME );
        !           316: 
        !           317:                ctrl = falcon_mdio_read ( efab, mmd, MDIO_MMDREG_CTRL1 );
        !           318:                if ( ~ctrl & ( 1 << MDIO_MMDREG_CTRL1_RESET_LBN ) )
        !           319:                        return 0;
        !           320:        } while ( --tries );
        !           321: 
        !           322:        EFAB_ERR ( "Failed to reset mmd %d\n", mmd );
        !           323: 
        !           324:        return -ETIMEDOUT;
        !           325: }
        !           326: 
        !           327: static int
        !           328: mdio_clause45_links_ok(struct efab_nic *efab )
        !           329: {
        !           330:        int status, good;
        !           331:        int ok = 1;
        !           332:        int mmd = 0;
        !           333:        int mmd_mask = efab->phy_op->mmds;
        !           334: 
        !           335:        while (mmd_mask) {
        !           336:                if (mmd_mask & 1) {
        !           337:                        /* Double reads because link state is latched, and a
        !           338:                         * read moves the current state into the register */
        !           339:                        status = falcon_mdio_read ( efab, mmd,
        !           340:                                                    MDIO_MMDREG_STAT1 );
        !           341:                        status = falcon_mdio_read ( efab, mmd,
        !           342:                                                    MDIO_MMDREG_STAT1 );
        !           343: 
        !           344:                        good = status & (1 << MDIO_MMDREG_STAT1_LINK_LBN);
        !           345:                        ok = ok && good;
        !           346:                }
        !           347:                mmd_mask = (mmd_mask >> 1);
        !           348:                mmd++;
        !           349:        }
        !           350:        return ok;
        !           351: }
        !           352: 
        !           353: static int
        !           354: mdio_clause45_check_mmds ( struct efab_nic *efab )
        !           355: {
        !           356:        int mmd = 0;
        !           357:        int devices = falcon_mdio_read ( efab, MDIO_MMD_PHYXS,
        !           358:                                         MDIO_MMDREG_DEVS0 );
        !           359:        int mmd_mask = efab->phy_op->mmds;
        !           360: 
        !           361:        /* Check all the expected MMDs are present */
        !           362:        if ( devices < 0 ) {
        !           363:                EFAB_ERR ( "Failed to read devices present\n" );
        !           364:                return -EIO;
        !           365:        }
        !           366:        if ( ( devices & mmd_mask ) != mmd_mask ) {
        !           367:                EFAB_ERR ( "required MMDs not present: got %x, wanted %x\n",
        !           368:                           devices, mmd_mask );
        !           369:                return -EIO;
        !           370:        }
        !           371: 
        !           372:        /* Check all required MMDs are responding and happy. */
        !           373:        while ( mmd_mask ) {
        !           374:                if ( mmd_mask & 1 ) {
        !           375:                        efab_dword_t reg;
        !           376:                        int status;
        !           377:                        reg.opaque = falcon_mdio_read ( efab, mmd,
        !           378:                                                        MDIO_MMDREG_STAT2 );
        !           379:                        status = EFAB_DWORD_FIELD ( reg,
        !           380:                                                    MDIO_MMDREG_STAT2_PRESENT );
        !           381:                        if ( status != MDIO_MMDREG_STAT2_PRESENT_VAL ) {
        !           382: 
        !           383: 
        !           384:                                return -EIO;
        !           385:                        }
        !           386:                }
        !           387:                mmd_mask >>= 1;
        !           388:                mmd++;
        !           389:        }
        !           390: 
        !           391:        return 0;
        !           392: }
        !           393: 
        !           394: /* I/O BAR address register */
        !           395: #define FCN_IOM_IND_ADR_REG 0x0
        !           396: 
        !           397: /* I/O BAR data register */
        !           398: #define FCN_IOM_IND_DAT_REG 0x4
        !           399: 
        !           400: /* Address region register */
        !           401: #define FCN_ADR_REGION_REG_KER 0x00
        !           402: #define FCN_ADR_REGION0_LBN    0
        !           403: #define FCN_ADR_REGION0_WIDTH  18
        !           404: #define FCN_ADR_REGION1_LBN    32
        !           405: #define FCN_ADR_REGION1_WIDTH  18
        !           406: #define FCN_ADR_REGION2_LBN    64
        !           407: #define FCN_ADR_REGION2_WIDTH  18
        !           408: #define FCN_ADR_REGION3_LBN    96
        !           409: #define FCN_ADR_REGION3_WIDTH  18
        !           410: 
        !           411: /* Interrupt enable register */
        !           412: #define FCN_INT_EN_REG_KER 0x0010
        !           413: #define FCN_MEM_PERR_INT_EN_KER_LBN 5
        !           414: #define FCN_MEM_PERR_INT_EN_KER_WIDTH 1
        !           415: #define FCN_KER_INT_CHAR_LBN 4
        !           416: #define FCN_KER_INT_CHAR_WIDTH 1
        !           417: #define FCN_KER_INT_KER_LBN 3
        !           418: #define FCN_KER_INT_KER_WIDTH 1
        !           419: #define FCN_ILL_ADR_ERR_INT_EN_KER_LBN 2
        !           420: #define FCN_ILL_ADR_ERR_INT_EN_KER_WIDTH 1
        !           421: #define FCN_SRM_PERR_INT_EN_KER_LBN 1
        !           422: #define FCN_SRM_PERR_INT_EN_KER_WIDTH 1
        !           423: #define FCN_DRV_INT_EN_KER_LBN 0
        !           424: #define FCN_DRV_INT_EN_KER_WIDTH 1
        !           425: 
        !           426: /* Interrupt status register */
        !           427: #define FCN_INT_ADR_REG_KER    0x0030
        !           428: #define FCN_INT_ADR_KER_LBN 0
        !           429: #define FCN_INT_ADR_KER_WIDTH EFAB_DMA_TYPE_WIDTH ( 64 )
        !           430: 
        !           431: /* Interrupt status register (B0 only) */
        !           432: #define INT_ISR0_B0 0x90
        !           433: #define INT_ISR1_B0 0xA0
        !           434: 
        !           435: /* Interrupt acknowledge register (A0/A1 only) */
        !           436: #define FCN_INT_ACK_KER_REG_A1 0x0050
        !           437: #define INT_ACK_DUMMY_DATA_LBN 0
        !           438: #define INT_ACK_DUMMY_DATA_WIDTH 32
        !           439: 
        !           440: /* Interrupt acknowledge work-around register (A0/A1 only )*/
        !           441: #define WORK_AROUND_BROKEN_PCI_READS_REG_KER_A1 0x0070
        !           442: 
        !           443: /* Hardware initialisation register */
        !           444: #define FCN_HW_INIT_REG_KER 0x00c0
        !           445: #define FCN_BCSR_TARGET_MASK_LBN 101
        !           446: #define FCN_BCSR_TARGET_MASK_WIDTH 4
        !           447: 
        !           448: /* SPI host command register */
        !           449: #define FCN_EE_SPI_HCMD_REG 0x0100
        !           450: #define FCN_EE_SPI_HCMD_CMD_EN_LBN 31
        !           451: #define FCN_EE_SPI_HCMD_CMD_EN_WIDTH 1
        !           452: #define FCN_EE_WR_TIMER_ACTIVE_LBN 28
        !           453: #define FCN_EE_WR_TIMER_ACTIVE_WIDTH 1
        !           454: #define FCN_EE_SPI_HCMD_SF_SEL_LBN 24
        !           455: #define FCN_EE_SPI_HCMD_SF_SEL_WIDTH 1
        !           456: #define FCN_EE_SPI_EEPROM 0
        !           457: #define FCN_EE_SPI_FLASH 1
        !           458: #define FCN_EE_SPI_HCMD_DABCNT_LBN 16
        !           459: #define FCN_EE_SPI_HCMD_DABCNT_WIDTH 5
        !           460: #define FCN_EE_SPI_HCMD_READ_LBN 15
        !           461: #define FCN_EE_SPI_HCMD_READ_WIDTH 1
        !           462: #define FCN_EE_SPI_READ 1
        !           463: #define FCN_EE_SPI_WRITE 0
        !           464: #define FCN_EE_SPI_HCMD_DUBCNT_LBN 12
        !           465: #define FCN_EE_SPI_HCMD_DUBCNT_WIDTH 2
        !           466: #define FCN_EE_SPI_HCMD_ADBCNT_LBN 8
        !           467: #define FCN_EE_SPI_HCMD_ADBCNT_WIDTH 2
        !           468: #define FCN_EE_SPI_HCMD_ENC_LBN 0
        !           469: #define FCN_EE_SPI_HCMD_ENC_WIDTH 8
        !           470: 
        !           471: /* SPI host address register */
        !           472: #define FCN_EE_SPI_HADR_REG 0x0110
        !           473: #define FCN_EE_SPI_HADR_DUBYTE_LBN 24
        !           474: #define FCN_EE_SPI_HADR_DUBYTE_WIDTH 8
        !           475: #define FCN_EE_SPI_HADR_ADR_LBN 0
        !           476: #define FCN_EE_SPI_HADR_ADR_WIDTH 24
        !           477: 
        !           478: /* SPI host data register */
        !           479: #define FCN_EE_SPI_HDATA_REG 0x0120
        !           480: #define FCN_EE_SPI_HDATA3_LBN 96
        !           481: #define FCN_EE_SPI_HDATA3_WIDTH 32
        !           482: #define FCN_EE_SPI_HDATA2_LBN 64
        !           483: #define FCN_EE_SPI_HDATA2_WIDTH 32
        !           484: #define FCN_EE_SPI_HDATA1_LBN 32
        !           485: #define FCN_EE_SPI_HDATA1_WIDTH 32
        !           486: #define FCN_EE_SPI_HDATA0_LBN 0
        !           487: #define FCN_EE_SPI_HDATA0_WIDTH 32
        !           488: 
        !           489: /* VPD Config 0 Register register */
        !           490: #define FCN_EE_VPD_CFG_REG 0x0140
        !           491: #define FCN_EE_VPD_EN_LBN 0
        !           492: #define FCN_EE_VPD_EN_WIDTH 1
        !           493: #define FCN_EE_VPD_EN_AD9_MODE_LBN 1
        !           494: #define FCN_EE_VPD_EN_AD9_MODE_WIDTH 1
        !           495: #define FCN_EE_EE_CLOCK_DIV_LBN 112
        !           496: #define FCN_EE_EE_CLOCK_DIV_WIDTH 7
        !           497: #define FCN_EE_SF_CLOCK_DIV_LBN 120
        !           498: #define FCN_EE_SF_CLOCK_DIV_WIDTH 7
        !           499: 
        !           500: 
        !           501: /* NIC status register */
        !           502: #define FCN_NIC_STAT_REG 0x0200
        !           503: #define FCN_ONCHIP_SRAM_LBN 16
        !           504: #define FCN_ONCHIP_SRAM_WIDTH 1
        !           505: #define FCN_SF_PRST_LBN 9
        !           506: #define FCN_SF_PRST_WIDTH 1
        !           507: #define FCN_EE_PRST_LBN 8
        !           508: #define FCN_EE_PRST_WIDTH 1
        !           509: #define FCN_EE_STRAP_LBN 7
        !           510: #define FCN_EE_STRAP_WIDTH 1
        !           511: #define FCN_PCI_PCIX_MODE_LBN 4
        !           512: #define FCN_PCI_PCIX_MODE_WIDTH 3
        !           513: #define FCN_PCI_PCIX_MODE_PCI33_DECODE 0
        !           514: #define FCN_PCI_PCIX_MODE_PCI66_DECODE 1
        !           515: #define FCN_PCI_PCIX_MODE_PCIX66_DECODE 5
        !           516: #define FCN_PCI_PCIX_MODE_PCIX100_DECODE 6
        !           517: #define FCN_PCI_PCIX_MODE_PCIX133_DECODE 7
        !           518: #define FCN_STRAP_ISCSI_EN_LBN 3
        !           519: #define FCN_STRAP_ISCSI_EN_WIDTH 1
        !           520: #define FCN_STRAP_PINS_LBN 0
        !           521: #define FCN_STRAP_PINS_WIDTH 3
        !           522: #define FCN_STRAP_10G_LBN 2
        !           523: #define FCN_STRAP_10G_WIDTH 1
        !           524: #define FCN_STRAP_DUAL_PORT_LBN 1
        !           525: #define FCN_STRAP_DUAL_PORT_WIDTH 1
        !           526: #define FCN_STRAP_PCIE_LBN 0
        !           527: #define FCN_STRAP_PCIE_WIDTH 1
        !           528: 
        !           529: /* Falcon revisions */
        !           530: #define FALCON_REV_A0 0
        !           531: #define FALCON_REV_A1 1
        !           532: #define FALCON_REV_B0 2
        !           533: 
        !           534: /* GPIO control register */
        !           535: #define FCN_GPIO_CTL_REG_KER 0x0210
        !           536: #define FCN_GPIO_CTL_REG_KER 0x0210
        !           537: 
        !           538: #define FCN_GPIO3_OEN_LBN 27
        !           539: #define FCN_GPIO3_OEN_WIDTH 1
        !           540: #define FCN_GPIO2_OEN_LBN 26
        !           541: #define FCN_GPIO2_OEN_WIDTH 1
        !           542: #define FCN_GPIO1_OEN_LBN 25
        !           543: #define FCN_GPIO1_OEN_WIDTH 1
        !           544: #define FCN_GPIO0_OEN_LBN 24
        !           545: #define FCN_GPIO0_OEN_WIDTH 1
        !           546: 
        !           547: #define FCN_GPIO3_OUT_LBN 19
        !           548: #define FCN_GPIO3_OUT_WIDTH 1
        !           549: #define FCN_GPIO2_OUT_LBN 18
        !           550: #define FCN_GPIO2_OUT_WIDTH 1
        !           551: #define FCN_GPIO1_OUT_LBN 17
        !           552: #define FCN_GPIO1_OUT_WIDTH 1
        !           553: #define FCN_GPIO0_OUT_LBN 16
        !           554: #define FCN_GPIO0_OUT_WIDTH 1
        !           555: 
        !           556: #define FCN_GPIO3_IN_LBN 11
        !           557: #define FCN_GPIO3_IN_WIDTH 1
        !           558: #define FCN_GPIO2_IN_LBN 10
        !           559: #define FCN_GPIO2_IN_WIDTH 1
        !           560: #define FCN_GPIO1_IN_LBN 9
        !           561: #define FCN_GPIO1_IN_WIDTH 1
        !           562: #define FCN_GPIO0_IN_LBN 8
        !           563: #define FCN_GPIO0_IN_WIDTH 1
        !           564: 
        !           565: #define FCN_FLASH_PRESENT_LBN 7
        !           566: #define FCN_FLASH_PRESENT_WIDTH 1
        !           567: #define FCN_EEPROM_PRESENT_LBN 6
        !           568: #define FCN_EEPROM_PRESENT_WIDTH 1
        !           569: #define FCN_BOOTED_USING_NVDEVICE_LBN 3
        !           570: #define FCN_BOOTED_USING_NVDEVICE_WIDTH 1
        !           571: 
        !           572: /* Defines for extra non-volatile storage */
        !           573: #define FCN_NV_MAGIC_NUMBER 0xFA1C
        !           574: 
        !           575: /* Global control register */
        !           576: #define FCN_GLB_CTL_REG_KER    0x0220
        !           577: #define FCN_EXT_PHY_RST_CTL_LBN 63
        !           578: #define FCN_EXT_PHY_RST_CTL_WIDTH 1
        !           579: #define FCN_PCIE_SD_RST_CTL_LBN 61
        !           580: #define FCN_PCIE_SD_RST_CTL_WIDTH 1
        !           581: #define FCN_PCIE_STCK_RST_CTL_LBN 59
        !           582: #define FCN_PCIE_STCK_RST_CTL_WIDTH 1
        !           583: #define FCN_PCIE_NSTCK_RST_CTL_LBN 58
        !           584: #define FCN_PCIE_NSTCK_RST_CTL_WIDTH 1
        !           585: #define FCN_PCIE_CORE_RST_CTL_LBN 57
        !           586: #define FCN_PCIE_CORE_RST_CTL_WIDTH 1
        !           587: #define FCN_EE_RST_CTL_LBN 49
        !           588: #define FCN_EE_RST_CTL_WIDTH 1
        !           589: #define FCN_RST_EXT_PHY_LBN 31
        !           590: #define FCN_RST_EXT_PHY_WIDTH 1
        !           591: #define FCN_EXT_PHY_RST_DUR_LBN 1
        !           592: #define FCN_EXT_PHY_RST_DUR_WIDTH 3
        !           593: #define FCN_SWRST_LBN 0
        !           594: #define FCN_SWRST_WIDTH 1
        !           595: #define INCLUDE_IN_RESET 0
        !           596: #define EXCLUDE_FROM_RESET 1
        !           597: 
        !           598: /* FPGA build version */
        !           599: #define FCN_ALTERA_BUILD_REG_KER 0x0300
        !           600: #define FCN_VER_MAJOR_LBN 24
        !           601: #define FCN_VER_MAJOR_WIDTH 8
        !           602: #define FCN_VER_MINOR_LBN 16
        !           603: #define FCN_VER_MINOR_WIDTH 8
        !           604: #define FCN_VER_BUILD_LBN 0
        !           605: #define FCN_VER_BUILD_WIDTH 16
        !           606: #define FCN_VER_ALL_LBN 0
        !           607: #define FCN_VER_ALL_WIDTH 32
        !           608: 
        !           609: /* Spare EEPROM bits register (flash 0x390) */
        !           610: #define FCN_SPARE_REG_KER 0x310
        !           611: #define FCN_MEM_PERR_EN_TX_DATA_LBN 72
        !           612: #define FCN_MEM_PERR_EN_TX_DATA_WIDTH 2
        !           613: 
        !           614: /* Timer table for kernel access */
        !           615: #define FCN_TIMER_CMD_REG_KER 0x420
        !           616: #define FCN_TIMER_MODE_LBN 12
        !           617: #define FCN_TIMER_MODE_WIDTH 2
        !           618: #define FCN_TIMER_MODE_DIS 0
        !           619: #define FCN_TIMER_MODE_INT_HLDOFF 1
        !           620: #define FCN_TIMER_VAL_LBN 0
        !           621: #define FCN_TIMER_VAL_WIDTH 12
        !           622: 
        !           623: /* Receive configuration register */
        !           624: #define FCN_RX_CFG_REG_KER 0x800
        !           625: #define FCN_RX_XOFF_EN_LBN 0
        !           626: #define FCN_RX_XOFF_EN_WIDTH 1
        !           627: 
        !           628: /* SRAM receive descriptor cache configuration register */
        !           629: #define FCN_SRM_RX_DC_CFG_REG_KER 0x610
        !           630: #define FCN_SRM_RX_DC_BASE_ADR_LBN 0
        !           631: #define FCN_SRM_RX_DC_BASE_ADR_WIDTH 21
        !           632: 
        !           633: /* SRAM transmit descriptor cache configuration register */
        !           634: #define FCN_SRM_TX_DC_CFG_REG_KER 0x620
        !           635: #define FCN_SRM_TX_DC_BASE_ADR_LBN 0
        !           636: #define FCN_SRM_TX_DC_BASE_ADR_WIDTH 21
        !           637: 
        !           638: /* SRAM configuration register */
        !           639: #define FCN_SRM_CFG_REG_KER 0x630
        !           640: #define FCN_SRAM_OOB_ADR_INTEN_LBN 5
        !           641: #define FCN_SRAM_OOB_ADR_INTEN_WIDTH 1
        !           642: #define FCN_SRAM_OOB_BUF_INTEN_LBN 4
        !           643: #define FCN_SRAM_OOB_BUF_INTEN_WIDTH 1
        !           644: #define FCN_SRAM_OOB_BT_INIT_EN_LBN 3
        !           645: #define FCN_SRAM_OOB_BT_INIT_EN_WIDTH 1
        !           646: #define FCN_SRM_NUM_BANK_LBN 2
        !           647: #define FCN_SRM_NUM_BANK_WIDTH 1
        !           648: #define FCN_SRM_BANK_SIZE_LBN 0
        !           649: #define FCN_SRM_BANK_SIZE_WIDTH 2
        !           650: #define FCN_SRM_NUM_BANKS_AND_BANK_SIZE_LBN 0
        !           651: #define FCN_SRM_NUM_BANKS_AND_BANK_SIZE_WIDTH 3
        !           652: 
        !           653: #define FCN_RX_CFG_REG_KER 0x800
        !           654: #define FCN_RX_INGR_EN_B0_LBN 47
        !           655: #define FCN_RX_INGR_EN_B0_WIDTH 1
        !           656: #define FCN_RX_USR_BUF_SIZE_B0_LBN 19
        !           657: #define FCN_RX_USR_BUF_SIZE_B0_WIDTH 9
        !           658: #define FCN_RX_XON_MAC_TH_B0_LBN 10
        !           659: #define FCN_RX_XON_MAC_TH_B0_WIDTH 9
        !           660: #define FCN_RX_XOFF_MAC_TH_B0_LBN 1
        !           661: #define FCN_RX_XOFF_MAC_TH_B0_WIDTH 9
        !           662: #define FCN_RX_XOFF_MAC_EN_B0_LBN 0
        !           663: #define FCN_RX_XOFF_MAC_EN_B0_WIDTH 1
        !           664: #define FCN_RX_USR_BUF_SIZE_A1_LBN 11
        !           665: #define FCN_RX_USR_BUF_SIZE_A1_WIDTH 9
        !           666: #define FCN_RX_XON_MAC_TH_A1_LBN 6
        !           667: #define FCN_RX_XON_MAC_TH_A1_WIDTH 5
        !           668: #define FCN_RX_XOFF_MAC_TH_A1_LBN 1
        !           669: #define FCN_RX_XOFF_MAC_TH_A1_WIDTH 5
        !           670: #define FCN_RX_XOFF_MAC_EN_A1_LBN 0
        !           671: #define FCN_RX_XOFF_MAC_EN_A1_WIDTH 1
        !           672: 
        !           673: #define FCN_RX_USR_BUF_SIZE_A1_LBN 11
        !           674: #define FCN_RX_USR_BUF_SIZE_A1_WIDTH 9
        !           675: #define FCN_RX_XOFF_MAC_EN_A1_LBN 0
        !           676: #define FCN_RX_XOFF_MAC_EN_A1_WIDTH 1
        !           677: 
        !           678: /* Receive filter control register */
        !           679: #define FCN_RX_FILTER_CTL_REG_KER 0x810
        !           680: #define FCN_UDP_FULL_SRCH_LIMIT_LBN 32
        !           681: #define FCN_UDP_FULL_SRCH_LIMIT_WIDTH 8
        !           682: #define FCN_NUM_KER_LBN 24
        !           683: #define FCN_NUM_KER_WIDTH 2
        !           684: #define FCN_UDP_WILD_SRCH_LIMIT_LBN 16
        !           685: #define FCN_UDP_WILD_SRCH_LIMIT_WIDTH 8
        !           686: #define FCN_TCP_WILD_SRCH_LIMIT_LBN 8
        !           687: #define FCN_TCP_WILD_SRCH_LIMIT_WIDTH 8
        !           688: #define FCN_TCP_FULL_SRCH_LIMIT_LBN 0
        !           689: #define FCN_TCP_FULL_SRCH_LIMIT_WIDTH 8
        !           690: 
        !           691: /* RX queue flush register */
        !           692: #define FCN_RX_FLUSH_DESCQ_REG_KER 0x0820
        !           693: #define FCN_RX_FLUSH_DESCQ_CMD_LBN 24
        !           694: #define FCN_RX_FLUSH_DESCQ_CMD_WIDTH 1
        !           695: #define FCN_RX_FLUSH_DESCQ_LBN 0
        !           696: #define FCN_RX_FLUSH_DESCQ_WIDTH 12
        !           697: 
        !           698: /* Receive descriptor update register */
        !           699: #define FCN_RX_DESC_UPD_REG_KER 0x0830
        !           700: #define FCN_RX_DESC_WPTR_LBN 96
        !           701: #define FCN_RX_DESC_WPTR_WIDTH 12
        !           702: #define FCN_RX_DESC_UPD_REG_KER_DWORD ( FCN_RX_DESC_UPD_REG_KER + 12 )
        !           703: #define FCN_RX_DESC_WPTR_DWORD_LBN 0
        !           704: #define FCN_RX_DESC_WPTR_DWORD_WIDTH 12
        !           705: 
        !           706: /* Receive descriptor cache configuration register */
        !           707: #define FCN_RX_DC_CFG_REG_KER 0x840
        !           708: #define FCN_RX_DC_SIZE_LBN 0
        !           709: #define FCN_RX_DC_SIZE_WIDTH 2
        !           710: 
        !           711: #define FCN_RX_SELF_RST_REG_KER 0x890
        !           712: #define FCN_RX_ISCSI_DIS_LBN 17
        !           713: #define FCN_RX_ISCSI_DIS_WIDTH 1
        !           714: #define FCN_RX_NODESC_WAIT_DIS_LBN 9
        !           715: #define FCN_RX_NODESC_WAIT_DIS_WIDTH 1
        !           716: #define FCN_RX_RECOVERY_EN_LBN 8
        !           717: #define FCN_RX_RECOVERY_EN_WIDTH 1
        !           718: 
        !           719: /* TX queue flush register */
        !           720: #define FCN_TX_FLUSH_DESCQ_REG_KER 0x0a00
        !           721: #define FCN_TX_FLUSH_DESCQ_CMD_LBN 12
        !           722: #define FCN_TX_FLUSH_DESCQ_CMD_WIDTH 1
        !           723: #define FCN_TX_FLUSH_DESCQ_LBN 0
        !           724: #define FCN_TX_FLUSH_DESCQ_WIDTH 12
        !           725: 
        !           726: /* Transmit configuration register 2 */
        !           727: #define FCN_TX_CFG2_REG_KER 0xa80
        !           728: #define FCN_TX_DIS_NON_IP_EV_LBN 17
        !           729: #define FCN_TX_DIS_NON_IP_EV_WIDTH 1
        !           730: 
        !           731: /* Transmit descriptor update register */
        !           732: #define FCN_TX_DESC_UPD_REG_KER 0x0a10
        !           733: #define FCN_TX_DESC_WPTR_LBN 96
        !           734: #define FCN_TX_DESC_WPTR_WIDTH 12
        !           735: #define FCN_TX_DESC_UPD_REG_KER_DWORD ( FCN_TX_DESC_UPD_REG_KER + 12 )
        !           736: #define FCN_TX_DESC_WPTR_DWORD_LBN 0
        !           737: #define FCN_TX_DESC_WPTR_DWORD_WIDTH 12
        !           738: 
        !           739: /* Transmit descriptor cache configuration register */
        !           740: #define FCN_TX_DC_CFG_REG_KER 0xa20
        !           741: #define FCN_TX_DC_SIZE_LBN 0
        !           742: #define FCN_TX_DC_SIZE_WIDTH 2
        !           743: 
        !           744: /* PHY management transmit data register */
        !           745: #define FCN_MD_TXD_REG_KER 0xc00
        !           746: #define FCN_MD_TXD_LBN 0
        !           747: #define FCN_MD_TXD_WIDTH 16
        !           748: 
        !           749: /* PHY management receive data register */
        !           750: #define FCN_MD_RXD_REG_KER 0xc10
        !           751: #define FCN_MD_RXD_LBN 0
        !           752: #define FCN_MD_RXD_WIDTH 16
        !           753: 
        !           754: /* PHY management configuration & status register */
        !           755: #define FCN_MD_CS_REG_KER 0xc20
        !           756: #define FCN_MD_GC_LBN 4
        !           757: #define FCN_MD_GC_WIDTH 1
        !           758: #define FCN_MD_RIC_LBN 2
        !           759: #define FCN_MD_RIC_WIDTH 1
        !           760: #define FCN_MD_RDC_LBN 1
        !           761: #define FCN_MD_RDC_WIDTH 1
        !           762: #define FCN_MD_WRC_LBN 0
        !           763: #define FCN_MD_WRC_WIDTH 1
        !           764: 
        !           765: /* PHY management PHY address register */
        !           766: #define FCN_MD_PHY_ADR_REG_KER 0xc30
        !           767: #define FCN_MD_PHY_ADR_LBN 0
        !           768: #define FCN_MD_PHY_ADR_WIDTH 16
        !           769: 
        !           770: /* PHY management ID register */
        !           771: #define FCN_MD_ID_REG_KER 0xc40
        !           772: #define FCN_MD_PRT_ADR_LBN 11
        !           773: #define FCN_MD_PRT_ADR_WIDTH 5
        !           774: #define FCN_MD_DEV_ADR_LBN 6
        !           775: #define FCN_MD_DEV_ADR_WIDTH 5
        !           776: 
        !           777: /* PHY management status & mask register */
        !           778: #define FCN_MD_STAT_REG_KER 0xc50
        !           779: #define FCN_MD_PINT_LBN 4
        !           780: #define FCN_MD_PINT_WIDTH 1
        !           781: #define FCN_MD_DONE_LBN 3
        !           782: #define FCN_MD_DONE_WIDTH 1
        !           783: #define FCN_MD_BSERR_LBN 2
        !           784: #define FCN_MD_BSERR_WIDTH 1
        !           785: #define FCN_MD_LNFL_LBN 1
        !           786: #define FCN_MD_LNFL_WIDTH 1
        !           787: #define FCN_MD_BSY_LBN 0
        !           788: #define FCN_MD_BSY_WIDTH 1
        !           789: 
        !           790: /* Port 0 and 1 MAC control registers */
        !           791: #define FCN_MAC0_CTRL_REG_KER 0xc80
        !           792: #define FCN_MAC1_CTRL_REG_KER 0xc90
        !           793: #define FCN_MAC_XOFF_VAL_LBN 16
        !           794: #define FCN_MAC_XOFF_VAL_WIDTH 16
        !           795: #define FCN_MAC_BCAD_ACPT_LBN 4
        !           796: #define FCN_MAC_BCAD_ACPT_WIDTH 1
        !           797: #define FCN_MAC_UC_PROM_LBN 3
        !           798: #define FCN_MAC_UC_PROM_WIDTH 1
        !           799: #define FCN_MAC_LINK_STATUS_LBN 2
        !           800: #define FCN_MAC_LINK_STATUS_WIDTH 1
        !           801: #define FCN_MAC_SPEED_LBN 0
        !           802: #define FCN_MAC_SPEED_WIDTH 2
        !           803: 
        !           804: /* 10Gig Xaui XGXS Default Values  */
        !           805: #define XX_TXDRV_DEQ_DEFAULT 0xe /* deq=.6 */
        !           806: #define XX_TXDRV_DTX_DEFAULT 0x5 /* 1.25 */
        !           807: #define XX_SD_CTL_DRV_DEFAULT 0  /* 20mA */
        !           808: 
        !           809: /* GMAC registers */
        !           810: #define FALCON_GMAC_REGBANK 0xe00
        !           811: #define FALCON_GMAC_REGBANK_SIZE 0x200
        !           812: #define FALCON_GMAC_REG_SIZE 0x10
        !           813: 
        !           814: /* XGMAC registers */
        !           815: #define FALCON_XMAC_REGBANK 0x1200
        !           816: #define FALCON_XMAC_REGBANK_SIZE 0x200
        !           817: #define FALCON_XMAC_REG_SIZE 0x10
        !           818: 
        !           819: /* XGMAC address register low */
        !           820: #define FCN_XM_ADR_LO_REG_MAC 0x00
        !           821: #define FCN_XM_ADR_3_LBN 24
        !           822: #define FCN_XM_ADR_3_WIDTH 8
        !           823: #define FCN_XM_ADR_2_LBN 16
        !           824: #define FCN_XM_ADR_2_WIDTH 8
        !           825: #define FCN_XM_ADR_1_LBN 8
        !           826: #define FCN_XM_ADR_1_WIDTH 8
        !           827: #define FCN_XM_ADR_0_LBN 0
        !           828: #define FCN_XM_ADR_0_WIDTH 8
        !           829: 
        !           830: /* XGMAC address register high */
        !           831: #define FCN_XM_ADR_HI_REG_MAC 0x01
        !           832: #define FCN_XM_ADR_5_LBN 8
        !           833: #define FCN_XM_ADR_5_WIDTH 8
        !           834: #define FCN_XM_ADR_4_LBN 0
        !           835: #define FCN_XM_ADR_4_WIDTH 8
        !           836: 
        !           837: /* XGMAC global configuration - port 0*/
        !           838: #define FCN_XM_GLB_CFG_REG_MAC 0x02
        !           839: #define FCN_XM_RX_STAT_EN_LBN 11
        !           840: #define FCN_XM_RX_STAT_EN_WIDTH 1
        !           841: #define FCN_XM_TX_STAT_EN_LBN 10
        !           842: #define FCN_XM_TX_STAT_EN_WIDTH 1
        !           843: #define FCN_XM_RX_JUMBO_MODE_LBN 6
        !           844: #define FCN_XM_RX_JUMBO_MODE_WIDTH 1
        !           845: #define FCN_XM_CORE_RST_LBN 0
        !           846: #define FCN_XM_CORE_RST_WIDTH 1
        !           847: 
        !           848: /* XGMAC transmit configuration - port 0 */
        !           849: #define FCN_XM_TX_CFG_REG_MAC 0x03
        !           850: #define FCN_XM_IPG_LBN 16
        !           851: #define FCN_XM_IPG_WIDTH 4
        !           852: #define FCN_XM_FCNTL_LBN 10
        !           853: #define FCN_XM_FCNTL_WIDTH 1
        !           854: #define FCN_XM_TXCRC_LBN 8
        !           855: #define FCN_XM_TXCRC_WIDTH 1
        !           856: #define FCN_XM_AUTO_PAD_LBN 5
        !           857: #define FCN_XM_AUTO_PAD_WIDTH 1
        !           858: #define FCN_XM_TX_PRMBL_LBN 2
        !           859: #define FCN_XM_TX_PRMBL_WIDTH 1
        !           860: #define FCN_XM_TXEN_LBN 1
        !           861: #define FCN_XM_TXEN_WIDTH 1
        !           862: 
        !           863: /* XGMAC receive configuration - port 0 */
        !           864: #define FCN_XM_RX_CFG_REG_MAC 0x04
        !           865: #define FCN_XM_PASS_CRC_ERR_LBN 25
        !           866: #define FCN_XM_PASS_CRC_ERR_WIDTH 1
        !           867: #define FCN_XM_AUTO_DEPAD_LBN 8
        !           868: #define FCN_XM_AUTO_DEPAD_WIDTH 1
        !           869: #define FCN_XM_RXEN_LBN 1
        !           870: #define FCN_XM_RXEN_WIDTH 1
        !           871: 
        !           872: /* XGMAC management interrupt mask register */
        !           873: #define FCN_XM_MGT_INT_MSK_REG_MAC_B0 0x5
        !           874: #define FCN_XM_MSK_PRMBLE_ERR_LBN 2
        !           875: #define FCN_XM_MSK_PRMBLE_ERR_WIDTH 1
        !           876: #define FCN_XM_MSK_RMTFLT_LBN 1
        !           877: #define FCN_XM_MSK_RMTFLT_WIDTH 1
        !           878: #define FCN_XM_MSK_LCLFLT_LBN 0
        !           879: #define FCN_XM_MSK_LCLFLT_WIDTH 1
        !           880: 
        !           881: /* XGMAC flow control register */
        !           882: #define FCN_XM_FC_REG_MAC 0x7
        !           883: #define FCN_XM_PAUSE_TIME_LBN 16
        !           884: #define FCN_XM_PAUSE_TIME_WIDTH 16
        !           885: #define FCN_XM_DIS_FCNTL_LBN 0
        !           886: #define FCN_XM_DIS_FCNTL_WIDTH 1
        !           887: 
        !           888: /* XGMAC transmit parameter register */
        !           889: #define FCN_XM_TX_PARAM_REG_MAC 0x0d
        !           890: #define FCN_XM_TX_JUMBO_MODE_LBN 31
        !           891: #define FCN_XM_TX_JUMBO_MODE_WIDTH 1
        !           892: #define FCN_XM_MAX_TX_FRM_SIZE_LBN 16
        !           893: #define FCN_XM_MAX_TX_FRM_SIZE_WIDTH 14
        !           894: #define FCN_XM_ACPT_ALL_MCAST_LBN 11
        !           895: #define FCN_XM_ACPT_ALL_MCAST_WIDTH 1
        !           896: 
        !           897: /* XGMAC receive parameter register */
        !           898: #define FCN_XM_RX_PARAM_REG_MAC 0x0e
        !           899: #define FCN_XM_MAX_RX_FRM_SIZE_LBN 0
        !           900: #define FCN_XM_MAX_RX_FRM_SIZE_WIDTH 14
        !           901: 
        !           902: /* XGMAC management interrupt status register */
        !           903: #define FCN_XM_MGT_INT_REG_MAC_B0 0x0f
        !           904: #define FCN_XM_PRMBLE_ERR 2
        !           905: #define FCN_XM_PRMBLE_WIDTH 1
        !           906: #define FCN_XM_RMTFLT_LBN 1
        !           907: #define FCN_XM_RMTFLT_WIDTH 1
        !           908: #define FCN_XM_LCLFLT_LBN 0
        !           909: #define FCN_XM_LCLFLT_WIDTH 1
        !           910: 
        !           911: /* XAUI XGXS core status register */
        !           912: #define FCN_XX_ALIGN_DONE_LBN 20
        !           913: #define FCN_XX_ALIGN_DONE_WIDTH 1
        !           914: #define FCN_XX_CORE_STAT_REG_MAC 0x16
        !           915: #define FCN_XX_SYNC_STAT_LBN 16
        !           916: #define FCN_XX_SYNC_STAT_WIDTH 4
        !           917: #define FCN_XX_SYNC_STAT_DECODE_SYNCED 0xf
        !           918: #define FCN_XX_COMMA_DET_LBN 12
        !           919: #define FCN_XX_COMMA_DET_WIDTH 4
        !           920: #define FCN_XX_COMMA_DET_RESET 0xf
        !           921: #define FCN_XX_CHARERR_LBN 4
        !           922: #define FCN_XX_CHARERR_WIDTH 4
        !           923: #define FCN_XX_CHARERR_RESET 0xf
        !           924: #define FCN_XX_DISPERR_LBN 0
        !           925: #define FCN_XX_DISPERR_WIDTH 4
        !           926: #define FCN_XX_DISPERR_RESET 0xf
        !           927: 
        !           928: /* XGXS/XAUI powerdown/reset register */
        !           929: #define FCN_XX_PWR_RST_REG_MAC 0x10
        !           930: #define FCN_XX_PWRDND_EN_LBN 15
        !           931: #define FCN_XX_PWRDND_EN_WIDTH 1
        !           932: #define FCN_XX_PWRDNC_EN_LBN 14
        !           933: #define FCN_XX_PWRDNC_EN_WIDTH 1
        !           934: #define FCN_XX_PWRDNB_EN_LBN 13
        !           935: #define FCN_XX_PWRDNB_EN_WIDTH 1
        !           936: #define FCN_XX_PWRDNA_EN_LBN 12
        !           937: #define FCN_XX_PWRDNA_EN_WIDTH 1
        !           938: #define FCN_XX_RSTPLLCD_EN_LBN 9
        !           939: #define FCN_XX_RSTPLLCD_EN_WIDTH 1
        !           940: #define FCN_XX_RSTPLLAB_EN_LBN 8
        !           941: #define FCN_XX_RSTPLLAB_EN_WIDTH 1
        !           942: #define FCN_XX_RESETD_EN_LBN 7
        !           943: #define FCN_XX_RESETD_EN_WIDTH 1
        !           944: #define FCN_XX_RESETC_EN_LBN 6
        !           945: #define FCN_XX_RESETC_EN_WIDTH 1
        !           946: #define FCN_XX_RESETB_EN_LBN 5
        !           947: #define FCN_XX_RESETB_EN_WIDTH 1
        !           948: #define FCN_XX_RESETA_EN_LBN 4
        !           949: #define FCN_XX_RESETA_EN_WIDTH 1
        !           950: #define FCN_XX_RSTXGXSRX_EN_LBN 2
        !           951: #define FCN_XX_RSTXGXSRX_EN_WIDTH 1
        !           952: #define FCN_XX_RSTXGXSTX_EN_LBN 1
        !           953: #define FCN_XX_RSTXGXSTX_EN_WIDTH 1
        !           954: #define FCN_XX_RST_XX_EN_LBN 0
        !           955: #define FCN_XX_RST_XX_EN_WIDTH 1
        !           956: 
        !           957: 
        !           958: /* XGXS/XAUI powerdown/reset control register */
        !           959: #define FCN_XX_SD_CTL_REG_MAC 0x11
        !           960: #define FCN_XX_TERMADJ1_LBN 17
        !           961: #define FCN_XX_TERMADJ1_WIDTH 1
        !           962: #define FCN_XX_TERMADJ0_LBN 16
        !           963: #define FCN_XX_TERMADJ0_WIDTH 1
        !           964: #define FCN_XX_HIDRVD_LBN 15
        !           965: #define FCN_XX_HIDRVD_WIDTH 1
        !           966: #define FCN_XX_LODRVD_LBN 14
        !           967: #define FCN_XX_LODRVD_WIDTH 1
        !           968: #define FCN_XX_HIDRVC_LBN 13
        !           969: #define FCN_XX_HIDRVC_WIDTH 1
        !           970: #define FCN_XX_LODRVC_LBN 12
        !           971: #define FCN_XX_LODRVC_WIDTH 1
        !           972: #define FCN_XX_HIDRVB_LBN 11
        !           973: #define FCN_XX_HIDRVB_WIDTH 1
        !           974: #define FCN_XX_LODRVB_LBN 10
        !           975: #define FCN_XX_LODRVB_WIDTH 1
        !           976: #define FCN_XX_HIDRVA_LBN 9
        !           977: #define FCN_XX_HIDRVA_WIDTH 1
        !           978: #define FCN_XX_LODRVA_LBN 8
        !           979: #define FCN_XX_LODRVA_WIDTH 1
        !           980: #define FCN_XX_LPBKD_LBN 3
        !           981: #define FCN_XX_LPBKD_WIDTH 1
        !           982: #define FCN_XX_LPBKC_LBN 2
        !           983: #define FCN_XX_LPBKC_WIDTH 1
        !           984: #define FCN_XX_LPBKB_LBN 1
        !           985: #define FCN_XX_LPBKB_WIDTH 1
        !           986: #define FCN_XX_LPBKA_LBN 0
        !           987: #define FCN_XX_LPBKA_WIDTH 1
        !           988: 
        !           989: #define FCN_XX_TXDRV_CTL_REG_MAC 0x12
        !           990: #define FCN_XX_DEQD_LBN 28
        !           991: #define FCN_XX_DEQD_WIDTH 4
        !           992: #define FCN_XX_DEQC_LBN 24
        !           993: #define FCN_XX_DEQC_WIDTH 4
        !           994: #define FCN_XX_DEQB_LBN 20
        !           995: #define FCN_XX_DEQB_WIDTH 4
        !           996: #define FCN_XX_DEQA_LBN 16
        !           997: #define FCN_XX_DEQA_WIDTH 4
        !           998: #define FCN_XX_DTXD_LBN 12
        !           999: #define FCN_XX_DTXD_WIDTH 4
        !          1000: #define FCN_XX_DTXC_LBN 8
        !          1001: #define FCN_XX_DTXC_WIDTH 4
        !          1002: #define FCN_XX_DTXB_LBN 4
        !          1003: #define FCN_XX_DTXB_WIDTH 4
        !          1004: #define FCN_XX_DTXA_LBN 0
        !          1005: #define FCN_XX_DTXA_WIDTH 4
        !          1006: 
        !          1007: /* Receive filter table */
        !          1008: #define FCN_RX_FILTER_TBL0 0xF00000 
        !          1009: 
        !          1010: /* Receive descriptor pointer table */
        !          1011: #define FCN_RX_DESC_PTR_TBL_KER_A1 0x11800
        !          1012: #define FCN_RX_DESC_PTR_TBL_KER_B0 0xF40000
        !          1013: #define FCN_RX_ISCSI_DDIG_EN_LBN 88
        !          1014: #define FCN_RX_ISCSI_DDIG_EN_WIDTH 1
        !          1015: #define FCN_RX_ISCSI_HDIG_EN_LBN 87
        !          1016: #define FCN_RX_ISCSI_HDIG_EN_WIDTH 1
        !          1017: #define FCN_RX_DESCQ_BUF_BASE_ID_LBN 36
        !          1018: #define FCN_RX_DESCQ_BUF_BASE_ID_WIDTH 20
        !          1019: #define FCN_RX_DESCQ_EVQ_ID_LBN 24
        !          1020: #define FCN_RX_DESCQ_EVQ_ID_WIDTH 12
        !          1021: #define FCN_RX_DESCQ_OWNER_ID_LBN 10
        !          1022: #define FCN_RX_DESCQ_OWNER_ID_WIDTH 14
        !          1023: #define FCN_RX_DESCQ_SIZE_LBN 3
        !          1024: #define FCN_RX_DESCQ_SIZE_WIDTH 2
        !          1025: #define FCN_RX_DESCQ_SIZE_4K 3
        !          1026: #define FCN_RX_DESCQ_SIZE_2K 2
        !          1027: #define FCN_RX_DESCQ_SIZE_1K 1
        !          1028: #define FCN_RX_DESCQ_SIZE_512 0
        !          1029: #define FCN_RX_DESCQ_TYPE_LBN 2
        !          1030: #define FCN_RX_DESCQ_TYPE_WIDTH 1
        !          1031: #define FCN_RX_DESCQ_JUMBO_LBN 1
        !          1032: #define FCN_RX_DESCQ_JUMBO_WIDTH 1
        !          1033: #define FCN_RX_DESCQ_EN_LBN 0
        !          1034: #define FCN_RX_DESCQ_EN_WIDTH 1
        !          1035: 
        !          1036: /* Transmit descriptor pointer table */
        !          1037: #define FCN_TX_DESC_PTR_TBL_KER_A1 0x11900
        !          1038: #define FCN_TX_DESC_PTR_TBL_KER_B0 0xF50000
        !          1039: #define FCN_TX_NON_IP_DROP_DIS_B0_LBN 91
        !          1040: #define FCN_TX_NON_IP_DROP_DIS_B0_WIDTH 1
        !          1041: #define FCN_TX_DESCQ_EN_LBN 88
        !          1042: #define FCN_TX_DESCQ_EN_WIDTH 1
        !          1043: #define FCN_TX_ISCSI_DDIG_EN_LBN 87
        !          1044: #define FCN_TX_ISCSI_DDIG_EN_WIDTH 1
        !          1045: #define FCN_TX_ISCSI_HDIG_EN_LBN 86
        !          1046: #define FCN_TX_ISCSI_HDIG_EN_WIDTH 1
        !          1047: #define FCN_TX_DESCQ_BUF_BASE_ID_LBN 36
        !          1048: #define FCN_TX_DESCQ_BUF_BASE_ID_WIDTH 20
        !          1049: #define FCN_TX_DESCQ_EVQ_ID_LBN 24
        !          1050: #define FCN_TX_DESCQ_EVQ_ID_WIDTH 12
        !          1051: #define FCN_TX_DESCQ_OWNER_ID_LBN 10
        !          1052: #define FCN_TX_DESCQ_OWNER_ID_WIDTH 14
        !          1053: #define FCN_TX_DESCQ_SIZE_LBN 3
        !          1054: #define FCN_TX_DESCQ_SIZE_WIDTH 2
        !          1055: #define FCN_TX_DESCQ_SIZE_4K 3
        !          1056: #define FCN_TX_DESCQ_SIZE_2K 2
        !          1057: #define FCN_TX_DESCQ_SIZE_1K 1
        !          1058: #define FCN_TX_DESCQ_SIZE_512 0
        !          1059: #define FCN_TX_DESCQ_TYPE_LBN 1
        !          1060: #define FCN_TX_DESCQ_TYPE_WIDTH 2
        !          1061: #define FCN_TX_DESCQ_FLUSH_LBN 0
        !          1062: #define FCN_TX_DESCQ_FLUSH_WIDTH 1
        !          1063: 
        !          1064: /* Event queue pointer */
        !          1065: #define FCN_EVQ_PTR_TBL_KER_A1 0x11a00
        !          1066: #define FCN_EVQ_PTR_TBL_KER_B0 0xf60000
        !          1067: #define FCN_EVQ_EN_LBN 23
        !          1068: #define FCN_EVQ_EN_WIDTH 1
        !          1069: #define FCN_EVQ_SIZE_LBN 20
        !          1070: #define FCN_EVQ_SIZE_WIDTH 3
        !          1071: #define FCN_EVQ_SIZE_32K 6
        !          1072: #define FCN_EVQ_SIZE_16K 5
        !          1073: #define FCN_EVQ_SIZE_8K 4
        !          1074: #define FCN_EVQ_SIZE_4K 3
        !          1075: #define FCN_EVQ_SIZE_2K 2
        !          1076: #define FCN_EVQ_SIZE_1K 1
        !          1077: #define FCN_EVQ_SIZE_512 0
        !          1078: #define FCN_EVQ_BUF_BASE_ID_LBN 0
        !          1079: #define FCN_EVQ_BUF_BASE_ID_WIDTH 20
        !          1080: 
        !          1081: /* RSS indirection table */
        !          1082: #define FCN_RX_RSS_INDIR_TBL_B0 0xFB0000
        !          1083: 
        !          1084: /* Event queue read pointer */
        !          1085: #define FCN_EVQ_RPTR_REG_KER_A1 0x11b00
        !          1086: #define FCN_EVQ_RPTR_REG_KER_B0 0xfa0000
        !          1087: #define FCN_EVQ_RPTR_LBN 0
        !          1088: #define FCN_EVQ_RPTR_WIDTH 14
        !          1089: #define FCN_EVQ_RPTR_REG_KER_DWORD_A1 ( FCN_EVQ_RPTR_REG_KER_A1 + 0 )
        !          1090: #define FCN_EVQ_RPTR_REG_KER_DWORD_B0 ( FCN_EVQ_RPTR_REG_KER_B0 + 0 )
        !          1091: #define FCN_EVQ_RPTR_DWORD_LBN 0
        !          1092: #define FCN_EVQ_RPTR_DWORD_WIDTH 14
        !          1093: 
        !          1094: /* Special buffer descriptors */
        !          1095: #define FCN_BUF_FULL_TBL_KER_A1 0x18000
        !          1096: #define FCN_BUF_FULL_TBL_KER_B0 0x800000
        !          1097: #define FCN_IP_DAT_BUF_SIZE_LBN 50
        !          1098: #define FCN_IP_DAT_BUF_SIZE_WIDTH 1
        !          1099: #define FCN_IP_DAT_BUF_SIZE_8K 1
        !          1100: #define FCN_IP_DAT_BUF_SIZE_4K 0
        !          1101: #define FCN_BUF_ADR_FBUF_LBN 14
        !          1102: #define FCN_BUF_ADR_FBUF_WIDTH 34
        !          1103: #define FCN_BUF_OWNER_ID_FBUF_LBN 0
        !          1104: #define FCN_BUF_OWNER_ID_FBUF_WIDTH 14
        !          1105: 
        !          1106: /** Offset of a GMAC register within Falcon */
        !          1107: #define FALCON_GMAC_REG( efab, mac_reg )                               \
        !          1108:        ( FALCON_GMAC_REGBANK +                                 \
        !          1109:          ( (mac_reg) * FALCON_GMAC_REG_SIZE ) )
        !          1110: 
        !          1111: /** Offset of an XMAC register within Falcon */
        !          1112: #define FALCON_XMAC_REG( efab_port, mac_reg )                  \
        !          1113:        ( FALCON_XMAC_REGBANK +                                 \
        !          1114:          ( (mac_reg) * FALCON_XMAC_REG_SIZE ) )
        !          1115: 
        !          1116: #define FCN_MAC_DATA_LBN 0
        !          1117: #define FCN_MAC_DATA_WIDTH 32
        !          1118: 
        !          1119: /* Transmit descriptor */
        !          1120: #define FCN_TX_KER_PORT_LBN 63
        !          1121: #define FCN_TX_KER_PORT_WIDTH 1
        !          1122: #define FCN_TX_KER_BYTE_CNT_LBN 48
        !          1123: #define FCN_TX_KER_BYTE_CNT_WIDTH 14
        !          1124: #define FCN_TX_KER_BUF_ADR_LBN 0
        !          1125: #define FCN_TX_KER_BUF_ADR_WIDTH EFAB_DMA_TYPE_WIDTH ( 46 )
        !          1126: 
        !          1127: 
        !          1128: /* Receive descriptor */
        !          1129: #define FCN_RX_KER_BUF_SIZE_LBN 48
        !          1130: #define FCN_RX_KER_BUF_SIZE_WIDTH 14
        !          1131: #define FCN_RX_KER_BUF_ADR_LBN 0
        !          1132: #define FCN_RX_KER_BUF_ADR_WIDTH EFAB_DMA_TYPE_WIDTH ( 46 )
        !          1133: 
        !          1134: /* Event queue entries */
        !          1135: #define FCN_EV_CODE_LBN 60
        !          1136: #define FCN_EV_CODE_WIDTH 4
        !          1137: #define FCN_RX_IP_EV_DECODE 0
        !          1138: #define FCN_TX_IP_EV_DECODE 2
        !          1139: #define FCN_DRIVER_EV_DECODE 5
        !          1140: 
        !          1141: /* Receive events */
        !          1142: #define FCN_RX_EV_PKT_OK_LBN 56
        !          1143: #define FCN_RX_EV_PKT_OK_WIDTH 1
        !          1144: #define FCN_RX_PORT_LBN 30
        !          1145: #define FCN_RX_PORT_WIDTH 1
        !          1146: #define FCN_RX_EV_BYTE_CNT_LBN 16
        !          1147: #define FCN_RX_EV_BYTE_CNT_WIDTH 14
        !          1148: #define FCN_RX_EV_DESC_PTR_LBN 0
        !          1149: #define FCN_RX_EV_DESC_PTR_WIDTH 12
        !          1150: 
        !          1151: /* Transmit events */
        !          1152: #define FCN_TX_EV_DESC_PTR_LBN 0
        !          1153: #define FCN_TX_EV_DESC_PTR_WIDTH 12
        !          1154: 
        !          1155: /*******************************************************************************
        !          1156:  *
        !          1157:  *
        !          1158:  * Low-level hardware access
        !          1159:  *
        !          1160:  *
        !          1161:  *******************************************************************************/ 
        !          1162: 
        !          1163: #define FCN_REVISION_REG(efab, reg) \
        !          1164:        ( ( efab->pci_revision == FALCON_REV_B0 ) ? reg ## _B0 : reg ## _A1 )
        !          1165: 
        !          1166: #define EFAB_SET_OWORD_FIELD_VER(efab, reg, field, val)                        \
        !          1167:        if ( efab->pci_revision == FALCON_REV_B0 )                      \
        !          1168:                EFAB_SET_OWORD_FIELD ( reg, field ## _B0, val );        \
        !          1169:        else                                                            \
        !          1170:                EFAB_SET_OWORD_FIELD ( reg, field ## _A1, val );
        !          1171: 
        !          1172: #if FALCON_USE_IO_BAR
        !          1173: 
        !          1174: /* Write dword via the I/O BAR */
        !          1175: static inline void _falcon_writel ( struct efab_nic *efab, uint32_t value,
        !          1176:                                    unsigned int reg ) {
        !          1177:        outl ( reg, efab->iobase + FCN_IOM_IND_ADR_REG );
        !          1178:        outl ( value, efab->iobase + FCN_IOM_IND_DAT_REG );
        !          1179: }
        !          1180: 
        !          1181: /* Read dword via the I/O BAR */
        !          1182: static inline uint32_t _falcon_readl ( struct efab_nic *efab,
        !          1183:                                       unsigned int reg ) {
        !          1184:        outl ( reg, efab->iobase + FCN_IOM_IND_ADR_REG );
        !          1185:        return inl ( efab->iobase + FCN_IOM_IND_DAT_REG );
        !          1186: }
        !          1187: 
        !          1188: #else /* FALCON_USE_IO_BAR */
        !          1189: 
        !          1190: #define _falcon_writel( efab, value, reg ) \
        !          1191:        writel ( (value), (efab)->membase + (reg) )
        !          1192: #define _falcon_readl( efab, reg ) readl ( (efab)->membase + (reg) )
        !          1193: 
        !          1194: #endif /* FALCON_USE_IO_BAR */
        !          1195: 
        !          1196: /**
        !          1197:  * Write to a Falcon register
        !          1198:  *
        !          1199:  */
        !          1200: static inline void
        !          1201: falcon_write ( struct efab_nic *efab, efab_oword_t *value, unsigned int reg )
        !          1202: {
        !          1203: 
        !          1204:        EFAB_REGDUMP ( "Writing register %x with " EFAB_OWORD_FMT "\n",
        !          1205:                       reg, EFAB_OWORD_VAL ( *value ) );
        !          1206: 
        !          1207:        _falcon_writel ( efab, value->u32[0], reg + 0  );
        !          1208:        _falcon_writel ( efab, value->u32[1], reg + 4  );
        !          1209:        _falcon_writel ( efab, value->u32[2], reg + 8  );
        !          1210:        wmb();
        !          1211:        _falcon_writel ( efab, value->u32[3], reg + 12 );
        !          1212:        wmb();
        !          1213: }
        !          1214: 
        !          1215: /**
        !          1216:  * Write to Falcon SRAM
        !          1217:  *
        !          1218:  */
        !          1219: static inline void
        !          1220: falcon_write_sram ( struct efab_nic *efab, efab_qword_t *value,
        !          1221:                    unsigned int index )
        !          1222: {
        !          1223:        unsigned int reg = ( FCN_REVISION_REG ( efab, FCN_BUF_FULL_TBL_KER ) +
        !          1224:                             ( index * sizeof ( *value ) ) );
        !          1225: 
        !          1226:        EFAB_REGDUMP ( "Writing SRAM register %x with " EFAB_QWORD_FMT "\n",
        !          1227:                       reg, EFAB_QWORD_VAL ( *value ) );
        !          1228: 
        !          1229:        _falcon_writel ( efab, value->u32[0], reg + 0  );
        !          1230:        _falcon_writel ( efab, value->u32[1], reg + 4  );
        !          1231:        wmb();
        !          1232: }
        !          1233: 
        !          1234: /**
        !          1235:  * Write dword to Falcon register that allows partial writes
        !          1236:  *
        !          1237:  */
        !          1238: static inline void
        !          1239: falcon_writel ( struct efab_nic *efab, efab_dword_t *value, unsigned int reg )
        !          1240: {
        !          1241:        EFAB_REGDUMP ( "Writing partial register %x with " EFAB_DWORD_FMT "\n",
        !          1242:                       reg, EFAB_DWORD_VAL ( *value ) );
        !          1243:        _falcon_writel ( efab, value->u32[0], reg );
        !          1244: }
        !          1245: 
        !          1246: /**
        !          1247:  * Read from a Falcon register
        !          1248:  *
        !          1249:  */
        !          1250: static inline void
        !          1251: falcon_read ( struct efab_nic *efab, efab_oword_t *value, unsigned int reg )
        !          1252: {
        !          1253:        value->u32[0] = _falcon_readl ( efab, reg + 0  );
        !          1254:        wmb();
        !          1255:        value->u32[1] = _falcon_readl ( efab, reg + 4  );
        !          1256:        value->u32[2] = _falcon_readl ( efab, reg + 8  );
        !          1257:        value->u32[3] = _falcon_readl ( efab, reg + 12 );
        !          1258: 
        !          1259:        EFAB_REGDUMP ( "Read from register %x, got " EFAB_OWORD_FMT "\n",
        !          1260:                       reg, EFAB_OWORD_VAL ( *value ) );
        !          1261: }
        !          1262: 
        !          1263: /** 
        !          1264:  * Read from Falcon SRAM
        !          1265:  *
        !          1266:  */
        !          1267: static inline void
        !          1268: falcon_read_sram ( struct efab_nic *efab, efab_qword_t *value,
        !          1269:                   unsigned int index )
        !          1270: {
        !          1271:        unsigned int reg = ( FCN_REVISION_REG ( efab, FCN_BUF_FULL_TBL_KER ) +
        !          1272:                             ( index * sizeof ( *value ) ) );
        !          1273: 
        !          1274:        value->u32[0] = _falcon_readl ( efab, reg + 0 );
        !          1275:        value->u32[1] = _falcon_readl ( efab, reg + 4 );
        !          1276:        EFAB_REGDUMP ( "Read from SRAM register %x, got " EFAB_QWORD_FMT "\n",
        !          1277:                       reg, EFAB_QWORD_VAL ( *value ) );
        !          1278: }
        !          1279: 
        !          1280: /**
        !          1281:  * Read dword from a portion of a Falcon register
        !          1282:  *
        !          1283:  */
        !          1284: static inline void
        !          1285: falcon_readl ( struct efab_nic *efab, efab_dword_t *value, unsigned int reg )
        !          1286: {
        !          1287:        value->u32[0] = _falcon_readl ( efab, reg );
        !          1288:        EFAB_REGDUMP ( "Read from register %x, got " EFAB_DWORD_FMT "\n",
        !          1289:                       reg, EFAB_DWORD_VAL ( *value ) );
        !          1290: }
        !          1291: 
        !          1292: #define FCN_DUMP_REG( efab, _reg ) do {                                \
        !          1293:                efab_oword_t reg;                               \
        !          1294:                falcon_read ( efab, &reg, _reg );               \
        !          1295:                EFAB_LOG ( #_reg " = " EFAB_OWORD_FMT "\n",     \
        !          1296:                           EFAB_OWORD_VAL ( reg ) );            \
        !          1297:        } while ( 0 );
        !          1298: 
        !          1299: #define FCN_DUMP_MAC_REG( efab, _mac_reg ) do {                                \
        !          1300:                efab_dword_t reg;                                       \
        !          1301:                efab->mac_op->mac_readl ( efab, &reg, _mac_reg );       \
        !          1302:                EFAB_LOG ( #_mac_reg " = " EFAB_DWORD_FMT "\n",         \
        !          1303:                           EFAB_DWORD_VAL ( reg ) );                    \
        !          1304:        } while ( 0 );
        !          1305: 
        !          1306: /**
        !          1307:  * See if an event is present
        !          1308:  *
        !          1309:  * @v event            Falcon event structure
        !          1310:  * @ret True           An event is pending
        !          1311:  * @ret False          No event is pending
        !          1312:  *
        !          1313:  * We check both the high and low dword of the event for all ones.  We
        !          1314:  * wrote all ones when we cleared the event, and no valid event can
        !          1315:  * have all ones in either its high or low dwords.  This approach is
        !          1316:  * robust against reordering.
        !          1317:  *
        !          1318:  * Note that using a single 64-bit comparison is incorrect; even
        !          1319:  * though the CPU read will be atomic, the DMA write may not be.
        !          1320:  */
        !          1321: static inline int
        !          1322: falcon_event_present ( falcon_event_t* event )
        !          1323: {
        !          1324:        return ( ! ( EFAB_DWORD_IS_ALL_ONES ( event->dword[0] ) |
        !          1325:                     EFAB_DWORD_IS_ALL_ONES ( event->dword[1] ) ) );
        !          1326: }
        !          1327: 
        !          1328: static void
        !          1329: falcon_eventq_read_ack ( struct efab_nic *efab, struct efab_ev_queue *ev_queue )
        !          1330: {
        !          1331:        efab_dword_t reg;
        !          1332: 
        !          1333:        EFAB_POPULATE_DWORD_1 ( reg, FCN_EVQ_RPTR_DWORD, ev_queue->read_ptr );
        !          1334:        falcon_writel ( efab, &reg,
        !          1335:                        FCN_REVISION_REG ( efab, FCN_EVQ_RPTR_REG_KER_DWORD ) );
        !          1336: }
        !          1337: 
        !          1338: #if 0
        !          1339: /**
        !          1340:  * Dump register contents (for debugging)
        !          1341:  *
        !          1342:  * Marked as static inline so that it will not be compiled in if not
        !          1343:  * used.
        !          1344:  */
        !          1345: static inline void
        !          1346: falcon_dump_regs ( struct efab_nic *efab )
        !          1347: {
        !          1348:        FCN_DUMP_REG ( efab, FCN_INT_EN_REG_KER );
        !          1349:        FCN_DUMP_REG ( efab, FCN_INT_ADR_REG_KER );
        !          1350:        FCN_DUMP_REG ( efab, FCN_GLB_CTL_REG_KER );
        !          1351:        FCN_DUMP_REG ( efab, FCN_TIMER_CMD_REG_KER );
        !          1352:        FCN_DUMP_REG ( efab, FCN_SRM_RX_DC_CFG_REG_KER );
        !          1353:        FCN_DUMP_REG ( efab, FCN_SRM_TX_DC_CFG_REG_KER );
        !          1354:        FCN_DUMP_REG ( efab, FCN_RX_FILTER_CTL_REG_KER );
        !          1355:        FCN_DUMP_REG ( efab, FCN_RX_DC_CFG_REG_KER );
        !          1356:        FCN_DUMP_REG ( efab, FCN_TX_DC_CFG_REG_KER );
        !          1357:        FCN_DUMP_REG ( efab, FCN_MAC0_CTRL_REG_KER );
        !          1358:        FCN_DUMP_REG ( efab, FCN_MAC1_CTRL_REG_KER );
        !          1359:        FCN_DUMP_REG ( efab, FCN_REVISION_REG ( efab, FCN_RX_DESC_PTR_TBL_KER ) );
        !          1360:        FCN_DUMP_REG ( efab, FCN_REVISION_REG ( efab, FCN_TX_DESC_PTR_TBL_KER ) );
        !          1361:        FCN_DUMP_REG ( efab, FCN_REVISION_REG ( efab, FCN_EVQ_PTR_TBL_KER ) );
        !          1362:        FCN_DUMP_MAC_REG ( efab, GM_CFG1_REG_MAC );
        !          1363:        FCN_DUMP_MAC_REG ( efab, GM_CFG2_REG_MAC );
        !          1364:        FCN_DUMP_MAC_REG ( efab, GM_MAX_FLEN_REG_MAC );
        !          1365:        FCN_DUMP_MAC_REG ( efab, GM_MII_MGMT_CFG_REG_MAC );
        !          1366:        FCN_DUMP_MAC_REG ( efab, GM_ADR1_REG_MAC );
        !          1367:        FCN_DUMP_MAC_REG ( efab, GM_ADR2_REG_MAC );
        !          1368:        FCN_DUMP_MAC_REG ( efab, GMF_CFG0_REG_MAC );
        !          1369:        FCN_DUMP_MAC_REG ( efab, GMF_CFG1_REG_MAC );
        !          1370:        FCN_DUMP_MAC_REG ( efab, GMF_CFG2_REG_MAC );
        !          1371:        FCN_DUMP_MAC_REG ( efab, GMF_CFG3_REG_MAC );
        !          1372:        FCN_DUMP_MAC_REG ( efab, GMF_CFG4_REG_MAC );
        !          1373:        FCN_DUMP_MAC_REG ( efab, GMF_CFG5_REG_MAC );
        !          1374: }
        !          1375: #endif
        !          1376: 
        !          1377: static void
        !          1378: falcon_interrupts ( struct efab_nic *efab, int enabled, int force )
        !          1379: {
        !          1380:        efab_oword_t int_en_reg_ker;
        !          1381: 
        !          1382:        EFAB_POPULATE_OWORD_2 ( int_en_reg_ker,
        !          1383:                                FCN_KER_INT_KER, force,
        !          1384:                                FCN_DRV_INT_EN_KER, enabled );
        !          1385:        falcon_write ( efab, &int_en_reg_ker, FCN_INT_EN_REG_KER );     
        !          1386: }
        !          1387: 
        !          1388: /*******************************************************************************
        !          1389:  *
        !          1390:  *
        !          1391:  * SPI access
        !          1392:  *
        !          1393:  *
        !          1394:  *******************************************************************************/ 
        !          1395: 
        !          1396: 
        !          1397: /** Maximum length for a single SPI transaction */
        !          1398: #define FALCON_SPI_MAX_LEN 16
        !          1399: 
        !          1400: static int
        !          1401: falcon_spi_wait ( struct efab_nic *efab )
        !          1402: {
        !          1403:        efab_oword_t reg;
        !          1404:        int count;
        !          1405: 
        !          1406:        count = 0;
        !          1407:        do {
        !          1408:                udelay ( 100 );
        !          1409:                falcon_read ( efab, &reg, FCN_EE_SPI_HCMD_REG );
        !          1410:                if ( EFAB_OWORD_FIELD ( reg, FCN_EE_SPI_HCMD_CMD_EN ) == 0 )
        !          1411:                        return 0;
        !          1412:        } while ( ++count < 1000 );
        !          1413: 
        !          1414:        EFAB_ERR ( "Timed out waiting for SPI\n" );
        !          1415:        return -ETIMEDOUT;
        !          1416: }
        !          1417: 
        !          1418: static int
        !          1419: falcon_spi_rw ( struct spi_bus* bus, struct spi_device *device,
        !          1420:                unsigned int command, int address,
        !          1421:                const void* data_out, void *data_in, size_t len )
        !          1422: {
        !          1423:        struct efab_nic *efab = container_of ( bus, struct efab_nic, spi_bus );
        !          1424:        int address_len, rc, device_id, read_cmd;
        !          1425:        efab_oword_t reg;
        !          1426: 
        !          1427:        /* falcon_init_spi_device() should have reduced the block size
        !          1428:         * down so this constraint holds */
        !          1429:        assert ( len <= FALCON_SPI_MAX_LEN );
        !          1430: 
        !          1431:        /* Is this the FLASH or EEPROM device? */
        !          1432:        if ( device == &efab->spi_flash )
        !          1433:                device_id = FCN_EE_SPI_FLASH;
        !          1434:        else if ( device == &efab->spi_eeprom )
        !          1435:                device_id = FCN_EE_SPI_EEPROM;
        !          1436:        else {
        !          1437:                EFAB_ERR ( "Unknown device %p\n", device );
        !          1438:                return -EINVAL;
        !          1439:        }
        !          1440: 
        !          1441:        EFAB_TRACE ( "Executing spi command %d on device %d at %d for %zd bytes\n",
        !          1442:                     command, device_id, address, len );
        !          1443: 
        !          1444:        /* The bus must be idle */
        !          1445:        rc = falcon_spi_wait ( efab );
        !          1446:        if ( rc )
        !          1447:                goto fail1;
        !          1448: 
        !          1449:        /* Copy data out */
        !          1450:        if ( data_out ) {
        !          1451:                memcpy ( &reg, data_out, len );
        !          1452:                falcon_write ( efab, &reg, FCN_EE_SPI_HDATA_REG );
        !          1453:        }
        !          1454: 
        !          1455:        /* Program address register */
        !          1456:        if ( address >= 0 ) {
        !          1457:                EFAB_POPULATE_OWORD_1 ( reg, FCN_EE_SPI_HADR_ADR, address );
        !          1458:                falcon_write ( efab, &reg, FCN_EE_SPI_HADR_REG );
        !          1459:        }
        !          1460: 
        !          1461:        /* Issue command */
        !          1462:        address_len = ( address >= 0 ) ? device->address_len / 8 : 0;
        !          1463:        read_cmd = ( data_in ? FCN_EE_SPI_READ : FCN_EE_SPI_WRITE );
        !          1464:        EFAB_POPULATE_OWORD_7 ( reg,
        !          1465:                                FCN_EE_SPI_HCMD_CMD_EN, 1,
        !          1466:                                FCN_EE_SPI_HCMD_SF_SEL, device_id,
        !          1467:                                FCN_EE_SPI_HCMD_DABCNT, len,
        !          1468:                                FCN_EE_SPI_HCMD_READ, read_cmd,
        !          1469:                                FCN_EE_SPI_HCMD_DUBCNT, 0,
        !          1470:                                FCN_EE_SPI_HCMD_ADBCNT, address_len,
        !          1471:                                FCN_EE_SPI_HCMD_ENC, command );
        !          1472:        falcon_write ( efab, &reg, FCN_EE_SPI_HCMD_REG );
        !          1473: 
        !          1474:        /* Wait for the command to complete */
        !          1475:        rc = falcon_spi_wait ( efab );
        !          1476:        if ( rc )
        !          1477:                goto fail2;
        !          1478: 
        !          1479:        /* Copy data in */
        !          1480:        if ( data_in ) {
        !          1481:                falcon_read ( efab, &reg, FCN_EE_SPI_HDATA_REG );
        !          1482:                memcpy ( data_in, &reg, len );
        !          1483:        }
        !          1484: 
        !          1485:        return 0;
        !          1486: 
        !          1487: fail2:
        !          1488: fail1:
        !          1489:        EFAB_ERR ( "Failed SPI command %d to device %d address 0x%x len 0x%zx\n",
        !          1490:                   command, device_id, address, len );
        !          1491: 
        !          1492:        return rc;
        !          1493: }
        !          1494: 
        !          1495: /*******************************************************************************
        !          1496:  *
        !          1497:  *
        !          1498:  * Falcon bit-bashed I2C interface
        !          1499:  *
        !          1500:  *
        !          1501:  *******************************************************************************/ 
        !          1502: 
        !          1503: static void
        !          1504: falcon_i2c_bit_write ( struct bit_basher *basher, unsigned int bit_id,
        !          1505:                       unsigned long data )
        !          1506: {
        !          1507:        struct efab_nic *efab = container_of ( basher, struct efab_nic,
        !          1508:                                               i2c_bb.basher );
        !          1509:        efab_oword_t reg;
        !          1510: 
        !          1511:        falcon_read ( efab, &reg, FCN_GPIO_CTL_REG_KER );
        !          1512:        switch ( bit_id ) {
        !          1513:        case I2C_BIT_SCL:
        !          1514:                EFAB_SET_OWORD_FIELD ( reg, FCN_GPIO0_OEN, ( data ? 0 : 1 ) );
        !          1515:                break;
        !          1516:        case I2C_BIT_SDA:
        !          1517:                EFAB_SET_OWORD_FIELD ( reg, FCN_GPIO3_OEN, ( data ? 0 : 1 ) );
        !          1518:                break;
        !          1519:        default:
        !          1520:                EFAB_ERR ( "%s bit=%d\n", __func__, bit_id );
        !          1521:                break;
        !          1522:        }
        !          1523: 
        !          1524:        falcon_write ( efab, &reg,  FCN_GPIO_CTL_REG_KER );
        !          1525: }
        !          1526: 
        !          1527: static int
        !          1528: falcon_i2c_bit_read ( struct bit_basher *basher, unsigned int bit_id )
        !          1529: {
        !          1530:        struct efab_nic *efab = container_of ( basher, struct efab_nic,
        !          1531:                                               i2c_bb.basher );
        !          1532:        efab_oword_t reg;
        !          1533:        
        !          1534:        falcon_read ( efab, &reg, FCN_GPIO_CTL_REG_KER );
        !          1535:        switch ( bit_id ) {
        !          1536:        case I2C_BIT_SCL:
        !          1537:                return EFAB_OWORD_FIELD ( reg, FCN_GPIO0_IN );
        !          1538:                break;
        !          1539:        case I2C_BIT_SDA:
        !          1540:                return EFAB_OWORD_FIELD ( reg, FCN_GPIO3_IN );
        !          1541:                break;
        !          1542:        default:
        !          1543:                EFAB_ERR ( "%s bit=%d\n", __func__, bit_id );
        !          1544:                break;
        !          1545:        }
        !          1546: 
        !          1547:        return -1;
        !          1548: }
        !          1549: 
        !          1550: static struct bit_basher_operations falcon_i2c_bit_ops = {
        !          1551:        .read           = falcon_i2c_bit_read,
        !          1552:        .write          = falcon_i2c_bit_write,
        !          1553: };
        !          1554: 
        !          1555: 
        !          1556: /*******************************************************************************
        !          1557:  *
        !          1558:  *
        !          1559:  * MDIO access
        !          1560:  *
        !          1561:  *
        !          1562:  *******************************************************************************/ 
        !          1563: 
        !          1564: static int
        !          1565: falcon_gmii_wait ( struct efab_nic *efab )
        !          1566: {
        !          1567:        efab_dword_t md_stat;
        !          1568:        int count;
        !          1569: 
        !          1570:        /* wait upto 10ms */
        !          1571:        for (count = 0; count < 1000; count++) {
        !          1572:                falcon_readl ( efab, &md_stat, FCN_MD_STAT_REG_KER );
        !          1573:                if ( EFAB_DWORD_FIELD ( md_stat, FCN_MD_BSY ) == 0 ) {
        !          1574:                        if ( EFAB_DWORD_FIELD ( md_stat, FCN_MD_LNFL ) != 0 ||
        !          1575:                             EFAB_DWORD_FIELD ( md_stat, FCN_MD_BSERR ) != 0 ) {
        !          1576:                                EFAB_ERR ( "Error from GMII access "
        !          1577:                                           EFAB_DWORD_FMT"\n",
        !          1578:                                           EFAB_DWORD_VAL ( md_stat ));
        !          1579:                                return -EIO;
        !          1580:                        }
        !          1581:                        return 0;
        !          1582:                }
        !          1583:                udelay(10);
        !          1584:        }
        !          1585: 
        !          1586:        EFAB_ERR ( "Timed out waiting for GMII\n" );
        !          1587:        return -ETIMEDOUT;
        !          1588: }
        !          1589: 
        !          1590: static void
        !          1591: falcon_mdio_write ( struct efab_nic *efab, int device,
        !          1592:                    int location, int value )
        !          1593: {
        !          1594:        efab_oword_t reg;
        !          1595: 
        !          1596:        EFAB_TRACE ( "Writing GMII %d register %02x with %04x\n",
        !          1597:                     device, location, value );
        !          1598: 
        !          1599:        /* Check MII not currently being accessed */
        !          1600:        if ( falcon_gmii_wait ( efab ) )
        !          1601:                return;
        !          1602: 
        !          1603:        /* Write the address/ID register */
        !          1604:        EFAB_POPULATE_OWORD_1 ( reg, FCN_MD_PHY_ADR, location );
        !          1605:        falcon_write ( efab, &reg, FCN_MD_PHY_ADR_REG_KER );
        !          1606: 
        !          1607:        if ( efab->phy_10g ) {
        !          1608:                /* clause45 */
        !          1609:                EFAB_POPULATE_OWORD_2 ( reg, 
        !          1610:                                        FCN_MD_PRT_ADR, efab->phy_addr,
        !          1611:                                        FCN_MD_DEV_ADR, device );
        !          1612:        }
        !          1613:        else {
        !          1614:                /* clause22 */
        !          1615:                assert ( device == 0 );
        !          1616: 
        !          1617:                EFAB_POPULATE_OWORD_2 ( reg,
        !          1618:                                        FCN_MD_PRT_ADR, efab->phy_addr,
        !          1619:                                        FCN_MD_DEV_ADR, location );
        !          1620:        }
        !          1621:        falcon_write ( efab, &reg, FCN_MD_ID_REG_KER );
        !          1622:                
        !          1623: 
        !          1624:        /* Write data */
        !          1625:        EFAB_POPULATE_OWORD_1 ( reg, FCN_MD_TXD, value );
        !          1626:        falcon_write ( efab, &reg, FCN_MD_TXD_REG_KER );
        !          1627: 
        !          1628:        EFAB_POPULATE_OWORD_2 ( reg,
        !          1629:                                FCN_MD_WRC, 1,
        !          1630:                                FCN_MD_GC, ( efab->phy_10g ? 0 : 1 ) );
        !          1631:        falcon_write ( efab, &reg, FCN_MD_CS_REG_KER );
        !          1632:                
        !          1633:        /* Wait for data to be written */
        !          1634:        if ( falcon_gmii_wait ( efab ) ) {
        !          1635:                /* Abort the write operation */
        !          1636:                EFAB_POPULATE_OWORD_2 ( reg,
        !          1637:                                        FCN_MD_WRC, 0,
        !          1638:                                        FCN_MD_GC, 1);
        !          1639:                falcon_write ( efab, &reg, FCN_MD_CS_REG_KER );
        !          1640:                udelay(10);
        !          1641:        }
        !          1642: }
        !          1643: 
        !          1644: static int
        !          1645: falcon_mdio_read ( struct efab_nic *efab, int device, int location )
        !          1646: {
        !          1647:        efab_oword_t reg;
        !          1648:        int value;
        !          1649: 
        !          1650:        /* Check MII not currently being accessed */
        !          1651:        if ( falcon_gmii_wait ( efab ) ) 
        !          1652:                return -1;
        !          1653: 
        !          1654:        if ( efab->phy_10g ) {
        !          1655:                /* clause45 */
        !          1656:                EFAB_POPULATE_OWORD_1 ( reg, FCN_MD_PHY_ADR, location );
        !          1657:                falcon_write ( efab, &reg, FCN_MD_PHY_ADR_REG_KER );
        !          1658: 
        !          1659:                EFAB_POPULATE_OWORD_2 ( reg,
        !          1660:                                        FCN_MD_PRT_ADR, efab->phy_addr,
        !          1661:                                        FCN_MD_DEV_ADR, device );
        !          1662:                falcon_write ( efab, &reg, FCN_MD_ID_REG_KER);
        !          1663: 
        !          1664:                /* request data to be read */
        !          1665:                EFAB_POPULATE_OWORD_2 ( reg,
        !          1666:                                        FCN_MD_RDC, 1,
        !          1667:                                        FCN_MD_GC, 0 );
        !          1668:        }
        !          1669:        else {
        !          1670:                /* clause22 */
        !          1671:                assert ( device == 0 );
        !          1672: 
        !          1673:                EFAB_POPULATE_OWORD_2 ( reg,
        !          1674:                                        FCN_MD_PRT_ADR, efab->phy_addr,
        !          1675:                                        FCN_MD_DEV_ADR, location );
        !          1676:                falcon_write ( efab, &reg, FCN_MD_ID_REG_KER );
        !          1677: 
        !          1678:                /* Request data to be read */
        !          1679:                EFAB_POPULATE_OWORD_2 ( reg,
        !          1680:                                        FCN_MD_RIC, 1,
        !          1681:                                        FCN_MD_GC, 1 );
        !          1682:        }
        !          1683: 
        !          1684:        falcon_write ( efab, &reg, FCN_MD_CS_REG_KER );
        !          1685:                
        !          1686:        /* Wait for data to become available */
        !          1687:        if ( falcon_gmii_wait ( efab ) ) {
        !          1688:                /* Abort the read operation */
        !          1689:                EFAB_POPULATE_OWORD_2 ( reg,
        !          1690:                                        FCN_MD_RIC, 0,
        !          1691:                                        FCN_MD_GC, 1 );
        !          1692:                falcon_write ( efab, &reg, FCN_MD_CS_REG_KER );
        !          1693:                udelay ( 10 );
        !          1694:                value = -1;
        !          1695:        }
        !          1696:        else {
        !          1697:                /* Read the data */
        !          1698:                falcon_read ( efab, &reg, FCN_MD_RXD_REG_KER );
        !          1699:                value = EFAB_OWORD_FIELD ( reg, FCN_MD_RXD );
        !          1700:        }
        !          1701: 
        !          1702:        EFAB_TRACE ( "Read from GMII %d register %02x, got %04x\n",
        !          1703:                     device, location, value );
        !          1704: 
        !          1705:        return value;
        !          1706: }
        !          1707: 
        !          1708: /*******************************************************************************
        !          1709:  *
        !          1710:  *
        !          1711:  * MAC wrapper
        !          1712:  *
        !          1713:  *
        !          1714:  *******************************************************************************/
        !          1715: 
        !          1716: static void
        !          1717: falcon_reconfigure_mac_wrapper ( struct efab_nic *efab )
        !          1718: {
        !          1719:        efab_oword_t reg;
        !          1720:        int link_speed;
        !          1721: 
        !          1722:        if ( efab->link_options & LPA_EF_10000 ) {
        !          1723:                link_speed = 0x3;
        !          1724:        } else if ( efab->link_options & LPA_EF_1000 ) {
        !          1725:                link_speed = 0x2;
        !          1726:        } else if ( efab->link_options & LPA_100 ) {
        !          1727:                link_speed = 0x1;
        !          1728:        } else {
        !          1729:                link_speed = 0x0;
        !          1730:        }
        !          1731:        EFAB_POPULATE_OWORD_5 ( reg,
        !          1732:                                FCN_MAC_XOFF_VAL, 0xffff /* datasheet */,
        !          1733:                                FCN_MAC_BCAD_ACPT, 1,
        !          1734:                                FCN_MAC_UC_PROM, 0,
        !          1735:                                FCN_MAC_LINK_STATUS, 1,
        !          1736:                                FCN_MAC_SPEED, link_speed );
        !          1737: 
        !          1738:        falcon_write ( efab, &reg, FCN_MAC0_CTRL_REG_KER );
        !          1739: }
        !          1740: 
        !          1741: /*******************************************************************************
        !          1742:  *
        !          1743:  *
        !          1744:  * GMAC handling
        !          1745:  *
        !          1746:  *
        !          1747:  *******************************************************************************/
        !          1748: 
        !          1749: /* GMAC configuration register 1 */
        !          1750: #define GM_CFG1_REG_MAC 0x00
        !          1751: #define GM_SW_RST_LBN 31
        !          1752: #define GM_SW_RST_WIDTH 1
        !          1753: #define GM_RX_FC_EN_LBN 5
        !          1754: #define GM_RX_FC_EN_WIDTH 1
        !          1755: #define GM_TX_FC_EN_LBN 4
        !          1756: #define GM_TX_FC_EN_WIDTH 1
        !          1757: #define GM_RX_EN_LBN 2
        !          1758: #define GM_RX_EN_WIDTH 1
        !          1759: #define GM_TX_EN_LBN 0
        !          1760: #define GM_TX_EN_WIDTH 1
        !          1761: 
        !          1762: /* GMAC configuration register 2 */
        !          1763: #define GM_CFG2_REG_MAC 0x01
        !          1764: #define GM_PAMBL_LEN_LBN 12
        !          1765: #define GM_PAMBL_LEN_WIDTH 4
        !          1766: #define GM_IF_MODE_LBN 8
        !          1767: #define GM_IF_MODE_WIDTH 2
        !          1768: #define GM_PAD_CRC_EN_LBN 2
        !          1769: #define GM_PAD_CRC_EN_WIDTH 1
        !          1770: #define GM_FD_LBN 0
        !          1771: #define GM_FD_WIDTH 1
        !          1772: 
        !          1773: /* GMAC maximum frame length register */
        !          1774: #define GM_MAX_FLEN_REG_MAC 0x04
        !          1775: #define GM_MAX_FLEN_LBN 0
        !          1776: #define GM_MAX_FLEN_WIDTH 16
        !          1777: 
        !          1778: /* GMAC MII management configuration register */
        !          1779: #define GM_MII_MGMT_CFG_REG_MAC 0x08
        !          1780: #define GM_MGMT_CLK_SEL_LBN 0
        !          1781: #define GM_MGMT_CLK_SEL_WIDTH 3
        !          1782: 
        !          1783: /* GMAC MII management command register */
        !          1784: #define GM_MII_MGMT_CMD_REG_MAC 0x09
        !          1785: #define GM_MGMT_SCAN_CYC_LBN 1
        !          1786: #define GM_MGMT_SCAN_CYC_WIDTH 1
        !          1787: #define GM_MGMT_RD_CYC_LBN 0
        !          1788: #define GM_MGMT_RD_CYC_WIDTH 1
        !          1789: 
        !          1790: /* GMAC MII management address register */
        !          1791: #define GM_MII_MGMT_ADR_REG_MAC 0x0a
        !          1792: #define GM_MGMT_PHY_ADDR_LBN 8
        !          1793: #define GM_MGMT_PHY_ADDR_WIDTH 5
        !          1794: #define GM_MGMT_REG_ADDR_LBN 0
        !          1795: #define GM_MGMT_REG_ADDR_WIDTH 5
        !          1796: 
        !          1797: /* GMAC MII management control register */
        !          1798: #define GM_MII_MGMT_CTL_REG_MAC 0x0b
        !          1799: #define GM_MGMT_CTL_LBN 0
        !          1800: #define GM_MGMT_CTL_WIDTH 16
        !          1801: 
        !          1802: /* GMAC MII management status register */
        !          1803: #define GM_MII_MGMT_STAT_REG_MAC 0x0c
        !          1804: #define GM_MGMT_STAT_LBN 0
        !          1805: #define GM_MGMT_STAT_WIDTH 16
        !          1806: 
        !          1807: /* GMAC MII management indicators register */
        !          1808: #define GM_MII_MGMT_IND_REG_MAC 0x0d
        !          1809: #define GM_MGMT_BUSY_LBN 0
        !          1810: #define GM_MGMT_BUSY_WIDTH 1
        !          1811: 
        !          1812: /* GMAC station address register 1 */
        !          1813: #define GM_ADR1_REG_MAC 0x10
        !          1814: #define GM_HWADDR_5_LBN 24
        !          1815: #define GM_HWADDR_5_WIDTH 8
        !          1816: #define GM_HWADDR_4_LBN 16
        !          1817: #define GM_HWADDR_4_WIDTH 8
        !          1818: #define GM_HWADDR_3_LBN 8
        !          1819: #define GM_HWADDR_3_WIDTH 8
        !          1820: #define GM_HWADDR_2_LBN 0
        !          1821: #define GM_HWADDR_2_WIDTH 8
        !          1822: 
        !          1823: /* GMAC station address register 2 */
        !          1824: #define GM_ADR2_REG_MAC 0x11
        !          1825: #define GM_HWADDR_1_LBN 24
        !          1826: #define GM_HWADDR_1_WIDTH 8
        !          1827: #define GM_HWADDR_0_LBN 16
        !          1828: #define GM_HWADDR_0_WIDTH 8
        !          1829: 
        !          1830: /* GMAC FIFO configuration register 0 */
        !          1831: #define GMF_CFG0_REG_MAC 0x12
        !          1832: #define GMF_FTFENREQ_LBN 12
        !          1833: #define GMF_FTFENREQ_WIDTH 1
        !          1834: #define GMF_STFENREQ_LBN 11
        !          1835: #define GMF_STFENREQ_WIDTH 1
        !          1836: #define GMF_FRFENREQ_LBN 10
        !          1837: #define GMF_FRFENREQ_WIDTH 1
        !          1838: #define GMF_SRFENREQ_LBN 9
        !          1839: #define GMF_SRFENREQ_WIDTH 1
        !          1840: #define GMF_WTMENREQ_LBN 8
        !          1841: #define GMF_WTMENREQ_WIDTH 1
        !          1842: 
        !          1843: /* GMAC FIFO configuration register 1 */
        !          1844: #define GMF_CFG1_REG_MAC 0x13
        !          1845: #define GMF_CFGFRTH_LBN 16
        !          1846: #define GMF_CFGFRTH_WIDTH 5
        !          1847: #define GMF_CFGXOFFRTX_LBN 0
        !          1848: #define GMF_CFGXOFFRTX_WIDTH 16
        !          1849: 
        !          1850: /* GMAC FIFO configuration register 2 */
        !          1851: #define GMF_CFG2_REG_MAC 0x14
        !          1852: #define GMF_CFGHWM_LBN 16
        !          1853: #define GMF_CFGHWM_WIDTH 6
        !          1854: #define GMF_CFGLWM_LBN 0
        !          1855: #define GMF_CFGLWM_WIDTH 6
        !          1856: 
        !          1857: /* GMAC FIFO configuration register 3 */
        !          1858: #define GMF_CFG3_REG_MAC 0x15
        !          1859: #define GMF_CFGHWMFT_LBN 16
        !          1860: #define GMF_CFGHWMFT_WIDTH 6
        !          1861: #define GMF_CFGFTTH_LBN 0
        !          1862: #define GMF_CFGFTTH_WIDTH 6
        !          1863: 
        !          1864: /* GMAC FIFO configuration register 4 */
        !          1865: #define GMF_CFG4_REG_MAC 0x16
        !          1866: #define GMF_HSTFLTRFRM_PAUSE_LBN 12
        !          1867: #define GMF_HSTFLTRFRM_PAUSE_WIDTH 12
        !          1868: 
        !          1869: /* GMAC FIFO configuration register 5 */
        !          1870: #define GMF_CFG5_REG_MAC 0x17
        !          1871: #define GMF_CFGHDPLX_LBN 22
        !          1872: #define GMF_CFGHDPLX_WIDTH 1
        !          1873: #define GMF_CFGBYTMODE_LBN 19
        !          1874: #define GMF_CFGBYTMODE_WIDTH 1
        !          1875: #define GMF_HSTDRPLT64_LBN 18
        !          1876: #define GMF_HSTDRPLT64_WIDTH 1
        !          1877: #define GMF_HSTFLTRFRMDC_PAUSE_LBN 12
        !          1878: #define GMF_HSTFLTRFRMDC_PAUSE_WIDTH 1
        !          1879: 
        !          1880: static void
        !          1881: falcon_gmac_writel ( struct efab_nic *efab, efab_dword_t *value,
        !          1882:                     unsigned int mac_reg )
        !          1883: {
        !          1884:        efab_oword_t temp;
        !          1885: 
        !          1886:        EFAB_POPULATE_OWORD_1 ( temp, FCN_MAC_DATA,
        !          1887:                                EFAB_DWORD_FIELD ( *value, FCN_MAC_DATA ) );
        !          1888:        falcon_write ( efab, &temp, FALCON_GMAC_REG ( efab, mac_reg ) );
        !          1889: }
        !          1890: 
        !          1891: static void
        !          1892: falcon_gmac_readl ( struct efab_nic *efab, efab_dword_t *value,
        !          1893:                    unsigned int mac_reg )
        !          1894: {
        !          1895:        efab_oword_t temp;
        !          1896: 
        !          1897:        falcon_read ( efab, &temp, FALCON_GMAC_REG ( efab, mac_reg ) );
        !          1898:        EFAB_POPULATE_DWORD_1 ( *value, FCN_MAC_DATA,
        !          1899:                                EFAB_OWORD_FIELD ( temp, FCN_MAC_DATA ) );
        !          1900: }
        !          1901: 
        !          1902: static void
        !          1903: mentormac_reset ( struct efab_nic *efab )
        !          1904: {
        !          1905:        efab_dword_t reg;
        !          1906: 
        !          1907:        /* Take into reset */
        !          1908:        EFAB_POPULATE_DWORD_1 ( reg, GM_SW_RST, 1 );
        !          1909:        falcon_gmac_writel ( efab, &reg, GM_CFG1_REG_MAC );
        !          1910:        udelay ( 1000 );
        !          1911: 
        !          1912:        /* Take out of reset */
        !          1913:        EFAB_POPULATE_DWORD_1 ( reg, GM_SW_RST, 0 );
        !          1914:        falcon_gmac_writel ( efab, &reg, GM_CFG1_REG_MAC );
        !          1915:        udelay ( 1000 );
        !          1916: 
        !          1917:        /* Configure GMII interface so PHY is accessible.  Note that
        !          1918:         * GMII interface is connected only to port 0, and that on
        !          1919:         * Falcon this is a no-op.
        !          1920:         */
        !          1921:        EFAB_POPULATE_DWORD_1 ( reg, GM_MGMT_CLK_SEL, 0x4 );
        !          1922:        falcon_gmac_writel ( efab, &reg, GM_MII_MGMT_CFG_REG_MAC );
        !          1923:        udelay ( 10 );
        !          1924: }
        !          1925: 
        !          1926: static void
        !          1927: mentormac_init ( struct efab_nic *efab )
        !          1928: {
        !          1929:        int pause, if_mode, full_duplex, bytemode, half_duplex;
        !          1930:        efab_dword_t reg;
        !          1931: 
        !          1932:        /* Configuration register 1 */
        !          1933:        pause = ( efab->link_options & LPA_PAUSE_CAP ) ? 1 : 0;
        !          1934:        if ( ! ( efab->link_options & LPA_EF_DUPLEX ) ) {
        !          1935:                /* Half-duplex operation requires TX flow control */
        !          1936:                pause = 1;
        !          1937:        }
        !          1938:        EFAB_POPULATE_DWORD_4 ( reg,
        !          1939:                                GM_TX_EN, 1,
        !          1940:                                GM_TX_FC_EN, pause,
        !          1941:                                GM_RX_EN, 1,
        !          1942:                                GM_RX_FC_EN, 1 );
        !          1943:        falcon_gmac_writel ( efab, &reg, GM_CFG1_REG_MAC );
        !          1944:        udelay ( 10 );
        !          1945: 
        !          1946:        /* Configuration register 2 */
        !          1947:        if_mode = ( efab->link_options & LPA_EF_1000 ) ? 2 : 1;
        !          1948:        full_duplex = ( efab->link_options & LPA_EF_DUPLEX ) ? 1 : 0;
        !          1949:        EFAB_POPULATE_DWORD_4 ( reg,
        !          1950:                                GM_IF_MODE, if_mode,
        !          1951:                                GM_PAD_CRC_EN, 1,
        !          1952:                                GM_FD, full_duplex,
        !          1953:                                GM_PAMBL_LEN, 0x7 /* ? */ );
        !          1954:        falcon_gmac_writel ( efab, &reg, GM_CFG2_REG_MAC );
        !          1955:        udelay ( 10 );
        !          1956: 
        !          1957:        /* Max frame len register */
        !          1958:        EFAB_POPULATE_DWORD_1 ( reg, GM_MAX_FLEN,
        !          1959:                                EFAB_MAX_FRAME_LEN ( ETH_FRAME_LEN ) );
        !          1960:        falcon_gmac_writel ( efab, &reg, GM_MAX_FLEN_REG_MAC );
        !          1961:        udelay ( 10 );
        !          1962: 
        !          1963:        /* FIFO configuration register 0 */
        !          1964:        EFAB_POPULATE_DWORD_5 ( reg,
        !          1965:                                GMF_FTFENREQ, 1,
        !          1966:                                GMF_STFENREQ, 1,
        !          1967:                                GMF_FRFENREQ, 1,
        !          1968:                                GMF_SRFENREQ, 1,
        !          1969:                                GMF_WTMENREQ, 1 );
        !          1970:        falcon_gmac_writel ( efab, &reg, GMF_CFG0_REG_MAC );
        !          1971:        udelay ( 10 );
        !          1972: 
        !          1973:        /* FIFO configuration register 1 */
        !          1974:        EFAB_POPULATE_DWORD_2 ( reg,
        !          1975:                                GMF_CFGFRTH, 0x12,
        !          1976:                                GMF_CFGXOFFRTX, 0xffff );
        !          1977:        falcon_gmac_writel ( efab, &reg, GMF_CFG1_REG_MAC );
        !          1978:        udelay ( 10 );
        !          1979: 
        !          1980:        /* FIFO configuration register 2 */
        !          1981:        EFAB_POPULATE_DWORD_2 ( reg,
        !          1982:                                GMF_CFGHWM, 0x3f,
        !          1983:                                GMF_CFGLWM, 0xa );
        !          1984:        falcon_gmac_writel ( efab, &reg, GMF_CFG2_REG_MAC );
        !          1985:        udelay ( 10 );
        !          1986: 
        !          1987:        /* FIFO configuration register 3 */
        !          1988:        EFAB_POPULATE_DWORD_2 ( reg,
        !          1989:                                GMF_CFGHWMFT, 0x1c,
        !          1990:                                GMF_CFGFTTH, 0x08 );
        !          1991:        falcon_gmac_writel ( efab, &reg, GMF_CFG3_REG_MAC );
        !          1992:        udelay ( 10 );
        !          1993: 
        !          1994:        /* FIFO configuration register 4 */
        !          1995:        EFAB_POPULATE_DWORD_1 ( reg, GMF_HSTFLTRFRM_PAUSE, 1 );
        !          1996:        falcon_gmac_writel ( efab, &reg, GMF_CFG4_REG_MAC );
        !          1997:        udelay ( 10 );
        !          1998:        
        !          1999:        /* FIFO configuration register 5 */
        !          2000:        bytemode = ( efab->link_options & LPA_EF_1000 ) ? 1 : 0;
        !          2001:        half_duplex = ( efab->link_options & LPA_EF_DUPLEX ) ? 0 : 1;
        !          2002:        falcon_gmac_readl ( efab, &reg, GMF_CFG5_REG_MAC );
        !          2003:        EFAB_SET_DWORD_FIELD ( reg, GMF_CFGBYTMODE, bytemode );
        !          2004:        EFAB_SET_DWORD_FIELD ( reg, GMF_CFGHDPLX, half_duplex );
        !          2005:        EFAB_SET_DWORD_FIELD ( reg, GMF_HSTDRPLT64, half_duplex );
        !          2006:        EFAB_SET_DWORD_FIELD ( reg, GMF_HSTFLTRFRMDC_PAUSE, 0 );
        !          2007:        falcon_gmac_writel ( efab, &reg, GMF_CFG5_REG_MAC );
        !          2008:        udelay ( 10 );
        !          2009:        
        !          2010:        /* MAC address */
        !          2011:        EFAB_POPULATE_DWORD_4 ( reg,
        !          2012:                                GM_HWADDR_5, efab->mac_addr[5],
        !          2013:                                GM_HWADDR_4, efab->mac_addr[4],
        !          2014:                                GM_HWADDR_3, efab->mac_addr[3],
        !          2015:                                GM_HWADDR_2, efab->mac_addr[2] );
        !          2016:        falcon_gmac_writel ( efab, &reg, GM_ADR1_REG_MAC );
        !          2017:        udelay ( 10 );
        !          2018:        EFAB_POPULATE_DWORD_2 ( reg,
        !          2019:                                GM_HWADDR_1, efab->mac_addr[1],
        !          2020:                                GM_HWADDR_0, efab->mac_addr[0] );
        !          2021:        falcon_gmac_writel ( efab, &reg, GM_ADR2_REG_MAC );
        !          2022:        udelay ( 10 );
        !          2023: }
        !          2024: 
        !          2025: static int
        !          2026: falcon_init_gmac ( struct efab_nic *efab )
        !          2027: {
        !          2028:        /* Reset the MAC */
        !          2029:        mentormac_reset ( efab );
        !          2030: 
        !          2031:        /* Initialise PHY */
        !          2032:        efab->phy_op->init ( efab );
        !          2033: 
        !          2034:        /* check the link is up */
        !          2035:        if ( !efab->link_up )
        !          2036:                return -EAGAIN;
        !          2037: 
        !          2038:        /* Initialise MAC */
        !          2039:        mentormac_init ( efab );
        !          2040: 
        !          2041:        /* reconfigure the MAC wrapper */
        !          2042:        falcon_reconfigure_mac_wrapper ( efab );
        !          2043: 
        !          2044:        return 0;
        !          2045: }
        !          2046: 
        !          2047: static struct efab_mac_operations falcon_gmac_operations = {
        !          2048:        .init                   = falcon_init_gmac,
        !          2049: };
        !          2050: 
        !          2051: 
        !          2052: /*******************************************************************************
        !          2053:  *
        !          2054:  *
        !          2055:  * XMAC handling
        !          2056:  *
        !          2057:  *
        !          2058:  *******************************************************************************/
        !          2059: 
        !          2060: /**
        !          2061:  * Write dword to a Falcon XMAC register
        !          2062:  *
        !          2063:  */
        !          2064: static void
        !          2065: falcon_xmac_writel ( struct efab_nic *efab, efab_dword_t *value,
        !          2066:                     unsigned int mac_reg )
        !          2067: {
        !          2068:        efab_oword_t temp;
        !          2069: 
        !          2070:        EFAB_POPULATE_OWORD_1 ( temp, FCN_MAC_DATA,
        !          2071:                                EFAB_DWORD_FIELD ( *value, FCN_MAC_DATA ) );
        !          2072:        falcon_write ( efab, &temp,
        !          2073:                       FALCON_XMAC_REG ( efab, mac_reg ) );
        !          2074: }
        !          2075: 
        !          2076: /**
        !          2077:  * Read dword from a Falcon XMAC register
        !          2078:  *
        !          2079:  */
        !          2080: static void
        !          2081: falcon_xmac_readl ( struct efab_nic *efab, efab_dword_t *value,
        !          2082:                    unsigned int mac_reg )
        !          2083: {
        !          2084:        efab_oword_t temp;
        !          2085: 
        !          2086:        falcon_read ( efab, &temp,
        !          2087:                      FALCON_XMAC_REG ( efab, mac_reg ) );
        !          2088:        EFAB_POPULATE_DWORD_1 ( *value, FCN_MAC_DATA,
        !          2089:                                EFAB_OWORD_FIELD ( temp, FCN_MAC_DATA ) );
        !          2090: }
        !          2091: 
        !          2092: /**
        !          2093:  * Configure Falcon XAUI output
        !          2094:  */
        !          2095: static void
        !          2096: falcon_setup_xaui ( struct efab_nic *efab )
        !          2097: {
        !          2098:        efab_dword_t sdctl, txdrv;
        !          2099: 
        !          2100:        falcon_xmac_readl ( efab, &sdctl, FCN_XX_SD_CTL_REG_MAC );
        !          2101:        EFAB_SET_DWORD_FIELD ( sdctl, FCN_XX_HIDRVD, XX_SD_CTL_DRV_DEFAULT );
        !          2102:        EFAB_SET_DWORD_FIELD ( sdctl, FCN_XX_LODRVD, XX_SD_CTL_DRV_DEFAULT );
        !          2103:        EFAB_SET_DWORD_FIELD ( sdctl, FCN_XX_HIDRVC, XX_SD_CTL_DRV_DEFAULT );
        !          2104:        EFAB_SET_DWORD_FIELD ( sdctl, FCN_XX_LODRVC, XX_SD_CTL_DRV_DEFAULT );
        !          2105:        EFAB_SET_DWORD_FIELD ( sdctl, FCN_XX_HIDRVB, XX_SD_CTL_DRV_DEFAULT );
        !          2106:        EFAB_SET_DWORD_FIELD ( sdctl, FCN_XX_LODRVB, XX_SD_CTL_DRV_DEFAULT );
        !          2107:        EFAB_SET_DWORD_FIELD ( sdctl, FCN_XX_HIDRVA, XX_SD_CTL_DRV_DEFAULT );
        !          2108:        EFAB_SET_DWORD_FIELD ( sdctl, FCN_XX_LODRVA, XX_SD_CTL_DRV_DEFAULT );
        !          2109:        falcon_xmac_writel ( efab, &sdctl, FCN_XX_SD_CTL_REG_MAC );
        !          2110: 
        !          2111:        EFAB_POPULATE_DWORD_8 ( txdrv,
        !          2112:                                FCN_XX_DEQD, XX_TXDRV_DEQ_DEFAULT,
        !          2113:                                FCN_XX_DEQC, XX_TXDRV_DEQ_DEFAULT,
        !          2114:                                FCN_XX_DEQB, XX_TXDRV_DEQ_DEFAULT,
        !          2115:                                FCN_XX_DEQA, XX_TXDRV_DEQ_DEFAULT,
        !          2116:                                FCN_XX_DTXD, XX_TXDRV_DTX_DEFAULT,
        !          2117:                                FCN_XX_DTXC, XX_TXDRV_DTX_DEFAULT,
        !          2118:                                FCN_XX_DTXB, XX_TXDRV_DTX_DEFAULT,
        !          2119:                                FCN_XX_DTXA, XX_TXDRV_DTX_DEFAULT);
        !          2120:        falcon_xmac_writel ( efab, &txdrv, FCN_XX_TXDRV_CTL_REG_MAC);
        !          2121: }
        !          2122: 
        !          2123: static int
        !          2124: falcon_xgmii_status ( struct efab_nic *efab )
        !          2125: {
        !          2126:        efab_dword_t reg;
        !          2127: 
        !          2128:        if ( efab->pci_revision  < FALCON_REV_B0 )
        !          2129:                return 1;
        !          2130:        /* The ISR latches, so clear it and re-read */
        !          2131:        falcon_xmac_readl ( efab, &reg, FCN_XM_MGT_INT_REG_MAC_B0 );
        !          2132:        falcon_xmac_readl ( efab, &reg, FCN_XM_MGT_INT_REG_MAC_B0 );
        !          2133: 
        !          2134:        if ( EFAB_DWORD_FIELD ( reg, FCN_XM_LCLFLT ) ||
        !          2135:             EFAB_DWORD_FIELD ( reg, FCN_XM_RMTFLT ) ) {
        !          2136:                EFAB_TRACE ( "MGT_INT: "EFAB_DWORD_FMT"\n",
        !          2137:                             EFAB_DWORD_VAL ( reg ) );
        !          2138:                return 0;
        !          2139:        }
        !          2140: 
        !          2141:        return 1;
        !          2142: }
        !          2143: 
        !          2144: static void
        !          2145: falcon_mask_status_intr ( struct efab_nic *efab, int enable )
        !          2146: {
        !          2147:        efab_dword_t reg;
        !          2148: 
        !          2149:        if ( efab->pci_revision  < FALCON_REV_B0 )
        !          2150:                return;
        !          2151: 
        !          2152:        /* Flush the ISR */
        !          2153:        if ( enable )
        !          2154:                falcon_xmac_readl ( efab, &reg, FCN_XM_MGT_INT_REG_MAC_B0 );
        !          2155: 
        !          2156:        EFAB_POPULATE_DWORD_2 ( reg,
        !          2157:                                FCN_XM_MSK_RMTFLT, !enable,
        !          2158:                                FCN_XM_MSK_LCLFLT, !enable);
        !          2159:        falcon_xmac_readl ( efab, &reg, FCN_XM_MGT_INT_MSK_REG_MAC_B0 );
        !          2160: }
        !          2161: 
        !          2162: /**
        !          2163:  * Reset 10G MAC connected to port
        !          2164:  *
        !          2165:  */
        !          2166: static int
        !          2167: falcon_reset_xmac ( struct efab_nic *efab )
        !          2168: {
        !          2169:        efab_dword_t reg;
        !          2170:        int count;
        !          2171: 
        !          2172:        EFAB_POPULATE_DWORD_1 ( reg, FCN_XM_CORE_RST, 1 );
        !          2173:        falcon_xmac_writel ( efab, &reg, FCN_XM_GLB_CFG_REG_MAC );
        !          2174: 
        !          2175:        for ( count = 0 ; count < 1000 ; count++ ) {
        !          2176:                udelay ( 10 );
        !          2177:                falcon_xmac_readl ( efab, &reg,
        !          2178:                                    FCN_XM_GLB_CFG_REG_MAC );
        !          2179:                if ( EFAB_DWORD_FIELD ( reg, FCN_XM_CORE_RST ) == 0 )
        !          2180:                        return 0;
        !          2181:        }
        !          2182:        return -ETIMEDOUT;
        !          2183: }
        !          2184: 
        !          2185: 
        !          2186: static int
        !          2187: falcon_reset_xaui ( struct efab_nic *efab )
        !          2188: {
        !          2189:        efab_dword_t reg;
        !          2190:        int count;
        !          2191: 
        !          2192:        if (!efab->is_asic)
        !          2193:                return 0;
        !          2194: 
        !          2195:        EFAB_POPULATE_DWORD_1 ( reg, FCN_XX_RST_XX_EN, 1 );
        !          2196:        falcon_xmac_writel ( efab, &reg, FCN_XX_PWR_RST_REG_MAC );
        !          2197: 
        !          2198:        /* Give some time for the link to establish */
        !          2199:        for (count = 0; count < 1000; count++) { /* wait upto 10ms */
        !          2200:                falcon_xmac_readl ( efab, &reg, FCN_XX_PWR_RST_REG_MAC );
        !          2201:                if ( EFAB_DWORD_FIELD ( reg, FCN_XX_RST_XX_EN ) == 0 ) {
        !          2202:                        falcon_setup_xaui ( efab );
        !          2203:                        return 0;
        !          2204:                }
        !          2205:                udelay(10);
        !          2206:        }
        !          2207:        EFAB_ERR ( "timed out waiting for XAUI/XGXS reset\n" );
        !          2208:        return -ETIMEDOUT;
        !          2209: }
        !          2210: 
        !          2211: static int
        !          2212: falcon_xaui_link_ok ( struct efab_nic *efab )
        !          2213: {
        !          2214:        efab_dword_t reg;
        !          2215:        int align_done, lane_status, sync;
        !          2216:        int has_phyxs;
        !          2217:        int link_ok = 1;
        !          2218: 
        !          2219:        /* Read Falcon XAUI side */
        !          2220:        if ( efab->is_asic ) {
        !          2221:                /* Read link status */
        !          2222:                falcon_xmac_readl ( efab, &reg, FCN_XX_CORE_STAT_REG_MAC );
        !          2223:                align_done = EFAB_DWORD_FIELD ( reg, FCN_XX_ALIGN_DONE );
        !          2224: 
        !          2225:                sync = EFAB_DWORD_FIELD ( reg, FCN_XX_SYNC_STAT );
        !          2226:                sync = ( sync == FCN_XX_SYNC_STAT_DECODE_SYNCED );
        !          2227:                
        !          2228:                link_ok = align_done && sync;
        !          2229:        }
        !          2230: 
        !          2231:        /* Clear link status ready for next read */
        !          2232:        EFAB_SET_DWORD_FIELD ( reg, FCN_XX_COMMA_DET, FCN_XX_COMMA_DET_RESET );
        !          2233:        EFAB_SET_DWORD_FIELD ( reg, FCN_XX_CHARERR, FCN_XX_CHARERR_RESET);
        !          2234:        EFAB_SET_DWORD_FIELD ( reg, FCN_XX_DISPERR, FCN_XX_DISPERR_RESET);
        !          2235:        falcon_xmac_writel ( efab, &reg, FCN_XX_CORE_STAT_REG_MAC );
        !          2236: 
        !          2237:        has_phyxs = ( efab->phy_op->mmds & ( 1 << MDIO_MMD_PHYXS ) );
        !          2238:        if ( link_ok && has_phyxs ) {
        !          2239:                lane_status = falcon_mdio_read ( efab, MDIO_MMD_PHYXS,
        !          2240:                                                 MDIO_PHYXS_LANE_STATE );
        !          2241:                link_ok = ( lane_status & ( 1 << MDIO_PHYXS_LANE_ALIGNED_LBN ) );
        !          2242: 
        !          2243:                if (!link_ok )
        !          2244:                        EFAB_LOG ( "XGXS lane status: %x\n", lane_status );
        !          2245:        }
        !          2246: 
        !          2247:        return link_ok;
        !          2248: }
        !          2249: 
        !          2250: /**
        !          2251:  * Initialise XMAC
        !          2252:  *
        !          2253:  */
        !          2254: static void
        !          2255: falcon_reconfigure_xmac ( struct efab_nic *efab )
        !          2256: {
        !          2257:        efab_dword_t reg;
        !          2258:        int max_frame_len;
        !          2259: 
        !          2260:        /* Configure MAC - cut-thru mode is hard wired on */
        !          2261:        EFAB_POPULATE_DWORD_3 ( reg,
        !          2262:                                FCN_XM_RX_JUMBO_MODE, 1,
        !          2263:                                FCN_XM_TX_STAT_EN, 1,
        !          2264:                                FCN_XM_RX_STAT_EN, 1);
        !          2265:        falcon_xmac_writel ( efab, &reg, FCN_XM_GLB_CFG_REG_MAC );
        !          2266: 
        !          2267:        /* Configure TX */
        !          2268:        EFAB_POPULATE_DWORD_6 ( reg, 
        !          2269:                                FCN_XM_TXEN, 1,
        !          2270:                                FCN_XM_TX_PRMBL, 1,
        !          2271:                                FCN_XM_AUTO_PAD, 1,
        !          2272:                                FCN_XM_TXCRC, 1,
        !          2273:                                FCN_XM_FCNTL, 1,
        !          2274:                                FCN_XM_IPG, 0x3 );
        !          2275:        falcon_xmac_writel ( efab, &reg, FCN_XM_TX_CFG_REG_MAC );
        !          2276: 
        !          2277:        /* Configure RX */
        !          2278:        EFAB_POPULATE_DWORD_4 ( reg,
        !          2279:                                FCN_XM_RXEN, 1,
        !          2280:                                FCN_XM_AUTO_DEPAD, 0,
        !          2281:                                FCN_XM_ACPT_ALL_MCAST, 1,
        !          2282:                                FCN_XM_PASS_CRC_ERR, 1 );
        !          2283:        falcon_xmac_writel ( efab, &reg, FCN_XM_RX_CFG_REG_MAC );
        !          2284: 
        !          2285:        /* Set frame length */
        !          2286:        max_frame_len = EFAB_MAX_FRAME_LEN ( ETH_FRAME_LEN );
        !          2287:        EFAB_POPULATE_DWORD_1 ( reg,
        !          2288:                                FCN_XM_MAX_RX_FRM_SIZE, max_frame_len );
        !          2289:        falcon_xmac_writel ( efab, &reg, FCN_XM_RX_PARAM_REG_MAC );
        !          2290:        EFAB_POPULATE_DWORD_2 ( reg,
        !          2291:                                FCN_XM_MAX_TX_FRM_SIZE, max_frame_len,
        !          2292:                                FCN_XM_TX_JUMBO_MODE, 1 );
        !          2293:        falcon_xmac_writel ( efab, &reg, FCN_XM_TX_PARAM_REG_MAC );
        !          2294: 
        !          2295:        /* Enable flow control receipt */
        !          2296:        EFAB_POPULATE_DWORD_2 ( reg,
        !          2297:                                FCN_XM_PAUSE_TIME, 0xfffe,
        !          2298:                                FCN_XM_DIS_FCNTL, 0 );
        !          2299:        falcon_xmac_writel ( efab, &reg, FCN_XM_FC_REG_MAC );
        !          2300: 
        !          2301:        /* Set MAC address */
        !          2302:        EFAB_POPULATE_DWORD_4 ( reg,
        !          2303:                                FCN_XM_ADR_0, efab->mac_addr[0],
        !          2304:                                FCN_XM_ADR_1, efab->mac_addr[1],
        !          2305:                                FCN_XM_ADR_2, efab->mac_addr[2],
        !          2306:                                FCN_XM_ADR_3, efab->mac_addr[3] );
        !          2307:        falcon_xmac_writel ( efab, &reg, FCN_XM_ADR_LO_REG_MAC );
        !          2308:        EFAB_POPULATE_DWORD_2 ( reg,
        !          2309:                                FCN_XM_ADR_4, efab->mac_addr[4],
        !          2310:                                FCN_XM_ADR_5, efab->mac_addr[5] );
        !          2311:        falcon_xmac_writel ( efab, &reg, FCN_XM_ADR_HI_REG_MAC );
        !          2312: }
        !          2313: 
        !          2314: static int
        !          2315: falcon_init_xmac ( struct efab_nic *efab )
        !          2316: {
        !          2317:        int count, rc;
        !          2318: 
        !          2319:        /* Mask the PHY management interrupt */
        !          2320:        falcon_mask_status_intr ( efab, 0 );
        !          2321: 
        !          2322:        /* Initialise the PHY to instantiate the clock. */
        !          2323:        rc = efab->phy_op->init ( efab );
        !          2324:        if ( rc ) {
        !          2325:                EFAB_ERR ( "unable to initialise PHY\n" );
        !          2326:                goto fail1;
        !          2327:        }
        !          2328: 
        !          2329:        falcon_reset_xaui ( efab );
        !          2330: 
        !          2331:        /* Give the PHY and MAC time to faff */
        !          2332:        mdelay ( 100 );
        !          2333: 
        !          2334:        /* Reset and reconfigure the XMAC */
        !          2335:        rc = falcon_reset_xmac ( efab );
        !          2336:        if ( rc )
        !          2337:                goto fail2;
        !          2338:        falcon_reconfigure_xmac ( efab );
        !          2339:        falcon_reconfigure_mac_wrapper ( efab );
        !          2340:        /**
        !          2341:         * Now wait for the link to come up. This may take a while
        !          2342:         * for some slower PHY's.
        !          2343:         */
        !          2344:        for (count=0; count<50; count++) {
        !          2345:                int link_ok = 1;
        !          2346: 
        !          2347:                /* Wait a while for the link to come up. */
        !          2348:                mdelay ( 100 );
        !          2349:                if ((count % 5) == 0)
        !          2350:                        putchar ( '.' );
        !          2351: 
        !          2352:                /* Does the PHY think the wire-side link is up? */
        !          2353:                link_ok = mdio_clause45_links_ok ( efab );
        !          2354:                /* Ensure the XAUI link to the PHY is good */
        !          2355:                if ( link_ok ) {
        !          2356:                        link_ok = falcon_xaui_link_ok ( efab );
        !          2357:                        if ( !link_ok )
        !          2358:                                falcon_reset_xaui ( efab );
        !          2359:                }
        !          2360: 
        !          2361:                /* Check fault indication */
        !          2362:                if ( link_ok )
        !          2363:                        link_ok = falcon_xgmii_status ( efab );
        !          2364: 
        !          2365:                efab->link_up = link_ok;
        !          2366:                if ( link_ok ) {
        !          2367:                        /* unmask the status interrupt */
        !          2368:                        falcon_mask_status_intr ( efab, 1 );
        !          2369:                        return 0;
        !          2370:                }
        !          2371:        }
        !          2372: 
        !          2373:        /* Link failed to come up, but initialisation was fine. */
        !          2374:        rc = -ETIMEDOUT;
        !          2375: 
        !          2376: fail2:
        !          2377: fail1:
        !          2378:        return rc;
        !          2379: }
        !          2380: 
        !          2381: static struct efab_mac_operations falcon_xmac_operations = {
        !          2382:        .init                   = falcon_init_xmac,
        !          2383: };
        !          2384: 
        !          2385: /*******************************************************************************
        !          2386:  *
        !          2387:  *
        !          2388:  * Null PHY handling
        !          2389:  *
        !          2390:  *
        !          2391:  *******************************************************************************/
        !          2392: 
        !          2393: static int
        !          2394: falcon_xaui_phy_init ( struct efab_nic *efab )
        !          2395: {
        !          2396:        /* CX4 is always 10000FD only */
        !          2397:        efab->link_options = LPA_EF_10000FULL;
        !          2398: 
        !          2399:        /* There is no PHY! */
        !          2400:        return 0;
        !          2401: }
        !          2402: 
        !          2403: static struct efab_phy_operations falcon_xaui_phy_ops = {
        !          2404:        .init                   = falcon_xaui_phy_init,
        !          2405:        .mmds                   = 0,
        !          2406: };
        !          2407: 
        !          2408: 
        !          2409: /*******************************************************************************
        !          2410:  *
        !          2411:  *
        !          2412:  * Alaska PHY
        !          2413:  *
        !          2414:  *
        !          2415:  *******************************************************************************/
        !          2416: 
        !          2417: /**
        !          2418:  * Initialise Alaska PHY
        !          2419:  *
        !          2420:  */
        !          2421: static int
        !          2422: alaska_init ( struct efab_nic *efab )
        !          2423: {
        !          2424:        unsigned int advertised, lpa;
        !          2425: 
        !          2426:        /* Read link up status */
        !          2427:        efab->link_up = gmii_link_ok ( efab );
        !          2428: 
        !          2429:        if ( ! efab->link_up )
        !          2430:                return -EIO;
        !          2431: 
        !          2432:        /* Determine link options from PHY. */
        !          2433:        advertised = gmii_autoneg_advertised ( efab );
        !          2434:        lpa = gmii_autoneg_lpa ( efab );
        !          2435:        efab->link_options = gmii_nway_result ( advertised & lpa );
        !          2436: 
        !          2437:        return 0;
        !          2438: }
        !          2439: 
        !          2440: static struct efab_phy_operations falcon_alaska_phy_ops = {
        !          2441:        .init           = alaska_init,
        !          2442: };
        !          2443: 
        !          2444: /*******************************************************************************
        !          2445:  *
        !          2446:  *
        !          2447:  * xfp
        !          2448:  *
        !          2449:  *
        !          2450:  *******************************************************************************/
        !          2451: 
        !          2452: #define XFP_REQUIRED_DEVS ( MDIO_MMDREG_DEVS0_PCS    |         \
        !          2453:                            MDIO_MMDREG_DEVS0_PMAPMD |          \
        !          2454:                            MDIO_MMDREG_DEVS0_PHYXS )
        !          2455: 
        !          2456: static int
        !          2457: falcon_xfp_phy_init ( struct efab_nic *efab )
        !          2458: {
        !          2459:        int rc;
        !          2460: 
        !          2461:        /* Optical link is always 10000FD only */
        !          2462:        efab->link_options = LPA_EF_10000FULL;
        !          2463: 
        !          2464:        /* Reset the PHY */
        !          2465:        rc = mdio_clause45_reset_mmd ( efab, MDIO_MMD_PHYXS );
        !          2466:        if ( rc )
        !          2467:                return rc;
        !          2468: 
        !          2469:        return 0;
        !          2470: }
        !          2471: 
        !          2472: static struct efab_phy_operations falcon_xfp_phy_ops = {
        !          2473:        .init                   = falcon_xfp_phy_init,
        !          2474:        .mmds                   = XFP_REQUIRED_DEVS,
        !          2475: };
        !          2476: 
        !          2477: /*******************************************************************************
        !          2478:  *
        !          2479:  *
        !          2480:  * txc43128
        !          2481:  *
        !          2482:  *
        !          2483:  *******************************************************************************/
        !          2484: 
        !          2485: /* Command register */
        !          2486: #define TXC_GLRGS_GLCMD                (0xc004)
        !          2487: #define TXC_GLCMD_LMTSWRST_LBN (14)
        !          2488: 
        !          2489: /* Amplitude on lanes 0+1, 2+3 */
        !          2490: #define  TXC_ALRGS_ATXAMP0     (0xc041)
        !          2491: #define  TXC_ALRGS_ATXAMP1     (0xc042)
        !          2492: /* Bit position of value for lane 0+2, 1+3 */
        !          2493: #define TXC_ATXAMP_LANE02_LBN  (3)
        !          2494: #define TXC_ATXAMP_LANE13_LBN  (11)
        !          2495: 
        !          2496: #define TXC_ATXAMP_1280_mV     (0)
        !          2497: #define TXC_ATXAMP_1200_mV     (8)
        !          2498: #define TXC_ATXAMP_1120_mV     (12)
        !          2499: #define TXC_ATXAMP_1060_mV     (14)
        !          2500: #define TXC_ATXAMP_0820_mV     (25)
        !          2501: #define TXC_ATXAMP_0720_mV     (26)
        !          2502: #define TXC_ATXAMP_0580_mV     (27)
        !          2503: #define TXC_ATXAMP_0440_mV     (28)
        !          2504: 
        !          2505: #define TXC_ATXAMP_0820_BOTH   ( (TXC_ATXAMP_0820_mV << TXC_ATXAMP_LANE02_LBN) | \
        !          2506:                                  (TXC_ATXAMP_0820_mV << TXC_ATXAMP_LANE13_LBN) )
        !          2507: 
        !          2508: #define TXC_ATXAMP_DEFAULT     (0x6060) /* From databook */
        !          2509: 
        !          2510: /* Preemphasis on lanes 0+1, 2+3 */
        !          2511: #define  TXC_ALRGS_ATXPRE0     (0xc043)
        !          2512: #define  TXC_ALRGS_ATXPRE1     (0xc044)
        !          2513: 
        !          2514: #define TXC_ATXPRE_NONE (0)
        !          2515: #define TXC_ATXPRE_DEFAULT     (0x1010) /* From databook */
        !          2516: 
        !          2517: #define TXC_REQUIRED_DEVS ( MDIO_MMDREG_DEVS0_PCS    |        \
        !          2518:                            MDIO_MMDREG_DEVS0_PMAPMD |         \
        !          2519:                            MDIO_MMDREG_DEVS0_PHYXS )
        !          2520: 
        !          2521: static int
        !          2522: falcon_txc_logic_reset ( struct efab_nic *efab )
        !          2523: {
        !          2524:        int val;
        !          2525:        int tries = 50;
        !          2526: 
        !          2527:        val = falcon_mdio_read ( efab, MDIO_MMD_PCS, TXC_GLRGS_GLCMD );
        !          2528:        val |= (1 << TXC_GLCMD_LMTSWRST_LBN);
        !          2529:        falcon_mdio_write ( efab, MDIO_MMD_PCS, TXC_GLRGS_GLCMD, val );
        !          2530: 
        !          2531:        while ( tries--) {
        !          2532:                val = falcon_mdio_read ( efab, MDIO_MMD_PCS, TXC_GLRGS_GLCMD );
        !          2533:                if ( ~val & ( 1 << TXC_GLCMD_LMTSWRST_LBN ) )
        !          2534:                        return 0;
        !          2535:                udelay(1);
        !          2536:        }
        !          2537: 
        !          2538:        EFAB_ERR ( "logic reset failed\n" );
        !          2539: 
        !          2540:        return -ETIMEDOUT;
        !          2541: }
        !          2542: 
        !          2543: static int
        !          2544: falcon_txc_phy_init ( struct efab_nic *efab )
        !          2545: {
        !          2546:        int rc;
        !          2547: 
        !          2548:        /* CX4 is always 10000FD only */
        !          2549:        efab->link_options = LPA_EF_10000FULL;
        !          2550: 
        !          2551:        /* reset the phy */
        !          2552:        rc = mdio_clause45_reset_mmd ( efab, MDIO_MMD_PMAPMD );
        !          2553:        if ( rc )
        !          2554:                goto fail1;
        !          2555: 
        !          2556:        rc = mdio_clause45_check_mmds ( efab );
        !          2557:        if ( rc )
        !          2558:                goto fail2;
        !          2559: 
        !          2560:        /* Turn amplitude down and preemphasis off on the host side
        !          2561:         * (PHY<->MAC) as this is believed less likely to upset falcon
        !          2562:         * and no adverse effects have been noted. It probably also 
        !          2563:         * saves a picowatt or two */
        !          2564: 
        !          2565:        /* Turn off preemphasis */
        !          2566:        falcon_mdio_write ( efab, MDIO_MMD_PHYXS, TXC_ALRGS_ATXPRE0,
        !          2567:                            TXC_ATXPRE_NONE );
        !          2568:        falcon_mdio_write ( efab, MDIO_MMD_PHYXS, TXC_ALRGS_ATXPRE1,
        !          2569:                            TXC_ATXPRE_NONE );
        !          2570: 
        !          2571:        /* Turn down the amplitude */
        !          2572:        falcon_mdio_write ( efab, MDIO_MMD_PHYXS, TXC_ALRGS_ATXAMP0,
        !          2573:                            TXC_ATXAMP_0820_BOTH );
        !          2574:        falcon_mdio_write ( efab, MDIO_MMD_PHYXS, TXC_ALRGS_ATXAMP1,
        !          2575:                            TXC_ATXAMP_0820_BOTH );
        !          2576: 
        !          2577:        /* Set the line side amplitude and preemphasis to the databook
        !          2578:         * defaults as an erratum causes them to be 0 on at least some
        !          2579:         * PHY rev.s */
        !          2580:        falcon_mdio_write ( efab, MDIO_MMD_PMAPMD, TXC_ALRGS_ATXPRE0,
        !          2581:                            TXC_ATXPRE_DEFAULT );
        !          2582:        falcon_mdio_write ( efab, MDIO_MMD_PMAPMD, TXC_ALRGS_ATXPRE1,
        !          2583:                            TXC_ATXPRE_DEFAULT );
        !          2584:        falcon_mdio_write ( efab, MDIO_MMD_PMAPMD, TXC_ALRGS_ATXAMP0,
        !          2585:                            TXC_ATXAMP_DEFAULT );
        !          2586:        falcon_mdio_write ( efab, MDIO_MMD_PMAPMD, TXC_ALRGS_ATXAMP1,
        !          2587:                            TXC_ATXAMP_DEFAULT );
        !          2588: 
        !          2589:        rc = falcon_txc_logic_reset ( efab );
        !          2590:        if ( rc )
        !          2591:                goto fail3;
        !          2592: 
        !          2593:        return 0;
        !          2594: 
        !          2595: fail3:
        !          2596: fail2:
        !          2597: fail1:
        !          2598:        return rc;
        !          2599: }
        !          2600: 
        !          2601: static struct efab_phy_operations falcon_txc_phy_ops = {
        !          2602:        .init                   = falcon_txc_phy_init,
        !          2603:        .mmds                   = TXC_REQUIRED_DEVS,
        !          2604: };
        !          2605: 
        !          2606: /*******************************************************************************
        !          2607:  *
        !          2608:  *
        !          2609:  * tenxpress
        !          2610:  *
        !          2611:  *
        !          2612:  *******************************************************************************/
        !          2613: 
        !          2614: 
        !          2615: #define TENXPRESS_REQUIRED_DEVS ( MDIO_MMDREG_DEVS0_PMAPMD |   \
        !          2616:                                  MDIO_MMDREG_DEVS0_PCS    |    \
        !          2617:                                  MDIO_MMDREG_DEVS0_PHYXS )
        !          2618: 
        !          2619: #define        PCS_TEST_SELECT_REG 0xd807      /* PRM 10.5.8 */
        !          2620: #define        CLK312_EN_LBN 3
        !          2621: #define        CLK312_EN_WIDTH 1
        !          2622: 
        !          2623: #define PCS_CLOCK_CTRL_REG 0xd801
        !          2624: #define PLL312_RST_N_LBN 2
        !          2625: 
        !          2626: /* Special Software reset register */
        !          2627: #define PMA_PMD_EXT_CTRL_REG 49152
        !          2628: #define PMA_PMD_EXT_SSR_LBN 15
        !          2629: 
        !          2630: /* Boot status register */
        !          2631: #define PCS_BOOT_STATUS_REG    0xd000
        !          2632: #define PCS_BOOT_FATAL_ERR_LBN 0
        !          2633: #define PCS_BOOT_PROGRESS_LBN  1
        !          2634: #define PCS_BOOT_PROGRESS_WIDTH        2
        !          2635: #define PCS_BOOT_COMPLETE_LBN  3
        !          2636: 
        !          2637: #define PCS_SOFT_RST2_REG 0xd806
        !          2638: #define SERDES_RST_N_LBN 13
        !          2639: #define XGXS_RST_N_LBN 12
        !          2640: 
        !          2641: static int
        !          2642: falcon_tenxpress_check_c11 ( struct efab_nic *efab )
        !          2643: {
        !          2644:        int count;
        !          2645:        uint32_t boot_stat;
        !          2646: 
        !          2647:        /* Check that the C11 CPU has booted */
        !          2648:        for (count=0; count<10; count++) {
        !          2649:                boot_stat = falcon_mdio_read ( efab, MDIO_MMD_PCS,
        !          2650:                                               PCS_BOOT_STATUS_REG );
        !          2651:                if ( boot_stat & ( 1 << PCS_BOOT_COMPLETE_LBN ) )
        !          2652:                        return 0;
        !          2653: 
        !          2654:                udelay(10);
        !          2655:        }
        !          2656: 
        !          2657:        EFAB_ERR ( "C11 failed to boot\n" );
        !          2658:        return -ETIMEDOUT;
        !          2659: }
        !          2660: 
        !          2661: static int
        !          2662: falcon_tenxpress_phy_init ( struct efab_nic *efab )
        !          2663: {
        !          2664:        int rc, reg;
        !          2665: 
        !          2666:        /* 10XPRESS is always 10000FD (at the moment) */
        !          2667:        efab->link_options = LPA_EF_10000FULL;
        !          2668: 
        !          2669:        /* Wait for the blocks to come out of reset */
        !          2670:        rc = mdio_clause45_wait_reset_mmds ( efab );
        !          2671:        if ( rc )
        !          2672:                goto fail1;
        !          2673: 
        !          2674:        rc = mdio_clause45_check_mmds ( efab );
        !          2675:        if ( rc )
        !          2676:                goto fail2;
        !          2677: 
        !          2678:        /* Turn on the clock  */
        !          2679:        reg = (1 << CLK312_EN_LBN);
        !          2680:        falcon_mdio_write ( efab, MDIO_MMD_PCS, PCS_TEST_SELECT_REG, reg);
        !          2681: 
        !          2682:        /* Wait 200ms for the PHY to boot */
        !          2683:        mdelay(200);
        !          2684: 
        !          2685:        rc = falcon_tenxpress_check_c11 ( efab );
        !          2686:        if ( rc )
        !          2687:                goto fail3;
        !          2688: 
        !          2689:        return 0;
        !          2690: 
        !          2691: fail3:
        !          2692: fail2:
        !          2693: fail1:
        !          2694:        return rc;
        !          2695: }
        !          2696: 
        !          2697: static struct efab_phy_operations falcon_tenxpress_phy_ops = {
        !          2698:        .init                   = falcon_tenxpress_phy_init,
        !          2699:        .mmds                   = TENXPRESS_REQUIRED_DEVS,
        !          2700: };
        !          2701: 
        !          2702: /*******************************************************************************
        !          2703:  *
        !          2704:  *
        !          2705:  * PM8358
        !          2706:  *
        !          2707:  *
        !          2708:  *******************************************************************************/
        !          2709: 
        !          2710: /* The PM8358 just presents a DTE XS */
        !          2711: #define PM8358_REQUIRED_DEVS (MDIO_MMDREG_DEVS0_DTEXS)
        !          2712: 
        !          2713: /* PHY-specific definitions */
        !          2714: /* Master ID and Global Performance Monitor Update */
        !          2715: #define PMC_MASTER_REG (0xd000)
        !          2716: /* Analog Tx Rx settings under software control */
        !          2717: #define PMC_MASTER_ANLG_CTRL (1<< 11)
        !          2718: 
        !          2719: /* Master Configuration register 2 */
        !          2720: #define PMC_MCONF2_REG (0xd002)
        !          2721: /* Drive Tx off centre of data eye (1) vs. clock edge (0) */
        !          2722: #define        PMC_MCONF2_TEDGE (1 << 2) 
        !          2723: /* Drive Rx off centre of data eye (1) vs. clock edge (0) */
        !          2724: #define PMC_MCONF2_REDGE (1 << 3)
        !          2725: 
        !          2726: /* Analog Rx settings */
        !          2727: #define PMC_ANALOG_RX_CFG0   (0xd025)
        !          2728: #define PMC_ANALOG_RX_CFG1   (0xd02d)
        !          2729: #define PMC_ANALOG_RX_CFG2   (0xd035)
        !          2730: #define PMC_ANALOG_RX_CFG3   (0xd03d)
        !          2731: 
        !          2732: 
        !          2733: #define PMC_ANALOG_RX_TERM     (1 << 15) /* Bit 15 of RX CFG: 0 for 100 ohms float,
        !          2734:                                            1 for 50 to 1.2V */
        !          2735: #define PMC_ANALOG_RX_EQ_MASK (3 << 8)
        !          2736: #define PMC_ANALOG_RX_EQ_NONE (0 << 8)
        !          2737: #define PMC_ANALOG_RX_EQ_HALF (1 << 8)
        !          2738: #define PMC_ANALOG_RX_EQ_FULL (2 << 8)
        !          2739: #define PMC_ANALOG_RX_EQ_RSVD (3 << 8)
        !          2740: 
        !          2741: static int
        !          2742: falcon_pm8358_phy_init ( struct efab_nic *efab )
        !          2743: {
        !          2744:        int rc, reg, i;
        !          2745: 
        !          2746:        /* This is a XAUI retimer part */
        !          2747:        efab->link_options = LPA_EF_10000FULL;
        !          2748: 
        !          2749:        rc = mdio_clause45_reset_mmd ( efab, MDIO_MMDREG_DEVS0_DTEXS );
        !          2750:        if ( rc )
        !          2751:                return rc;
        !          2752:        
        !          2753:        /* Enable software control of analogue settings */
        !          2754:        reg = falcon_mdio_read ( efab, MDIO_MMD_DTEXS,  PMC_MASTER_REG );
        !          2755:        reg |= PMC_MASTER_ANLG_CTRL;
        !          2756:        falcon_mdio_write ( efab, MDIO_MMD_DTEXS, PMC_MASTER_REG, reg );
        !          2757: 
        !          2758:        /* Turn rx eq on for all channels */
        !          2759:        for (i=0; i< 3; i++) {
        !          2760:                /* The analog CFG registers are evenly spaced 8 apart */
        !          2761:                uint16_t addr = PMC_ANALOG_RX_CFG0 + 8*i;
        !          2762:                reg = falcon_mdio_read ( efab, MDIO_MMD_DTEXS, addr );
        !          2763:                reg = ( reg & ~PMC_ANALOG_RX_EQ_MASK ) | PMC_ANALOG_RX_EQ_FULL;
        !          2764:                falcon_mdio_write ( efab, MDIO_MMD_DTEXS, addr, reg );
        !          2765:        }
        !          2766: 
        !          2767:        /* Set TEDGE, clear REDGE */
        !          2768:        reg = falcon_mdio_read ( efab, MDIO_MMD_DTEXS, PMC_MCONF2_REG );
        !          2769:        reg = ( reg & ~PMC_MCONF2_REDGE) | PMC_MCONF2_TEDGE;
        !          2770:        falcon_mdio_write ( efab, MDIO_MMD_DTEXS, PMC_MCONF2_REG, reg );
        !          2771: 
        !          2772:        return 0;
        !          2773: }
        !          2774: 
        !          2775: static struct efab_phy_operations falcon_pm8358_phy_ops = {
        !          2776:        .init                   = falcon_pm8358_phy_init,
        !          2777:        .mmds                   = PM8358_REQUIRED_DEVS,
        !          2778: };
        !          2779: 
        !          2780: /*******************************************************************************
        !          2781:  *
        !          2782:  *
        !          2783:  * SFE4001 support
        !          2784:  *
        !          2785:  *
        !          2786:  *******************************************************************************/
        !          2787: 
        !          2788: #define MAX_TEMP_THRESH 90
        !          2789: 
        !          2790: /* I2C Expander */
        !          2791: #define PCA9539 0x74
        !          2792: 
        !          2793: #define P0_IN 0x00
        !          2794: #define P0_OUT 0x02
        !          2795: #define P0_CONFIG 0x06
        !          2796: 
        !          2797: #define P0_EN_1V0X_LBN 0
        !          2798: #define P0_EN_1V0X_WIDTH 1
        !          2799: #define P0_EN_1V2_LBN 1
        !          2800: #define P0_EN_1V2_WIDTH 1
        !          2801: #define P0_EN_2V5_LBN 2
        !          2802: #define P0_EN_2V5_WIDTH 1
        !          2803: #define P0_EN_3V3X_LBN 3
        !          2804: #define P0_EN_3V3X_WIDTH 1
        !          2805: #define P0_EN_5V_LBN 4
        !          2806: #define P0_EN_5V_WIDTH 1
        !          2807: #define P0_X_TRST_LBN 6
        !          2808: #define P0_X_TRST_WIDTH 1
        !          2809: 
        !          2810: #define P1_IN 0x01
        !          2811: #define P1_CONFIG 0x07
        !          2812: 
        !          2813: #define P1_AFE_PWD_LBN 0
        !          2814: #define P1_AFE_PWD_WIDTH 1
        !          2815: #define P1_DSP_PWD25_LBN 1
        !          2816: #define P1_DSP_PWD25_WIDTH 1
        !          2817: #define P1_SPARE_LBN 4
        !          2818: #define P1_SPARE_WIDTH 4
        !          2819: 
        !          2820: /* Temperature Sensor */
        !          2821: #define MAX6647        0x4e
        !          2822: 
        !          2823: #define RSL    0x02
        !          2824: #define RLHN   0x05
        !          2825: #define WLHO   0x0b
        !          2826: 
        !          2827: static struct i2c_device i2c_pca9539 = {
        !          2828:        .dev_addr = PCA9539,
        !          2829:        .dev_addr_len = 1,
        !          2830:        .word_addr_len = 1,
        !          2831: };
        !          2832: 
        !          2833: 
        !          2834: static struct i2c_device i2c_max6647 = {
        !          2835:        .dev_addr = MAX6647,
        !          2836:        .dev_addr_len = 1,
        !          2837:        .word_addr_len = 1,
        !          2838: };
        !          2839: 
        !          2840: static int
        !          2841: sfe4001_init ( struct efab_nic *efab )
        !          2842: {
        !          2843:        struct i2c_interface *i2c = &efab->i2c_bb.i2c;
        !          2844:        efab_dword_t reg;
        !          2845:        uint8_t in, cfg, out;
        !          2846:        int count, rc;
        !          2847: 
        !          2848:        EFAB_LOG ( "Initialise SFE4001 board\n" );
        !          2849: 
        !          2850:        /* Ensure XGXS and XAUI SerDes are held in reset */
        !          2851:        EFAB_POPULATE_DWORD_7 ( reg,
        !          2852:                                FCN_XX_PWRDNA_EN, 1,
        !          2853:                                FCN_XX_PWRDNB_EN, 1,
        !          2854:                                FCN_XX_RSTPLLAB_EN, 1,
        !          2855:                                FCN_XX_RESETA_EN, 1,
        !          2856:                                FCN_XX_RESETB_EN, 1,
        !          2857:                                FCN_XX_RSTXGXSRX_EN, 1,
        !          2858:                                FCN_XX_RSTXGXSTX_EN, 1 );
        !          2859:        falcon_xmac_writel ( efab, &reg, FCN_XX_PWR_RST_REG_MAC);
        !          2860:        udelay(10);
        !          2861: 
        !          2862:        /* Set DSP over-temperature alert threshold */
        !          2863:        cfg = MAX_TEMP_THRESH;
        !          2864:        rc = i2c->write ( i2c, &i2c_max6647, WLHO, &cfg, EFAB_BYTE );
        !          2865:        if ( rc )
        !          2866:                goto fail1;
        !          2867: 
        !          2868:        /* Read it back and verify */
        !          2869:        rc = i2c->read ( i2c, &i2c_max6647, RLHN, &in, EFAB_BYTE );
        !          2870:        if ( rc )
        !          2871:                goto fail2;
        !          2872: 
        !          2873:        if ( in != MAX_TEMP_THRESH ) {
        !          2874:                EFAB_ERR ( "Unable to verify MAX6647 limit (requested=%d "
        !          2875:                           "confirmed=%d)\n", cfg, in );
        !          2876:                rc = -EIO;
        !          2877:                goto fail3;
        !          2878:        }
        !          2879: 
        !          2880:        /* Clear any previous over-temperature alert */
        !          2881:        rc = i2c->read ( i2c, &i2c_max6647, RSL, &in, EFAB_BYTE );
        !          2882:        if ( rc )
        !          2883:                goto fail4;
        !          2884: 
        !          2885:        /* Enable port 0 and 1 outputs on IO expander */
        !          2886:        cfg = 0x00;
        !          2887:        rc = i2c->write ( i2c, &i2c_pca9539, P0_CONFIG, &cfg, EFAB_BYTE );
        !          2888:        if ( rc )
        !          2889:                goto fail5;
        !          2890:        cfg = 0xff & ~(1 << P1_SPARE_LBN);
        !          2891:        rc = i2c->write ( i2c, &i2c_pca9539, P1_CONFIG, &cfg, EFAB_BYTE );
        !          2892:        if ( rc )
        !          2893:                goto fail6;
        !          2894: 
        !          2895:        /* Turn all power off then wait 1 sec. This ensures PHY is reset */
        !          2896:        out = 0xff & ~((0 << P0_EN_1V2_LBN) | (0 << P0_EN_2V5_LBN) |
        !          2897:                       (0 << P0_EN_3V3X_LBN) | (0 << P0_EN_5V_LBN) |
        !          2898:                       (0 << P0_EN_1V0X_LBN));
        !          2899: 
        !          2900:        rc = i2c->write ( i2c, &i2c_pca9539, P0_OUT, &out, EFAB_BYTE );
        !          2901:        if ( rc )
        !          2902:                goto fail7;
        !          2903: 
        !          2904:        mdelay(1000);
        !          2905: 
        !          2906:        for (count=0; count<20; count++) {
        !          2907:                /* Turn on 1.2V, 2.5V, 3.3V and 5V power rails */
        !          2908:                out = 0xff & ~( (1 << P0_EN_1V2_LBN)  | (1 << P0_EN_2V5_LBN) |
        !          2909:                                (1 << P0_EN_3V3X_LBN) | (1 << P0_EN_5V_LBN)  | 
        !          2910:                                (1 << P0_X_TRST_LBN) );
        !          2911: 
        !          2912:                rc = i2c->write ( i2c, &i2c_pca9539, P0_OUT, &out, EFAB_BYTE );
        !          2913:                if ( rc )
        !          2914:                        goto fail8;
        !          2915: 
        !          2916:                mdelay ( 10 );
        !          2917:                
        !          2918:                /* Turn on the 1V power rail */
        !          2919:                out  &= ~( 1 << P0_EN_1V0X_LBN );
        !          2920:                rc = i2c->write ( i2c, &i2c_pca9539, P0_OUT, &out, EFAB_BYTE );
        !          2921:                if ( rc )
        !          2922:                        goto fail9;
        !          2923: 
        !          2924:                EFAB_LOG ( "Waiting for power...(attempt %d)\n", count);
        !          2925:                mdelay ( 1000 );
        !          2926: 
        !          2927:                /* Check DSP is powered */
        !          2928:                rc = i2c->read ( i2c, &i2c_pca9539, P1_IN, &in, EFAB_BYTE );
        !          2929:                if ( rc )
        !          2930:                        goto fail10;
        !          2931: 
        !          2932:                if ( in & ( 1 << P1_AFE_PWD_LBN ) )
        !          2933:                        return 0;
        !          2934:        }
        !          2935: 
        !          2936:        rc = -ETIMEDOUT;
        !          2937: 
        !          2938: fail10:
        !          2939: fail9:
        !          2940: fail8:
        !          2941: fail7:
        !          2942:        /* Turn off power rails */
        !          2943:        out = 0xff;
        !          2944:        (void) i2c->write ( i2c, &i2c_pca9539, P0_OUT, &out, EFAB_BYTE );
        !          2945:        /* Disable port 1 outputs on IO expander */
        !          2946:        out = 0xff;
        !          2947:        (void) i2c->write ( i2c, &i2c_pca9539, P1_CONFIG, &out, EFAB_BYTE );
        !          2948: fail6:
        !          2949:        /* Disable port 0 outputs */
        !          2950:        out = 0xff;
        !          2951:        (void) i2c->write ( i2c, &i2c_pca9539, P1_CONFIG, &out, EFAB_BYTE );
        !          2952: fail5:
        !          2953: fail4:
        !          2954: fail3:
        !          2955: fail2:
        !          2956: fail1:
        !          2957:        EFAB_ERR ( "Failed initialising SFE4001 board\n" );
        !          2958:        return rc;
        !          2959: }
        !          2960: 
        !          2961: static void
        !          2962: sfe4001_fini ( struct efab_nic *efab )
        !          2963: {
        !          2964:        struct i2c_interface *i2c = &efab->i2c_bb.i2c;
        !          2965:        uint8_t in, cfg, out;
        !          2966: 
        !          2967:        EFAB_ERR ( "Turning off SFE4001\n" );
        !          2968: 
        !          2969:        /* Turn off all power rails */
        !          2970:        out = 0xff;
        !          2971:        (void) i2c->write ( i2c, &i2c_pca9539, P0_OUT, &out, EFAB_BYTE );
        !          2972: 
        !          2973:        /* Disable port 1 outputs on IO expander */
        !          2974:        cfg = 0xff;
        !          2975:        (void) i2c->write ( i2c, &i2c_pca9539, P1_CONFIG, &cfg, EFAB_BYTE );
        !          2976: 
        !          2977:        /* Disable port 0 outputs on IO expander */
        !          2978:        cfg = 0xff;
        !          2979:        (void) i2c->write ( i2c, &i2c_pca9539, P0_CONFIG, &cfg, EFAB_BYTE );
        !          2980: 
        !          2981:        /* Clear any over-temperature alert */
        !          2982:        (void) i2c->read ( i2c, &i2c_max6647, RSL, &in, EFAB_BYTE );
        !          2983: }
        !          2984: 
        !          2985: struct efab_board_operations sfe4001_ops = {
        !          2986:        .init           = sfe4001_init,
        !          2987:        .fini           = sfe4001_fini,
        !          2988: };
        !          2989: 
        !          2990: static int sfe4002_init ( struct efab_nic *efab __attribute__((unused)) )
        !          2991: {
        !          2992:        return 0;
        !          2993: }
        !          2994: static void sfe4002_fini ( struct efab_nic *efab __attribute__((unused)) )
        !          2995: {
        !          2996: }
        !          2997: 
        !          2998: struct efab_board_operations sfe4002_ops = {
        !          2999:        .init           = sfe4002_init,
        !          3000:        .fini           = sfe4002_fini,
        !          3001: };
        !          3002: 
        !          3003: static int sfe4003_init ( struct efab_nic *efab __attribute__((unused)) )
        !          3004: {
        !          3005:        return 0;
        !          3006: }
        !          3007: static void sfe4003_fini ( struct efab_nic *efab __attribute__((unused)) )
        !          3008: {
        !          3009: }
        !          3010: 
        !          3011: struct efab_board_operations sfe4003_ops = {
        !          3012:        .init           = sfe4003_init,
        !          3013:        .fini           = sfe4003_fini,
        !          3014: };
        !          3015: 
        !          3016: /*******************************************************************************
        !          3017:  *
        !          3018:  *
        !          3019:  * Hardware initialisation
        !          3020:  *
        !          3021:  *
        !          3022:  *******************************************************************************/ 
        !          3023: 
        !          3024: static void
        !          3025: falcon_free_special_buffer ( void *p )
        !          3026: {
        !          3027:        /* We don't bother cleaning up the buffer table entries -
        !          3028:         * we're hardly limited */
        !          3029:        free_dma ( p, EFAB_BUF_ALIGN );
        !          3030: }
        !          3031: 
        !          3032: static void*
        !          3033: falcon_alloc_special_buffer ( struct efab_nic *efab, int bytes,
        !          3034:                              struct efab_special_buffer *entry )
        !          3035: {
        !          3036:        void* buffer;
        !          3037:        int remaining;
        !          3038:        efab_qword_t buf_desc;
        !          3039:        unsigned long dma_addr;
        !          3040: 
        !          3041:        /* Allocate the buffer, aligned on a buffer address boundary */
        !          3042:        buffer = malloc_dma ( bytes, EFAB_BUF_ALIGN );
        !          3043:        if ( ! buffer )
        !          3044:                return NULL;
        !          3045: 
        !          3046:        /* Push buffer table entries to back the buffer */
        !          3047:        entry->id = efab->buffer_head;
        !          3048:        entry->dma_addr = dma_addr = virt_to_bus ( buffer );
        !          3049:        assert ( ( dma_addr & ( EFAB_BUF_ALIGN - 1 ) ) == 0 );
        !          3050: 
        !          3051:        remaining = bytes;
        !          3052:        while ( remaining > 0 ) {
        !          3053:                EFAB_POPULATE_QWORD_3 ( buf_desc,
        !          3054:                                        FCN_IP_DAT_BUF_SIZE, FCN_IP_DAT_BUF_SIZE_4K,
        !          3055:                                        FCN_BUF_ADR_FBUF, ( dma_addr >> 12 ),
        !          3056:                                        FCN_BUF_OWNER_ID_FBUF, 0 );
        !          3057: 
        !          3058:                falcon_write_sram ( efab, &buf_desc, efab->buffer_head );
        !          3059: 
        !          3060:                ++efab->buffer_head;
        !          3061:                dma_addr += EFAB_BUF_ALIGN;
        !          3062:                remaining -= EFAB_BUF_ALIGN;
        !          3063:        }
        !          3064: 
        !          3065:        EFAB_TRACE ( "Allocated 0x%x bytes at %p backed by buffer table "
        !          3066:                     "entries 0x%x..0x%x\n", bytes, buffer, entry->id,
        !          3067:                     efab->buffer_head - 1 );
        !          3068: 
        !          3069:        return buffer;
        !          3070: }
        !          3071: 
        !          3072: static void
        !          3073: clear_b0_fpga_memories ( struct efab_nic *efab)
        !          3074: {
        !          3075:        efab_oword_t blanko, temp;
        !          3076:        int offset; 
        !          3077: 
        !          3078:        EFAB_ZERO_OWORD ( blanko );
        !          3079: 
        !          3080:        /* Clear the address region register */
        !          3081:        EFAB_POPULATE_OWORD_4 ( temp,
        !          3082:                                FCN_ADR_REGION0, 0,
        !          3083:                                FCN_ADR_REGION1, ( 1 << 16 ),
        !          3084:                                FCN_ADR_REGION2, ( 2 << 16 ),
        !          3085:                                FCN_ADR_REGION3, ( 3 << 16 ) );
        !          3086:        falcon_write ( efab, &temp, FCN_ADR_REGION_REG_KER );
        !          3087:        
        !          3088:        EFAB_TRACE ( "Clearing filter and RSS tables\n" );
        !          3089: 
        !          3090:        for ( offset = FCN_RX_FILTER_TBL0 ;
        !          3091:              offset < FCN_RX_RSS_INDIR_TBL_B0+0x800 ;
        !          3092:              offset += 0x10 ) {
        !          3093:                falcon_write ( efab, &blanko, offset );
        !          3094:        }
        !          3095: 
        !          3096:        EFAB_TRACE ( "Wiping buffer tables\n" );
        !          3097: 
        !          3098:        /* Notice the 8 byte access mode */
        !          3099:        for ( offset = 0x2800000 ;
        !          3100:              offset < 0x3000000 ;
        !          3101:              offset += 0x8) {
        !          3102:                _falcon_writel ( efab, 0, offset );
        !          3103:                _falcon_writel ( efab, 0, offset + 4 );
        !          3104:                wmb();
        !          3105:        }
        !          3106: }
        !          3107: 
        !          3108: static int
        !          3109: falcon_reset ( struct efab_nic *efab )
        !          3110: {
        !          3111:        efab_oword_t glb_ctl_reg_ker;
        !          3112: 
        !          3113:        /* Initiate software reset */
        !          3114:        EFAB_POPULATE_OWORD_6 ( glb_ctl_reg_ker,
        !          3115:                                FCN_PCIE_CORE_RST_CTL, EXCLUDE_FROM_RESET,
        !          3116:                                FCN_PCIE_NSTCK_RST_CTL, EXCLUDE_FROM_RESET,
        !          3117:                                FCN_PCIE_SD_RST_CTL, EXCLUDE_FROM_RESET,
        !          3118:                                FCN_EE_RST_CTL, EXCLUDE_FROM_RESET,
        !          3119:                                FCN_EXT_PHY_RST_DUR, 0x7, /* 10ms */
        !          3120:                                FCN_SWRST, 1 );
        !          3121: 
        !          3122:        falcon_write ( efab, &glb_ctl_reg_ker, FCN_GLB_CTL_REG_KER );
        !          3123: 
        !          3124:        /* Allow 50ms for reset */
        !          3125:        mdelay ( 50 );
        !          3126: 
        !          3127:        /* Check for device reset complete */
        !          3128:        falcon_read ( efab, &glb_ctl_reg_ker, FCN_GLB_CTL_REG_KER );
        !          3129:        if ( EFAB_OWORD_FIELD ( glb_ctl_reg_ker, FCN_SWRST ) != 0 ) {
        !          3130:                EFAB_ERR ( "Reset failed\n" );
        !          3131:                return -ETIMEDOUT;
        !          3132:        }
        !          3133: 
        !          3134:        if ( ( efab->pci_revision == FALCON_REV_B0 ) && !efab->is_asic ) {
        !          3135:                clear_b0_fpga_memories ( efab );
        !          3136:        }
        !          3137: 
        !          3138:        return 0;
        !          3139: }
        !          3140: 
        !          3141: /** Offset of MAC address within EEPROM or Flash */
        !          3142: #define FALCON_MAC_ADDRESS_OFFSET 0x310
        !          3143: 
        !          3144: /*
        !          3145:  * Falcon EEPROM structure
        !          3146:  */
        !          3147: #define SF_NV_CONFIG_BASE 0x300
        !          3148: #define SF_NV_CONFIG_EXTRA 0xA0
        !          3149: 
        !          3150: struct falcon_nv_config_ver2 {
        !          3151:        uint16_t nports;
        !          3152:        uint8_t  port0_phy_addr;
        !          3153:        uint8_t  port0_phy_type;
        !          3154:        uint8_t  port1_phy_addr;
        !          3155:        uint8_t  port1_phy_type;
        !          3156:        uint16_t asic_sub_revision;
        !          3157:        uint16_t board_revision;
        !          3158:        uint8_t mac_location;
        !          3159: };
        !          3160: 
        !          3161: struct falcon_nv_extra {
        !          3162:        uint16_t magicnumber;
        !          3163:        uint16_t structure_version;
        !          3164:        uint16_t checksum;
        !          3165:        union {
        !          3166:                struct falcon_nv_config_ver2 ver2;
        !          3167:        } ver_specific;
        !          3168: };
        !          3169: 
        !          3170: #define BOARD_TYPE(_rev) (_rev >> 8)
        !          3171: 
        !          3172: static void
        !          3173: falcon_probe_nic_variant ( struct efab_nic *efab, struct pci_device *pci )
        !          3174: {
        !          3175:        efab_oword_t altera_build, nic_stat;
        !          3176:        int fpga_version;
        !          3177:        uint8_t revision;
        !          3178: 
        !          3179:        /* PCI revision */
        !          3180:        pci_read_config_byte ( pci, PCI_CLASS_REVISION, &revision );
        !          3181:        efab->pci_revision = revision;
        !          3182: 
        !          3183:        /* Asic vs FPGA */
        !          3184:        falcon_read ( efab, &altera_build, FCN_ALTERA_BUILD_REG_KER );
        !          3185:        fpga_version = EFAB_OWORD_FIELD ( altera_build, FCN_VER_ALL );
        !          3186:        efab->is_asic = (fpga_version == 0);
        !          3187: 
        !          3188:        /* MAC and PCI type */
        !          3189:        falcon_read ( efab, &nic_stat, FCN_NIC_STAT_REG );
        !          3190:        if ( efab->pci_revision == FALCON_REV_B0 ) {
        !          3191:                efab->phy_10g = EFAB_OWORD_FIELD ( nic_stat, FCN_STRAP_10G );
        !          3192:        }
        !          3193:        else if ( efab->is_asic ) {
        !          3194:                efab->phy_10g = EFAB_OWORD_FIELD ( nic_stat, FCN_STRAP_10G );
        !          3195:        }
        !          3196:        else {
        !          3197:                int minor = EFAB_OWORD_FIELD ( altera_build,  FCN_VER_MINOR );
        !          3198:                efab->phy_10g = ( minor == 0x14 );
        !          3199:        }
        !          3200: }
        !          3201: 
        !          3202: static void
        !          3203: falcon_init_spi_device ( struct efab_nic *efab, struct spi_device *spi )
        !          3204: {
        !          3205:        /* Falcon's SPI interface only supports reads/writes of up to 16 bytes.
        !          3206:         * Reduce the nvs block size down to satisfy this - which means callers
        !          3207:         * should use the nvs_* functions rather than spi_*. */
        !          3208:        if ( spi->nvs.block_size > FALCON_SPI_MAX_LEN )
        !          3209:                spi->nvs.block_size = FALCON_SPI_MAX_LEN;
        !          3210: 
        !          3211:        spi->bus = &efab->spi_bus;
        !          3212:        efab->spi = spi;
        !          3213: }
        !          3214: 
        !          3215: static int
        !          3216: falcon_probe_spi ( struct efab_nic *efab )
        !          3217: {
        !          3218:        efab_oword_t nic_stat, gpio_ctl, ee_vpd_cfg;
        !          3219:        int has_flash, has_eeprom, ad9bit;
        !          3220: 
        !          3221:        falcon_read ( efab, &nic_stat, FCN_NIC_STAT_REG );
        !          3222:        falcon_read ( efab, &gpio_ctl, FCN_GPIO_CTL_REG_KER );
        !          3223:        falcon_read ( efab, &ee_vpd_cfg, FCN_EE_VPD_CFG_REG );
        !          3224: 
        !          3225:        /* determine if FLASH / EEPROM is present */
        !          3226:        if ( ( efab->pci_revision >= FALCON_REV_B0 ) || efab->is_asic ) {
        !          3227:                has_flash = EFAB_OWORD_FIELD ( nic_stat, FCN_SF_PRST );
        !          3228:                has_eeprom = EFAB_OWORD_FIELD ( nic_stat, FCN_EE_PRST );
        !          3229:        } else {
        !          3230:                has_flash = EFAB_OWORD_FIELD ( gpio_ctl, FCN_FLASH_PRESENT );
        !          3231:                has_eeprom = EFAB_OWORD_FIELD ( gpio_ctl, FCN_EEPROM_PRESENT );
        !          3232:        }
        !          3233:        ad9bit = EFAB_OWORD_FIELD ( ee_vpd_cfg, FCN_EE_VPD_EN_AD9_MODE );
        !          3234: 
        !          3235:        /* Configure the SPI and I2C bus */
        !          3236:        efab->spi_bus.rw = falcon_spi_rw;
        !          3237:        init_i2c_bit_basher ( &efab->i2c_bb, &falcon_i2c_bit_ops );
        !          3238: 
        !          3239:        /* Configure the EEPROM SPI device. Generally, an Atmel 25040
        !          3240:         * (or similar) is used, but this is only possible if there is also
        !          3241:         * a flash device present to store the boot-time chip configuration.
        !          3242:         */
        !          3243:        if ( has_eeprom ) {
        !          3244:                if ( has_flash && ad9bit )
        !          3245:                        init_at25040 ( &efab->spi_eeprom );
        !          3246:                else
        !          3247:                        init_mc25xx640 ( &efab->spi_eeprom );
        !          3248:                falcon_init_spi_device ( efab, &efab->spi_eeprom );
        !          3249:        }
        !          3250: 
        !          3251:        /* Configure the FLASH SPI device */
        !          3252:        if ( has_flash ) {
        !          3253:                init_at25f1024 ( &efab->spi_flash );
        !          3254:                falcon_init_spi_device ( efab, &efab->spi_flash );
        !          3255:        }
        !          3256: 
        !          3257:        EFAB_LOG ( "flash is %s, EEPROM is %s%s\n",
        !          3258:                   ( has_flash ? "present" : "absent" ),
        !          3259:                   ( has_eeprom ? "present " : "absent" ),
        !          3260:                   ( has_eeprom ? (ad9bit ? "(9bit)" : "(16bit)") : "") );
        !          3261: 
        !          3262:        /* The device MUST have flash or eeprom */
        !          3263:        if ( ! efab->spi ) {
        !          3264:                EFAB_ERR ( "Device appears to have no flash or eeprom\n" );
        !          3265:                return -EIO;
        !          3266:        }
        !          3267: 
        !          3268:        /* If the device has EEPROM attached, then advertise NVO space */
        !          3269:        if ( has_eeprom ) {
        !          3270:                nvo_init ( &efab->nvo, &efab->spi_eeprom.nvs, 0x100, 0xf0,
        !          3271:                           NULL, &efab->netdev->refcnt );
        !          3272:        }
        !          3273: 
        !          3274:        return 0;
        !          3275: }
        !          3276: 
        !          3277: static int
        !          3278: falcon_probe_nvram ( struct efab_nic *efab )
        !          3279: {
        !          3280:        struct nvs_device *nvs = &efab->spi->nvs;
        !          3281:        struct falcon_nv_extra nv;
        !          3282:        int rc, board_revision;
        !          3283: 
        !          3284:        /* Read the MAC address */
        !          3285:        rc = nvs_read ( nvs, FALCON_MAC_ADDRESS_OFFSET,
        !          3286:                        efab->mac_addr, ETH_ALEN );
        !          3287:        if ( rc )
        !          3288:                return rc;
        !          3289: 
        !          3290:        /* Poke through the NVRAM structure for the PHY type. */
        !          3291:        rc = nvs_read ( nvs, SF_NV_CONFIG_BASE + SF_NV_CONFIG_EXTRA,
        !          3292:                        &nv, sizeof ( nv ) );
        !          3293:        if ( rc )
        !          3294:                return rc;
        !          3295: 
        !          3296:        /* Handle each supported NVRAM version */
        !          3297:        if ( ( le16_to_cpu ( nv.magicnumber ) == FCN_NV_MAGIC_NUMBER ) &&
        !          3298:             ( le16_to_cpu ( nv.structure_version ) >= 2 ) ) {
        !          3299:                struct falcon_nv_config_ver2* ver2 = &nv.ver_specific.ver2;
        !          3300:                
        !          3301:                /* Get the PHY type */
        !          3302:                efab->phy_addr = le16_to_cpu ( ver2->port0_phy_addr );
        !          3303:                efab->phy_type = le16_to_cpu ( ver2->port0_phy_type );
        !          3304:                board_revision = le16_to_cpu ( ver2->board_revision );
        !          3305:        }
        !          3306:        else {
        !          3307:                EFAB_ERR ( "NVram is not recognised\n" );
        !          3308:                return -EINVAL;
        !          3309:        }
        !          3310: 
        !          3311:        efab->board_type = BOARD_TYPE ( board_revision );
        !          3312:        
        !          3313:        EFAB_TRACE ( "Falcon board %d phy %d @ addr %d\n",
        !          3314:                     efab->board_type, efab->phy_type, efab->phy_addr );
        !          3315: 
        !          3316:        /* Patch in the board operations */
        !          3317:        switch ( efab->board_type ) {
        !          3318:        case EFAB_BOARD_SFE4001:
        !          3319:                efab->board_op = &sfe4001_ops;
        !          3320:                break;
        !          3321:        case EFAB_BOARD_SFE4002:
        !          3322:                efab->board_op = &sfe4002_ops;
        !          3323:                break;
        !          3324:        case EFAB_BOARD_SFE4003:
        !          3325:                efab->board_op = &sfe4003_ops;
        !          3326:                break;
        !          3327:        default:
        !          3328:                EFAB_ERR ( "Unrecognised board type\n" );
        !          3329:                return -EINVAL;
        !          3330:        }
        !          3331: 
        !          3332:        /* Patch in MAC operations */
        !          3333:        if ( efab->phy_10g )
        !          3334:                efab->mac_op = &falcon_xmac_operations;
        !          3335:        else
        !          3336:                efab->mac_op = &falcon_gmac_operations;
        !          3337: 
        !          3338:        /* Hook in the PHY ops */
        !          3339:        switch ( efab->phy_type ) {
        !          3340:        case PHY_TYPE_10XPRESS:
        !          3341:                efab->phy_op = &falcon_tenxpress_phy_ops;
        !          3342:                break;
        !          3343:        case PHY_TYPE_CX4:
        !          3344:                efab->phy_op = &falcon_xaui_phy_ops;
        !          3345:                break;
        !          3346:        case PHY_TYPE_XFP:
        !          3347:                efab->phy_op = &falcon_xfp_phy_ops;
        !          3348:                break;
        !          3349:        case PHY_TYPE_CX4_RTMR:
        !          3350:                efab->phy_op = &falcon_txc_phy_ops;
        !          3351:                break;
        !          3352:        case PHY_TYPE_PM8358:
        !          3353:                efab->phy_op = &falcon_pm8358_phy_ops;
        !          3354:                break;
        !          3355:        case PHY_TYPE_1GIG_ALASKA:
        !          3356:                efab->phy_op = &falcon_alaska_phy_ops;
        !          3357:                break;
        !          3358:        default:
        !          3359:                EFAB_ERR ( "Unknown PHY type: %d\n", efab->phy_type );
        !          3360:                return -EINVAL;
        !          3361:        }
        !          3362: 
        !          3363:        return 0;
        !          3364: }
        !          3365: 
        !          3366: static int
        !          3367: falcon_init_sram ( struct efab_nic *efab )
        !          3368: {
        !          3369:        efab_oword_t reg;
        !          3370:        int count;
        !          3371: 
        !          3372:        /* use card in internal SRAM mode */
        !          3373:        falcon_read ( efab, &reg, FCN_NIC_STAT_REG );
        !          3374:        EFAB_SET_OWORD_FIELD ( reg, FCN_ONCHIP_SRAM, 1 );
        !          3375:        falcon_write ( efab, &reg, FCN_NIC_STAT_REG );
        !          3376: 
        !          3377:        /* Deactivate any external SRAM that might be present */
        !          3378:        EFAB_POPULATE_OWORD_2 ( reg, 
        !          3379:                                FCN_GPIO1_OEN, 1,
        !          3380:                                FCN_GPIO1_OUT, 1 );
        !          3381:        falcon_write ( efab, &reg, FCN_GPIO_CTL_REG_KER );
        !          3382: 
        !          3383:        /* Initiate SRAM reset */
        !          3384:        EFAB_POPULATE_OWORD_2 ( reg,
        !          3385:                                FCN_SRAM_OOB_BT_INIT_EN, 1,
        !          3386:                                FCN_SRM_NUM_BANKS_AND_BANK_SIZE, 0 );
        !          3387:        falcon_write ( efab, &reg, FCN_SRM_CFG_REG_KER );
        !          3388: 
        !          3389:        /* Wait for SRAM reset to complete */
        !          3390:        count = 0;
        !          3391:        do {
        !          3392:                /* SRAM reset is slow; expect around 16ms */
        !          3393:                mdelay ( 20 );
        !          3394: 
        !          3395:                /* Check for reset complete */
        !          3396:                falcon_read ( efab, &reg, FCN_SRM_CFG_REG_KER );
        !          3397:                if ( !EFAB_OWORD_FIELD ( reg, FCN_SRAM_OOB_BT_INIT_EN ) )
        !          3398:                        return 0;
        !          3399:        } while (++count < 20); /* wait upto 0.4 sec */
        !          3400: 
        !          3401:        EFAB_ERR ( "timed out waiting for SRAM reset\n");
        !          3402:        return -ETIMEDOUT;
        !          3403: }
        !          3404: 
        !          3405: static void
        !          3406: falcon_setup_nic ( struct efab_nic *efab )
        !          3407: {
        !          3408:        efab_dword_t timer_cmd;
        !          3409:        efab_oword_t reg;
        !          3410:        int tx_fc, xoff_thresh, xon_thresh;
        !          3411: 
        !          3412:        /* bug5129: Clear the parity enables on the TX data fifos as 
        !          3413:         * they produce false parity errors because of timing issues 
        !          3414:         */
        !          3415:        falcon_read ( efab, &reg, FCN_SPARE_REG_KER );
        !          3416:        EFAB_SET_OWORD_FIELD ( reg, FCN_MEM_PERR_EN_TX_DATA, 0 );
        !          3417:        falcon_write ( efab, &reg, FCN_SPARE_REG_KER );
        !          3418:        
        !          3419:        /* Set up TX and RX descriptor caches in SRAM */
        !          3420:        EFAB_POPULATE_OWORD_1 ( reg, FCN_SRM_TX_DC_BASE_ADR, 0x130000 );
        !          3421:        falcon_write ( efab, &reg, FCN_SRM_TX_DC_CFG_REG_KER );
        !          3422:        EFAB_POPULATE_OWORD_1 ( reg, FCN_TX_DC_SIZE, 1 /* 16 descriptors */ );
        !          3423:        falcon_write ( efab, &reg, FCN_TX_DC_CFG_REG_KER );
        !          3424:        EFAB_POPULATE_OWORD_1 ( reg, FCN_SRM_RX_DC_BASE_ADR, 0x100000 );
        !          3425:        falcon_write ( efab, &reg, FCN_SRM_RX_DC_CFG_REG_KER );
        !          3426:        EFAB_POPULATE_OWORD_1 ( reg, FCN_RX_DC_SIZE, 2 /* 32 descriptors */ );
        !          3427:        falcon_write ( efab, &reg, FCN_RX_DC_CFG_REG_KER );
        !          3428:        
        !          3429:        /* Set number of RSS CPUs
        !          3430:         * bug7244: Increase filter depth to reduce RX_RESET likelyhood
        !          3431:         */
        !          3432:        EFAB_POPULATE_OWORD_5 ( reg,
        !          3433:                                FCN_NUM_KER, 0,
        !          3434:                                FCN_UDP_FULL_SRCH_LIMIT, 8,
        !          3435:                                 FCN_UDP_WILD_SRCH_LIMIT, 8,
        !          3436:                                 FCN_TCP_WILD_SRCH_LIMIT, 8,
        !          3437:                                 FCN_TCP_FULL_SRCH_LIMIT, 8);
        !          3438:        falcon_write ( efab, &reg, FCN_RX_FILTER_CTL_REG_KER );
        !          3439:        udelay ( 1000 );
        !          3440: 
        !          3441:        /* Setup RX.  Wait for descriptor is broken and must
        !          3442:         * be disabled.  RXDP recovery shouldn't be needed, but is.
        !          3443:         * disable ISCSI parsing because we don't need it
        !          3444:         */
        !          3445:        falcon_read ( efab, &reg, FCN_RX_SELF_RST_REG_KER );
        !          3446:        EFAB_SET_OWORD_FIELD ( reg, FCN_RX_NODESC_WAIT_DIS, 1 );
        !          3447:        EFAB_SET_OWORD_FIELD ( reg, FCN_RX_RECOVERY_EN, 1 );
        !          3448:        EFAB_SET_OWORD_FIELD ( reg, FCN_RX_ISCSI_DIS, 1 );
        !          3449:        falcon_write ( efab, &reg, FCN_RX_SELF_RST_REG_KER );
        !          3450:        
        !          3451:        /* Determine recommended flow control settings. *
        !          3452:         * Flow control is qualified on B0 and A1/1G, not on A1/10G */
        !          3453:        if ( efab->pci_revision == FALCON_REV_B0 ) {
        !          3454:                tx_fc = 1;
        !          3455:                xoff_thresh = 54272;  /* ~80Kb - 3*max MTU */
        !          3456:                xon_thresh = 27648; /* ~3*max MTU */
        !          3457:        }
        !          3458:        else if ( !efab->phy_10g ) {
        !          3459:                tx_fc = 1;
        !          3460:                xoff_thresh = 2048;
        !          3461:                xon_thresh = 512;
        !          3462:        }
        !          3463:        else {
        !          3464:                tx_fc = xoff_thresh = xon_thresh = 0;
        !          3465:        }
        !          3466: 
        !          3467:        /* Setup TX and RX */
        !          3468:        falcon_read ( efab, &reg, FCN_TX_CFG2_REG_KER );
        !          3469:        EFAB_SET_OWORD_FIELD ( reg, FCN_TX_DIS_NON_IP_EV, 1 );
        !          3470:        falcon_write ( efab, &reg, FCN_TX_CFG2_REG_KER );
        !          3471: 
        !          3472:        falcon_read ( efab, &reg, FCN_RX_CFG_REG_KER );
        !          3473:        EFAB_SET_OWORD_FIELD_VER ( efab, reg, FCN_RX_USR_BUF_SIZE,
        !          3474:                                   (3*4096) / 32 );
        !          3475:        if ( efab->pci_revision == FALCON_REV_B0)
        !          3476:                EFAB_SET_OWORD_FIELD ( reg, FCN_RX_INGR_EN_B0, 1 );
        !          3477:        EFAB_SET_OWORD_FIELD_VER ( efab, reg, FCN_RX_XON_MAC_TH,
        !          3478:                                   xon_thresh / 256);
        !          3479:        EFAB_SET_OWORD_FIELD_VER ( efab, reg, FCN_RX_XOFF_MAC_TH,
        !          3480:                                   xoff_thresh / 256);
        !          3481:        EFAB_SET_OWORD_FIELD_VER ( efab, reg, FCN_RX_XOFF_MAC_EN, tx_fc);
        !          3482:        falcon_write ( efab, &reg, FCN_RX_CFG_REG_KER );
        !          3483: 
        !          3484:        /* Set timer register */
        !          3485:        EFAB_POPULATE_DWORD_2 ( timer_cmd,
        !          3486:                                FCN_TIMER_MODE, FCN_TIMER_MODE_DIS,
        !          3487:                                FCN_TIMER_VAL, 0 );
        !          3488:        falcon_writel ( efab, &timer_cmd, FCN_TIMER_CMD_REG_KER );
        !          3489: }
        !          3490: 
        !          3491: static void
        !          3492: falcon_init_resources ( struct efab_nic *efab )
        !          3493: {
        !          3494:        struct efab_ev_queue *ev_queue = &efab->ev_queue;
        !          3495:        struct efab_rx_queue *rx_queue = &efab->rx_queue;
        !          3496:        struct efab_tx_queue *tx_queue = &efab->tx_queue;
        !          3497: 
        !          3498:        efab_oword_t reg;
        !          3499:        int jumbo;
        !          3500: 
        !          3501:        /* Initialise the ptrs */
        !          3502:        tx_queue->read_ptr = tx_queue->write_ptr = 0;
        !          3503:        rx_queue->read_ptr = rx_queue->write_ptr = 0;
        !          3504:        ev_queue->read_ptr = 0;
        !          3505: 
        !          3506:        /* Push the event queue to the hardware */
        !          3507:        EFAB_POPULATE_OWORD_3 ( reg,
        !          3508:                                FCN_EVQ_EN, 1,
        !          3509:                                FCN_EVQ_SIZE, FQS(FCN_EVQ, EFAB_EVQ_SIZE),
        !          3510:                                FCN_EVQ_BUF_BASE_ID, ev_queue->entry.id );
        !          3511:        falcon_write ( efab, &reg, 
        !          3512:                       FCN_REVISION_REG ( efab, FCN_EVQ_PTR_TBL_KER ) );
        !          3513:        
        !          3514:        /* Push the tx queue to the hardware */
        !          3515:        EFAB_POPULATE_OWORD_8 ( reg,
        !          3516:                                FCN_TX_DESCQ_EN, 1,
        !          3517:                                FCN_TX_ISCSI_DDIG_EN, 0,
        !          3518:                                FCN_TX_ISCSI_DDIG_EN, 0,
        !          3519:                                FCN_TX_DESCQ_BUF_BASE_ID, tx_queue->entry.id,
        !          3520:                                FCN_TX_DESCQ_EVQ_ID, 0,
        !          3521:                                FCN_TX_DESCQ_SIZE, FQS(FCN_TX_DESCQ, EFAB_TXD_SIZE),
        !          3522:                                FCN_TX_DESCQ_TYPE, 0 /* kernel queue */,
        !          3523:                                FCN_TX_NON_IP_DROP_DIS_B0, 1 );
        !          3524:        falcon_write ( efab, &reg, 
        !          3525:                       FCN_REVISION_REG ( efab, FCN_TX_DESC_PTR_TBL_KER ) );
        !          3526:        
        !          3527:        /* Push the rx queue to the hardware */
        !          3528:        jumbo = ( efab->pci_revision == FALCON_REV_B0 ) ? 0 : 1;
        !          3529:        EFAB_POPULATE_OWORD_8 ( reg,
        !          3530:                                FCN_RX_ISCSI_DDIG_EN, 0,
        !          3531:                                FCN_RX_ISCSI_HDIG_EN, 0,
        !          3532:                                FCN_RX_DESCQ_BUF_BASE_ID, rx_queue->entry.id,
        !          3533:                                FCN_RX_DESCQ_EVQ_ID, 0,
        !          3534:                                FCN_RX_DESCQ_SIZE, FQS(FCN_RX_DESCQ, EFAB_RXD_SIZE),
        !          3535:                                FCN_RX_DESCQ_TYPE, 0 /* kernel queue */,
        !          3536:                                FCN_RX_DESCQ_JUMBO, jumbo,
        !          3537:                                FCN_RX_DESCQ_EN, 1 );
        !          3538:        falcon_write ( efab, &reg,
        !          3539:                       FCN_REVISION_REG ( efab, FCN_RX_DESC_PTR_TBL_KER ) );
        !          3540: 
        !          3541:        /* Program INT_ADR_REG_KER */
        !          3542:        EFAB_POPULATE_OWORD_1 ( reg,
        !          3543:                                FCN_INT_ADR_KER, virt_to_bus ( &efab->int_ker ) );
        !          3544:        falcon_write ( efab, &reg, FCN_INT_ADR_REG_KER );
        !          3545: 
        !          3546:        /* Ack the event queue */
        !          3547:        falcon_eventq_read_ack ( efab, ev_queue );
        !          3548: }
        !          3549: 
        !          3550: static void
        !          3551: falcon_fini_resources ( struct efab_nic *efab )
        !          3552: {
        !          3553:        efab_oword_t cmd;
        !          3554:        
        !          3555:        /* Disable interrupts */
        !          3556:        falcon_interrupts ( efab, 0, 0 );
        !          3557: 
        !          3558:        /* Flush the dma queues */
        !          3559:        EFAB_POPULATE_OWORD_2 ( cmd,
        !          3560:                                FCN_TX_FLUSH_DESCQ_CMD, 1,
        !          3561:                                FCN_TX_FLUSH_DESCQ, 0 );
        !          3562:        falcon_write ( efab, &cmd, 
        !          3563:                       FCN_REVISION_REG ( efab, FCN_TX_DESC_PTR_TBL_KER ) );
        !          3564: 
        !          3565:        EFAB_POPULATE_OWORD_2 ( cmd,
        !          3566:                                FCN_RX_FLUSH_DESCQ_CMD, 1,
        !          3567:                                FCN_RX_FLUSH_DESCQ, 0 );
        !          3568:        falcon_write ( efab, &cmd,
        !          3569:                       FCN_REVISION_REG ( efab, FCN_RX_DESC_PTR_TBL_KER ) );
        !          3570: 
        !          3571:        mdelay ( 100 );
        !          3572: 
        !          3573:        /* Remove descriptor rings from card */
        !          3574:        EFAB_ZERO_OWORD ( cmd );
        !          3575:        falcon_write ( efab, &cmd, 
        !          3576:                       FCN_REVISION_REG ( efab, FCN_TX_DESC_PTR_TBL_KER ) );
        !          3577:        falcon_write ( efab, &cmd, 
        !          3578:                       FCN_REVISION_REG ( efab, FCN_RX_DESC_PTR_TBL_KER ) );
        !          3579:        falcon_write ( efab, &cmd, 
        !          3580:                       FCN_REVISION_REG ( efab, FCN_EVQ_PTR_TBL_KER ) );
        !          3581: }
        !          3582: 
        !          3583: /*******************************************************************************
        !          3584:  *
        !          3585:  *
        !          3586:  * Hardware rx path
        !          3587:  *
        !          3588:  *
        !          3589:  *******************************************************************************/
        !          3590: 
        !          3591: static void
        !          3592: falcon_build_rx_desc ( falcon_rx_desc_t *rxd, struct io_buffer *iob )
        !          3593: {
        !          3594:        EFAB_POPULATE_QWORD_2 ( *rxd,
        !          3595:                                FCN_RX_KER_BUF_SIZE, EFAB_RX_BUF_SIZE,
        !          3596:                                FCN_RX_KER_BUF_ADR, virt_to_bus ( iob->data ) );
        !          3597: }
        !          3598: 
        !          3599: static void
        !          3600: falcon_notify_rx_desc ( struct efab_nic *efab, struct efab_rx_queue *rx_queue )
        !          3601: {
        !          3602:        efab_dword_t reg;
        !          3603:        int ptr = rx_queue->write_ptr % EFAB_RXD_SIZE;
        !          3604: 
        !          3605:        EFAB_POPULATE_DWORD_1 ( reg, FCN_RX_DESC_WPTR_DWORD, ptr );
        !          3606:        falcon_writel ( efab, &reg, FCN_RX_DESC_UPD_REG_KER_DWORD );
        !          3607: }
        !          3608: 
        !          3609: 
        !          3610: /*******************************************************************************
        !          3611:  *
        !          3612:  *
        !          3613:  * Hardware tx path
        !          3614:  *
        !          3615:  *
        !          3616:  *******************************************************************************/
        !          3617: 
        !          3618: static void
        !          3619: falcon_build_tx_desc ( falcon_tx_desc_t *txd, struct io_buffer *iob )
        !          3620: {
        !          3621:        EFAB_POPULATE_QWORD_2 ( *txd,
        !          3622:                                FCN_TX_KER_BYTE_CNT, iob_len ( iob ),
        !          3623:                                FCN_TX_KER_BUF_ADR, virt_to_bus ( iob->data ) );
        !          3624: }
        !          3625: 
        !          3626: static void
        !          3627: falcon_notify_tx_desc ( struct efab_nic *efab,
        !          3628:                        struct efab_tx_queue *tx_queue )
        !          3629: {
        !          3630:        efab_dword_t reg;
        !          3631:        int ptr = tx_queue->write_ptr % EFAB_TXD_SIZE;
        !          3632: 
        !          3633:        EFAB_POPULATE_DWORD_1 ( reg, FCN_TX_DESC_WPTR_DWORD, ptr );
        !          3634:        falcon_writel ( efab, &reg, FCN_TX_DESC_UPD_REG_KER_DWORD );
        !          3635: }
        !          3636: 
        !          3637: 
        !          3638: /*******************************************************************************
        !          3639:  *
        !          3640:  *
        !          3641:  * Software receive interface
        !          3642:  *
        !          3643:  *
        !          3644:  *******************************************************************************/ 
        !          3645: 
        !          3646: static int
        !          3647: efab_fill_rx_queue ( struct efab_nic *efab,
        !          3648:                     struct efab_rx_queue *rx_queue )
        !          3649: {
        !          3650:        int fill_level = rx_queue->write_ptr - rx_queue->read_ptr;
        !          3651:        int space = EFAB_NUM_RX_DESC - fill_level - 1;
        !          3652:        int pushed = 0;
        !          3653: 
        !          3654:        while ( space ) {
        !          3655:                int buf_id = rx_queue->write_ptr % EFAB_NUM_RX_DESC;
        !          3656:                int desc_id = rx_queue->write_ptr % EFAB_RXD_SIZE;
        !          3657:                struct io_buffer *iob;
        !          3658:                falcon_rx_desc_t *rxd;
        !          3659: 
        !          3660:                assert ( rx_queue->buf[buf_id] == NULL );
        !          3661:                iob = alloc_iob ( EFAB_RX_BUF_SIZE );
        !          3662:                if ( !iob )
        !          3663:                        break;
        !          3664: 
        !          3665:                EFAB_TRACE ( "pushing rx_buf[%d] iob %p data %p\n",
        !          3666:                             buf_id, iob, iob->data );
        !          3667: 
        !          3668:                rx_queue->buf[buf_id] = iob;
        !          3669:                rxd = rx_queue->ring + desc_id;
        !          3670:                falcon_build_rx_desc ( rxd, iob );
        !          3671:                ++rx_queue->write_ptr;
        !          3672:                ++pushed;
        !          3673:                --space;
        !          3674:        }
        !          3675: 
        !          3676:        if ( pushed ) {
        !          3677:                /* Push the ptr to hardware */
        !          3678:                falcon_notify_rx_desc ( efab, rx_queue );
        !          3679: 
        !          3680:                fill_level = rx_queue->write_ptr - rx_queue->read_ptr;
        !          3681:                EFAB_TRACE ( "pushed %d rx buffers to fill level %d\n",
        !          3682:                             pushed, fill_level );
        !          3683:        }
        !          3684: 
        !          3685:        if ( fill_level == 0 )
        !          3686:                return -ENOMEM;
        !          3687:        return 0;
        !          3688: }
        !          3689:        
        !          3690: static void
        !          3691: efab_receive ( struct efab_nic *efab, unsigned int id, int len, int drop )
        !          3692: {
        !          3693:        struct efab_rx_queue *rx_queue = &efab->rx_queue;
        !          3694:        struct io_buffer *iob;
        !          3695:        unsigned int read_ptr = rx_queue->read_ptr % EFAB_RXD_SIZE;
        !          3696:        unsigned int buf_ptr = rx_queue->read_ptr % EFAB_NUM_RX_DESC;
        !          3697: 
        !          3698:        assert ( id == read_ptr );
        !          3699:        
        !          3700:        /* Pop this rx buffer out of the software ring */
        !          3701:        iob = rx_queue->buf[buf_ptr];
        !          3702:        rx_queue->buf[buf_ptr] = NULL;
        !          3703: 
        !          3704:        EFAB_TRACE ( "popping rx_buf[%d] iob %p data %p with %d bytes %s\n",
        !          3705:                     id, iob, iob->data, len, drop ? "bad" : "ok" );
        !          3706: 
        !          3707:        /* Pass the packet up if required */
        !          3708:        if ( drop )
        !          3709:                free_iob ( iob );
        !          3710:        else {
        !          3711:                iob_put ( iob, len );
        !          3712:                netdev_rx ( efab->netdev, iob );
        !          3713:        }
        !          3714: 
        !          3715:        ++rx_queue->read_ptr;
        !          3716: }
        !          3717: 
        !          3718: /*******************************************************************************
        !          3719:  *
        !          3720:  *
        !          3721:  * Software transmit interface
        !          3722:  *
        !          3723:  *
        !          3724:  *******************************************************************************/ 
        !          3725: 
        !          3726: static int
        !          3727: efab_transmit ( struct net_device *netdev, struct io_buffer *iob )
        !          3728: {
        !          3729:        struct efab_nic *efab = netdev_priv ( netdev );
        !          3730:        struct efab_tx_queue *tx_queue = &efab->tx_queue;
        !          3731:        int fill_level, space;
        !          3732:        falcon_tx_desc_t *txd;
        !          3733:        int buf_id;
        !          3734: 
        !          3735:        fill_level = tx_queue->write_ptr - tx_queue->read_ptr;
        !          3736:        space = EFAB_TXD_SIZE - fill_level - 1;
        !          3737:        if ( space < 1 )
        !          3738:                return -ENOBUFS;
        !          3739: 
        !          3740:        /* Save the iobuffer for later completion */
        !          3741:        buf_id = tx_queue->write_ptr % EFAB_TXD_SIZE;
        !          3742:        assert ( tx_queue->buf[buf_id] == NULL );
        !          3743:        tx_queue->buf[buf_id] = iob;
        !          3744: 
        !          3745:        EFAB_TRACE ( "tx_buf[%d] for iob %p data %p len %zd\n",
        !          3746:                     buf_id, iob, iob->data, iob_len ( iob ) );
        !          3747: 
        !          3748:        /* Form the descriptor, and push it to hardware */
        !          3749:        txd = tx_queue->ring + buf_id;
        !          3750:        falcon_build_tx_desc ( txd, iob );
        !          3751:        ++tx_queue->write_ptr;
        !          3752:        falcon_notify_tx_desc ( efab, tx_queue );
        !          3753: 
        !          3754:        return 0;
        !          3755: }
        !          3756: 
        !          3757: static int
        !          3758: efab_transmit_done ( struct efab_nic *efab, int id )
        !          3759: {
        !          3760:        struct efab_tx_queue *tx_queue = &efab->tx_queue;
        !          3761:        unsigned int read_ptr, stop;
        !          3762: 
        !          3763:        /* Complete all buffers from read_ptr up to and including id */
        !          3764:        read_ptr = tx_queue->read_ptr % EFAB_TXD_SIZE;
        !          3765:        stop = ( id + 1 ) % EFAB_TXD_SIZE;
        !          3766: 
        !          3767:        while ( read_ptr != stop ) {
        !          3768:                struct io_buffer *iob = tx_queue->buf[read_ptr];
        !          3769:                assert ( iob );
        !          3770: 
        !          3771:                /* Complete the tx buffer */
        !          3772:                if ( iob )
        !          3773:                        netdev_tx_complete ( efab->netdev, iob );
        !          3774:                tx_queue->buf[read_ptr] = NULL;
        !          3775:                
        !          3776:                ++tx_queue->read_ptr;
        !          3777:                read_ptr = tx_queue->read_ptr % EFAB_TXD_SIZE;
        !          3778:        }
        !          3779: 
        !          3780:        return 0;
        !          3781: }
        !          3782: 
        !          3783: /*******************************************************************************
        !          3784:  *
        !          3785:  *
        !          3786:  * Hardware event path
        !          3787:  *
        !          3788:  *
        !          3789:  *******************************************************************************/
        !          3790: 
        !          3791: static void
        !          3792: falcon_clear_interrupts ( struct efab_nic *efab )
        !          3793: {
        !          3794:        efab_dword_t reg;
        !          3795: 
        !          3796:        if ( efab->pci_revision == FALCON_REV_B0 ) {
        !          3797:                /* read the ISR */
        !          3798:                falcon_readl( efab, &reg, INT_ISR0_B0 );
        !          3799:        }
        !          3800:        else {
        !          3801:                /* write to the INT_ACK register */
        !          3802:                falcon_writel ( efab, 0, FCN_INT_ACK_KER_REG_A1 );
        !          3803:                mb();
        !          3804:                falcon_readl ( efab, &reg,
        !          3805:                               WORK_AROUND_BROKEN_PCI_READS_REG_KER_A1 );
        !          3806:        }
        !          3807: }
        !          3808: 
        !          3809: static void
        !          3810: falcon_handle_event ( struct efab_nic *efab, falcon_event_t *evt )
        !          3811: {
        !          3812:        int ev_code, desc_ptr, len, drop;
        !          3813: 
        !          3814:        /* Decode event */
        !          3815:        ev_code = EFAB_QWORD_FIELD ( *evt, FCN_EV_CODE );
        !          3816:        switch ( ev_code ) {
        !          3817:        case FCN_TX_IP_EV_DECODE:
        !          3818:                desc_ptr = EFAB_QWORD_FIELD ( *evt, FCN_TX_EV_DESC_PTR );
        !          3819:                efab_transmit_done ( efab, desc_ptr );
        !          3820:                break;
        !          3821:        
        !          3822:        case FCN_RX_IP_EV_DECODE:
        !          3823:                desc_ptr = EFAB_QWORD_FIELD ( *evt, FCN_RX_EV_DESC_PTR );
        !          3824:                len = EFAB_QWORD_FIELD ( *evt, FCN_RX_EV_BYTE_CNT );
        !          3825:                drop = !EFAB_QWORD_FIELD ( *evt, FCN_RX_EV_PKT_OK );
        !          3826: 
        !          3827:                efab_receive ( efab, desc_ptr, len, drop );
        !          3828:                break;
        !          3829: 
        !          3830:        default:
        !          3831:                EFAB_TRACE ( "Unknown event type %d\n", ev_code );
        !          3832:                break;
        !          3833:        }
        !          3834: }
        !          3835: 
        !          3836: /*******************************************************************************
        !          3837:  *
        !          3838:  *
        !          3839:  * Software (polling) interrupt handler
        !          3840:  *
        !          3841:  *
        !          3842:  *******************************************************************************/
        !          3843: 
        !          3844: static void
        !          3845: efab_poll ( struct net_device *netdev )
        !          3846: {
        !          3847:        struct efab_nic *efab = netdev_priv ( netdev );
        !          3848:        struct efab_ev_queue *ev_queue = &efab->ev_queue;
        !          3849:        struct efab_rx_queue *rx_queue = &efab->rx_queue;
        !          3850:        falcon_event_t *evt;
        !          3851: 
        !          3852:        /* Read the event queue by directly looking for events
        !          3853:         * (we don't even bother to read the eventq write ptr) */
        !          3854:        evt = ev_queue->ring + ev_queue->read_ptr;
        !          3855:        while ( falcon_event_present ( evt ) ) {
        !          3856:                
        !          3857:                EFAB_TRACE ( "Event at index 0x%x address %p is "
        !          3858:                             EFAB_QWORD_FMT "\n", ev_queue->read_ptr,
        !          3859:                             evt, EFAB_QWORD_VAL ( *evt ) );
        !          3860:                
        !          3861:                falcon_handle_event ( efab, evt );
        !          3862:                
        !          3863:                /* Clear the event */
        !          3864:                EFAB_SET_QWORD ( *evt );
        !          3865:        
        !          3866:                /* Move to the next event. We don't ack the event
        !          3867:                 * queue until the end */
        !          3868:                ev_queue->read_ptr = ( ( ev_queue->read_ptr + 1 ) %
        !          3869:                                       EFAB_EVQ_SIZE );
        !          3870:                evt = ev_queue->ring + ev_queue->read_ptr;
        !          3871:        }
        !          3872: 
        !          3873:        /* Push more buffers if needed */
        !          3874:        (void) efab_fill_rx_queue ( efab, rx_queue );
        !          3875: 
        !          3876:        /* Clear any pending interrupts */
        !          3877:        falcon_clear_interrupts ( efab );
        !          3878: 
        !          3879:        /* Ack the event queue */
        !          3880:        falcon_eventq_read_ack ( efab, ev_queue );
        !          3881: }
        !          3882: 
        !          3883: static void
        !          3884: efab_irq ( struct net_device *netdev, int enable )
        !          3885: {
        !          3886:        struct efab_nic *efab = netdev_priv ( netdev );
        !          3887:        struct efab_ev_queue *ev_queue = &efab->ev_queue;
        !          3888: 
        !          3889:        switch ( enable ) {
        !          3890:        case 0:
        !          3891:                falcon_interrupts ( efab, 0, 0 );
        !          3892:                break;
        !          3893:        case 1:
        !          3894:                falcon_interrupts ( efab, 1, 0 );
        !          3895:                falcon_eventq_read_ack ( efab, ev_queue );
        !          3896:                break;
        !          3897:        case 2:
        !          3898:                falcon_interrupts ( efab, 1, 1 );
        !          3899:                break;
        !          3900:        }
        !          3901: }
        !          3902: 
        !          3903: /*******************************************************************************
        !          3904:  *
        !          3905:  *
        !          3906:  * Software open/close
        !          3907:  *
        !          3908:  *
        !          3909:  *******************************************************************************/
        !          3910: 
        !          3911: static void
        !          3912: efab_free_resources ( struct efab_nic *efab )
        !          3913: {
        !          3914:        struct efab_ev_queue *ev_queue = &efab->ev_queue;
        !          3915:        struct efab_rx_queue *rx_queue = &efab->rx_queue;
        !          3916:        struct efab_tx_queue *tx_queue = &efab->tx_queue;
        !          3917:        int i;
        !          3918: 
        !          3919:        for ( i = 0; i < EFAB_NUM_RX_DESC; i++ ) {
        !          3920:                if ( rx_queue->buf[i] )
        !          3921:                        free_iob ( rx_queue->buf[i] );
        !          3922:        }
        !          3923: 
        !          3924:        for ( i = 0; i < EFAB_TXD_SIZE; i++ ) {
        !          3925:                if ( tx_queue->buf[i] )
        !          3926:                        netdev_tx_complete ( efab->netdev,  tx_queue->buf[i] );
        !          3927:        }
        !          3928: 
        !          3929:        if ( rx_queue->ring )
        !          3930:                falcon_free_special_buffer ( rx_queue->ring );
        !          3931: 
        !          3932:        if ( tx_queue->ring )
        !          3933:                falcon_free_special_buffer ( tx_queue->ring );
        !          3934: 
        !          3935:        if ( ev_queue->ring )
        !          3936:                falcon_free_special_buffer ( ev_queue->ring );
        !          3937: 
        !          3938:        memset ( rx_queue, 0, sizeof ( *rx_queue ) );
        !          3939:        memset ( tx_queue, 0, sizeof ( *tx_queue ) );
        !          3940:        memset ( ev_queue, 0, sizeof ( *ev_queue ) );
        !          3941: 
        !          3942:        /* Ensure subsequent buffer allocations start at id 0 */
        !          3943:        efab->buffer_head = 0;
        !          3944: }
        !          3945: 
        !          3946: static int
        !          3947: efab_alloc_resources ( struct efab_nic *efab )
        !          3948: {
        !          3949:        struct efab_ev_queue *ev_queue = &efab->ev_queue;
        !          3950:        struct efab_rx_queue *rx_queue = &efab->rx_queue;
        !          3951:        struct efab_tx_queue *tx_queue = &efab->tx_queue;
        !          3952:        size_t bytes;
        !          3953: 
        !          3954:        /* Allocate the hardware event queue */
        !          3955:        bytes = sizeof ( falcon_event_t ) * EFAB_TXD_SIZE;
        !          3956:        ev_queue->ring = falcon_alloc_special_buffer ( efab, bytes,
        !          3957:                                                       &ev_queue->entry );
        !          3958:        if ( !ev_queue->ring )
        !          3959:                goto fail1;
        !          3960: 
        !          3961:        /* Initialise the hardware event queue */
        !          3962:        memset ( ev_queue->ring, 0xff, bytes );
        !          3963: 
        !          3964:        /* Allocate the hardware tx queue */
        !          3965:        bytes = sizeof ( falcon_tx_desc_t ) * EFAB_TXD_SIZE;
        !          3966:        tx_queue->ring = falcon_alloc_special_buffer ( efab, bytes,
        !          3967:                                                       &tx_queue->entry );
        !          3968:        if ( ! tx_queue->ring )
        !          3969:                goto fail2;
        !          3970: 
        !          3971:        /* Allocate the hardware rx queue */
        !          3972:        bytes = sizeof ( falcon_rx_desc_t ) * EFAB_RXD_SIZE;
        !          3973:        rx_queue->ring = falcon_alloc_special_buffer ( efab, bytes,
        !          3974:                                                       &rx_queue->entry );
        !          3975:        if ( ! rx_queue->ring )
        !          3976:                goto fail3;
        !          3977: 
        !          3978:        return 0;
        !          3979: 
        !          3980: fail3:
        !          3981:        falcon_free_special_buffer ( tx_queue->ring );
        !          3982:        tx_queue->ring = NULL;
        !          3983: fail2:
        !          3984:        falcon_free_special_buffer ( ev_queue->ring );
        !          3985:        ev_queue->ring = NULL;
        !          3986: fail1:
        !          3987:        return -ENOMEM;
        !          3988: }
        !          3989: 
        !          3990: static int
        !          3991: efab_init_mac ( struct efab_nic *efab )
        !          3992: {
        !          3993:        int count, rc;
        !          3994: 
        !          3995:        /* This can take several seconds */
        !          3996:        EFAB_LOG ( "Waiting for link..\n" );
        !          3997:        for ( count=0; count<5; count++ ) {
        !          3998:                rc = efab->mac_op->init ( efab );
        !          3999:                if ( rc ) {
        !          4000:                        EFAB_ERR ( "Failed reinitialising MAC, error %s\n",
        !          4001:                                strerror ( rc ));
        !          4002:                        return rc;
        !          4003:                }
        !          4004: 
        !          4005:                /* Sleep for 2s to wait for the link to settle, either
        !          4006:                 * because we want to use it, or because we're about
        !          4007:                 * to reset the mac anyway
        !          4008:                 */
        !          4009:                sleep ( 2 );
        !          4010: 
        !          4011:                if ( ! efab->link_up ) {
        !          4012:                        EFAB_ERR ( "!\n" );
        !          4013:                        continue;
        !          4014:                }
        !          4015: 
        !          4016:                EFAB_LOG ( "\n%dMbps %s-duplex\n",
        !          4017:                           ( efab->link_options & LPA_EF_10000 ? 10000 :
        !          4018:                             ( efab->link_options & LPA_EF_1000 ? 1000 :
        !          4019:                               ( efab->link_options & LPA_100 ? 100 : 10 ) ) ),
        !          4020:                           ( efab->link_options & LPA_EF_DUPLEX ?
        !          4021:                             "full" : "half" ) );
        !          4022: 
        !          4023:                /* TODO: Move link state handling to the poll() routine */
        !          4024:                netdev_link_up ( efab->netdev );
        !          4025:                return 0;
        !          4026:        }
        !          4027: 
        !          4028:        EFAB_ERR ( "timed initialising MAC\n" );
        !          4029:        return -ETIMEDOUT;
        !          4030: }
        !          4031: 
        !          4032: static void
        !          4033: efab_close ( struct net_device *netdev )
        !          4034: {
        !          4035:        struct efab_nic *efab = netdev_priv ( netdev );
        !          4036: 
        !          4037:        falcon_fini_resources ( efab );
        !          4038:        efab_free_resources ( efab );
        !          4039:        efab->board_op->fini ( efab );
        !          4040:        falcon_reset ( efab );
        !          4041: }
        !          4042: 
        !          4043: static int
        !          4044: efab_open ( struct net_device *netdev )
        !          4045: {
        !          4046:        struct efab_nic *efab = netdev_priv ( netdev );
        !          4047:        struct efab_rx_queue *rx_queue = &efab->rx_queue;
        !          4048:        int rc;
        !          4049: 
        !          4050:        rc = falcon_reset ( efab );
        !          4051:        if ( rc )
        !          4052:                goto fail1;
        !          4053: 
        !          4054:        rc = efab->board_op->init ( efab );
        !          4055:        if ( rc )
        !          4056:                goto fail2;
        !          4057:        
        !          4058:        rc = falcon_init_sram ( efab );
        !          4059:        if ( rc )
        !          4060:                goto fail3;
        !          4061: 
        !          4062:        /* Configure descriptor caches before pushing hardware queues */
        !          4063:        falcon_setup_nic ( efab );
        !          4064: 
        !          4065:        rc = efab_alloc_resources ( efab );
        !          4066:        if ( rc )
        !          4067:                goto fail4;
        !          4068:        
        !          4069:        falcon_init_resources ( efab );
        !          4070: 
        !          4071:        /* Push rx buffers */
        !          4072:        rc = efab_fill_rx_queue ( efab, rx_queue );
        !          4073:        if ( rc )
        !          4074:                goto fail5;
        !          4075: 
        !          4076:        /* Try and bring the interface up */
        !          4077:        rc = efab_init_mac ( efab );
        !          4078:        if ( rc )
        !          4079:                goto fail6;
        !          4080: 
        !          4081:        return 0;
        !          4082: 
        !          4083: fail6:
        !          4084: fail5:
        !          4085:        efab_free_resources ( efab );
        !          4086: fail4:
        !          4087: fail3:
        !          4088:        efab->board_op->fini ( efab );
        !          4089: fail2:
        !          4090:        falcon_reset ( efab );
        !          4091: fail1:
        !          4092:        return rc;
        !          4093: }
        !          4094: 
        !          4095: static struct net_device_operations efab_operations = {
        !          4096:         .open           = efab_open,
        !          4097:         .close          = efab_close,
        !          4098:         .transmit       = efab_transmit,
        !          4099:         .poll           = efab_poll,
        !          4100:         .irq            = efab_irq,
        !          4101: };
        !          4102: 
        !          4103: static void
        !          4104: efab_remove ( struct pci_device *pci )
        !          4105: {
        !          4106:        struct net_device *netdev = pci_get_drvdata ( pci );
        !          4107:        struct efab_nic *efab = netdev_priv ( netdev );
        !          4108: 
        !          4109:        if ( efab->membase ) {
        !          4110:                falcon_reset ( efab );
        !          4111: 
        !          4112:                iounmap ( efab->membase );
        !          4113:                efab->membase = NULL;
        !          4114:        }
        !          4115: 
        !          4116:        if ( efab->nvo.nvs ) {
        !          4117:                unregister_nvo ( &efab->nvo );
        !          4118:                efab->nvo.nvs = NULL;
        !          4119:        }
        !          4120: 
        !          4121:        unregister_netdev ( netdev );
        !          4122:        netdev_nullify ( netdev );
        !          4123:        netdev_put ( netdev );
        !          4124: }
        !          4125: 
        !          4126: static int
        !          4127: efab_probe ( struct pci_device *pci )
        !          4128: {
        !          4129:        struct net_device *netdev;
        !          4130:        struct efab_nic *efab;
        !          4131:        unsigned long mmio_start, mmio_len;
        !          4132:        int rc;
        !          4133: 
        !          4134:        /* Create the network adapter */
        !          4135:        netdev = alloc_etherdev ( sizeof ( struct efab_nic ) );
        !          4136:        if ( ! netdev ) {
        !          4137:                rc = -ENOMEM;
        !          4138:                goto fail1;
        !          4139:        }
        !          4140: 
        !          4141:        /* Initialise the network adapter, and initialise private storage */
        !          4142:        netdev_init ( netdev, &efab_operations );
        !          4143:        pci_set_drvdata ( pci, netdev );
        !          4144:        netdev->dev = &pci->dev;
        !          4145: 
        !          4146:        efab = netdev_priv ( netdev );
        !          4147:        memset ( efab, 0, sizeof ( *efab ) );
        !          4148:        efab->netdev = netdev;
        !          4149: 
        !          4150:        /* Get iobase/membase */
        !          4151:        mmio_start = pci_bar_start ( pci, PCI_BASE_ADDRESS_2 );
        !          4152:        mmio_len = pci_bar_size ( pci, PCI_BASE_ADDRESS_2 );
        !          4153:        efab->membase = ioremap ( mmio_start, mmio_len );
        !          4154:        EFAB_TRACE ( "BAR of %lx bytes at phys %lx mapped at %p\n",
        !          4155:                     mmio_len, mmio_start, efab->membase );
        !          4156: 
        !          4157:        /* Enable the PCI device */
        !          4158:        adjust_pci_device ( pci );
        !          4159:        efab->iobase = pci->ioaddr & ~3;
        !          4160: 
        !          4161:        /* Determine the NIC variant */
        !          4162:        falcon_probe_nic_variant ( efab, pci );
        !          4163: 
        !          4164:        /* Read the SPI interface and determine the MAC address,
        !          4165:         * and the board and phy variant. Hook in the op tables */
        !          4166:        rc = falcon_probe_spi ( efab );
        !          4167:        if ( rc )
        !          4168:                goto fail2;
        !          4169:        rc = falcon_probe_nvram ( efab );
        !          4170:        if ( rc )
        !          4171:                goto fail3;
        !          4172: 
        !          4173:        memcpy ( netdev->hw_addr, efab->mac_addr, ETH_ALEN );
        !          4174: 
        !          4175:        rc = register_netdev ( netdev );
        !          4176:        if ( rc )
        !          4177:                goto fail4;
        !          4178:        netdev_link_up ( netdev );
        !          4179: 
        !          4180:        /* Advertise non-volatile storage */
        !          4181:        if ( efab->nvo.nvs ) {
        !          4182:                rc = register_nvo ( &efab->nvo, netdev_settings ( netdev ) );
        !          4183:                if ( rc )
        !          4184:                        goto fail5;
        !          4185:        }
        !          4186: 
        !          4187:        EFAB_LOG ( "Found %s EtherFabric %s %s revision %d\n", pci->id->name,
        !          4188:                   efab->is_asic ? "ASIC" : "FPGA",
        !          4189:                   efab->phy_10g ? "10G" : "1G",
        !          4190:                   efab->pci_revision );
        !          4191: 
        !          4192:        return 0;
        !          4193: 
        !          4194: fail5:
        !          4195:        unregister_netdev ( netdev );
        !          4196: fail4:
        !          4197: fail3:
        !          4198: fail2:
        !          4199:        iounmap ( efab->membase );
        !          4200:        efab->membase = NULL;
        !          4201:        netdev_put ( netdev );
        !          4202: fail1:
        !          4203:        return rc;
        !          4204: }
        !          4205: 
        !          4206: 
        !          4207: static struct pci_device_id efab_nics[] = {
        !          4208:        PCI_ROM(0x1924, 0x0703, "falcon", "EtherFabric Falcon", 0),
        !          4209:        PCI_ROM(0x1924, 0x0710, "falconb0", "EtherFabric FalconB0", 0),
        !          4210: };
        !          4211: 
        !          4212: struct pci_driver etherfabric_driver __pci_driver = {
        !          4213:        .ids = efab_nics,
        !          4214:        .id_count = sizeof ( efab_nics ) / sizeof ( efab_nics[0] ),
        !          4215:        .probe = efab_probe,
        !          4216:        .remove = efab_remove,
        !          4217: };
        !          4218: 
        !          4219: /*
        !          4220:  * Local variables:
        !          4221:  *  c-basic-offset: 8
        !          4222:  *  c-indent-level: 8
        !          4223:  *  tab-width: 8
        !          4224:  * End:
        !          4225:  */

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