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1.1 root 1: /*
2: * forcedeth.c -- Driver for NVIDIA nForce media access controllers for iPXE
3: * Copyright (c) 2010 Andrei Faur <[email protected]>
4: *
5: * This program is free software; you can redistribute it and/or
6: * modify it under the terms of the GNU General Public License as
7: * published by the Free Software Foundation; either version 2 of the
8: * License, or any later version.
9: *
10: * This program is distributed in the hope that it will be useful, but
11: * WITHOUT ANY WARRANTY; without even the implied warranty of
12: * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
13: * General Public License for more details.
14: *
15: * You should have received a copy of the GNU General Public License
16: * along with this program; if not, write to the Free Software
17: * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
18: *
19: * Portions of this code are taken from the Linux forcedeth driver that was
20: * based on a cleanroom reimplementation which was based on reverse engineered
21: * documentation written by Carl-Daniel Hailfinger and Andrew de Quincey:
22: * Copyright (C) 2003,4,5 Manfred Spraul
23: * Copyright (C) 2004 Andrew de Quincey (wol support)
24: * Copyright (C) 2004 Carl-Daniel Hailfinger (invalid MAC handling, insane
25: * IRQ rate fixes, bigendian fixes, cleanups, verification)
26: * Copyright (c) 2004,2005,2006,2007,2008,2009 NVIDIA Corporation
27: *
28: * The probe, remove, open and close functions, along with the functions they
29: * call, are direct copies of the above mentioned driver, modified where
30: * necessary to make them work for iPXE.
31: *
32: * The poll and transmit functions were completely rewritten to make use of
33: * the iPXE API. This process was aided by constant referencing of the above
34: * mentioned Linux driver. This driver would not have been possible without this
35: * prior work.
36: *
37: */
38:
39: FILE_LICENCE ( GPL2_OR_LATER );
40:
41: #include <stdint.h>
42: #include <stdio.h>
43: #include <stdlib.h>
44: #include <string.h>
45: #include <unistd.h>
46: #include <assert.h>
47: #include <byteswap.h>
48: #include <errno.h>
49: #include <ipxe/ethernet.h>
50: #include <ipxe/if_ether.h>
51: #include <ipxe/io.h>
52: #include <ipxe/iobuf.h>
53: #include <ipxe/malloc.h>
54: #include <ipxe/netdevice.h>
55: #include <ipxe/crypto.h>
56: #include <ipxe/pci.h>
57: #include <ipxe/timer.h>
58: #include <mii.h>
59: #include "forcedeth.h"
60:
61: static inline void pci_push ( void *ioaddr )
62: {
63: /* force out pending posted writes */
64: readl ( ioaddr );
65: }
66:
67: static int
68: reg_delay ( struct forcedeth_private *priv, int offset, u32 mask,
69: u32 target, int delay, int delaymax, const char *msg )
70: {
71: void *ioaddr = priv->mmio_addr;
72:
73: pci_push ( ioaddr );
74: do {
75: udelay ( delay );
76: delaymax -= delay;
77: if ( delaymax < 0 ) {
78: if ( msg )
79: DBG ( "%s\n", msg );
80: return 1;
81: }
82: } while ( ( readl ( ioaddr + offset ) & mask ) != target );
83:
84: return 0;
85: }
86:
87: /* read/write a register on the PHY */
88: static int
89: mii_rw ( struct forcedeth_private *priv, int addr, int miireg, int value )
90: {
91: void *ioaddr = priv->mmio_addr;
92: u32 reg;
93: int retval;
94:
95: writel ( NVREG_MIISTAT_MASK_RW, ioaddr + NvRegMIIStatus );
96:
97: reg = readl ( ioaddr + NvRegMIIControl );
98: if ( reg & NVREG_MIICTL_INUSE ) {
99: writel ( NVREG_MIICTL_INUSE, ioaddr + NvRegMIIControl );
100: udelay ( NV_MIIBUSY_DELAY );
101: }
102:
103: reg = ( addr << NVREG_MIICTL_ADDRSHIFT ) | miireg;
104: if ( value != MII_READ ) {
105: writel ( value, ioaddr + NvRegMIIData );
106: reg |= NVREG_MIICTL_WRITE;
107: }
108: writel ( reg, ioaddr + NvRegMIIControl );
109:
110: if ( reg_delay ( priv, NvRegMIIControl, NVREG_MIICTL_INUSE, 0,
111: NV_MIIPHY_DELAY, NV_MIIPHY_DELAYMAX, NULL ) ) {
112: DBG ( "mii_rw of reg %d at PHY %d timed out.\n",
113: miireg, addr );
114: retval = -1;
115: } else if ( value != MII_READ ) {
116: /* it was a write operation - fewer failures are detectable */
117: DBG ( "mii_rw wrote 0x%x to reg %d at PHY %d\n",
118: value, miireg, addr );
119: retval = 0;
120: } else if ( readl ( ioaddr + NvRegMIIStatus ) & NVREG_MIISTAT_ERROR ) {
121: DBG ( "mii_rw of reg %d at PHY %d failed.\n",
122: miireg, addr );
123: retval = -1;
124: } else {
125: retval = readl ( ioaddr + NvRegMIIData );
126: DBG ( "mii_rw read from reg %d at PHY %d: 0x%x.\n",
127: miireg, addr, retval );
128: }
129:
130: return retval;
131: }
132:
133: static void
134: nv_txrx_gate ( struct forcedeth_private *priv, int gate )
135: {
136: void *ioaddr = priv->mmio_addr;
137: u32 powerstate;
138:
139: if ( ! priv->mac_in_use &&
140: ( priv->driver_data & DEV_HAS_POWER_CNTRL ) ) {
141: powerstate = readl ( ioaddr + NvRegPowerState2 );
142: if ( gate )
143: powerstate |= NVREG_POWERSTATE2_GATE_CLOCKS;
144: else
145: powerstate &= ~NVREG_POWERSTATE2_GATE_CLOCKS;
146: writel ( powerstate, ioaddr + NvRegPowerState2 );
147: }
148: }
149:
150: static void
151: nv_mac_reset ( struct forcedeth_private * priv )
152: {
153: void *ioaddr = priv->mmio_addr;
154: u32 temp1, temp2, temp3;
155:
156: writel ( NVREG_TXRXCTL_BIT2 | NVREG_TXRXCTL_RESET | NVREG_TXRXCTL_DESC_1,
157: ioaddr + NvRegTxRxControl );
158: pci_push ( ioaddr );
159:
160: /* save registers since they will be cleared on reset */
161: temp1 = readl ( ioaddr + NvRegMacAddrA );
162: temp2 = readl ( ioaddr + NvRegMacAddrB );
163: temp3 = readl ( ioaddr + NvRegTransmitPoll );
164:
165: writel ( NVREG_MAC_RESET_ASSERT, ioaddr + NvRegMacReset );
166: pci_push ( ioaddr );
167: udelay ( NV_MAC_RESET_DELAY );
168: writel ( 0, ioaddr + NvRegMacReset );
169: pci_push ( ioaddr );
170: udelay ( NV_MAC_RESET_DELAY );
171:
172: /* restore saved registers */
173: writel ( temp1, ioaddr + NvRegMacAddrA );
174: writel ( temp2, ioaddr + NvRegMacAddrB );
175: writel ( temp3, ioaddr + NvRegTransmitPoll );
176:
177: writel ( NVREG_TXRXCTL_BIT2 | NVREG_TXRXCTL_DESC_1,
178: ioaddr + NvRegTxRxControl );
179: pci_push ( ioaddr );
180: }
181:
182: static void
183: nv_init_tx_ring ( struct forcedeth_private *priv )
184: {
185: int i;
186:
187: for ( i = 0; i < TX_RING_SIZE; i++ ) {
188: priv->tx_ring[i].flaglen = 0;
189: priv->tx_ring[i].buf = 0;
190: priv->tx_iobuf[i] = NULL;
191: }
192:
193: priv->tx_fill_ctr = 0;
194: priv->tx_curr = 0;
195: priv->tx_tail = 0;
196: }
197:
198: /**
199: * nv_alloc_rx - Allocates iobufs for every Rx descriptor
200: * that doesn't have one and isn't in use by the hardware
201: *
202: * @v priv Driver private structure
203: */
204: static void
205: nv_alloc_rx ( struct forcedeth_private *priv )
206: {
207: struct ring_desc *rx_curr_desc;
208: int i;
209: u32 status;
210:
211: DBGP ( "nv_alloc_rx\n" );
212:
213: for ( i = 0; i < RX_RING_SIZE; i++ ) {
214: rx_curr_desc = priv->rx_ring + i;
215: status = le32_to_cpu ( rx_curr_desc->flaglen );
216:
217: /* Don't touch the descriptors owned by the hardware */
218: if ( status & NV_RX_AVAIL )
219: continue;
220:
221: /* Descriptors with iobufs still need to be processed */
222: if ( priv->rx_iobuf[i] != NULL )
223: continue;
224:
225: /* If alloc_iob fails, try again later (next poll) */
226: if ( ! ( priv->rx_iobuf[i] = alloc_iob ( RX_BUF_SZ ) ) ) {
227: DBG ( "Refill rx_ring failed, size %d\n", RX_BUF_SZ );
228: break;
229: }
230:
231: rx_curr_desc->buf =
232: cpu_to_le32 ( virt_to_bus ( priv->rx_iobuf[i]->data ) );
233: wmb();
234: rx_curr_desc->flaglen =
235: cpu_to_le32 ( RX_BUF_SZ | NV_RX_AVAIL );
236: }
237: }
238:
239: static void
240: nv_init_rx_ring ( struct forcedeth_private *priv )
241: {
242: int i;
243:
244: for ( i = 0; i < RX_RING_SIZE; i++ ) {
245: priv->rx_ring[i].flaglen = 0;
246: priv->rx_ring[i].buf = 0;
247: priv->rx_iobuf[i] = NULL;
248: }
249:
250: priv->rx_curr = 0;
251: }
252:
253: /**
254: * nv_init_rings - Allocate and intialize descriptor rings
255: *
256: * @v priv Driver private structure
257: *
258: * @ret rc Return status code
259: **/
260: static int
261: nv_init_rings ( struct forcedeth_private *priv )
262: {
263: void *ioaddr = priv->mmio_addr;
264: int rc = -ENOMEM;
265:
266: /* Allocate ring for both TX and RX */
267: priv->rx_ring =
268: malloc_dma ( sizeof(struct ring_desc) * RXTX_RING_SIZE, 32 );
269: if ( ! priv->rx_ring )
270: goto err_malloc;
271: priv->tx_ring = &priv->rx_ring[RX_RING_SIZE];
272:
273: /* Initialize rings */
274: nv_init_tx_ring ( priv );
275: nv_init_rx_ring ( priv );
276:
277: /* Allocate iobufs for RX */
278: nv_alloc_rx ( priv );
279:
280: /* Give hw rings */
281: writel ( cpu_to_le32 ( virt_to_bus ( priv->rx_ring ) ),
282: ioaddr + NvRegRxRingPhysAddr );
283: writel ( cpu_to_le32 ( virt_to_bus ( priv->tx_ring ) ),
284: ioaddr + NvRegTxRingPhysAddr );
285:
286: DBG ( "RX ring at phys addr: %#08lx\n",
287: virt_to_bus ( priv->rx_ring ) );
288: DBG ( "TX ring at phys addr: %#08lx\n",
289: virt_to_bus ( priv->tx_ring ) );
290:
291: writel ( ( ( RX_RING_SIZE - 1 ) << NVREG_RINGSZ_RXSHIFT ) +
292: ( ( TX_RING_SIZE - 1 ) << NVREG_RINGSZ_TXSHIFT ),
293: ioaddr + NvRegRingSizes );
294:
295: return 0;
296:
297: err_malloc:
298: DBG ( "Could not allocate descriptor rings\n");
299: return rc;
300: }
301:
302: static void
303: nv_free_rxtx_resources ( struct forcedeth_private *priv )
304: {
305: int i;
306:
307: DBGP ( "nv_free_rxtx_resources\n" );
308:
309: free_dma ( priv->rx_ring, sizeof(struct ring_desc) * RXTX_RING_SIZE );
310:
311: for ( i = 0; i < RX_RING_SIZE; i++ ) {
312: free_iob ( priv->rx_iobuf[i] );
313: priv->rx_iobuf[i] = NULL;
314: }
315: }
316:
317: static void
318: nv_txrx_reset ( struct forcedeth_private *priv )
319: {
320: void *ioaddr = priv->mmio_addr;
321:
322: writel ( NVREG_TXRXCTL_BIT2 | NVREG_TXRXCTL_RESET | NVREG_TXRXCTL_DESC_1,
323: ioaddr + NvRegTxRxControl );
324: pci_push ( ioaddr );
325: udelay ( NV_TXRX_RESET_DELAY );
326: writel ( NVREG_TXRXCTL_BIT2 | NVREG_TXRXCTL_DESC_1,
327: ioaddr + NvRegTxRxControl );
328: pci_push ( ioaddr );
329: }
330:
331: static void
332: nv_disable_hw_interrupts ( struct forcedeth_private *priv )
333: {
334: void *ioaddr = priv->mmio_addr;
335:
336: writel ( 0, ioaddr + NvRegIrqMask );
337: }
338:
339: static void
340: nv_enable_hw_interrupts ( struct forcedeth_private *priv )
341: {
342: void *ioaddr = priv->mmio_addr;
343:
344: writel ( NVREG_IRQMASK_THROUGHPUT, ioaddr + NvRegIrqMask );
345: }
346:
347: static void
348: nv_start_rx ( struct forcedeth_private *priv )
349: {
350: void *ioaddr = priv->mmio_addr;
351: u32 rx_ctrl = readl ( ioaddr + NvRegReceiverControl );
352:
353: DBGP ( "nv_start_rx\n" );
354: /* Already running? Stop it. */
355: if ( ( readl ( ioaddr + NvRegReceiverControl ) & NVREG_RCVCTL_START ) && !priv->mac_in_use ) {
356: rx_ctrl &= ~NVREG_RCVCTL_START;
357: writel ( rx_ctrl, ioaddr + NvRegReceiverControl );
358: pci_push ( ioaddr );
359: }
360: writel ( priv->linkspeed, ioaddr + NvRegLinkSpeed );
361: pci_push ( ioaddr );
362: rx_ctrl |= NVREG_RCVCTL_START;
363: if ( priv->mac_in_use )
364: rx_ctrl &= ~NVREG_RCVCTL_RX_PATH_EN;
365: writel ( rx_ctrl, ioaddr + NvRegReceiverControl );
366: DBG ( "nv_start_rx to duplex %d, speed 0x%08x.\n",
367: priv->duplex, priv->linkspeed);
368: pci_push ( ioaddr );
369: }
370:
371: static void
372: nv_stop_rx ( struct forcedeth_private *priv )
373: {
374: void *ioaddr = priv->mmio_addr;
375: u32 rx_ctrl = readl ( ioaddr + NvRegReceiverControl );
376:
377: DBGP ( "nv_stop_rx\n" );
378: if ( ! priv->mac_in_use )
379: rx_ctrl &= ~NVREG_RCVCTL_START;
380: else
381: rx_ctrl |= NVREG_RCVCTL_RX_PATH_EN;
382: writel ( rx_ctrl, ioaddr + NvRegReceiverControl );
383: reg_delay ( priv, NvRegReceiverStatus, NVREG_RCVSTAT_BUSY, 0,
384: NV_RXSTOP_DELAY1, NV_RXSTOP_DELAY1MAX,
385: "nv_stop_rx: ReceiverStatus remained busy");
386:
387: udelay ( NV_RXSTOP_DELAY2 );
388: if ( ! priv->mac_in_use )
389: writel ( 0, priv + NvRegLinkSpeed );
390: }
391:
392: static void
393: nv_start_tx ( struct forcedeth_private *priv )
394: {
395: void *ioaddr = priv->mmio_addr;
396: u32 tx_ctrl = readl ( ioaddr + NvRegTransmitterControl );
397:
398: DBGP ( "nv_start_tx\n" );
399: tx_ctrl |= NVREG_XMITCTL_START;
400: if ( priv->mac_in_use )
401: tx_ctrl &= ~NVREG_XMITCTL_TX_PATH_EN;
402: writel ( tx_ctrl, ioaddr + NvRegTransmitterControl );
403: pci_push ( ioaddr );
404: }
405:
406: static void
407: nv_stop_tx ( struct forcedeth_private *priv )
408: {
409: void *ioaddr = priv->mmio_addr;
410: u32 tx_ctrl = readl ( ioaddr + NvRegTransmitterControl );
411:
412: DBGP ( "nv_stop_tx");
413:
414: if ( ! priv->mac_in_use )
415: tx_ctrl &= ~NVREG_XMITCTL_START;
416: else
417: tx_ctrl |= NVREG_XMITCTL_TX_PATH_EN;
418: writel ( tx_ctrl, ioaddr + NvRegTransmitterControl );
419: reg_delay ( priv, NvRegTransmitterStatus, NVREG_XMITSTAT_BUSY, 0,
420: NV_TXSTOP_DELAY1, NV_TXSTOP_DELAY1MAX,
421: "nv_stop_tx: TransmitterStatus remained busy");
422:
423: udelay ( NV_TXSTOP_DELAY2 );
424: if ( ! priv->mac_in_use )
425: writel( readl ( ioaddr + NvRegTransmitPoll) &
426: NVREG_TRANSMITPOLL_MAC_ADDR_REV,
427: ioaddr + NvRegTransmitPoll);
428: }
429:
430:
431: static void
432: nv_update_pause ( struct forcedeth_private *priv, u32 pause_flags )
433: {
434: void *ioaddr = priv->mmio_addr;
435:
436: priv->pause_flags &= ~ ( NV_PAUSEFRAME_TX_ENABLE |
437: NV_PAUSEFRAME_RX_ENABLE );
438:
439: if ( priv->pause_flags & NV_PAUSEFRAME_RX_CAPABLE ) {
440: u32 pff = readl ( ioaddr + NvRegPacketFilterFlags ) & ~NVREG_PFF_PAUSE_RX;
441: if ( pause_flags & NV_PAUSEFRAME_RX_ENABLE ) {
442: writel ( pff | NVREG_PFF_PAUSE_RX, ioaddr + NvRegPacketFilterFlags );
443: priv->pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
444: } else {
445: writel ( pff, ioaddr + NvRegPacketFilterFlags );
446: }
447: }
448: if ( priv->pause_flags & NV_PAUSEFRAME_TX_CAPABLE ) {
449: u32 regmisc = readl ( ioaddr + NvRegMisc1 ) & ~NVREG_MISC1_PAUSE_TX;
450: if ( pause_flags & NV_PAUSEFRAME_TX_ENABLE ) {
451: u32 pause_enable = NVREG_TX_PAUSEFRAME_ENABLE_V1;
452: if ( priv->driver_data & DEV_HAS_PAUSEFRAME_TX_V2 )
453: pause_enable = NVREG_TX_PAUSEFRAME_ENABLE_V2;
454: if ( priv->driver_data & DEV_HAS_PAUSEFRAME_TX_V3 ) {
455: pause_enable = NVREG_TX_PAUSEFRAME_ENABLE_V3;
456: /* limit the number of tx pause frames to a default of 8 */
457: writel ( readl ( ioaddr + NvRegTxPauseFrameLimit ) |
458: NVREG_TX_PAUSEFRAMELIMIT_ENABLE,
459: ioaddr + NvRegTxPauseFrameLimit );
460: }
461: writel ( pause_enable, ioaddr + NvRegTxPauseFrame );
462: writel ( regmisc | NVREG_MISC1_PAUSE_TX, ioaddr + NvRegMisc1 );
463: priv->pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
464: } else {
465: writel ( NVREG_TX_PAUSEFRAME_DISABLE, ioaddr + NvRegTxPauseFrame );
466: writel ( regmisc, ioaddr + NvRegMisc1 );
467: }
468: }
469: }
470:
471: static int
472: nv_update_linkspeed ( struct forcedeth_private *priv )
473: {
474: void *ioaddr = priv->mmio_addr;
475: int adv = 0;
476: int lpa = 0;
477: int adv_lpa, adv_pause, lpa_pause;
478: u32 newls = priv->linkspeed;
479: int newdup = priv->duplex;
480: int mii_status;
481: int retval = 0;
482: u32 control_1000, status_1000, phyreg, pause_flags, txreg;
483: u32 txrxFlags = 0;
484: u32 phy_exp;
485:
486: /* BMSR_LSTATUS is latched, read it twice:
487: * we want the current value.
488: */
489: mii_rw ( priv, priv->phyaddr, MII_BMSR, MII_READ );
490: mii_status = mii_rw ( priv, priv->phyaddr, MII_BMSR, MII_READ );
491:
492: if ( ! ( mii_status & BMSR_LSTATUS ) ) {
493: DBG ( "No link detected by phy - falling back to 10HD.\n" );
494: newls = NVREG_LINKSPEED_FORCE | NVREG_LINKSPEED_10;
495: newdup = 0;
496: retval = 0;
497: goto set_speed;
498: }
499:
500: /* check auto negotiation is complete */
501: if ( ! ( mii_status & BMSR_ANEGCOMPLETE ) ) {
502: /* still in autonegotiation - configure nic for 10 MBit HD and wait. */
503: newls = NVREG_LINKSPEED_FORCE | NVREG_LINKSPEED_10;
504: newdup = 0;
505: retval = 0;
506: DBG ( "autoneg not completed - falling back to 10HD.\n" );
507: goto set_speed;
508: }
509:
510: adv = mii_rw ( priv, priv->phyaddr, MII_ADVERTISE, MII_READ );
511: lpa = mii_rw ( priv, priv->phyaddr, MII_LPA, MII_READ );
512: DBG ( "nv_update_linkspeed: PHY advertises 0x%04x, lpa 0x%04x.\n", adv, lpa );
513:
514: retval = 1;
515: if ( priv->gigabit == PHY_GIGABIT ) {
516: control_1000 = mii_rw ( priv, priv->phyaddr, MII_CTRL1000, MII_READ);
517: status_1000 = mii_rw ( priv, priv->phyaddr, MII_STAT1000, MII_READ);
518:
519: if ( ( control_1000 & ADVERTISE_1000FULL ) &&
520: ( status_1000 & LPA_1000FULL ) ) {
521: DBG ( "nv_update_linkspeed: GBit ethernet detected.\n" );
522: newls = NVREG_LINKSPEED_FORCE | NVREG_LINKSPEED_1000;
523: newdup = 1;
524: goto set_speed;
525: }
526: }
527:
528: /* FIXME: handle parallel detection properly */
529: adv_lpa = lpa & adv;
530: if ( adv_lpa & LPA_100FULL ) {
531: newls = NVREG_LINKSPEED_FORCE | NVREG_LINKSPEED_100;
532: newdup = 1;
533: } else if ( adv_lpa & LPA_100HALF ) {
534: newls = NVREG_LINKSPEED_FORCE | NVREG_LINKSPEED_100;
535: newdup = 0;
536: } else if ( adv_lpa & LPA_10FULL ) {
537: newls = NVREG_LINKSPEED_FORCE | NVREG_LINKSPEED_10;
538: newdup = 1;
539: } else if ( adv_lpa & LPA_10HALF ) {
540: newls = NVREG_LINKSPEED_FORCE | NVREG_LINKSPEED_10;
541: newdup = 0;
542: } else {
543: DBG ( "bad ability %04x - falling back to 10HD.\n", adv_lpa);
544: newls = NVREG_LINKSPEED_FORCE | NVREG_LINKSPEED_10;
545: newdup = 0;
546: }
547:
548: set_speed:
549: if ( priv->duplex == newdup && priv->linkspeed == newls )
550: return retval;
551:
552: DBG ( "changing link setting from %d/%d to %d/%d.\n",
553: priv->linkspeed, priv->duplex, newls, newdup);
554:
555: priv->duplex = newdup;
556: priv->linkspeed = newls;
557:
558: /* The transmitter and receiver must be restarted for safe update */
559: if ( readl ( ioaddr + NvRegTransmitterControl ) & NVREG_XMITCTL_START ) {
560: txrxFlags |= NV_RESTART_TX;
561: nv_stop_tx ( priv );
562: }
563: if ( readl ( ioaddr + NvRegReceiverControl ) & NVREG_RCVCTL_START) {
564: txrxFlags |= NV_RESTART_RX;
565: nv_stop_rx ( priv );
566: }
567:
568: if ( priv->gigabit == PHY_GIGABIT ) {
569: phyreg = readl ( ioaddr + NvRegSlotTime );
570: phyreg &= ~(0x3FF00);
571: if ( ( ( priv->linkspeed & 0xFFF ) == NVREG_LINKSPEED_10 ) ||
572: ( ( priv->linkspeed & 0xFFF ) == NVREG_LINKSPEED_100) )
573: phyreg |= NVREG_SLOTTIME_10_100_FULL;
574: else if ( ( priv->linkspeed & 0xFFF ) == NVREG_LINKSPEED_1000 )
575: phyreg |= NVREG_SLOTTIME_1000_FULL;
576: writel( phyreg, priv + NvRegSlotTime );
577: }
578:
579: phyreg = readl ( ioaddr + NvRegPhyInterface );
580: phyreg &= ~( PHY_HALF | PHY_100 | PHY_1000 );
581: if ( priv->duplex == 0 )
582: phyreg |= PHY_HALF;
583: if ( ( priv->linkspeed & NVREG_LINKSPEED_MASK ) == NVREG_LINKSPEED_100 )
584: phyreg |= PHY_100;
585: else if ( ( priv->linkspeed & NVREG_LINKSPEED_MASK ) == NVREG_LINKSPEED_1000 )
586: phyreg |= PHY_1000;
587: writel ( phyreg, ioaddr + NvRegPhyInterface );
588:
589: phy_exp = mii_rw ( priv, priv->phyaddr, MII_EXPANSION, MII_READ ) & EXPANSION_NWAY; /* autoneg capable */
590: if ( phyreg & PHY_RGMII ) {
591: if ( ( priv->linkspeed & NVREG_LINKSPEED_MASK ) == NVREG_LINKSPEED_1000 ) {
592: txreg = NVREG_TX_DEFERRAL_RGMII_1000;
593: } else {
594: if ( !phy_exp && !priv->duplex && ( priv->driver_data & DEV_HAS_COLLISION_FIX ) ) {
595: if ( ( priv->linkspeed & NVREG_LINKSPEED_MASK ) == NVREG_LINKSPEED_10 )
596: txreg = NVREG_TX_DEFERRAL_RGMII_STRETCH_10;
597: else
598: txreg = NVREG_TX_DEFERRAL_RGMII_STRETCH_100;
599: } else {
600: txreg = NVREG_TX_DEFERRAL_RGMII_10_100;
601: }
602: }
603: } else {
604: if ( !phy_exp && !priv->duplex && ( priv->driver_data & DEV_HAS_COLLISION_FIX ) )
605: txreg = NVREG_TX_DEFERRAL_MII_STRETCH;
606: else
607: txreg = NVREG_TX_DEFERRAL_DEFAULT;
608: }
609: writel ( txreg, ioaddr + NvRegTxDeferral );
610:
611: txreg = NVREG_TX_WM_DESC1_DEFAULT;
612: writel ( txreg, ioaddr + NvRegTxWatermark );
613:
614: writel ( NVREG_MISC1_FORCE | ( priv->duplex ? 0 : NVREG_MISC1_HD ), ioaddr + NvRegMisc1 );
615: pci_push ( ioaddr );
616: writel ( priv->linkspeed, priv + NvRegLinkSpeed);
617: pci_push ( ioaddr );
618:
619: pause_flags = 0;
620: /* setup pause frame */
621: if ( priv->duplex != 0 ) {
622: if ( priv->pause_flags & NV_PAUSEFRAME_AUTONEG ) {
623: adv_pause = adv & ( ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM );
624: lpa_pause = lpa & ( LPA_PAUSE_CAP | LPA_PAUSE_ASYM );
625:
626: switch ( adv_pause ) {
627: case ADVERTISE_PAUSE_CAP:
628: if ( lpa_pause & LPA_PAUSE_CAP ) {
629: pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
630: if ( priv->pause_flags & NV_PAUSEFRAME_TX_REQ )
631: pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
632: }
633: break;
634: case ADVERTISE_PAUSE_ASYM:
635: if ( lpa_pause == ( LPA_PAUSE_CAP | LPA_PAUSE_ASYM ) )
636: {
637: pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
638: }
639: break;
640: case ADVERTISE_PAUSE_CAP| ADVERTISE_PAUSE_ASYM:
641: if ( lpa_pause & LPA_PAUSE_CAP )
642: {
643: pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
644: if ( priv->pause_flags & NV_PAUSEFRAME_TX_REQ )
645: pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
646: }
647: if ( lpa_pause == LPA_PAUSE_ASYM )
648: {
649: pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
650: }
651: break;
652: }
653: } else {
654: pause_flags = priv->pause_flags;
655: }
656: }
657: nv_update_pause ( priv, pause_flags );
658:
659: if ( txrxFlags & NV_RESTART_TX )
660: nv_start_tx ( priv );
661: if ( txrxFlags & NV_RESTART_RX )
662: nv_start_rx ( priv );
663:
664: return retval;
665: }
666:
667:
668: /**
669: * open - Called when a network interface is made active
670: *
671: * @v netdev Network device
672: * @ret rc Return status code, 0 on success, negative value on failure
673: **/
674: static int
675: forcedeth_open ( struct net_device *netdev )
676: {
677: struct forcedeth_private *priv = netdev_priv ( netdev );
678: void *ioaddr = priv->mmio_addr;
679: int i;
680: int rc;
681: u32 low;
682:
683: DBGP ( "forcedeth_open\n" );
684:
685: /* Power up phy */
686: mii_rw ( priv, priv->phyaddr, MII_BMCR,
687: mii_rw ( priv, priv->phyaddr, MII_BMCR, MII_READ ) & ~BMCR_PDOWN );
688:
689: nv_txrx_gate ( priv, 0 );
690:
691: /* Erase previous misconfiguration */
692: if ( priv->driver_data & DEV_HAS_POWER_CNTRL )
693: nv_mac_reset ( priv );
694:
695: /* Clear multicast masks and addresses, enter promiscuous mode */
696: writel ( 0, ioaddr + NvRegMulticastAddrA );
697: writel ( 0, ioaddr + NvRegMulticastAddrB );
698: writel ( NVREG_MCASTMASKA_NONE, ioaddr + NvRegMulticastMaskA );
699: writel ( NVREG_MCASTMASKB_NONE, ioaddr + NvRegMulticastMaskB );
700: writel ( NVREG_PFF_PROMISC, ioaddr + NvRegPacketFilterFlags );
701:
702: writel ( 0, ioaddr + NvRegTransmitterControl );
703: writel ( 0, ioaddr + NvRegReceiverControl );
704:
705: writel ( 0, ioaddr + NvRegAdapterControl );
706:
707: writel ( 0, ioaddr + NvRegLinkSpeed );
708: writel ( readl ( ioaddr + NvRegTransmitPoll ) & NVREG_TRANSMITPOLL_MAC_ADDR_REV,
709: ioaddr + NvRegTransmitPoll );
710: nv_txrx_reset ( priv );
711: writel ( 0, ioaddr + NvRegUnknownSetupReg6 );
712:
713: /* Initialize descriptor rings */
714: if ( ( rc = nv_init_rings ( priv ) ) != 0 )
715: goto err_init_rings;
716:
717: writel ( priv->linkspeed, ioaddr + NvRegLinkSpeed );
718: writel ( NVREG_TX_WM_DESC1_DEFAULT, ioaddr + NvRegTxWatermark );
719: writel ( NVREG_TXRXCTL_DESC_1, ioaddr + NvRegTxRxControl );
720: writel ( 0 , ioaddr + NvRegVlanControl );
721: pci_push ( ioaddr );
722: writel ( NVREG_TXRXCTL_BIT1 | NVREG_TXRXCTL_DESC_1,
723: ioaddr + NvRegTxRxControl );
724: reg_delay ( priv, NvRegUnknownSetupReg5, NVREG_UNKSETUP5_BIT31,
725: NVREG_UNKSETUP5_BIT31, NV_SETUP5_DELAY, NV_SETUP5_DELAYMAX,
726: "open: SetupReg5, Bit 31 remained off\n" );
727:
728: writel ( 0, ioaddr + NvRegMIIMask );
729: writel ( NVREG_IRQSTAT_MASK, ioaddr + NvRegIrqStatus );
730: writel ( NVREG_MIISTAT_MASK_ALL, ioaddr + NvRegMIIStatus );
731:
732: writel ( NVREG_MISC1_FORCE | NVREG_MISC1_HD, ioaddr + NvRegMisc1 );
733: writel ( readl ( ioaddr + NvRegTransmitterStatus ),
734: ioaddr + NvRegTransmitterStatus );
735: writel ( RX_BUF_SZ, ioaddr + NvRegOffloadConfig );
736:
737: writel ( readl ( ioaddr + NvRegReceiverStatus),
738: ioaddr + NvRegReceiverStatus );
739:
740: /* Set up slot time */
741: get_random_bytes ( &low, sizeof(low) );
742: low &= NVREG_SLOTTIME_MASK;
743: writel ( low | NVREG_SLOTTIME_DEFAULT, ioaddr + NvRegSlotTime );
744:
745: writel ( NVREG_TX_DEFERRAL_DEFAULT , ioaddr + NvRegTxDeferral );
746: writel ( NVREG_RX_DEFERRAL_DEFAULT , ioaddr + NvRegRxDeferral );
747:
748: writel ( NVREG_POLL_DEFAULT_THROUGHPUT, ioaddr + NvRegPollingInterval );
749:
750: writel ( NVREG_UNKSETUP6_VAL, ioaddr + NvRegUnknownSetupReg6 );
751: writel ( ( priv->phyaddr << NVREG_ADAPTCTL_PHYSHIFT ) |
752: NVREG_ADAPTCTL_PHYVALID | NVREG_ADAPTCTL_RUNNING,
753: ioaddr + NvRegAdapterControl );
754: writel ( NVREG_MIISPEED_BIT8 | NVREG_MIIDELAY, ioaddr + NvRegMIISpeed );
755: writel ( NVREG_MII_LINKCHANGE, ioaddr + NvRegMIIMask );
756:
757: i = readl ( ioaddr + NvRegPowerState );
758: if ( ( i & NVREG_POWERSTATE_POWEREDUP ) == 0 )
759: writel ( NVREG_POWERSTATE_POWEREDUP | i, ioaddr + NvRegPowerState );
760:
761: pci_push ( ioaddr );
762: udelay ( 10 );
763: writel ( readl ( ioaddr + NvRegPowerState ) | NVREG_POWERSTATE_VALID,
764: ioaddr + NvRegPowerState );
765:
766: nv_disable_hw_interrupts ( priv );
767: pci_push ( ioaddr );
768: writel ( NVREG_MIISTAT_MASK_ALL, ioaddr + NvRegMIIStatus );
769: writel ( NVREG_IRQSTAT_MASK, ioaddr + NvRegIrqStatus );
770: pci_push ( ioaddr );
771:
772: readl ( ioaddr + NvRegMIIStatus );
773: writel ( NVREG_MIISTAT_MASK_ALL, ioaddr + NvRegMIIStatus );
774: priv->linkspeed = 0;
775: nv_update_linkspeed ( priv );
776: nv_start_rx ( priv );
777: nv_start_tx ( priv );
778:
779: return 0;
780:
781: err_init_rings:
782: return rc;
783: }
784:
785: /**
786: * transmit - Transmit a packet
787: *
788: * @v netdev Network device
789: * @v iobuf I/O buffer
790: *
791: * @ret rc Returns 0 on success, negative on failure
792: */
793: static int
794: forcedeth_transmit ( struct net_device *netdev, struct io_buffer *iobuf )
795: {
796: struct forcedeth_private *priv = netdev_priv ( netdev );
797: void *ioaddr = priv->mmio_addr;
798: struct ring_desc *tx_curr_desc;
799: u32 size = iob_len ( iobuf );
800:
801: DBGP ( "forcedeth_transmit\n" );
802:
803: /* NOTE: Some NICs have a hw bug that causes them to malfunction
804: * when there are more than 16 outstanding TXs. Increasing the TX
805: * ring size might trigger this bug */
806: if ( priv->tx_fill_ctr == TX_RING_SIZE ) {
807: DBG ( "Tx overflow\n" );
808: return -ENOBUFS;
809: }
810:
811: /* Pad small packets to minimum length */
812: iob_pad ( iobuf, ETH_ZLEN );
813:
814: priv->tx_iobuf[priv->tx_curr] = iobuf;
815:
816: tx_curr_desc = priv->tx_ring + priv->tx_curr;
817:
818: /* Configure current descriptor to transmit packet
819: * ( NV_TX_VALID sets the ownership bit ) */
820: tx_curr_desc->buf =
821: cpu_to_le32 ( virt_to_bus ( iobuf->data ) );
822: wmb();
823: /* Since we don't do fragmentation offloading, we always have
824: * the last packet bit set */
825: tx_curr_desc->flaglen =
826: cpu_to_le32 ( ( size - 1 ) | NV_TX_VALID | NV_TX_LASTPACKET );
827:
828: DBG ( "forcedeth_transmit: flaglen = %#04x\n",
829: ( size - 1 ) | NV_TX_VALID | NV_TX_LASTPACKET );
830: DBG ( "forcedeth_transmit: tx_fill_ctr = %d\n",
831: priv->tx_fill_ctr );
832:
833: writel ( NVREG_TXRXCTL_KICK | NVREG_TXRXCTL_DESC_1,
834: ioaddr + NvRegTxRxControl );
835: pci_push ( ioaddr );
836:
837: /* Point to the next free descriptor */
838: priv->tx_curr = ( priv->tx_curr + 1 ) % TX_RING_SIZE;
839:
840: /* Increment number of descriptors in use */
841: priv->tx_fill_ctr++;
842:
843: return 0;
844: }
845:
846: /**
847: * nv_process_tx_packets - Checks for successfully sent packets,
848: * reports them to iPXE with netdev_tx_complete()
849: *
850: * @v netdev Network device
851: */
852: static void
853: nv_process_tx_packets ( struct net_device *netdev )
854: {
855: struct forcedeth_private *priv = netdev_priv ( netdev );
856: struct ring_desc *tx_curr_desc;
857: u32 flaglen;
858:
859: DBGP ( "nv_process_tx_packets\n" );
860:
861: while ( priv->tx_tail != priv->tx_curr ) {
862:
863: tx_curr_desc = priv->tx_ring + priv->tx_tail;
864: flaglen = le32_to_cpu ( tx_curr_desc->flaglen );
865: rmb();
866:
867: /* Skip this descriptor if hardware still owns it */
868: if ( flaglen & NV_TX_VALID )
869: break;
870:
871: DBG ( "Transmitted packet.\n" );
872: DBG ( "priv->tx_fill_ctr= %d\n", priv->tx_fill_ctr );
873: DBG ( "priv->tx_tail = %d\n", priv->tx_tail );
874: DBG ( "priv->tx_curr = %d\n", priv->tx_curr );
875: DBG ( "flaglen = %#04x\n", flaglen );
876:
877: /* This packet is ready for completion */
878: netdev_tx_complete ( netdev, priv->tx_iobuf[priv->tx_tail] );
879:
880: /* Clear the descriptor */
881: memset ( tx_curr_desc, 0, sizeof(*tx_curr_desc) );
882:
883: /* Reduce the number of tx descriptors in use */
884: priv->tx_fill_ctr--;
885:
886: /* Go to next available descriptor */
887: priv->tx_tail = ( priv->tx_tail + 1 ) % TX_RING_SIZE;
888: }
889: }
890:
891: /**
892: * nv_process_rx_packets - Checks for received packets, reports them
893: * to iPXE with netdev_rx() or netdev_rx_err() if there was an error receiving
894: * the packet
895: *
896: * @v netdev Network device
897: */
898: static void
899: nv_process_rx_packets ( struct net_device *netdev )
900: {
901: struct forcedeth_private *priv = netdev_priv ( netdev );
902: struct io_buffer *curr_iob;
903: struct ring_desc *rx_curr_desc;
904: u32 flags, len;
905: int i;
906:
907: DBGP ( "nv_process_rx_packets\n" );
908:
909: for ( i = 0; i < RX_RING_SIZE; i++ ) {
910:
911: rx_curr_desc = priv->rx_ring + priv->rx_curr;
912: flags = le32_to_cpu ( rx_curr_desc->flaglen );
913: rmb();
914:
915: /* Skip this descriptor if hardware still owns it */
916: if ( flags & NV_RX_AVAIL )
917: break;
918:
919: /* We own the descriptor, but it has not been refilled yet */
920: curr_iob = priv->rx_iobuf[priv->rx_curr];
921: DBG ( "%p %p\n", curr_iob, priv->rx_iobuf[priv->rx_curr] );
922: if ( curr_iob == NULL )
923: break;
924:
925: DBG ( "Received packet.\n" );
926: DBG ( "priv->rx_curr = %d\n", priv->rx_curr );
927: DBG ( "flags = %#04x\n", flags );
928:
929: /* Check for errors */
930: if ( ( flags & NV_RX_DESCRIPTORVALID ) &&
931: ( flags & NV_RX_ERROR ) ) {
932: netdev_rx_err ( netdev, curr_iob, -EINVAL );
933: DBG ( " Corrupted packet received!\n" );
934: } else {
935: len = flags & LEN_MASK_V1;
936:
937: iob_put ( curr_iob, len );
938: netdev_rx ( netdev, curr_iob );
939: }
940:
941: /* Invalidate iobuf */
942: priv->rx_iobuf[priv->rx_curr] = NULL;
943:
944: /* Invalidate descriptor */
945: memset ( rx_curr_desc, 0, sizeof(*rx_curr_desc) );
946:
947: /* Point to the next free descriptor */
948: priv->rx_curr = ( priv->rx_curr + 1 ) % RX_RING_SIZE;
949: }
950:
951: nv_alloc_rx ( priv );
952: }
953:
954: /**
955: * check_link - Check for link status change
956: *
957: * @v netdev Network device
958: */
959: static void
960: forcedeth_link_status ( struct net_device *netdev )
961: {
962: struct forcedeth_private *priv = netdev_priv ( netdev );
963: void *ioaddr = priv->mmio_addr;
964:
965: /* Clear the MII link change status by reading the MIIStatus register */
966: readl ( ioaddr + NvRegMIIStatus );
967: writel ( NVREG_MIISTAT_LINKCHANGE, ioaddr + NvRegMIIStatus );
968:
969: if ( nv_update_linkspeed ( priv ) == 1 )
970: netdev_link_up ( netdev );
971: else
972: netdev_link_down ( netdev );
973: }
974:
975: /**
976: * poll - Poll for received packets
977: *
978: * @v netdev Network device
979: */
980: static void
981: forcedeth_poll ( struct net_device *netdev )
982: {
983: struct forcedeth_private *priv = netdev_priv ( netdev );
984: void *ioaddr = priv->mmio_addr;
985: u32 status;
986:
987: DBGP ( "forcedeth_poll\n" );
988:
989: status = readl ( ioaddr + NvRegIrqStatus ) & NVREG_IRQSTAT_MASK;
990:
991: /* Return when no interrupts have been triggered */
992: if ( ! status )
993: return;
994:
995: /* Clear interrupts */
996: writel ( NVREG_IRQSTAT_MASK, ioaddr + NvRegIrqStatus );
997:
998: DBG ( "forcedeth_poll: status = %#04x\n", status );
999:
1000: /* Link change interrupt occured. Call always if link is down,
1001: * to give auto-neg a chance to finish */
1002: if ( ( status & NVREG_IRQ_LINK ) || ! ( netdev_link_ok ( netdev ) ) )
1003: forcedeth_link_status ( netdev );
1004:
1005: /* Process transmitted packets */
1006: nv_process_tx_packets ( netdev );
1007:
1008: /* Process received packets */
1009: nv_process_rx_packets ( netdev );
1010: }
1011:
1012: /**
1013: * close - Disable network interface
1014: *
1015: * @v netdev network interface device structure
1016: **/
1017: static void
1018: forcedeth_close ( struct net_device *netdev )
1019: {
1020: struct forcedeth_private *priv = netdev_priv ( netdev );
1021: void *ioaddr = priv->mmio_addr;
1022:
1023: DBGP ( "forcedeth_close\n" );
1024:
1025: nv_stop_rx ( priv );
1026: nv_stop_tx ( priv );
1027: nv_txrx_reset ( priv );
1028:
1029: /* Disable interrupts on the nic or we will lock up */
1030: nv_disable_hw_interrupts ( priv );
1031: pci_push ( ioaddr );
1032:
1033: nv_free_rxtx_resources ( priv );
1034:
1035: nv_txrx_gate ( priv, 0 );
1036:
1037: /* FIXME: power down nic */
1038: }
1039:
1040: /**
1041: * irq - enable or disable interrupts
1042: *
1043: * @v netdev network adapter
1044: * @v action requested interrupt action
1045: **/
1046: static void
1047: forcedeth_irq ( struct net_device *netdev, int action )
1048: {
1049: struct forcedeth_private *priv = netdev_priv ( netdev );
1050:
1051: DBGP ( "forcedeth_irq\n" );
1052:
1053: switch ( action ) {
1054: case 0:
1055: nv_disable_hw_interrupts ( priv );
1056: break;
1057: default:
1058: nv_enable_hw_interrupts ( priv );
1059: break;
1060: }
1061: }
1062:
1063: static struct net_device_operations forcedeth_operations = {
1064: .open = forcedeth_open,
1065: .transmit = forcedeth_transmit,
1066: .poll = forcedeth_poll,
1067: .close = forcedeth_close,
1068: .irq = forcedeth_irq,
1069: };
1070:
1071: static int
1072: nv_setup_mac_addr ( struct forcedeth_private *priv )
1073: {
1074: struct net_device *dev = priv->netdev;
1075: void *ioaddr = priv->mmio_addr;
1076: u32 orig_mac[2];
1077: u32 txreg;
1078:
1079: orig_mac[0] = readl ( ioaddr + NvRegMacAddrA );
1080: orig_mac[1] = readl ( ioaddr + NvRegMacAddrB );
1081:
1082: txreg = readl ( ioaddr + NvRegTransmitPoll );
1083:
1084: if ( ( priv->driver_data & DEV_HAS_CORRECT_MACADDR ) ||
1085: ( txreg & NVREG_TRANSMITPOLL_MAC_ADDR_REV ) ) {
1086: /* mac address is already in correct order */
1087: dev->hw_addr[0] = ( orig_mac[0] >> 0 ) & 0xff;
1088: dev->hw_addr[1] = ( orig_mac[0] >> 8 ) & 0xff;
1089: dev->hw_addr[2] = ( orig_mac[0] >> 16 ) & 0xff;
1090: dev->hw_addr[3] = ( orig_mac[0] >> 24 ) & 0xff;
1091: dev->hw_addr[4] = ( orig_mac[1] >> 0 ) & 0xff;
1092: dev->hw_addr[5] = ( orig_mac[1] >> 8 ) & 0xff;
1093: } else {
1094: /* need to reverse mac address to correct order */
1095: dev->hw_addr[0] = ( orig_mac[1] >> 8 ) & 0xff;
1096: dev->hw_addr[1] = ( orig_mac[1] >> 0 ) & 0xff;
1097: dev->hw_addr[2] = ( orig_mac[0] >> 24 ) & 0xff;
1098: dev->hw_addr[3] = ( orig_mac[0] >> 16 ) & 0xff;
1099: dev->hw_addr[4] = ( orig_mac[0] >> 8 ) & 0xff;
1100: dev->hw_addr[5] = ( orig_mac[0] >> 0 ) & 0xff;
1101: }
1102:
1103: if ( ! is_valid_ether_addr ( dev->hw_addr ) )
1104: return -EADDRNOTAVAIL;
1105:
1106: DBG ( "MAC address is: %s\n", eth_ntoa ( dev->hw_addr ) );
1107:
1108: return 0;
1109: }
1110:
1111: static int
1112: nv_mgmt_acquire_sema ( struct forcedeth_private *priv )
1113: {
1114: void *ioaddr = priv->mmio_addr;
1115: int i;
1116: u32 tx_ctrl, mgmt_sema;
1117:
1118: for ( i = 0; i < 10; i++ ) {
1119: mgmt_sema = readl ( ioaddr + NvRegTransmitterControl ) &
1120: NVREG_XMITCTL_MGMT_SEMA_MASK;
1121: if ( mgmt_sema == NVREG_XMITCTL_MGMT_SEMA_FREE )
1122: break;
1123: mdelay ( 500 );
1124: }
1125:
1126: if ( mgmt_sema != NVREG_XMITCTL_MGMT_SEMA_FREE )
1127: return 0;
1128:
1129: for ( i = 0; i < 2; i++ ) {
1130: tx_ctrl = readl ( ioaddr + NvRegTransmitterControl );
1131: tx_ctrl |= NVREG_XMITCTL_HOST_SEMA_ACQ;
1132: writel ( tx_ctrl, ioaddr + NvRegTransmitterControl );
1133:
1134: /* verify that the semaphore was acquired */
1135: tx_ctrl = readl ( ioaddr + NvRegTransmitterControl );
1136: if ( ( ( tx_ctrl & NVREG_XMITCTL_HOST_SEMA_MASK ) ==
1137: NVREG_XMITCTL_HOST_SEMA_ACQ ) &&
1138: ( ( tx_ctrl & NVREG_XMITCTL_MGMT_SEMA_MASK ) ==
1139: NVREG_XMITCTL_MGMT_SEMA_FREE ) ) {
1140: priv->mgmt_sema = 1;
1141: return 1;
1142: } else {
1143: udelay ( 50 );
1144: }
1145: }
1146:
1147: return 0;
1148: }
1149:
1150: static void
1151: nv_mgmt_release_sema ( struct forcedeth_private *priv )
1152: {
1153: void *ioaddr = priv->mmio_addr;
1154: u32 tx_ctrl;
1155:
1156: if ( priv->driver_data & DEV_HAS_MGMT_UNIT ) {
1157: if ( priv->mgmt_sema ) {
1158: tx_ctrl = readl (ioaddr + NvRegTransmitterControl );
1159: tx_ctrl &= ~NVREG_XMITCTL_HOST_SEMA_ACQ;
1160: writel ( tx_ctrl, ioaddr + NvRegTransmitterControl );
1161: }
1162: }
1163: }
1164:
1165: static int
1166: nv_mgmt_get_version ( struct forcedeth_private *priv )
1167: {
1168: void *ioaddr = priv->mmio_addr;
1169: u32 data_ready = readl ( ioaddr + NvRegTransmitterControl );
1170: u32 data_ready2 = 0;
1171: unsigned long start;
1172: int ready = 0;
1173:
1174: writel ( NVREG_MGMTUNITGETVERSION,
1175: ioaddr + NvRegMgmtUnitGetVersion );
1176: writel ( data_ready ^ NVREG_XMITCTL_DATA_START,
1177: ioaddr + NvRegTransmitterControl );
1178: start = currticks();
1179:
1180: while ( currticks() > start + 5 * ticks_per_sec() ) {
1181: data_ready2 = readl ( ioaddr + NvRegTransmitterControl );
1182: if ( ( data_ready & NVREG_XMITCTL_DATA_READY ) !=
1183: ( data_ready2 & NVREG_XMITCTL_DATA_READY ) ) {
1184: ready = 1;
1185: break;
1186: }
1187: mdelay ( 1000 );
1188: }
1189:
1190: if ( ! ready || ( data_ready2 & NVREG_XMITCTL_DATA_ERROR ) )
1191: return 0;
1192:
1193: priv->mgmt_version =
1194: readl ( ioaddr + NvRegMgmtUnitVersion ) & NVREG_MGMTUNITVERSION;
1195:
1196: return 1;
1197: }
1198:
1199:
1200:
1201: static int
1202: phy_reset ( struct forcedeth_private *priv, u32 bmcr_setup )
1203: {
1204: u32 miicontrol;
1205: unsigned int tries = 0;
1206:
1207: miicontrol = BMCR_RESET | bmcr_setup;
1208: if ( mii_rw ( priv, priv->phyaddr, MII_BMCR, miicontrol ) ) {
1209: return -1;
1210: }
1211:
1212: mdelay ( 500 );
1213:
1214: /* must wait till reset is deasserted */
1215: while ( miicontrol & BMCR_RESET ) {
1216: mdelay ( 10 );
1217: miicontrol = mii_rw ( priv, priv->phyaddr, MII_BMCR, MII_READ );
1218: if ( tries++ > 100 )
1219: return -1;
1220: }
1221: return 0;
1222: }
1223:
1224: static int
1225: phy_init ( struct forcedeth_private *priv )
1226: {
1227: void *ioaddr = priv->mmio_addr;
1228: u32 phyinterface, phy_reserved, mii_status;
1229: u32 mii_control, mii_control_1000, reg;
1230:
1231: /* phy errata for E3016 phy */
1232: if ( priv->phy_model == PHY_MODEL_MARVELL_E3016 ) {
1233: reg = mii_rw ( priv, priv->phyaddr, MII_NCONFIG, MII_READ );
1234: reg &= ~PHY_MARVELL_E3016_INITMASK;
1235: if ( mii_rw ( priv, priv->phyaddr, MII_NCONFIG, reg ) ) {
1236: DBG ( "PHY write to errata reg failed.\n" );
1237: return PHY_ERROR;
1238: }
1239: }
1240:
1241: if ( priv->phy_oui == PHY_OUI_REALTEK ) {
1242: if ( priv->phy_model == PHY_MODEL_REALTEK_8211 &&
1243: priv->phy_rev == PHY_REV_REALTEK_8211B ) {
1244: if ( mii_rw ( priv, priv->phyaddr,
1245: PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1 ) ) {
1246: DBG ( "PHY init failed.\n" );
1247: return PHY_ERROR;
1248: }
1249: if ( mii_rw ( priv, priv->phyaddr,
1250: PHY_REALTEK_INIT_REG2, PHY_REALTEK_INIT2 ) ) {
1251: DBG ( "PHY init failed.\n" );
1252: return PHY_ERROR;
1253: }
1254: if ( mii_rw ( priv, priv->phyaddr,
1255: PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT3 ) ) {
1256: DBG ( "PHY init failed.\n" );
1257: return PHY_ERROR;
1258: }
1259: if ( mii_rw ( priv, priv->phyaddr,
1260: PHY_REALTEK_INIT_REG3, PHY_REALTEK_INIT4 ) ) {
1261: DBG ( "PHY init failed.\n" );
1262: return PHY_ERROR;
1263: }
1264: if ( mii_rw ( priv, priv->phyaddr,
1265: PHY_REALTEK_INIT_REG4, PHY_REALTEK_INIT5 ) ) {
1266: DBG ( "PHY init failed.\n" );
1267: return PHY_ERROR;
1268: }
1269: if ( mii_rw ( priv, priv->phyaddr,
1270: PHY_REALTEK_INIT_REG5, PHY_REALTEK_INIT6 ) ) {
1271: DBG ( "PHY init failed.\n" );
1272: return PHY_ERROR;
1273: }
1274: if ( mii_rw ( priv, priv->phyaddr,
1275: PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1 ) ) {
1276: DBG ( "PHY init failed.\n" );
1277: return PHY_ERROR;
1278: }
1279: }
1280:
1281: if ( priv->phy_model == PHY_MODEL_REALTEK_8211 &&
1282: priv->phy_rev == PHY_REV_REALTEK_8211C ) {
1283: u32 powerstate = readl ( ioaddr + NvRegPowerState2 );
1284:
1285: /* need to perform hw phy reset */
1286: powerstate |= NVREG_POWERSTATE2_PHY_RESET;
1287: writel ( powerstate , ioaddr + NvRegPowerState2 );
1288: mdelay ( 25 );
1289:
1290: powerstate &= ~NVREG_POWERSTATE2_PHY_RESET;
1291: writel ( powerstate , ioaddr + NvRegPowerState2 );
1292: mdelay ( 25 );
1293:
1294: reg = mii_rw ( priv, priv->phyaddr,
1295: PHY_REALTEK_INIT_REG6, MII_READ );
1296: reg |= PHY_REALTEK_INIT9;
1297: if ( mii_rw ( priv, priv->phyaddr,
1298: PHY_REALTEK_INIT_REG6, reg ) ) {
1299: DBG ( "PHY init failed.\n" );
1300: return PHY_ERROR;
1301: }
1302: if ( mii_rw ( priv, priv->phyaddr,
1303: PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT10 ) ) {
1304: DBG ( "PHY init failed.\n" );
1305: return PHY_ERROR;
1306: }
1307:
1308: reg = mii_rw ( priv, priv->phyaddr,
1309: PHY_REALTEK_INIT_REG7, MII_READ );
1310: if ( ! ( reg & PHY_REALTEK_INIT11 ) ) {
1311: reg |= PHY_REALTEK_INIT11;
1312: if ( mii_rw ( priv, priv->phyaddr,
1313: PHY_REALTEK_INIT_REG7, reg ) ) {
1314: DBG ( "PHY init failed.\n" );
1315: return PHY_ERROR;
1316: }
1317: }
1318: if ( mii_rw ( priv, priv->phyaddr,
1319: PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1 ) ) {
1320: DBG ( "PHY init failed.\n" );
1321: return PHY_ERROR;
1322: }
1323: }
1324: if ( priv->phy_model == PHY_MODEL_REALTEK_8201 ) {
1325: if ( priv->driver_data & DEV_NEED_PHY_INIT_FIX ) {
1326: phy_reserved = mii_rw ( priv, priv->phyaddr,
1327: PHY_REALTEK_INIT_REG6,
1328: MII_READ );
1329: phy_reserved |= PHY_REALTEK_INIT7;
1330: if ( mii_rw ( priv, priv->phyaddr,
1331: PHY_REALTEK_INIT_REG6,
1332: phy_reserved ) ) {
1333: DBG ( "PHY init failed.\n" );
1334: return PHY_ERROR;
1335: }
1336: }
1337: }
1338: }
1339:
1340: /* set advertise register */
1341: reg = mii_rw ( priv, priv->phyaddr, MII_ADVERTISE, MII_READ );
1342: reg |= ( ADVERTISE_10HALF | ADVERTISE_10FULL | ADVERTISE_100HALF |
1343: ADVERTISE_100FULL | ADVERTISE_PAUSE_ASYM | ADVERTISE_PAUSE_CAP );
1344: if ( mii_rw ( priv, priv->phyaddr, MII_ADVERTISE, reg ) ) {
1345: DBG ( "PHY init failed.\n" );
1346: return PHY_ERROR;
1347: }
1348:
1349: /* get phy interface type */
1350: phyinterface = readl ( ioaddr + NvRegPhyInterface );
1351:
1352: /* see if gigabit phy */
1353: mii_status = mii_rw ( priv, priv->phyaddr, MII_BMSR, MII_READ );
1354: if ( mii_status & PHY_GIGABIT ) {
1355: priv->gigabit = PHY_GIGABIT;
1356: mii_control_1000 =
1357: mii_rw ( priv, priv->phyaddr, MII_CTRL1000, MII_READ );
1358: mii_control_1000 &= ~ADVERTISE_1000HALF;
1359: if ( phyinterface & PHY_RGMII )
1360: mii_control_1000 |= ADVERTISE_1000FULL;
1361: else
1362: mii_control_1000 &= ~ADVERTISE_1000FULL;
1363:
1364: if ( mii_rw ( priv, priv->phyaddr, MII_CTRL1000, mii_control_1000)) {
1365: DBG ( "PHY init failed.\n" );
1366: return PHY_ERROR;
1367: }
1368: } else {
1369: priv->gigabit = 0;
1370: }
1371:
1372: mii_control = mii_rw ( priv, priv->phyaddr, MII_BMCR, MII_READ );
1373: mii_control |= BMCR_ANENABLE;
1374:
1375: if ( priv->phy_oui == PHY_OUI_REALTEK &&
1376: priv->phy_model == PHY_MODEL_REALTEK_8211 &&
1377: priv->phy_rev == PHY_REV_REALTEK_8211C ) {
1378: /* start autoneg since we already performed hw reset above */
1379: mii_control |= BMCR_ANRESTART;
1380: if ( mii_rw ( priv, priv->phyaddr, MII_BMCR, mii_control ) ) {
1381: DBG ( "PHY init failed.\n" );
1382: return PHY_ERROR;
1383: }
1384: } else {
1385: /* reset the phy
1386: * (certain phys need bmcr to be setup with reset )
1387: */
1388: if ( phy_reset ( priv, mii_control ) ) {
1389: DBG ( "PHY reset failed\n" );
1390: return PHY_ERROR;
1391: }
1392: }
1393:
1394: /* phy vendor specific configuration */
1395: if ( ( priv->phy_oui == PHY_OUI_CICADA ) && ( phyinterface & PHY_RGMII ) ) {
1396: phy_reserved = mii_rw ( priv, priv->phyaddr, MII_RESV1, MII_READ );
1397: phy_reserved &= ~( PHY_CICADA_INIT1 | PHY_CICADA_INIT2 );
1398: phy_reserved |= ( PHY_CICADA_INIT3 | PHY_CICADA_INIT4 );
1399: if ( mii_rw ( priv, priv->phyaddr, MII_RESV1, phy_reserved ) ) {
1400: DBG ( "PHY init failed.\n" );
1401: return PHY_ERROR;
1402: }
1403: phy_reserved = mii_rw ( priv, priv->phyaddr, MII_NCONFIG, MII_READ );
1404: phy_reserved |= PHY_CICADA_INIT5;
1405: if ( mii_rw ( priv, priv->phyaddr, MII_NCONFIG, phy_reserved ) ) {
1406: DBG ( "PHY init failed.\n" );
1407: return PHY_ERROR;
1408: }
1409: }
1410: if ( priv->phy_oui == PHY_OUI_CICADA ) {
1411: phy_reserved = mii_rw ( priv, priv->phyaddr, MII_SREVISION, MII_READ );
1412: phy_reserved |= PHY_CICADA_INIT6;
1413: if ( mii_rw ( priv, priv->phyaddr, MII_SREVISION, phy_reserved ) ) {
1414: DBG ( "PHY init failed.\n" );
1415: return PHY_ERROR;
1416: }
1417: }
1418: if ( priv->phy_oui == PHY_OUI_VITESSE ) {
1419: if ( mii_rw ( priv, priv->phyaddr, PHY_VITESSE_INIT_REG1,
1420: PHY_VITESSE_INIT1)) {
1421: DBG ( "PHY init failed.\n" );
1422: return PHY_ERROR;
1423: }
1424: if ( mii_rw ( priv, priv->phyaddr, PHY_VITESSE_INIT_REG2,
1425: PHY_VITESSE_INIT2)) {
1426: DBG ( "PHY init failed.\n" );
1427: return PHY_ERROR;
1428: }
1429: phy_reserved = mii_rw ( priv, priv->phyaddr,
1430: PHY_VITESSE_INIT_REG4, MII_READ);
1431: if ( mii_rw ( priv, priv->phyaddr, PHY_VITESSE_INIT_REG4,
1432: phy_reserved ) ) {
1433: DBG ( "PHY init failed.\n" );
1434: return PHY_ERROR;
1435: }
1436: phy_reserved = mii_rw ( priv, priv->phyaddr,
1437: PHY_VITESSE_INIT_REG3, MII_READ);
1438: phy_reserved &= ~PHY_VITESSE_INIT_MSK1;
1439: phy_reserved |= PHY_VITESSE_INIT3;
1440: if ( mii_rw ( priv, priv->phyaddr, PHY_VITESSE_INIT_REG3,
1441: phy_reserved ) ) {
1442: DBG ( "PHY init failed.\n" );
1443: return PHY_ERROR;
1444: }
1445: if ( mii_rw ( priv, priv->phyaddr, PHY_VITESSE_INIT_REG2,
1446: PHY_VITESSE_INIT4 ) ) {
1447: DBG ( "PHY init failed.\n" );
1448: return PHY_ERROR;
1449: }
1450: if ( mii_rw ( priv, priv->phyaddr, PHY_VITESSE_INIT_REG2,
1451: PHY_VITESSE_INIT5 ) ) {
1452: DBG ( "PHY init failed.\n" );
1453: return PHY_ERROR;
1454: }
1455: phy_reserved = mii_rw ( priv, priv->phyaddr,
1456: PHY_VITESSE_INIT_REG4, MII_READ);
1457: phy_reserved &= ~PHY_VITESSE_INIT_MSK1;
1458: phy_reserved |= PHY_VITESSE_INIT3;
1459: if ( mii_rw ( priv, priv->phyaddr, PHY_VITESSE_INIT_REG4,
1460: phy_reserved ) ) {
1461: DBG ( "PHY init failed.\n" );
1462: return PHY_ERROR;
1463: }
1464: phy_reserved = mii_rw ( priv, priv->phyaddr,
1465: PHY_VITESSE_INIT_REG3, MII_READ);
1466: if ( mii_rw ( priv, priv->phyaddr, PHY_VITESSE_INIT_REG3,
1467: phy_reserved ) ) {
1468: DBG ( "PHY init failed.\n" );
1469: return PHY_ERROR;
1470: }
1471: if ( mii_rw ( priv, priv->phyaddr, PHY_VITESSE_INIT_REG2,
1472: PHY_VITESSE_INIT6 ) ) {
1473: DBG ( "PHY init failed.\n" );
1474: return PHY_ERROR;
1475: }
1476: if ( mii_rw ( priv, priv->phyaddr, PHY_VITESSE_INIT_REG2,
1477: PHY_VITESSE_INIT7 ) ) {
1478: DBG ( "PHY init failed.\n" );
1479: return PHY_ERROR;
1480: }
1481: phy_reserved = mii_rw ( priv, priv->phyaddr,
1482: PHY_VITESSE_INIT_REG4, MII_READ);
1483: if ( mii_rw ( priv, priv->phyaddr, PHY_VITESSE_INIT_REG4,
1484: phy_reserved ) ) {
1485: DBG ( "PHY init failed.\n" );
1486: return PHY_ERROR;
1487: }
1488: phy_reserved = mii_rw ( priv, priv->phyaddr,
1489: PHY_VITESSE_INIT_REG3, MII_READ);
1490: phy_reserved &= ~PHY_VITESSE_INIT_MSK2;
1491: phy_reserved |= PHY_VITESSE_INIT8;
1492: if ( mii_rw ( priv, priv->phyaddr, PHY_VITESSE_INIT_REG3,
1493: phy_reserved ) ) {
1494: DBG ( "PHY init failed.\n" );
1495: return PHY_ERROR;
1496: }
1497: if ( mii_rw ( priv, priv->phyaddr, PHY_VITESSE_INIT_REG2,
1498: PHY_VITESSE_INIT9 ) ) {
1499: DBG ( "PHY init failed.\n" );
1500: return PHY_ERROR;
1501: }
1502: if ( mii_rw ( priv, priv->phyaddr, PHY_VITESSE_INIT_REG1,
1503: PHY_VITESSE_INIT10 ) ) {
1504: DBG ( "PHY init failed.\n" );
1505: return PHY_ERROR;
1506: }
1507: }
1508:
1509: if ( priv->phy_oui == PHY_OUI_REALTEK ) {
1510: if ( priv->phy_model == PHY_MODEL_REALTEK_8211 &&
1511: priv->phy_rev == PHY_REV_REALTEK_8211B ) {
1512: /* reset could have cleared these out, set them back */
1513: if ( mii_rw ( priv, priv->phyaddr,
1514: PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1 ) ) {
1515: DBG ( "PHY init failed.\n" );
1516: return PHY_ERROR;
1517: }
1518: if ( mii_rw ( priv, priv->phyaddr,
1519: PHY_REALTEK_INIT_REG2, PHY_REALTEK_INIT2 ) ) {
1520: DBG ( "PHY init failed.\n" );
1521: return PHY_ERROR;
1522: }
1523: if ( mii_rw ( priv, priv->phyaddr,
1524: PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT3 ) ) {
1525: DBG ( "PHY init failed.\n" );
1526: return PHY_ERROR;
1527: }
1528: if ( mii_rw ( priv, priv->phyaddr,
1529: PHY_REALTEK_INIT_REG3, PHY_REALTEK_INIT4 ) ) {
1530: DBG ( "PHY init failed.\n" );
1531: return PHY_ERROR;
1532: }
1533: if ( mii_rw ( priv, priv->phyaddr,
1534: PHY_REALTEK_INIT_REG4, PHY_REALTEK_INIT5 ) ) {
1535: DBG ( "PHY init failed.\n" );
1536: return PHY_ERROR;
1537: }
1538: if ( mii_rw ( priv, priv->phyaddr,
1539: PHY_REALTEK_INIT_REG5, PHY_REALTEK_INIT6 ) ) {
1540: DBG ( "PHY init failed.\n" );
1541: return PHY_ERROR;
1542: }
1543: if ( mii_rw ( priv, priv->phyaddr,
1544: PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1 ) ) {
1545: DBG ( "PHY init failed.\n" );
1546: return PHY_ERROR;
1547: }
1548: }
1549: if ( priv->phy_model == PHY_MODEL_REALTEK_8201 ) {
1550: if ( priv->driver_data & DEV_NEED_PHY_INIT_FIX ) {
1551: phy_reserved = mii_rw ( priv, priv->phyaddr,
1552: PHY_REALTEK_INIT_REG6,
1553: MII_READ );
1554: phy_reserved |= PHY_REALTEK_INIT7;
1555: if ( mii_rw ( priv, priv->phyaddr,
1556: PHY_REALTEK_INIT_REG6,
1557: phy_reserved ) ) {
1558: DBG ( "PHY init failed.\n" );
1559: return PHY_ERROR;
1560: }
1561: }
1562:
1563: if ( mii_rw ( priv, priv->phyaddr,
1564: PHY_REALTEK_INIT_REG1,
1565: PHY_REALTEK_INIT3 ) ) {
1566: DBG ( "PHY init failed.\n" );
1567: return PHY_ERROR;
1568: }
1569: phy_reserved = mii_rw ( priv, priv->phyaddr,
1570: PHY_REALTEK_INIT_REG2,
1571: MII_READ );
1572: phy_reserved &= ~PHY_REALTEK_INIT_MSK1;
1573: phy_reserved |= PHY_REALTEK_INIT3;
1574: if ( mii_rw ( priv, priv->phyaddr,
1575: PHY_REALTEK_INIT_REG2,
1576: phy_reserved ) ) {
1577: DBG ( "PHY init failed.\n" );
1578: return PHY_ERROR;
1579: }
1580: if ( mii_rw ( priv, priv->phyaddr,
1581: PHY_REALTEK_INIT_REG1,
1582: PHY_REALTEK_INIT1 ) ) {
1583: DBG ( "PHY init failed.\n" );
1584: return PHY_ERROR;
1585: }
1586: }
1587: }
1588:
1589: /* some phys clear out pause advertisement on reset, set it back */
1590: mii_rw ( priv, priv->phyaddr, MII_ADVERTISE, reg );
1591:
1592: /* restart auto negotiation, power down phy */
1593: mii_control = mii_rw ( priv, priv->phyaddr, MII_BMCR, MII_READ );
1594: mii_control |= ( BMCR_ANRESTART | BMCR_ANENABLE );
1595: if ( mii_rw ( priv, priv->phyaddr, MII_BMCR, mii_control ) ) {
1596: return PHY_ERROR;
1597: }
1598:
1599: return 0;
1600: }
1601:
1602: /**
1603: * nv_setup_phy - Find PHY and initialize it
1604: *
1605: * @v priv Driver private structure
1606: *
1607: * @ret rc Return status code
1608: **/
1609: static int
1610: nv_setup_phy ( struct forcedeth_private *priv )
1611: {
1612: void *ioaddr = priv->mmio_addr;
1613: u32 phystate_orig = 0, phystate;
1614: int phyinitialised = 0;
1615: u32 powerstate;
1616: int rc = 0;
1617: int i;
1618:
1619: if ( priv->driver_data & DEV_HAS_POWER_CNTRL ) {
1620: /* take phy and nic out of low power mode */
1621: powerstate = readl ( ioaddr + NvRegPowerState2 );
1622: powerstate &= ~NVREG_POWERSTATE2_POWERUP_MASK;
1623: if ( ( priv->driver_data & DEV_NEED_LOW_POWER_FIX ) &&
1624: ( ( priv->pci_dev->class & 0xff ) >= 0xA3 ) )
1625: powerstate |= NVREG_POWERSTATE2_POWERUP_REV_A3;
1626: writel ( powerstate, ioaddr + NvRegPowerState2 );
1627: }
1628:
1629:
1630: /* clear phy state and temporarily halt phy interrupts */
1631: writel ( 0, ioaddr + NvRegMIIMask );
1632: phystate = readl ( ioaddr + NvRegAdapterControl );
1633: if ( phystate & NVREG_ADAPTCTL_RUNNING ) {
1634: phystate_orig = 1;
1635: phystate &= ~NVREG_ADAPTCTL_RUNNING;
1636: writel ( phystate, ioaddr + NvRegAdapterControl );
1637: }
1638: writel ( NVREG_MIISTAT_MASK_ALL, ioaddr + NvRegMIIStatus );
1639:
1640: if ( priv->driver_data & DEV_HAS_MGMT_UNIT ) {
1641: /* management unit running on the mac? */
1642: if ( ( readl ( ioaddr + NvRegTransmitterControl ) & NVREG_XMITCTL_MGMT_ST ) &&
1643: ( readl ( ioaddr + NvRegTransmitterControl ) & NVREG_XMITCTL_SYNC_PHY_INIT ) &&
1644: nv_mgmt_acquire_sema ( priv ) &&
1645: nv_mgmt_get_version ( priv ) ) {
1646: priv->mac_in_use = 1;
1647: if ( priv->mgmt_version > 0 ) {
1648: priv->mac_in_use = readl ( ioaddr + NvRegMgmtUnitControl ) & NVREG_MGMTUNITCONTROL_INUSE;
1649: }
1650:
1651: DBG ( "mgmt unit is running. mac in use\n" );
1652:
1653: /* management unit setup the phy already? */
1654: if ( priv->mac_in_use &&
1655: ( ( readl ( ioaddr + NvRegTransmitterControl ) & NVREG_XMITCTL_SYNC_MASK ) ==
1656: NVREG_XMITCTL_SYNC_PHY_INIT ) ) {
1657: /* phy is inited by mgmt unit */
1658: phyinitialised = 1;
1659: DBG ( "Phy already initialized by mgmt unit" );
1660: }
1661: }
1662: }
1663:
1664: /* find a suitable phy */
1665: for ( i = 1; i <= 32; i++ ) {
1666: int id1, id2;
1667: int phyaddr = i & 0x1f;
1668:
1669: id1 = mii_rw ( priv, phyaddr, MII_PHYSID1, MII_READ );
1670: if ( id1 < 0 || id1 == 0xffff )
1671: continue;
1672: id2 = mii_rw ( priv, phyaddr, MII_PHYSID2, MII_READ );
1673: if ( id2 < 0 || id2 == 0xffff )
1674: continue;
1675:
1676: priv->phy_model = id2 & PHYID2_MODEL_MASK;
1677: id1 = ( id1 & PHYID1_OUI_MASK ) << PHYID1_OUI_SHFT;
1678: id2 = ( id2 & PHYID2_OUI_MASK ) >> PHYID2_OUI_SHFT;
1679: DBG ( "Found PHY: %04x:%04x at address %d\n", id1, id2, phyaddr );
1680: priv->phyaddr = phyaddr;
1681: priv->phy_oui = id1 | id2;
1682:
1683: /* Realtek hardcoded phy id1 to all zeros on certain phys */
1684: if ( priv->phy_oui == PHY_OUI_REALTEK2 )
1685: priv->phy_oui = PHY_OUI_REALTEK;
1686: /* Setup phy revision for Realtek */
1687: if ( priv->phy_oui == PHY_OUI_REALTEK &&
1688: priv->phy_model == PHY_MODEL_REALTEK_8211 )
1689: priv->phy_rev = mii_rw ( priv, phyaddr, MII_RESV1,
1690: MII_READ ) & PHY_REV_MASK;
1691: break;
1692: }
1693: if ( i == 33 ) {
1694: DBG ( "Could not find a valid PHY.\n" );
1695: rc = -ENODEV;
1696: goto err_phy;
1697: }
1698:
1699: if ( ! phyinitialised ) {
1700: /* reset it */
1701: phy_init ( priv );
1702: } else {
1703: u32 mii_status = mii_rw ( priv, priv->phyaddr, MII_BMSR, MII_READ );
1704: if ( mii_status & PHY_GIGABIT ) {
1705: priv->gigabit = PHY_GIGABIT;
1706: }
1707: }
1708:
1709: return 0;
1710:
1711: err_phy:
1712: if ( phystate_orig )
1713: writel ( phystate | NVREG_ADAPTCTL_RUNNING,
1714: ioaddr + NvRegAdapterControl );
1715: return rc;
1716: }
1717:
1718: /**
1719: * forcedeth_map_regs - Find a suitable BAR for the NIC and
1720: * map the registers in memory
1721: *
1722: * @v priv Driver private structure
1723: *
1724: * @ret rc Return status code
1725: **/
1726: static int
1727: forcedeth_map_regs ( struct forcedeth_private *priv )
1728: {
1729: void *ioaddr;
1730: uint32_t bar;
1731: unsigned long addr;
1732: u32 register_size;
1733: int reg;
1734: int rc;
1735:
1736: /* Set register size based on NIC */
1737: if ( priv->driver_data & ( DEV_HAS_VLAN | DEV_HAS_MSI_X |
1738: DEV_HAS_POWER_CNTRL | DEV_HAS_STATISTICS_V2 |
1739: DEV_HAS_STATISTICS_V3 ) ) {
1740: register_size = NV_PCI_REGSZ_VER3;
1741: } else if ( priv->driver_data & DEV_HAS_STATISTICS_V1 ) {
1742: register_size = NV_PCI_REGSZ_VER2;
1743: } else {
1744: register_size = NV_PCI_REGSZ_VER1;
1745: }
1746:
1747: /* Find an appropriate region for all the registers */
1748: rc = -EINVAL;
1749: addr = 0;
1750: for ( reg = PCI_BASE_ADDRESS_0; reg <= PCI_BASE_ADDRESS_5; reg += 4 ) {
1751: pci_read_config_dword ( priv->pci_dev, reg, &bar );
1752:
1753: if ( ( ( bar & PCI_BASE_ADDRESS_SPACE ) ==
1754: PCI_BASE_ADDRESS_SPACE_MEMORY ) &&
1755: ( pci_bar_size ( priv->pci_dev, reg ) >=
1756: register_size ) ) {
1757: addr = pci_bar_start ( priv->pci_dev, reg );
1758: break;
1759: }
1760: }
1761:
1762: if ( reg > PCI_BASE_ADDRESS_5 ) {
1763: DBG ( "Couldn't find register window\n" );
1764: goto err_bar_sz;
1765: }
1766:
1767: rc = -ENOMEM;
1768: ioaddr = ioremap ( addr, register_size );
1769: if ( ! ioaddr ) {
1770: DBG ( "Cannot remap MMIO\n" );
1771: goto err_ioremap;
1772: }
1773:
1774: priv->mmio_addr = ioaddr;
1775:
1776: return 0;
1777:
1778: err_bar_sz:
1779: err_ioremap:
1780: return rc;
1781: }
1782:
1783: /**
1784: * probe - Initial configuration of NIC
1785: *
1786: * @v pdev PCI device
1787: * @v ent PCI IDs
1788: *
1789: * @ret rc Return status code
1790: **/
1791: static int
1792: forcedeth_probe ( struct pci_device *pdev )
1793: {
1794: struct net_device *netdev;
1795: struct forcedeth_private *priv;
1796: void *ioaddr;
1797: int rc;
1798:
1799: DBGP ( "forcedeth_probe\n" );
1800:
1801: DBG ( "Found %s, vendor = %#04x, device = %#04x\n",
1802: pdev->id->name, pdev->id->vendor, pdev->id->device );
1803:
1804: /* Allocate our private data */
1805: netdev = alloc_etherdev ( sizeof ( *priv ) );
1806: if ( ! netdev ) {
1807: rc = -ENOMEM;
1808: DBG ( "Failed to allocate net device\n" );
1809: goto err_alloc_etherdev;
1810: }
1811:
1812: /* Link our operations to the netdev struct */
1813: netdev_init ( netdev, &forcedeth_operations );
1814:
1815: /* Link the PCI device to the netdev struct */
1816: pci_set_drvdata ( pdev, netdev );
1817: netdev->dev = &pdev->dev;
1818:
1819: /* Get a reference to our private data */
1820: priv = netdev_priv ( netdev );
1821:
1822: /* We'll need these set up for the rest of the routines */
1823: priv->pci_dev = pdev;
1824: priv->netdev = netdev;
1825: priv->driver_data = pdev->id->driver_data;
1826:
1827: adjust_pci_device ( pdev );
1828:
1829: /* Use memory mapped I/O */
1830: if ( ( rc = forcedeth_map_regs ( priv ) ) != 0 )
1831: goto err_map_regs;
1832: ioaddr = priv->mmio_addr;
1833:
1834: /* Verify and get MAC address */
1835: if ( ( rc = nv_setup_mac_addr ( priv ) ) != 0 ) {
1836: DBG ( "Invalid MAC address detected\n" );
1837: goto err_mac_addr;
1838: }
1839:
1840: /* Disable WOL */
1841: writel ( 0, ioaddr + NvRegWakeUpFlags );
1842:
1843: if ( ( rc = nv_setup_phy ( priv ) ) != 0 )
1844: goto err_setup_phy;
1845:
1846: /* Set Pause Frame parameters */
1847: priv->pause_flags = NV_PAUSEFRAME_RX_CAPABLE |
1848: NV_PAUSEFRAME_RX_REQ |
1849: NV_PAUSEFRAME_AUTONEG;
1850: if ( ( priv->driver_data & DEV_HAS_PAUSEFRAME_TX_V1 ) ||
1851: ( priv->driver_data & DEV_HAS_PAUSEFRAME_TX_V2 ) ||
1852: ( priv->driver_data & DEV_HAS_PAUSEFRAME_TX_V3 ) ) {
1853: priv->pause_flags |= NV_PAUSEFRAME_TX_CAPABLE | NV_PAUSEFRAME_TX_REQ;
1854: }
1855:
1856: if ( priv->pause_flags & NV_PAUSEFRAME_TX_CAPABLE )
1857: writel ( NVREG_TX_PAUSEFRAME_DISABLE, ioaddr + NvRegTxPauseFrame );
1858:
1859: /* Set default link speed settings */
1860: priv->linkspeed = NVREG_LINKSPEED_FORCE | NVREG_LINKSPEED_10;
1861: priv->duplex = 0;
1862:
1863: if ( ( rc = register_netdev ( netdev ) ) != 0 ) {
1864: DBG ( "Error registering netdev\n" );
1865: goto err_register_netdev;
1866: }
1867:
1868: forcedeth_link_status ( netdev );
1869:
1870: return 0;
1871:
1872: err_register_netdev:
1873: err_setup_phy:
1874: err_mac_addr:
1875: iounmap ( priv->mmio_addr );
1876: err_map_regs:
1877: netdev_nullify ( netdev );
1878: netdev_put ( netdev );
1879: err_alloc_etherdev:
1880: return rc;
1881: }
1882:
1883: static void
1884: nv_restore_phy ( struct forcedeth_private *priv )
1885: {
1886: u16 phy_reserved, mii_control;
1887:
1888: if ( priv->phy_oui == PHY_OUI_REALTEK &&
1889: priv->phy_model == PHY_MODEL_REALTEK_8201 ) {
1890: mii_rw ( priv, priv->phyaddr, PHY_REALTEK_INIT_REG1,
1891: PHY_REALTEK_INIT3 );
1892: phy_reserved = mii_rw ( priv, priv->phyaddr,
1893: PHY_REALTEK_INIT_REG2, MII_READ );
1894: phy_reserved &= ~PHY_REALTEK_INIT_MSK1;
1895: phy_reserved |= PHY_REALTEK_INIT8;
1896: mii_rw ( priv, priv->phyaddr, PHY_REALTEK_INIT_REG2,
1897: phy_reserved );
1898: mii_rw ( priv, priv->phyaddr, PHY_REALTEK_INIT_REG1,
1899: PHY_REALTEK_INIT1 );
1900:
1901: /* restart auto negotiation */
1902: mii_control = mii_rw ( priv, priv->phyaddr, MII_BMCR, MII_READ );
1903: mii_control |= ( BMCR_ANRESTART | BMCR_ANENABLE );
1904: mii_rw ( priv, priv->phyaddr, MII_BMCR, mii_control );
1905: }
1906: }
1907:
1908: /**
1909: * remove - Device Removal Routine
1910: *
1911: * @v pdev PCI device information struct
1912: **/
1913: static void
1914: forcedeth_remove ( struct pci_device *pdev )
1915: {
1916: struct net_device *netdev = pci_get_drvdata ( pdev );
1917: struct forcedeth_private *priv = netdev->priv;
1918:
1919: DBGP ( "forcedeth_remove\n" );
1920:
1921: unregister_netdev ( netdev );
1922:
1923: nv_restore_phy ( priv );
1924:
1925: nv_mgmt_release_sema ( priv );
1926:
1927: iounmap ( priv->mmio_addr );
1928:
1929: netdev_nullify ( netdev );
1930: netdev_put ( netdev );
1931: }
1932:
1933: static struct pci_device_id forcedeth_nics[] = {
1934: PCI_ROM(0x10DE, 0x01C3, "nForce", "nForce Ethernet Controller", DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER),
1935: PCI_ROM(0x10DE, 0x0066, "nForce2", "nForce2 Ethernet Controller", DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER),
1936: PCI_ROM(0x10DE, 0x00D6, "nForce3", "nForce3 Ethernet Controller", DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER),
1937: PCI_ROM(0x10DE, 0x0086, "nForce3", "nForce3 Ethernet Controller", DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC| DEV_HAS_CHECKSUM),
1938: PCI_ROM(0x10DE, 0x008C, "nForce3", "nForce3 Ethernet Controller", DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC| DEV_HAS_CHECKSUM),
1939: PCI_ROM(0x10DE, 0x00E6, "nForce3", "nForce3 Ethernet Controller", DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC| DEV_HAS_CHECKSUM),
1940: PCI_ROM(0x10DE, 0x00DF, "nForce3", "nForce3 Ethernet Controller", DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC| DEV_HAS_CHECKSUM),
1941: PCI_ROM(0x10DE, 0x0056, "CK804", "CK804 Ethernet Controller", DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM| DEV_HAS_HIGH_DMA|DEV_HAS_STATISTICS_V1|DEV_NEED_TX_LIMIT),
1942: PCI_ROM(0x10DE, 0x0057, "CK804", "CK804 Ethernet Controller", DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM| DEV_HAS_HIGH_DMA|DEV_HAS_STATISTICS_V1|DEV_NEED_TX_LIMIT),
1943: PCI_ROM(0x10DE, 0x0037, "MCP04", "MCP04 Ethernet Controller", DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM| DEV_HAS_HIGH_DMA|DEV_HAS_STATISTICS_V1|DEV_NEED_TX_LIMIT),
1944: PCI_ROM(0x10DE, 0x0038, "MCP04", "MCP04 Ethernet Controller", DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM| DEV_HAS_HIGH_DMA|DEV_HAS_STATISTICS_V1|DEV_NEED_TX_LIMIT),
1945: PCI_ROM(0x10DE, 0x0268, "MCP51", "MCP51 Ethernet Controller", DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL| DEV_HAS_STATISTICS_V1|DEV_NEED_LOW_POWER_FIX),
1946: PCI_ROM(0x10DE, 0x0269, "MCP51", "MCP51 Ethernet Controller", DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL| DEV_HAS_STATISTICS_V1|DEV_NEED_LOW_POWER_FIX),
1947: PCI_ROM(0x10DE, 0x0372, "MCP55", "MCP55 Ethernet Controller", DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM| DEV_HAS_HIGH_DMA|DEV_HAS_VLAN|DEV_HAS_MSI|DEV_HAS_MSI_X| DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V1| DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED| DEV_HAS_MGMT_UNIT|DEV_NEED_TX_LIMIT|DEV_NEED_MSI_FIX),
1948: PCI_ROM(0x10DE, 0x0373, "MCP55", "MCP55 Ethernet Controller", DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM| DEV_HAS_HIGH_DMA|DEV_HAS_VLAN|DEV_HAS_MSI|DEV_HAS_MSI_X| DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V1| DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT| DEV_NEED_TX_LIMIT|DEV_NEED_MSI_FIX),
1949: PCI_ROM(0x10DE, 0x03E5, "MCP61", "MCP61 Ethernet Controller", DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL| DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2| DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR| DEV_NEED_MSI_FIX),
1950: PCI_ROM(0x10DE, 0x03E6, "MCP61", "MCP61 Ethernet Controller", DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL| DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2| DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR| DEV_NEED_MSI_FIX),
1951: PCI_ROM(0x10DE, 0x03EE, "MCP61", "MCP61 Ethernet Controller", DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL| DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2| DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR| DEV_NEED_MSI_FIX),
1952: PCI_ROM(0x10DE, 0x03EF, "MCP61", "MCP61 Ethernet Controller", DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL| DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2| DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR| DEV_NEED_MSI_FIX),
1953: PCI_ROM(0x10DE, 0x0450, "MCP65", "MCP65 Ethernet Controller", DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_HIGH_DMA| DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1| DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT| DEV_HAS_CORRECT_MACADDR|DEV_NEED_TX_LIMIT|DEV_HAS_GEAR_MODE| DEV_NEED_MSI_FIX),
1954: PCI_ROM(0x10DE, 0x0451, "MCP65", "MCP65 Ethernet Controller", DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_HIGH_DMA| DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1| DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT| DEV_HAS_CORRECT_MACADDR|DEV_NEED_TX_LIMIT|DEV_HAS_GEAR_MODE| DEV_NEED_MSI_FIX),
1955: PCI_ROM(0x10DE, 0x0452, "MCP65", "MCP65 Ethernet Controller", DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_HIGH_DMA| DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1| DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT| DEV_HAS_CORRECT_MACADDR|DEV_NEED_TX_LIMIT|DEV_HAS_GEAR_MODE| DEV_NEED_MSI_FIX),
1956: PCI_ROM(0x10DE, 0x0453, "MCP65", "MCP65 Ethernet Controller", DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_HIGH_DMA| DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1| DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT| DEV_HAS_CORRECT_MACADDR|DEV_NEED_TX_LIMIT|DEV_HAS_GEAR_MODE| DEV_NEED_MSI_FIX),
1957: PCI_ROM(0x10DE, 0x054C, "MCP67", "MCP67 Ethernet Controller", DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL| DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2| DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR| DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX),
1958: PCI_ROM(0x10DE, 0x054D, "MCP67", "MCP67 Ethernet Controller", DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL| DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2| DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR| DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX),
1959: PCI_ROM(0x10DE, 0x054E, "MCP67", "MCP67 Ethernet Controller", DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL| DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2| DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR| DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX),
1960: PCI_ROM(0x10DE, 0x054F, "MCP67", "MCP67 Ethernet Controller", DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL| DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2| DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR| DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX),
1961: PCI_ROM(0x10DE, 0x07DC, "MCP73", "MCP73 Ethernet Controller", DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL| DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2| DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR| DEV_HAS_COLLISION_FIX|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX),
1962: PCI_ROM(0x10DE, 0x07DD, "MCP73", "MCP73 Ethernet Controller", DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL| DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2| DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR| DEV_HAS_COLLISION_FIX|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX),
1963: PCI_ROM(0x10DE, 0x07DE, "MCP73", "MCP73 Ethernet Controller", DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL| DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2| DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR| DEV_HAS_COLLISION_FIX|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX),
1964: PCI_ROM(0x10DE, 0x07DF, "MCP73", "MCP73 Ethernet Controller", DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL| DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2| DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR| DEV_HAS_COLLISION_FIX|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX),
1965: PCI_ROM(0x10DE, 0x0760, "MCP77", "MCP77 Ethernet Controller", DEV_NEED_LINKTIMER|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA| DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V2| DEV_HAS_STATISTICS_V3|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT| DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX| DEV_NEED_TX_LIMIT2|DEV_HAS_GEAR_MODE|DEV_NEED_PHY_INIT_FIX| DEV_NEED_MSI_FIX),
1966: PCI_ROM(0x10DE, 0x0761, "MCP77", "MCP77 Ethernet Controller", DEV_NEED_LINKTIMER|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA| DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V2| DEV_HAS_STATISTICS_V3|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT| DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX| DEV_NEED_TX_LIMIT2|DEV_HAS_GEAR_MODE|DEV_NEED_PHY_INIT_FIX| DEV_NEED_MSI_FIX),
1967: PCI_ROM(0x10DE, 0x0762, "MCP77", "MCP77 Ethernet Controller", DEV_NEED_LINKTIMER|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA| DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V2| DEV_HAS_STATISTICS_V3|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT| DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX| DEV_NEED_TX_LIMIT2|DEV_HAS_GEAR_MODE|DEV_NEED_PHY_INIT_FIX| DEV_NEED_MSI_FIX),
1968: PCI_ROM(0x10DE, 0x0763, "MCP77", "MCP77 Ethernet Controller", DEV_NEED_LINKTIMER|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA| DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V2| DEV_HAS_STATISTICS_V3|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT| DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX| DEV_NEED_TX_LIMIT2|DEV_HAS_GEAR_MODE|DEV_NEED_PHY_INIT_FIX| DEV_NEED_MSI_FIX),
1969: PCI_ROM(0x10DE, 0x0AB0, "MCP79", "MCP79 Ethernet Controller", DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM| DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL| DEV_HAS_PAUSEFRAME_TX_V3|DEV_HAS_STATISTICS_V3| DEV_HAS_TEST_EXTENDED|DEV_HAS_CORRECT_MACADDR| DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT2|DEV_HAS_GEAR_MODE| DEV_NEED_PHY_INIT_FIX|DEV_NEED_MSI_FIX),
1970: PCI_ROM(0x10DE, 0x0AB1, "MCP79", "MCP79 Ethernet Controller", DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM| DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL| DEV_HAS_PAUSEFRAME_TX_V3|DEV_HAS_STATISTICS_V3| DEV_HAS_TEST_EXTENDED|DEV_HAS_CORRECT_MACADDR| DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT2|DEV_HAS_GEAR_MODE| DEV_NEED_PHY_INIT_FIX|DEV_NEED_MSI_FIX),
1971: PCI_ROM(0x10DE, 0x0AB2, "MCP79", "MCP79 Ethernet Controller", DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM| DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL| DEV_HAS_PAUSEFRAME_TX_V3|DEV_HAS_STATISTICS_V3| DEV_HAS_TEST_EXTENDED|DEV_HAS_CORRECT_MACADDR| DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT2|DEV_HAS_GEAR_MODE| DEV_NEED_PHY_INIT_FIX|DEV_NEED_MSI_FIX),
1972: PCI_ROM(0x10DE, 0x0AB3, "MCP79", "MCP79 Ethernet Controller", DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM| DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL| DEV_HAS_PAUSEFRAME_TX_V3|DEV_HAS_STATISTICS_V3| DEV_HAS_TEST_EXTENDED|DEV_HAS_CORRECT_MACADDR| DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT2|DEV_HAS_GEAR_MODE| DEV_NEED_PHY_INIT_FIX|DEV_NEED_MSI_FIX),
1973: PCI_ROM(0x10DE, 0x0D7D, "MCP89", "MCP89 Ethernet Controller", DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM| DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL| DEV_HAS_PAUSEFRAME_TX_V3|DEV_HAS_STATISTICS_V3| DEV_HAS_TEST_EXTENDED|DEV_HAS_CORRECT_MACADDR| DEV_HAS_COLLISION_FIX|DEV_HAS_GEAR_MODE|DEV_NEED_PHY_INIT_FIX),
1974: };
1975:
1976: struct pci_driver forcedeth_driver __pci_driver = {
1977: .ids = forcedeth_nics,
1978: .id_count = ARRAY_SIZE(forcedeth_nics),
1979: .probe = forcedeth_probe,
1980: .remove = forcedeth_remove,
1981: };
This archive runs on limited infrastructure. Preserving old code on modern bandwidth. Automated agents are requested to crawl responsibly.