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Annotation of qemu/roms/ipxe/src/drivers/net/forcedeth.h, revision 1.1

1.1     ! root        1: /*
        !             2:  *    forcedeth.h -- Driver for NVIDIA nForce media access controllers for iPXE
        !             3:  *    Copyright (c) 2010 Andrei Faur <[email protected]>
        !             4:  *
        !             5:  *    This program is free software; you can redistribute it and/or
        !             6:  *    modify it under the terms of the GNU General Public License as
        !             7:  *    published by the Free Software Foundation; either version 2 of the
        !             8:  *    License, or any later version.
        !             9:  *
        !            10:  *    This program is distributed in the hope that it will be useful, but
        !            11:  *    WITHOUT ANY WARRANTY; without even the implied warranty of
        !            12:  *    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
        !            13:  *    General Public License for more details.
        !            14:  *
        !            15:  *    You should have received a copy of the GNU General Public License
        !            16:  *    along with this program; if not, write to the Free Software
        !            17:  *    Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
        !            18:  *
        !            19:  * Portions of this code are taken from the Linux forcedeth driver that was
        !            20:  * based on a cleanroom reimplementation which was based on reverse engineered
        !            21:  * documentation written by Carl-Daniel Hailfinger and Andrew de Quincey:
        !            22:  * Copyright (C) 2003,4,5 Manfred Spraul
        !            23:  * Copyright (C) 2004 Andrew de Quincey (wol support)
        !            24:  * Copyright (C) 2004 Carl-Daniel Hailfinger (invalid MAC handling, insane
        !            25:  *             IRQ rate fixes, bigendian fixes, cleanups, verification)
        !            26:  * Copyright (c) 2004,2005,2006,2007,2008,2009 NVIDIA Corporation
        !            27:  *
        !            28:  * This header is a direct copy of #define lines and structs found in the
        !            29:  * above mentioned driver, modified where necessary to make them work for iPXE.
        !            30:  *
        !            31:  */
        !            32: 
        !            33: FILE_LICENCE ( GPL2_OR_LATER );
        !            34: 
        !            35: #ifndef _FORCEDETH_H_
        !            36: #define _FORCEDETH_H_
        !            37: 
        !            38: #define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
        !            39: 
        !            40: struct ring_desc {
        !            41:        u32 buf;
        !            42:        u32 flaglen;
        !            43: };
        !            44: 
        !            45: struct ring_desc_ex {
        !            46:        u32 bufhigh;
        !            47:        u32 buflow;
        !            48:        u32 txvlan;
        !            49:        u32 flaglen;
        !            50: };
        !            51: 
        !            52: #define DESC_VER_1     1
        !            53: #define DESC_VER_2     2
        !            54: #define DESC_VER_3     3
        !            55: 
        !            56: #define RX_RING_SIZE           16
        !            57: #define TX_RING_SIZE           16
        !            58: #define RXTX_RING_SIZE         ( ( RX_RING_SIZE ) + ( TX_RING_SIZE ) )
        !            59: #define RX_RING_MIN            128
        !            60: #define TX_RING_MIN            64
        !            61: #define RING_MAX_DESC_VER_1    1024
        !            62: #define RING_MAX_DESC_VER_2_3  16384
        !            63: 
        !            64: #define NV_RX_ALLOC_PAD        (64)
        !            65: 
        !            66: #define NV_RX_HEADERS  (64)
        !            67: 
        !            68: #define RX_BUF_SZ              ( ( ETH_FRAME_LEN ) + ( NV_RX_HEADERS ) )
        !            69: 
        !            70: #define NV_PKTLIMIT_1  1500
        !            71: #define NV_PKTLIMIT_2  9100
        !            72: 
        !            73: #define NV_LINK_POLL_FREQUENCY 128
        !            74: 
        !            75: /* PHY defines */
        !            76: #define PHY_OUI_MARVELL                0x5043
        !            77: #define PHY_OUI_CICADA         0x03f1
        !            78: #define PHY_OUI_VITESSE                0x01c1
        !            79: #define PHY_OUI_REALTEK                0x0732
        !            80: #define PHY_OUI_REALTEK2       0x0020
        !            81: #define PHYID1_OUI_MASK        0x03ff
        !            82: #define PHYID1_OUI_SHFT        6
        !            83: #define PHYID2_OUI_MASK        0xfc00
        !            84: #define PHYID2_OUI_SHFT        10
        !            85: #define PHYID2_MODEL_MASK              0x03f0
        !            86: #define PHY_MODEL_REALTEK_8211         0x0110
        !            87: #define PHY_REV_MASK                   0x0001
        !            88: #define PHY_REV_REALTEK_8211B          0x0000
        !            89: #define PHY_REV_REALTEK_8211C          0x0001
        !            90: #define PHY_MODEL_REALTEK_8201         0x0200
        !            91: #define PHY_MODEL_MARVELL_E3016                0x0220
        !            92: #define PHY_MARVELL_E3016_INITMASK     0x0300
        !            93: #define PHY_CICADA_INIT1       0x0f000
        !            94: #define PHY_CICADA_INIT2       0x0e00
        !            95: #define PHY_CICADA_INIT3       0x01000
        !            96: #define PHY_CICADA_INIT4       0x0200
        !            97: #define PHY_CICADA_INIT5       0x0004
        !            98: #define PHY_CICADA_INIT6       0x02000
        !            99: #define PHY_VITESSE_INIT_REG1  0x1f
        !           100: #define PHY_VITESSE_INIT_REG2  0x10
        !           101: #define PHY_VITESSE_INIT_REG3  0x11
        !           102: #define PHY_VITESSE_INIT_REG4  0x12
        !           103: #define PHY_VITESSE_INIT_MSK1  0xc
        !           104: #define PHY_VITESSE_INIT_MSK2  0x0180
        !           105: #define PHY_VITESSE_INIT1      0x52b5
        !           106: #define PHY_VITESSE_INIT2      0xaf8a
        !           107: #define PHY_VITESSE_INIT3      0x8
        !           108: #define PHY_VITESSE_INIT4      0x8f8a
        !           109: #define PHY_VITESSE_INIT5      0xaf86
        !           110: #define PHY_VITESSE_INIT6      0x8f86
        !           111: #define PHY_VITESSE_INIT7      0xaf82
        !           112: #define PHY_VITESSE_INIT8      0x0100
        !           113: #define PHY_VITESSE_INIT9      0x8f82
        !           114: #define PHY_VITESSE_INIT10     0x0
        !           115: #define PHY_REALTEK_INIT_REG1  0x1f
        !           116: #define PHY_REALTEK_INIT_REG2  0x19
        !           117: #define PHY_REALTEK_INIT_REG3  0x13
        !           118: #define PHY_REALTEK_INIT_REG4  0x14
        !           119: #define PHY_REALTEK_INIT_REG5  0x18
        !           120: #define PHY_REALTEK_INIT_REG6  0x11
        !           121: #define PHY_REALTEK_INIT_REG7  0x01
        !           122: #define PHY_REALTEK_INIT1      0x0000
        !           123: #define PHY_REALTEK_INIT2      0x8e00
        !           124: #define PHY_REALTEK_INIT3      0x0001
        !           125: #define PHY_REALTEK_INIT4      0xad17
        !           126: #define PHY_REALTEK_INIT5      0xfb54
        !           127: #define PHY_REALTEK_INIT6      0xf5c7
        !           128: #define PHY_REALTEK_INIT7      0x1000
        !           129: #define PHY_REALTEK_INIT8      0x0003
        !           130: #define PHY_REALTEK_INIT9      0x0008
        !           131: #define PHY_REALTEK_INIT10     0x0005
        !           132: #define PHY_REALTEK_INIT11     0x0200
        !           133: #define PHY_REALTEK_INIT_MSK1  0x0003
        !           134: 
        !           135: #define PHY_GIGABIT    0x0100
        !           136: 
        !           137: #define PHY_TIMEOUT    0x1
        !           138: #define PHY_ERROR      0x2
        !           139: 
        !           140: #define PHY_100        0x1
        !           141: #define PHY_1000       0x2
        !           142: #define PHY_HALF       0x100
        !           143: 
        !           144: 
        !           145: #define NV_PAUSEFRAME_RX_CAPABLE       0x0001
        !           146: #define NV_PAUSEFRAME_TX_CAPABLE       0x0002
        !           147: #define NV_PAUSEFRAME_RX_ENABLE                0x0004
        !           148: #define NV_PAUSEFRAME_TX_ENABLE                0x0008
        !           149: #define NV_PAUSEFRAME_RX_REQ           0x0010
        !           150: #define NV_PAUSEFRAME_TX_REQ           0x0020
        !           151: #define NV_PAUSEFRAME_AUTONEG          0x0040
        !           152: 
        !           153: /* MSI/MSI-X defines */
        !           154: #define NV_MSI_X_MAX_VECTORS  8
        !           155: #define NV_MSI_X_VECTORS_MASK 0x000f
        !           156: #define NV_MSI_CAPABLE        0x0010
        !           157: #define NV_MSI_X_CAPABLE      0x0020
        !           158: #define NV_MSI_ENABLED        0x0040
        !           159: #define NV_MSI_X_ENABLED      0x0080
        !           160: 
        !           161: #define NV_MSI_X_VECTOR_ALL   0x0
        !           162: #define NV_MSI_X_VECTOR_RX    0x0
        !           163: #define NV_MSI_X_VECTOR_TX    0x1
        !           164: #define NV_MSI_X_VECTOR_OTHER 0x2
        !           165: 
        !           166: #define NV_MSI_PRIV_OFFSET 0x68
        !           167: #define NV_MSI_PRIV_VALUE  0xffffffff
        !           168: 
        !           169: 
        !           170: #define NV_MIIBUSY_DELAY       50
        !           171: #define NV_MIIPHY_DELAY                10
        !           172: #define NV_MIIPHY_DELAYMAX     10000
        !           173: 
        !           174: /* Hardware access */
        !           175: #define DEV_NEED_TIMERIRQ          0x0000001  /* set the timer irq flag in the irq mask */
        !           176: #define DEV_NEED_LINKTIMER         0x0000002  /* poll link settings. Relies on the timer irq */
        !           177: #define DEV_HAS_LARGEDESC          0x0000004  /* device supports jumbo frames and needs packet format 2 */
        !           178: #define DEV_HAS_HIGH_DMA           0x0000008  /* device supports 64bit dma */
        !           179: #define DEV_HAS_CHECKSUM           0x0000010  /* device supports tx and rx checksum offloads */
        !           180: #define DEV_HAS_VLAN               0x0000020  /* device supports vlan tagging and striping */
        !           181: #define DEV_HAS_MSI                0x0000040  /* device supports MSI */
        !           182: #define DEV_HAS_MSI_X              0x0000080  /* device supports MSI-X */
        !           183: #define DEV_HAS_POWER_CNTRL        0x0000100  /* device supports power savings */
        !           184: #define DEV_HAS_STATISTICS_V1      0x0000200  /* device supports hw statistics version 1 */
        !           185: #define DEV_HAS_STATISTICS_V2      0x0000600  /* device supports hw statistics version 2 */
        !           186: #define DEV_HAS_STATISTICS_V3      0x0000e00  /* device supports hw statistics version 3 */
        !           187: #define DEV_HAS_TEST_EXTENDED      0x0001000  /* device supports extended diagnostic test */
        !           188: #define DEV_HAS_MGMT_UNIT          0x0002000  /* device supports management unit */
        !           189: #define DEV_HAS_CORRECT_MACADDR    0x0004000  /* device supports correct mac address order */
        !           190: #define DEV_HAS_COLLISION_FIX      0x0008000  /* device supports tx collision fix */
        !           191: #define DEV_HAS_PAUSEFRAME_TX_V1   0x0010000  /* device supports tx pause frames version 1 */
        !           192: #define DEV_HAS_PAUSEFRAME_TX_V2   0x0020000  /* device supports tx pause frames version 2 */
        !           193: #define DEV_HAS_PAUSEFRAME_TX_V3   0x0040000  /* device supports tx pause frames version 3 */
        !           194: #define DEV_NEED_TX_LIMIT          0x0080000  /* device needs to limit tx */
        !           195: #define DEV_NEED_TX_LIMIT2         0x0180000  /* device needs to limit tx, expect for some revs */
        !           196: #define DEV_HAS_GEAR_MODE          0x0200000  /* device supports gear mode */
        !           197: #define DEV_NEED_PHY_INIT_FIX      0x0400000  /* device needs specific phy workaround */
        !           198: #define DEV_NEED_LOW_POWER_FIX     0x0800000  /* device needs special power up workaround */
        !           199: #define DEV_NEED_MSI_FIX           0x1000000  /* device needs msi workaround */
        !           200: 
        !           201: #define FLAG_MASK_V1 0xffff0000
        !           202: #define FLAG_MASK_V2 0xffffc000
        !           203: #define LEN_MASK_V1 (0xffffffff ^ FLAG_MASK_V1)
        !           204: #define LEN_MASK_V2 (0xffffffff ^ FLAG_MASK_V2)
        !           205: 
        !           206: #define NV_TX_LASTPACKET       (1<<16)
        !           207: #define NV_TX_RETRYERROR       (1<<19)
        !           208: #define NV_TX_RETRYCOUNT_MASK  (0xF<<20)
        !           209: #define NV_TX_FORCED_INTERRUPT (1<<24)
        !           210: #define NV_TX_DEFERRED         (1<<26)
        !           211: #define NV_TX_CARRIERLOST      (1<<27)
        !           212: #define NV_TX_LATECOLLISION    (1<<28)
        !           213: #define NV_TX_UNDERFLOW                (1<<29)
        !           214: #define NV_TX_ERROR            (1<<30)
        !           215: #define NV_TX_VALID            (1<<31)
        !           216: 
        !           217: #define NV_TX2_LASTPACKET      (1<<29)
        !           218: #define NV_TX2_RETRYERROR      (1<<18)
        !           219: #define NV_TX2_RETRYCOUNT_MASK (0xF<<19)
        !           220: #define NV_TX2_FORCED_INTERRUPT        (1<<30)
        !           221: #define NV_TX2_DEFERRED                (1<<25)
        !           222: #define NV_TX2_CARRIERLOST     (1<<26)
        !           223: #define NV_TX2_LATECOLLISION   (1<<27)
        !           224: #define NV_TX2_UNDERFLOW       (1<<28)
        !           225: /* error and valid are the same for both */
        !           226: #define NV_TX2_ERROR           (1<<30)
        !           227: #define NV_TX2_VALID           (1<<31)
        !           228: #define NV_TX2_TSO             (1<<28)
        !           229: #define NV_TX2_TSO_SHIFT       14
        !           230: #define NV_TX2_TSO_MAX_SHIFT   14
        !           231: #define NV_TX2_TSO_MAX_SIZE    (1<<NV_TX2_TSO_MAX_SHIFT)
        !           232: #define NV_TX2_CHECKSUM_L3     (1<<27)
        !           233: #define NV_TX2_CHECKSUM_L4     (1<<26)
        !           234: 
        !           235: #define NV_TX3_VLAN_TAG_PRESENT (1<<18)
        !           236: 
        !           237: #define NV_RX_DESCRIPTORVALID  (1<<16)
        !           238: #define NV_RX_MISSEDFRAME      (1<<17)
        !           239: #define NV_RX_SUBSTRACT1       (1<<18)
        !           240: #define NV_RX_ERROR1           (1<<23)
        !           241: #define NV_RX_ERROR2           (1<<24)
        !           242: #define NV_RX_ERROR3           (1<<25)
        !           243: #define NV_RX_ERROR4           (1<<26)
        !           244: #define NV_RX_CRCERR           (1<<27)
        !           245: #define NV_RX_OVERFLOW         (1<<28)
        !           246: #define NV_RX_FRAMINGERR       (1<<29)
        !           247: #define NV_RX_ERROR            (1<<30)
        !           248: #define NV_RX_AVAIL            (1<<31)
        !           249: #define NV_RX_ERROR_MASK       (NV_RX_ERROR1|NV_RX_ERROR2|NV_RX_ERROR3|NV_RX_ERROR4|NV_RX_CRCERR|NV_RX_OVERFLOW|NV_RX_FRAMINGERR)
        !           250: 
        !           251: #define NV_RX2_CHECKSUMMASK    (0x1C000000)
        !           252: #define NV_RX2_CHECKSUM_IP     (0x10000000)
        !           253: #define NV_RX2_CHECKSUM_IP_TCP (0x14000000)
        !           254: #define NV_RX2_CHECKSUM_IP_UDP (0x18000000)
        !           255: #define NV_RX2_DESCRIPTORVALID (1<<29)
        !           256: #define NV_RX2_SUBSTRACT1      (1<<25)
        !           257: #define NV_RX2_ERROR1          (1<<18)
        !           258: #define NV_RX2_ERROR2          (1<<19)
        !           259: #define NV_RX2_ERROR3          (1<<20)
        !           260: #define NV_RX2_ERROR4          (1<<21)
        !           261: #define NV_RX2_CRCERR          (1<<22)
        !           262: #define NV_RX2_OVERFLOW                (1<<23)
        !           263: #define NV_RX2_FRAMINGERR      (1<<24)
        !           264: /* error and avail are the same for both */
        !           265: #define NV_RX2_ERROR           (1<<30)
        !           266: #define NV_RX2_AVAIL           (1<<31)
        !           267: #define NV_RX2_ERROR_MASK      (NV_RX2_ERROR1|NV_RX2_ERROR2|NV_RX2_ERROR3|NV_RX2_ERROR4|NV_RX2_CRCERR|NV_RX2_OVERFLOW|NV_RX2_FRAMINGERR)
        !           268: 
        !           269: #define NV_RX3_VLAN_TAG_PRESENT (1<<16)
        !           270: #define NV_RX3_VLAN_TAG_MASK   (0x0000FFFF)
        !           271: 
        !           272: /* Miscellaneous hardware related defines */
        !           273: #define NV_PCI_REGSZ_VER1      0x270
        !           274: #define NV_PCI_REGSZ_VER2      0x2d4
        !           275: #define NV_PCI_REGSZ_VER3      0x604
        !           276: #define NV_PCI_REGSZ_MAX       0x604
        !           277: 
        !           278: /* various timeout delays: all in usec */
        !           279: #define NV_TXRX_RESET_DELAY    4
        !           280: #define NV_TXSTOP_DELAY1       10
        !           281: #define NV_TXSTOP_DELAY1MAX    500000
        !           282: #define NV_TXSTOP_DELAY2       100
        !           283: #define NV_RXSTOP_DELAY1       10
        !           284: #define NV_RXSTOP_DELAY1MAX    500000
        !           285: #define NV_RXSTOP_DELAY2       100
        !           286: #define NV_SETUP5_DELAY                5
        !           287: #define NV_SETUP5_DELAYMAX     50000
        !           288: #define NV_POWERUP_DELAY       5
        !           289: #define NV_POWERUP_DELAYMAX    5000
        !           290: #define NV_MIIBUSY_DELAY       50
        !           291: #define NV_MIIPHY_DELAY        10
        !           292: #define NV_MIIPHY_DELAYMAX     10000
        !           293: #define NV_MAC_RESET_DELAY     64
        !           294: 
        !           295: #define NV_MSI_X_CAPABLE       0x0020
        !           296: 
        !           297: #define MII_READ       (-1)
        !           298: 
        !           299: struct forcedeth_private {
        !           300:        struct pci_device *pci_dev;
        !           301:        struct net_device *netdev;
        !           302: 
        !           303:        void *mmio_addr;
        !           304: 
        !           305:        u32 linkspeed;
        !           306:        int duplex;
        !           307: 
        !           308:        int phyaddr;
        !           309:        unsigned int phy_oui;
        !           310:        unsigned int phy_rev;
        !           311:        unsigned int phy_model;
        !           312: 
        !           313:        u16 gigabit;
        !           314:        u32 mac_in_use;
        !           315:        int mgmt_version;
        !           316:        int mgmt_sema;
        !           317: 
        !           318:        /* rx specific fields */
        !           319:        struct ring_desc *rx_ring;
        !           320:        struct io_buffer *rx_iobuf[RX_RING_SIZE];
        !           321:        int rx_curr;
        !           322: 
        !           323:        /* tx specific fields */
        !           324:        struct ring_desc *tx_ring;
        !           325:        struct io_buffer *tx_iobuf[TX_RING_SIZE];
        !           326:        int tx_fill_ctr;
        !           327:        int tx_curr;
        !           328:        int tx_tail;
        !           329: 
        !           330:        /* flow control */
        !           331:        u32 pause_flags;
        !           332: 
        !           333:        unsigned long driver_data;
        !           334: };
        !           335: 
        !           336: enum {
        !           337:        NvRegIrqStatus = 0x000,
        !           338: #define NVREG_IRQSTAT_MIIEVENT 0x040
        !           339: #define NVREG_IRQSTAT_MASK             0x83ff
        !           340:        NvRegIrqMask = 0x004,
        !           341: #define NVREG_IRQ_RX_ERROR             0x0001
        !           342: #define NVREG_IRQ_RX                   0x0002
        !           343: #define NVREG_IRQ_RX_NOBUF             0x0004
        !           344: #define NVREG_IRQ_TX_ERR               0x0008
        !           345: #define NVREG_IRQ_TX_OK                        0x0010
        !           346: #define NVREG_IRQ_TIMER                        0x0020
        !           347: #define NVREG_IRQ_LINK                 0x0040
        !           348: #define NVREG_IRQ_RX_FORCED            0x0080
        !           349: #define NVREG_IRQ_TX_FORCED            0x0100
        !           350: #define NVREG_IRQ_RECOVER_ERROR                0x8200
        !           351: #define NVREG_IRQMASK_THROUGHPUT       0x00df
        !           352: #define NVREG_IRQMASK_CPU              0x0060
        !           353: #define NVREG_IRQ_TX_ALL               (NVREG_IRQ_TX_ERR|NVREG_IRQ_TX_OK|NVREG_IRQ_TX_FORCED)
        !           354: #define NVREG_IRQ_RX_ALL               (NVREG_IRQ_RX_ERROR|NVREG_IRQ_RX|NVREG_IRQ_RX_NOBUF|NVREG_IRQ_RX_FORCED)
        !           355: #define NVREG_IRQ_OTHER                        (NVREG_IRQ_TIMER|NVREG_IRQ_LINK|NVREG_IRQ_RECOVER_ERROR)
        !           356: 
        !           357:        NvRegUnknownSetupReg6 = 0x008,
        !           358: #define NVREG_UNKSETUP6_VAL            3
        !           359: 
        !           360: /*
        !           361:  * NVREG_POLL_DEFAULT is the interval length of the timer source on the nic
        !           362:  * NVREG_POLL_DEFAULT=97 would result in an interval length of 1 ms
        !           363:  */
        !           364:        NvRegPollingInterval = 0x00c,
        !           365: #define NVREG_POLL_DEFAULT_THROUGHPUT  65535 /* backup tx cleanup if loop max reached */
        !           366: #define NVREG_POLL_DEFAULT_CPU 13
        !           367:        NvRegMSIMap0 = 0x020,
        !           368:        NvRegMSIMap1 = 0x024,
        !           369:        NvRegMSIIrqMask = 0x030,
        !           370: #define NVREG_MSI_VECTOR_0_ENABLED 0x01
        !           371:        NvRegMisc1 = 0x080,
        !           372: #define NVREG_MISC1_PAUSE_TX   0x01
        !           373: #define NVREG_MISC1_HD         0x02
        !           374: #define NVREG_MISC1_FORCE      0x3b0f3c
        !           375: 
        !           376:        NvRegMacReset = 0x34,
        !           377: #define NVREG_MAC_RESET_ASSERT 0x0F3
        !           378:        NvRegTransmitterControl = 0x084,
        !           379: #define NVREG_XMITCTL_START    0x01
        !           380: #define NVREG_XMITCTL_MGMT_ST  0x40000000
        !           381: #define NVREG_XMITCTL_SYNC_MASK                0x000f0000
        !           382: #define NVREG_XMITCTL_SYNC_NOT_READY   0x0
        !           383: #define NVREG_XMITCTL_SYNC_PHY_INIT    0x00040000
        !           384: #define NVREG_XMITCTL_MGMT_SEMA_MASK   0x00000f00
        !           385: #define NVREG_XMITCTL_MGMT_SEMA_FREE   0x0
        !           386: #define NVREG_XMITCTL_HOST_SEMA_MASK   0x0000f000
        !           387: #define NVREG_XMITCTL_HOST_SEMA_ACQ    0x0000f000
        !           388: #define NVREG_XMITCTL_HOST_LOADED      0x00004000
        !           389: #define NVREG_XMITCTL_TX_PATH_EN       0x01000000
        !           390: #define NVREG_XMITCTL_DATA_START       0x00100000
        !           391: #define NVREG_XMITCTL_DATA_READY       0x00010000
        !           392: #define NVREG_XMITCTL_DATA_ERROR       0x00020000
        !           393:        NvRegTransmitterStatus = 0x088,
        !           394: #define NVREG_XMITSTAT_BUSY    0x01
        !           395: 
        !           396:        NvRegPacketFilterFlags = 0x8c,
        !           397: #define NVREG_PFF_PAUSE_RX     0x08
        !           398: #define NVREG_PFF_ALWAYS       0x7F0000
        !           399: #define NVREG_PFF_PROMISC      0x80
        !           400: #define NVREG_PFF_MYADDR       0x20
        !           401: #define NVREG_PFF_LOOPBACK     0x10
        !           402: 
        !           403:        NvRegOffloadConfig = 0x90,
        !           404: #define NVREG_OFFLOAD_HOMEPHY  0x601
        !           405: #define NVREG_OFFLOAD_NORMAL   RX_NIC_BUFSIZE
        !           406:        NvRegReceiverControl = 0x094,
        !           407: #define NVREG_RCVCTL_START     0x01
        !           408: #define NVREG_RCVCTL_RX_PATH_EN        0x01000000
        !           409:        NvRegReceiverStatus = 0x98,
        !           410: #define NVREG_RCVSTAT_BUSY     0x01
        !           411: 
        !           412:        NvRegSlotTime = 0x9c,
        !           413: #define NVREG_SLOTTIME_LEGBF_ENABLED   0x80000000
        !           414: #define NVREG_SLOTTIME_10_100_FULL     0x00007f00
        !           415: #define NVREG_SLOTTIME_1000_FULL       0x0003ff00
        !           416: #define NVREG_SLOTTIME_HALF            0x0000ff00
        !           417: #define NVREG_SLOTTIME_DEFAULT         0x00007f00
        !           418: #define NVREG_SLOTTIME_MASK            0x000000ff
        !           419: 
        !           420:        NvRegTxDeferral = 0xA0,
        !           421: #define NVREG_TX_DEFERRAL_DEFAULT              0x15050f
        !           422: #define NVREG_TX_DEFERRAL_RGMII_10_100         0x16070f
        !           423: #define NVREG_TX_DEFERRAL_RGMII_1000           0x14050f
        !           424: #define NVREG_TX_DEFERRAL_RGMII_STRETCH_10     0x16190f
        !           425: #define NVREG_TX_DEFERRAL_RGMII_STRETCH_100    0x16300f
        !           426: #define NVREG_TX_DEFERRAL_MII_STRETCH          0x152000
        !           427:        NvRegRxDeferral = 0xA4,
        !           428: #define NVREG_RX_DEFERRAL_DEFAULT      0x16
        !           429:        NvRegMacAddrA = 0xA8,
        !           430:        NvRegMacAddrB = 0xAC,
        !           431:        NvRegMulticastAddrA = 0xB0,
        !           432: #define NVREG_MCASTADDRA_FORCE 0x01
        !           433:        NvRegMulticastAddrB = 0xB4,
        !           434:        NvRegMulticastMaskA = 0xB8,
        !           435: #define NVREG_MCASTMASKA_NONE          0xffffffff
        !           436:        NvRegMulticastMaskB = 0xBC,
        !           437: #define NVREG_MCASTMASKB_NONE          0xffff
        !           438: 
        !           439:        NvRegPhyInterface = 0xC0,
        !           440: #define PHY_RGMII              0x10000000
        !           441:        NvRegBackOffControl = 0xC4,
        !           442: #define NVREG_BKOFFCTRL_DEFAULT                        0x70000000
        !           443: #define NVREG_BKOFFCTRL_SEED_MASK              0x000003ff
        !           444: #define NVREG_BKOFFCTRL_SELECT                 24
        !           445: #define NVREG_BKOFFCTRL_GEAR                   12
        !           446: 
        !           447:        NvRegTxRingPhysAddr = 0x100,
        !           448:        NvRegRxRingPhysAddr = 0x104,
        !           449:        NvRegRingSizes = 0x108,
        !           450: #define NVREG_RINGSZ_TXSHIFT 0
        !           451: #define NVREG_RINGSZ_RXSHIFT 16
        !           452:        NvRegTransmitPoll = 0x10c,
        !           453: #define NVREG_TRANSMITPOLL_MAC_ADDR_REV        0x00008000
        !           454:        NvRegLinkSpeed = 0x110,
        !           455: #define NVREG_LINKSPEED_FORCE 0x10000
        !           456: #define NVREG_LINKSPEED_10     1000
        !           457: #define NVREG_LINKSPEED_100    100
        !           458: #define NVREG_LINKSPEED_1000   50
        !           459: #define NVREG_LINKSPEED_MASK   (0xFFF)
        !           460:        NvRegUnknownSetupReg5 = 0x130,
        !           461: #define NVREG_UNKSETUP5_BIT31  (1<<31)
        !           462:        NvRegTxWatermark = 0x13c,
        !           463: #define NVREG_TX_WM_DESC1_DEFAULT      0x0200010
        !           464: #define NVREG_TX_WM_DESC2_3_DEFAULT    0x1e08000
        !           465: #define NVREG_TX_WM_DESC2_3_1000       0xfe08000
        !           466:        NvRegTxRxControl = 0x144,
        !           467: #define NVREG_TXRXCTL_KICK     0x0001
        !           468: #define NVREG_TXRXCTL_BIT1     0x0002
        !           469: #define NVREG_TXRXCTL_BIT2     0x0004
        !           470: #define NVREG_TXRXCTL_IDLE     0x0008
        !           471: #define NVREG_TXRXCTL_RESET    0x0010
        !           472: #define NVREG_TXRXCTL_RXCHECK  0x0400
        !           473: #define NVREG_TXRXCTL_DESC_1   0
        !           474: #define NVREG_TXRXCTL_DESC_2   0x002100
        !           475: #define NVREG_TXRXCTL_DESC_3   0xc02200
        !           476: #define NVREG_TXRXCTL_VLANSTRIP 0x00040
        !           477: #define NVREG_TXRXCTL_VLANINS  0x00080
        !           478:        NvRegTxRingPhysAddrHigh = 0x148,
        !           479:        NvRegRxRingPhysAddrHigh = 0x14C,
        !           480:        NvRegTxPauseFrame = 0x170,
        !           481: #define NVREG_TX_PAUSEFRAME_DISABLE    0x0fff0080
        !           482: #define NVREG_TX_PAUSEFRAME_ENABLE_V1  0x01800010
        !           483: #define NVREG_TX_PAUSEFRAME_ENABLE_V2  0x056003f0
        !           484: #define NVREG_TX_PAUSEFRAME_ENABLE_V3  0x09f00880
        !           485:        NvRegTxPauseFrameLimit = 0x174,
        !           486: #define NVREG_TX_PAUSEFRAMELIMIT_ENABLE        0x00010000
        !           487:        NvRegMIIStatus = 0x180,
        !           488: #define NVREG_MIISTAT_ERROR            0x0001
        !           489: #define NVREG_MIISTAT_LINKCHANGE       0x0008
        !           490: #define NVREG_MIISTAT_MASK_RW          0x0007
        !           491: #define NVREG_MIISTAT_MASK_ALL         0x000f
        !           492:        NvRegMIIMask = 0x184,
        !           493: #define NVREG_MII_LINKCHANGE           0x0008
        !           494: 
        !           495:        NvRegAdapterControl = 0x188,
        !           496: #define NVREG_ADAPTCTL_START   0x02
        !           497: #define NVREG_ADAPTCTL_LINKUP  0x04
        !           498: #define NVREG_ADAPTCTL_PHYVALID        0x40000
        !           499: #define NVREG_ADAPTCTL_RUNNING 0x100000
        !           500: #define NVREG_ADAPTCTL_PHYSHIFT        24
        !           501:        NvRegMIISpeed = 0x18c,
        !           502: #define NVREG_MIISPEED_BIT8    (1<<8)
        !           503: #define NVREG_MIIDELAY 5
        !           504:        NvRegMIIControl = 0x190,
        !           505: #define NVREG_MIICTL_INUSE     0x08000
        !           506: #define NVREG_MIICTL_WRITE     0x00400
        !           507: #define NVREG_MIICTL_ADDRSHIFT 5
        !           508:        NvRegMIIData = 0x194,
        !           509:        NvRegTxUnicast = 0x1a0,
        !           510:        NvRegTxMulticast = 0x1a4,
        !           511:        NvRegTxBroadcast = 0x1a8,
        !           512:        NvRegWakeUpFlags = 0x200,
        !           513: #define NVREG_WAKEUPFLAGS_VAL          0x7770
        !           514: #define NVREG_WAKEUPFLAGS_BUSYSHIFT    24
        !           515: #define NVREG_WAKEUPFLAGS_ENABLESHIFT  16
        !           516: #define NVREG_WAKEUPFLAGS_D3SHIFT      12
        !           517: #define NVREG_WAKEUPFLAGS_D2SHIFT      8
        !           518: #define NVREG_WAKEUPFLAGS_D1SHIFT      4
        !           519: #define NVREG_WAKEUPFLAGS_D0SHIFT      0
        !           520: #define NVREG_WAKEUPFLAGS_ACCEPT_MAGPAT                0x01
        !           521: #define NVREG_WAKEUPFLAGS_ACCEPT_WAKEUPPAT     0x02
        !           522: #define NVREG_WAKEUPFLAGS_ACCEPT_LINKCHANGE    0x04
        !           523: #define NVREG_WAKEUPFLAGS_ENABLE       0x1111
        !           524: 
        !           525:        NvRegMgmtUnitGetVersion = 0x204,
        !           526: #define NVREG_MGMTUNITGETVERSION       0x01
        !           527:        NvRegMgmtUnitVersion = 0x208,
        !           528: #define NVREG_MGMTUNITVERSION          0x08
        !           529:        NvRegPowerCap = 0x268,
        !           530: #define NVREG_POWERCAP_D3SUPP  (1<<30)
        !           531: #define NVREG_POWERCAP_D2SUPP  (1<<26)
        !           532: #define NVREG_POWERCAP_D1SUPP  (1<<25)
        !           533:        NvRegPowerState = 0x26c,
        !           534: #define NVREG_POWERSTATE_POWEREDUP     0x8000
        !           535: #define NVREG_POWERSTATE_VALID         0x0100
        !           536: #define NVREG_POWERSTATE_MASK          0x0003
        !           537: #define NVREG_POWERSTATE_D0            0x0000
        !           538: #define NVREG_POWERSTATE_D1            0x0001
        !           539: #define NVREG_POWERSTATE_D2            0x0002
        !           540: #define NVREG_POWERSTATE_D3            0x0003
        !           541:        NvRegMgmtUnitControl = 0x278,
        !           542: #define NVREG_MGMTUNITCONTROL_INUSE    0x20000
        !           543:        NvRegTxCnt = 0x280,
        !           544:        NvRegTxZeroReXmt = 0x284,
        !           545:        NvRegTxOneReXmt = 0x288,
        !           546:        NvRegTxManyReXmt = 0x28c,
        !           547:        NvRegTxLateCol = 0x290,
        !           548:        NvRegTxUnderflow = 0x294,
        !           549:        NvRegTxLossCarrier = 0x298,
        !           550:        NvRegTxExcessDef = 0x29c,
        !           551:        NvRegTxRetryErr = 0x2a0,
        !           552:        NvRegRxFrameErr = 0x2a4,
        !           553:        NvRegRxExtraByte = 0x2a8,
        !           554:        NvRegRxLateCol = 0x2ac,
        !           555:        NvRegRxRunt = 0x2b0,
        !           556:        NvRegRxFrameTooLong = 0x2b4,
        !           557:        NvRegRxOverflow = 0x2b8,
        !           558:        NvRegRxFCSErr = 0x2bc,
        !           559:        NvRegRxFrameAlignErr = 0x2c0,
        !           560:        NvRegRxLenErr = 0x2c4,
        !           561:        NvRegRxUnicast = 0x2c8,
        !           562:        NvRegRxMulticast = 0x2cc,
        !           563:        NvRegRxBroadcast = 0x2d0,
        !           564:        NvRegTxDef = 0x2d4,
        !           565:        NvRegTxFrame = 0x2d8,
        !           566:        NvRegRxCnt = 0x2dc,
        !           567:        NvRegTxPause = 0x2e0,
        !           568:        NvRegRxPause = 0x2e4,
        !           569:        NvRegRxDropFrame = 0x2e8,
        !           570:        NvRegVlanControl = 0x300,
        !           571: #define NVREG_VLANCONTROL_ENABLE       0x2000
        !           572:        NvRegMSIXMap0 = 0x3e0,
        !           573:        NvRegMSIXMap1 = 0x3e4,
        !           574:        NvRegMSIXIrqStatus = 0x3f0,
        !           575: 
        !           576:        NvRegPowerState2 = 0x600,
        !           577: #define NVREG_POWERSTATE2_POWERUP_MASK         0x0F15
        !           578: #define NVREG_POWERSTATE2_POWERUP_REV_A3       0x0001
        !           579: #define NVREG_POWERSTATE2_PHY_RESET            0x0004
        !           580: #define NVREG_POWERSTATE2_GATE_CLOCKS          0x0F00
        !           581: };
        !           582: 
        !           583: enum {
        !           584:        NV_OPTIMIZATION_MODE_THROUGHPUT,
        !           585:        NV_OPTIMIZATION_MODE_CPU,
        !           586:        NV_OPTIMIZATION_MODE_DYNAMIC
        !           587: };
        !           588: 
        !           589: enum {
        !           590:        NV_CROSSOVER_DETECTION_DISABLED,
        !           591:        NV_CROSSOVER_DETECTION_ENABLED
        !           592: };
        !           593: 
        !           594: 
        !           595: #define NV_SETUP_RX_RING       0x01
        !           596: #define NV_SETUP_TX_RING       0x02
        !           597: 
        !           598: #define NV_RESTART_TX          0x1
        !           599: #define NV_RESTART_RX          0x2
        !           600: 
        !           601: #endif /* _FORCEDETH_H_ */
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