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1.1 root 1: /*
2: * Copyright (c) 2010 Andrei Faur <[email protected]>
3: *
4: * This program is free software; you can redistribute it and/or
5: * modify it under the terms of the GNU General Public License as
6: * published by the Free Software Foundation; either version 2 of the
7: * License, or any later version.
8: *
9: * This program is distributed in the hope that it will be useful, but
10: * WITHOUT ANY WARRANTY; without even the implied warranty of
11: * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
12: * General Public License for more details.
13: *
14: * You should have received a copy of the GNU General Public License
15: * along with this program; if not, write to the Free Software
16: * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
17: *
18: */
19:
20: FILE_LICENCE ( GPL2_OR_LATER );
21:
22: #ifndef _PCNET32_H_
23: #define _PCNET32_H_
24:
25: #define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
26:
27: /*
28: * Set the number of Tx and Rx buffers, using Log_2(# buffers).
29: * Set default values to 16 Tx buffers and 32 Rx buffers.
30: */
31: #define PCNET32_LOG_TX_BUFFERS 4
32: #define PCNET32_LOG_RX_BUFFERS 5
33:
34: /* Maximum number of descriptor rings is 512 */
35: #define PCNET32_LOG_MAX_TX_BUFFERS 9
36: #define PCNET32_LOG_MAX_RX_BUFFERS 9
37:
38: #define TX_RING_SIZE ( 1 << ( PCNET32_LOG_TX_BUFFERS ) )
39: #define TX_MAX_RING_SIZE ( 1 << ( PCNET32_LOG_MAX_TX_BUFFERS ) )
40:
41: #define RX_RING_SIZE ( 1 << ( PCNET32_LOG_RX_BUFFERS ) )
42: #define RX_MAX_RING_SIZE ( 1 << ( PCNET32_LOG_MAX_RX_BUFFERS ) )
43:
44: #define RX_RING_BYTES ( RX_RING_SIZE * sizeof(struct pcnet32_rx_desc ) )
45: #define TX_RING_BYTES ( TX_RING_SIZE * sizeof(struct pcnet32_tx_desc ) )
46:
47: #define PKT_BUF_SIZE 1536
48:
49: #define RX_RING_ALIGN 16
50: #define TX_RING_ALIGN 16
51:
52: #define INIT_BLOCK_ALIGN 32
53:
54: #define PCNET32_WIO_RDP 0x10
55: #define PCNET32_WIO_RAP 0x12
56: #define PCNET32_WIO_RESET 0x14
57: #define PCNET32_WIO_BDP 0x16
58:
59: #define PCNET32_DWIO_RDP 0x10
60: #define PCNET32_DWIO_RAP 0x14
61: #define PCNET32_DWIO_RESET 0x18
62: #define PCNET32_DWIO_BDP 0x1C
63:
64: #define PCNET32_PORT_AUI 0x00
65: #define PCNET32_PORT_10BT 0x01
66: #define PCNET32_PORT_GPSI 0x02
67: #define PCNET32_PORT_MII 0x03
68:
69: #define PCNET32_PORT_PORTSEL 0x03
70: #define PCNET32_PORT_ASEL 0x04
71: #define PCNET32_PORT_100 0x40
72: #define PCNET32_PORT_FD 0x80
73:
74: #define PCNET32_SWSTYLE_LANCE 0x00
75: #define PCNET32_SWSTYLE_ILACC 0x01
76: #define PCNET32_SWSTYLE_PCNET32 0x02
77:
78: #define PCNET32_MAX_PHYS 32
79:
80: #ifndef PCI_VENDOR_ID_AT
81: #define PCI_VENDOR_ID_AT 0x1259
82: #endif
83:
84: #ifndef PCI_SUBDEVICE_ID_AT_2700FX
85: #define PCI_SUBDEVICE_ID_AT_2700FX 0x2701
86: #endif
87:
88: #ifndef PCI_SUBDEVICE_ID_AT_2701FX
89: #define PCI_SUBDEVICE_ID_AT_2701FX 0x2703
90: #endif
91:
92: struct pcnet32_rx_desc {
93: u32 base;
94: s16 buf_length;
95: s16 status;
96: u32 msg_length;
97: u32 reserved;
98: };
99:
100: struct pcnet32_tx_desc {
101: u32 base;
102: s16 length;
103: s16 status;
104: u32 misc;
105: u32 reserved;
106: };
107:
108: struct pcnet32_init_block {
109: u16 mode;
110: u16 tlen_rlen;
111: u8 phys_addr[6];
112: u16 reserved;
113: u32 filter[2];
114: u32 rx_ring;
115: u32 tx_ring;
116: };
117:
118: struct pcnet32_access {
119: u16 ( *read_csr ) ( unsigned long, int );
120: void ( *write_csr ) ( unsigned long, int, u16 );
121: u16 ( *read_bcr ) ( unsigned long, int );
122: void ( *write_bcr ) ( unsigned long, int, u16 );
123: u16 ( *read_rap ) ( unsigned long );
124: void ( *write_rap ) ( unsigned long, u16 );
125: void ( *reset ) ( unsigned long );
126: };
127:
128: struct pcnet32_private {
129: struct pcnet32_init_block init_block __attribute__((aligned(32)));
130: struct pci_device *pci_dev;
131: struct net_device *netdev;
132:
133: struct io_buffer *rx_iobuf[RX_RING_SIZE];
134: struct io_buffer *tx_iobuf[TX_RING_SIZE];
135:
136: struct pcnet32_rx_desc *rx_base;
137: struct pcnet32_tx_desc *tx_base;
138: uint32_t rx_curr;
139: uint32_t tx_curr;
140: uint32_t tx_tail;
141: uint32_t tx_fill_ctr;
142:
143: struct pcnet32_access *a;
144: int options;
145: unsigned int mii:1,
146: full_duplex:1;
147:
148: unsigned short chip_version;
149:
150: char irq_enabled;
151: };
152:
153: enum pcnet32_desc_status_bit {
154: DescOwn = (1 << 15),
155: StartOfPacket = (1 << 9),
156: EndOfPacket = (1 << 8)
157: };
158:
159: enum pcnet32_register_content {
160: /* CSR0 bits - Controller status register */
161: RxInt = (1 << 10),
162: TxInt = (1 << 9),
163: InitDone = (1 << 8),
164: IntFlag = (1 << 7),
165: IntEnable = (1 << 6),
166: TxDemand = (1 << 3),
167: Stop = (1 << 2),
168: Strt = (1 << 1),
169: Init = (1 << 0),
170:
171: /* CSR3 bits - Controller status register */
172: BablMask = (1 << 14),
173: MissFrameMask = (1 << 12),
174: MemErrMask = (1 << 11),
175: RxIntMask = (1 << 10),
176: TxIntMask = (1 << 9),
177: InitDoneMask = (1 << 8)
178:
179: };
180:
181: #endif /* _PCNET32_H_ */
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