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1.1 root 1: /*
2: * Copyright (c) 2008 Marty Connor <[email protected]>
3: * Copyright (c) 2008 Entity Cyber, Inc.
4: *
5: * This program is free software; you can redistribute it and/or
6: * modify it under the terms of the GNU General Public License as
7: * published by the Free Software Foundation; either version 2 of the
8: * License, or any later version.
9: *
10: * This program is distributed in the hope that it will be useful, but
11: * WITHOUT ANY WARRANTY; without even the implied warranty of
12: * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
13: * General Public License for more details.
14: *
15: * You should have received a copy of the GNU General Public License
16: * along with this program; if not, write to the Free Software
17: * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
18: *
19: * This driver is based on rtl8169 data sheets and work by:
20: *
21: * Copyright (c) 2002 ShuChen <[email protected]>
22: * Copyright (c) 2003 - 2007 Francois Romieu <[email protected]>
23: * Copyright (c) a lot of people too. Please respect their work.
24: *
25: */
26:
27: FILE_LICENCE ( GPL2_OR_LATER );
28:
29: #ifndef _R8169_H_
30: #define _R8169_H_
31:
32: #define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
33:
34: /** FIXME: include/linux/pci_regs.h has these PCI regs, maybe
35: we need such a file in iPXE?
36: **/
37: #define PCI_EXP_DEVCTL 8 /* Device Control */
38: #define PCI_EXP_DEVCTL_READRQ 0x7000 /* Max_Read_Request_Size */
39: #define PCI_EXP_LNKCTL 16 /* Link Control */
40: #define PCI_EXP_LNKCTL_CLKREQ_EN 0x100 /* Enable clkreq */
41: #define PCI_EXP_DEVCTL_NOSNOOP_EN 0x0800 /* Enable No Snoop */
42:
43: /** FIXME: update mii.h in src/include/mii.h from Linux sources
44: so we don't have to include these definitiions.
45: **/
46: /* The forced speed, 10Mb, 100Mb, gigabit, 2.5Gb, 10GbE. */
47: #define SPEED_10 10
48: #define SPEED_100 100
49: #define SPEED_1000 1000
50: #define SPEED_2500 2500
51: #define SPEED_10000 10000
52:
53: /* Duplex, half or full. */
54: #define DUPLEX_HALF 0x00
55: #define DUPLEX_FULL 0x01
56:
57: #define AUTONEG_DISABLE 0x00
58: #define AUTONEG_ENABLE 0x01
59:
60: /* MAC address length */
61: #define MAC_ADDR_LEN 6
62:
63: #define MAX_READ_REQUEST_SHIFT 12
64: #define RX_FIFO_THRESH 7 /* 7 means NO threshold, Rx buffer level before first PCI xfer. */
65: #define RX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
66: #define TX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
67: #define EarlyTxThld 0x3F /* 0x3F means NO early transmit */
68: #define RxPacketMaxSize 0x3FE8 /* 16K - 1 - ETH_HLEN - VLAN - CRC... */
69: #define SafeMtu 0x1c20 /* ... actually life sucks beyond ~7k */
70: #define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */
71:
72: #define R8169_REGS_SIZE 256
73: #define R8169_NAPI_WEIGHT 64
74: #define NUM_TX_DESC 8 /* Number of Tx descriptor registers */
75: #define NUM_RX_DESC 8 /* Number of Rx descriptor registers */
76: #define RX_BUF_SIZE 1536 /* Rx Buffer size */
77: #define R8169_TX_RING_BYTES (NUM_TX_DESC * sizeof(struct TxDesc))
78: #define R8169_RX_RING_BYTES (NUM_RX_DESC * sizeof(struct RxDesc))
79:
80: #define TX_RING_ALIGN 256
81: #define RX_RING_ALIGN 256
82:
83: #define RTL8169_TX_TIMEOUT (6*HZ)
84: #define RTL8169_PHY_TIMEOUT (10*HZ)
85:
86: #define RTL_EEPROM_SIG cpu_to_le32(0x8129)
87: #define RTL_EEPROM_SIG_MASK cpu_to_le32(0xffff)
88: #define RTL_EEPROM_SIG_ADDR 0x0000
89:
90: /* write/read MMIO register */
91: #define RTL_W8(reg, val8) writeb ((val8), ioaddr + (reg))
92: #define RTL_W16(reg, val16) writew ((val16), ioaddr + (reg))
93: #define RTL_W32(reg, val32) writel ((val32), ioaddr + (reg))
94: #define RTL_R8(reg) readb (ioaddr + (reg))
95: #define RTL_R16(reg) readw (ioaddr + (reg))
96: #define RTL_R32(reg) ((unsigned long) readl (ioaddr + (reg)))
97:
98: enum mac_version {
99: RTL_GIGA_MAC_VER_01 = 0x01, // 8169
100: RTL_GIGA_MAC_VER_02 = 0x02, // 8169S
101: RTL_GIGA_MAC_VER_03 = 0x03, // 8110S
102: RTL_GIGA_MAC_VER_04 = 0x04, // 8169SB
103: RTL_GIGA_MAC_VER_05 = 0x05, // 8110SCd
104: RTL_GIGA_MAC_VER_06 = 0x06, // 8110SCe
105: RTL_GIGA_MAC_VER_07 = 0x07, // 8102e
106: RTL_GIGA_MAC_VER_08 = 0x08, // 8102e
107: RTL_GIGA_MAC_VER_09 = 0x09, // 8102e
108: RTL_GIGA_MAC_VER_10 = 0x0a, // 8101e
109: RTL_GIGA_MAC_VER_11 = 0x0b, // 8168Bb
110: RTL_GIGA_MAC_VER_12 = 0x0c, // 8168Be
111: RTL_GIGA_MAC_VER_13 = 0x0d, // 8101Eb
112: RTL_GIGA_MAC_VER_14 = 0x0e, // 8101 ?
113: RTL_GIGA_MAC_VER_15 = 0x0f, // 8101 ?
114: RTL_GIGA_MAC_VER_16 = 0x11, // 8101Ec
115: RTL_GIGA_MAC_VER_17 = 0x10, // 8168Bf
116: RTL_GIGA_MAC_VER_18 = 0x12, // 8168CP
117: RTL_GIGA_MAC_VER_19 = 0x13, // 8168C
118: RTL_GIGA_MAC_VER_20 = 0x14, // 8168C
119: RTL_GIGA_MAC_VER_21 = 0x15, // 8168C
120: RTL_GIGA_MAC_VER_22 = 0x16, // 8168C
121: RTL_GIGA_MAC_VER_23 = 0x17, // 8168CP
122: RTL_GIGA_MAC_VER_24 = 0x18, // 8168CP
123: RTL_GIGA_MAC_VER_25 = 0x19, // 8168D
124: };
125:
126: #define _R(NAME,MAC,MASK) \
127: { .name = NAME, .mac_version = MAC, .RxConfigMask = MASK }
128:
129: static const struct {
130: const char *name;
131: u8 mac_version;
132: u32 RxConfigMask; /* Clears the bits supported by this chip */
133: } rtl_chip_info[] = {
134: _R("RTL8169", RTL_GIGA_MAC_VER_01, 0xff7e1880), // 8169
135: _R("RTL8169s", RTL_GIGA_MAC_VER_02, 0xff7e1880), // 8169S
136: _R("RTL8110s", RTL_GIGA_MAC_VER_03, 0xff7e1880), // 8110S
137: _R("RTL8169sb/8110sb", RTL_GIGA_MAC_VER_04, 0xff7e1880), // 8169SB
138: _R("RTL8169sc/8110sc", RTL_GIGA_MAC_VER_05, 0xff7e1880), // 8110SCd
139: _R("RTL8169sc/8110sc", RTL_GIGA_MAC_VER_06, 0xff7e1880), // 8110SCe
140: _R("RTL8102e", RTL_GIGA_MAC_VER_07, 0xff7e1880), // PCI-E
141: _R("RTL8102e", RTL_GIGA_MAC_VER_08, 0xff7e1880), // PCI-E
142: _R("RTL8102e", RTL_GIGA_MAC_VER_09, 0xff7e1880), // PCI-E
143: _R("RTL8101e", RTL_GIGA_MAC_VER_10, 0xff7e1880), // PCI-E
144: _R("RTL8168b/8111b", RTL_GIGA_MAC_VER_11, 0xff7e1880), // PCI-E
145: _R("RTL8168b/8111b", RTL_GIGA_MAC_VER_12, 0xff7e1880), // PCI-E
146: _R("RTL8101e", RTL_GIGA_MAC_VER_13, 0xff7e1880), // PCI-E 8139
147: _R("RTL8100e", RTL_GIGA_MAC_VER_14, 0xff7e1880), // PCI-E 8139
148: _R("RTL8100e", RTL_GIGA_MAC_VER_15, 0xff7e1880), // PCI-E 8139
149: _R("RTL8168b/8111b", RTL_GIGA_MAC_VER_17, 0xff7e1880), // PCI-E
150: _R("RTL8101e", RTL_GIGA_MAC_VER_16, 0xff7e1880), // PCI-E
151: _R("RTL8168cp/8111cp", RTL_GIGA_MAC_VER_18, 0xff7e1880), // PCI-E
152: _R("RTL8168c/8111c", RTL_GIGA_MAC_VER_19, 0xff7e1880), // PCI-E
153: _R("RTL8168c/8111c", RTL_GIGA_MAC_VER_20, 0xff7e1880), // PCI-E
154: _R("RTL8168c/8111c", RTL_GIGA_MAC_VER_21, 0xff7e1880), // PCI-E
155: _R("RTL8168c/8111c", RTL_GIGA_MAC_VER_22, 0xff7e1880), // PCI-E
156: _R("RTL8168cp/8111cp", RTL_GIGA_MAC_VER_23, 0xff7e1880), // PCI-E
157: _R("RTL8168cp/8111cp", RTL_GIGA_MAC_VER_24, 0xff7e1880), // PCI-E
158: _R("RTL8168d/8111d", RTL_GIGA_MAC_VER_25, 0xff7e1880) // PCI-E
159: };
160: #undef _R
161:
162: enum cfg_version {
163: RTL_CFG_0 = 0x00,
164: RTL_CFG_1,
165: RTL_CFG_2
166: };
167:
168: #if 0
169: /** Device Table from Linux Driver **/
170: static struct pci_device_id rtl8169_pci_tbl[] = {
171: { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8129), 0, 0, RTL_CFG_0 },
172: { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8136), 0, 0, RTL_CFG_2 },
173: { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8167), 0, 0, RTL_CFG_0 },
174: { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8168), 0, 0, RTL_CFG_1 },
175: { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8169), 0, 0, RTL_CFG_0 },
176: { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4300), 0, 0, RTL_CFG_0 },
177: { PCI_DEVICE(PCI_VENDOR_ID_AT, 0xc107), 0, 0, RTL_CFG_0 },
178: { PCI_DEVICE(0x16ec, 0x0116), 0, 0, RTL_CFG_0 },
179: { PCI_VENDOR_ID_LINKSYS, 0x1032,
180: PCI_ANY_ID, 0x0024, 0, 0, RTL_CFG_0 },
181: { 0x0001, 0x8168,
182: PCI_ANY_ID, 0x2410, 0, 0, RTL_CFG_2 },
183: {0,},
184: };
185: #endif
186:
187: enum rtl_registers {
188: MAC0 = 0, /* Ethernet hardware address. */
189: MAC4 = 4,
190: MAR0 = 8, /* Multicast filter. */
191: CounterAddrLow = 0x10,
192: CounterAddrHigh = 0x14,
193: TxDescStartAddrLow = 0x20,
194: TxDescStartAddrHigh = 0x24,
195: TxHDescStartAddrLow = 0x28,
196: TxHDescStartAddrHigh = 0x2c,
197: FLASH = 0x30,
198: ERSR = 0x36,
199: ChipCmd = 0x37,
200: TxPoll = 0x38,
201: IntrMask = 0x3c,
202: IntrStatus = 0x3e,
203: TxConfig = 0x40,
204: RxConfig = 0x44,
205: RxMissed = 0x4c,
206: Cfg9346 = 0x50,
207: Config0 = 0x51,
208: Config1 = 0x52,
209: Config2 = 0x53,
210: Config3 = 0x54,
211: Config4 = 0x55,
212: Config5 = 0x56,
213: MultiIntr = 0x5c,
214: PHYAR = 0x60,
215: PHYstatus = 0x6c,
216: RxMaxSize = 0xda,
217: CPlusCmd = 0xe0,
218: IntrMitigate = 0xe2,
219: RxDescAddrLow = 0xe4,
220: RxDescAddrHigh = 0xe8,
221: EarlyTxThres = 0xec,
222: FuncEvent = 0xf0,
223: FuncEventMask = 0xf4,
224: FuncPresetState = 0xf8,
225: FuncForceEvent = 0xfc,
226: };
227:
228: enum rtl8110_registers {
229: TBICSR = 0x64,
230: TBI_ANAR = 0x68,
231: TBI_LPAR = 0x6a,
232: };
233:
234: enum rtl8168_8101_registers {
235: CSIDR = 0x64,
236: CSIAR = 0x68,
237: #define CSIAR_FLAG 0x80000000
238: #define CSIAR_WRITE_CMD 0x80000000
239: #define CSIAR_BYTE_ENABLE 0x0f
240: #define CSIAR_BYTE_ENABLE_SHIFT 12
241: #define CSIAR_ADDR_MASK 0x0fff
242:
243: EPHYAR = 0x80,
244: #define EPHYAR_FLAG 0x80000000
245: #define EPHYAR_WRITE_CMD 0x80000000
246: #define EPHYAR_REG_MASK 0x1f
247: #define EPHYAR_REG_SHIFT 16
248: #define EPHYAR_DATA_MASK 0xffff
249: DBG_REG = 0xd1,
250: #define FIX_NAK_1 (1 << 4)
251: #define FIX_NAK_2 (1 << 3)
252: };
253:
254: enum rtl_register_content {
255: /* InterruptStatusBits */
256: SYSErr = 0x8000,
257: PCSTimeout = 0x4000,
258: SWInt = 0x0100,
259: TxDescUnavail = 0x0080,
260: RxFIFOOver = 0x0040,
261: LinkChg = 0x0020,
262: RxOverflow = 0x0010,
263: TxErr = 0x0008,
264: TxOK = 0x0004,
265: RxErr = 0x0002,
266: RxOK = 0x0001,
267:
268: /* RxStatusDesc */
269: RxFOVF = (1 << 23),
270: RxRWT = (1 << 22),
271: RxRES = (1 << 21),
272: RxRUNT = (1 << 20),
273: RxCRC = (1 << 19),
274:
275: /* ChipCmdBits */
276: CmdReset = 0x10,
277: CmdRxEnb = 0x08,
278: CmdTxEnb = 0x04,
279: RxBufEmpty = 0x01,
280:
281: /* TXPoll register p.5 */
282: HPQ = 0x80, /* Poll cmd on the high prio queue */
283: NPQ = 0x40, /* Poll cmd on the low prio queue */
284: FSWInt = 0x01, /* Forced software interrupt */
285:
286: /* Cfg9346Bits */
287: Cfg9346_Lock = 0x00,
288: Cfg9346_Unlock = 0xc0,
289:
290: /* rx_mode_bits */
291: AcceptErr = 0x20,
292: AcceptRunt = 0x10,
293: AcceptBroadcast = 0x08,
294: AcceptMulticast = 0x04,
295: AcceptMyPhys = 0x02,
296: AcceptAllPhys = 0x01,
297:
298: /* RxConfigBits */
299: RxCfgFIFOShift = 13,
300: RxCfgDMAShift = 8,
301:
302: /* TxConfigBits */
303: TxInterFrameGapShift = 24,
304: TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
305:
306: /* Config1 register p.24 */
307: LEDS1 = (1 << 7),
308: LEDS0 = (1 << 6),
309: MSIEnable = (1 << 5), /* Enable Message Signaled Interrupt */
310: Speed_down = (1 << 4),
311: MEMMAP = (1 << 3),
312: IOMAP = (1 << 2),
313: VPD = (1 << 1),
314: PMEnable = (1 << 0), /* Power Management Enable */
315:
316: /* Config2 register p. 25 */
317: PCI_Clock_66MHz = 0x01,
318: PCI_Clock_33MHz = 0x00,
319:
320: /* Config3 register p.25 */
321: MagicPacket = (1 << 5), /* Wake up when receives a Magic Packet */
322: LinkUp = (1 << 4), /* Wake up when the cable connection is re-established */
323: Beacon_en = (1 << 0), /* 8168 only. Reserved in the 8168b */
324:
325: /* Config5 register p.27 */
326: BWF = (1 << 6), /* Accept Broadcast wakeup frame */
327: MWF = (1 << 5), /* Accept Multicast wakeup frame */
328: UWF = (1 << 4), /* Accept Unicast wakeup frame */
329: LanWake = (1 << 1), /* LanWake enable/disable */
330: PMEStatus = (1 << 0), /* PME status can be reset by PCI RST# */
331:
332: /* TBICSR p.28 */
333: TBIReset = 0x80000000,
334: TBILoopback = 0x40000000,
335: TBINwEnable = 0x20000000,
336: TBINwRestart = 0x10000000,
337: TBILinkOk = 0x02000000,
338: TBINwComplete = 0x01000000,
339:
340: /* CPlusCmd p.31 */
341: EnableBist = (1 << 15), // 8168 8101
342: Mac_dbgo_oe = (1 << 14), // 8168 8101
343: Normal_mode = (1 << 13), // unused
344: Force_half_dup = (1 << 12), // 8168 8101
345: Force_rxflow_en = (1 << 11), // 8168 8101
346: Force_txflow_en = (1 << 10), // 8168 8101
347: Cxpl_dbg_sel = (1 << 9), // 8168 8101
348: ASF = (1 << 8), // 8168 8101
349: PktCntrDisable = (1 << 7), // 8168 8101
350: Mac_dbgo_sel = 0x001c, // 8168
351: RxVlan = (1 << 6),
352: RxChkSum = (1 << 5),
353: PCIDAC = (1 << 4),
354: PCIMulRW = (1 << 3),
355: INTT_0 = 0x0000, // 8168
356: INTT_1 = 0x0001, // 8168
357: INTT_2 = 0x0002, // 8168
358: INTT_3 = 0x0003, // 8168
359:
360: /* rtl8169_PHYstatus */
361: TBI_Enable = 0x80,
362: TxFlowCtrl = 0x40,
363: RxFlowCtrl = 0x20,
364: _1000bpsF = 0x10,
365: _100bps = 0x08,
366: _10bps = 0x04,
367: LinkStatus = 0x02,
368: FullDup = 0x01,
369:
370: /* _TBICSRBit */
371: TBILinkOK = 0x02000000,
372:
373: /* DumpCounterCommand */
374: CounterDump = 0x8,
375: };
376:
377: enum desc_status_bit {
378: DescOwn = (1 << 31), /* Descriptor is owned by NIC */
379: RingEnd = (1 << 30), /* End of descriptor ring */
380: FirstFrag = (1 << 29), /* First segment of a packet */
381: LastFrag = (1 << 28), /* Final segment of a packet */
382:
383: /* Tx private */
384: LargeSend = (1 << 27), /* TCP Large Send Offload (TSO) */
385: MSSShift = 16, /* MSS value position */
386: MSSMask = 0xfff, /* MSS value + LargeSend bit: 12 bits */
387: IPCS = (1 << 18), /* Calculate IP checksum */
388: UDPCS = (1 << 17), /* Calculate UDP/IP checksum */
389: TCPCS = (1 << 16), /* Calculate TCP/IP checksum */
390: TxVlanTag = (1 << 17), /* Add VLAN tag */
391:
392: /* Rx private */
393: PID1 = (1 << 18), /* Protocol ID bit 1/2 */
394: PID0 = (1 << 17), /* Protocol ID bit 2/2 */
395:
396: #define RxProtoUDP (PID1)
397: #define RxProtoTCP (PID0)
398: #define RxProtoIP (PID1 | PID0)
399: #define RxProtoMask RxProtoIP
400:
401: IPFail = (1 << 16), /* IP checksum failed */
402: UDPFail = (1 << 15), /* UDP/IP checksum failed */
403: TCPFail = (1 << 14), /* TCP/IP checksum failed */
404: RxVlanTag = (1 << 16), /* VLAN tag available */
405: };
406:
407: #define RsvdMask 0x3fffc000
408:
409: struct TxDesc {
410: volatile uint32_t opts1;
411: volatile uint32_t opts2;
412: volatile uint32_t addr_lo;
413: volatile uint32_t addr_hi;
414: };
415:
416: struct RxDesc {
417: volatile uint32_t opts1;
418: volatile uint32_t opts2;
419: volatile uint32_t addr_lo;
420: volatile uint32_t addr_hi;
421: };
422:
423: enum features {
424: RTL_FEATURE_WOL = (1 << 0),
425: RTL_FEATURE_MSI = (1 << 1),
426: RTL_FEATURE_GMII = (1 << 2),
427: };
428:
429: static void rtl_hw_start_8169(struct net_device *);
430: static void rtl_hw_start_8168(struct net_device *);
431: static void rtl_hw_start_8101(struct net_device *);
432:
433: struct rtl8169_private {
434:
435: struct pci_device *pci_dev;
436: struct net_device *netdev;
437: uint8_t *hw_addr;
438: void *mmio_addr;
439: uint32_t irqno;
440:
441: int chipset;
442: int mac_version;
443: u16 intr_event;
444:
445: struct io_buffer *tx_iobuf[NUM_TX_DESC];
446: struct io_buffer *rx_iobuf[NUM_RX_DESC];
447:
448: struct TxDesc *tx_base;
449: struct RxDesc *rx_base;
450:
451: uint32_t tx_curr;
452: uint32_t rx_curr;
453:
454: uint32_t tx_tail;
455:
456: uint32_t tx_fill_ctr;
457:
458: u16 cp_cmd;
459:
460: int phy_auto_nego_reg;
461: int phy_1000_ctrl_reg;
462:
463: int ( *set_speed ) (struct net_device *, u8 autoneg, u16 speed, u8 duplex );
464: void ( *phy_reset_enable ) ( void *ioaddr );
465: void ( *hw_start ) ( struct net_device * );
466: unsigned int ( *phy_reset_pending ) ( void *ioaddr );
467: unsigned int ( *link_ok ) ( void *ioaddr );
468:
469: int pcie_cap;
470:
471: unsigned features;
472:
473: };
474:
475: static const unsigned int rtl8169_rx_config =
476: (RX_FIFO_THRESH << RxCfgFIFOShift) | (RX_DMA_BURST << RxCfgDMAShift);
477:
478: #endif /* _R8169_H_ */
479:
480: /*
481: * Local variables:
482: * c-basic-offset: 8
483: * c-indent-level: 8
484: * tab-width: 8
485: * End:
486: */
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