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1.1 root 1: /*------------------------------------------------------------------------
2: * smc9000.h
3: *
4: * Copyright (C) 1998 by Daniel Engstr�m
5: * Copyright (C) 1996 by Erik Stahlman
6: *
7: * This software may be used and distributed according to the terms
8: * of the GNU Public License, incorporated herein by reference.
9: *
10: * This file contains register information and access macros for
11: * the SMC91xxx chipset.
12: *
13: * Information contained in this file was obtained from the SMC91C94
14: * manual from SMC. To get a copy, if you really want one, you can find
15: * information under www.smsc.com in the components division.
16: * ( this thanks to advice from Donald Becker ).
17: *
18: * Authors
19: * Daniel Engstr�m <[email protected]>
20: * Erik Stahlman <[email protected]>
21: *
22: * History
23: * 96-01-06 Erik Stahlman moved definitions here from main .c
24: * file
25: * 96-01-19 Erik Stahlman polished this up some, and added
26: * better error handling
27: * 98-09-25 Daniel Engstr�m adjusted for Etherboot
28: * 98-09-27 Daniel Engstr�m moved some static strings back to the
29: * main .c file
30: * --------------------------------------------------------------------------*/
31:
32: FILE_LICENCE ( GPL_ANY );
33:
34: #ifndef _SMC9000_H_
35: # define _SMC9000_H_
36:
37: /* I want some simple types */
38: typedef unsigned char byte;
39: typedef unsigned short word;
40: typedef unsigned long int dword;
41:
42: /*---------------------------------------------------------------
43: *
44: * A description of the SMC registers is probably in order here,
45: * although for details, the SMC datasheet is invaluable.
46: *
47: * Basically, the chip has 4 banks of registers ( 0 to 3 ), which
48: * are accessed by writing a number into the BANK_SELECT register
49: * ( I also use a SMC_SELECT_BANK macro for this ).
50: *
51: * The banks are configured so that for most purposes, bank 2 is all
52: * that is needed for simple run time tasks.
53: * ----------------------------------------------------------------------*/
54:
55: /*
56: * Bank Select Register:
57: *
58: * yyyy yyyy 0000 00xx
59: * xx = bank number
60: * yyyy yyyy = 0x33, for identification purposes.
61: */
62: #define BANK_SELECT 14
63:
64: /* BANK 0 */
65:
66: #define TCR 0 /* transmit control register */
67: #define TCR_ENABLE 0x0001 /* if this is 1, we can transmit */
68: #define TCR_FDUPLX 0x0800 /* receive packets sent out */
69: #define TCR_STP_SQET 0x1000 /* stop transmitting if Signal quality error */
70: #define TCR_MON_CNS 0x0400 /* monitors the carrier status */
71: #define TCR_PAD_ENABLE 0x0080 /* pads short packets to 64 bytes */
72:
73: #define TCR_CLEAR 0 /* do NOTHING */
74: /* the normal settings for the TCR register : */
75: #define TCR_NORMAL (TCR_ENABLE | TCR_PAD_ENABLE)
76:
77:
78: #define EPH_STATUS 2
79: #define ES_LINK_OK 0x4000 /* is the link integrity ok ? */
80:
81: #define RCR 4
82: #define RCR_SOFTRESET 0x8000 /* resets the chip */
83: #define RCR_STRIP_CRC 0x200 /* strips CRC */
84: #define RCR_ENABLE 0x100 /* IFF this is set, we can receive packets */
85: #define RCR_ALMUL 0x4 /* receive all multicast packets */
86: #define RCR_PROMISC 0x2 /* enable promiscuous mode */
87:
88: /* the normal settings for the RCR register : */
89: #define RCR_NORMAL (RCR_STRIP_CRC | RCR_ENABLE)
90: #define RCR_CLEAR 0x0 /* set it to a base state */
91:
92: #define COUNTER 6
93: #define MIR 8
94: #define MCR 10
95: /* 12 is reserved */
96:
97: // Receive/Phy Control Register
98: /* BANK 0 */
99: #define RPC_REG 0x000A
100: #define RPC_SPEED 0x2000 // When 1 PHY is in 100Mbps mode.
101: #define RPC_DPLX 0x1000 // When 1 PHY is in Full-Duplex Mode
102: #define RPC_ANEG 0x0800 // When 1 PHY is in Auto-Negotiate Mode
103: #define RPC_LSXA_SHFT 5 // Bits to shift LS2A,LS1A,LS0A to lsb
104: #define RPC_LSXB_SHFT 2 // Bits to get LS2B,LS1B,LS0B to lsb
105: #define RPC_LED_100_10 (0x00) // LED = 100Mbps OR's with 10Mbps link detect
106: #define RPC_LED_RES (0x01) // LED = Reserved
107: #define RPC_LED_10 (0x02) // LED = 10Mbps link detect
108: #define RPC_LED_FD (0x03) // LED = Full Duplex Mode
109: #define RPC_LED_TX_RX (0x04) // LED = TX or RX packet occurred
110: #define RPC_LED_100 (0x05) // LED = 100Mbps link dectect
111: #define RPC_LED_TX (0x06) // LED = TX packet occurred
112: #define RPC_LED_RX (0x07) // LED = RX packet occurred
113: #define RPC_DEFAULT (RPC_ANEG | (RPC_LED_100 << RPC_LSXA_SHFT) | (RPC_LED_FD << RPC_LSXB_SHFT) | RPC_SPEED | RPC_DPLX)
114:
115: // Receive/Phy Control Register
116: /* BANK 0 */
117: #define RPC_REG 0x000A
118: #define RPC_SPEED 0x2000 // When 1 PHY is in 100Mbps mode.
119: #define RPC_DPLX 0x1000 // When 1 PHY is in Full-Duplex Mode
120: #define RPC_ANEG 0x0800 // When 1 PHY is in Auto-Negotiate Mode
121: #define RPC_LSXA_SHFT 5 // Bits to shift LS2A,LS1A,LS0A to lsb
122: #define RPC_LSXB_SHFT 2 // Bits to get LS2B,LS1B,LS0B to lsb
123: #define RPC_LED_100_10 (0x00) // LED = 100Mbps OR's with 10Mbps link detect
124: #define RPC_LED_RES (0x01) // LED = Reserved
125: #define RPC_LED_10 (0x02) // LED = 10Mbps link detect
126: #define RPC_LED_FD (0x03) // LED = Full Duplex Mode
127: #define RPC_LED_TX_RX (0x04) // LED = TX or RX packet occurred
128: #define RPC_LED_100 (0x05) // LED = 100Mbps link dectect
129: #define RPC_LED_TX (0x06) // LED = TX packet occurred
130: #define RPC_LED_RX (0x07) // LED = RX packet occurred
131: #define RPC_DEFAULT (RPC_ANEG | (RPC_LED_100 << RPC_LSXA_SHFT) | (RPC_LED_FD << RPC_LSXB_SHFT) | RPC_SPEED | RPC_DPLX)
132:
133: /* BANK 1 */
134: #define CONFIG 0
135: #define CFG_AUI_SELECT 0x100
136: #define BASE 2
137: #define ADDR0 4
138: #define ADDR1 6
139: #define ADDR2 8
140: #define GENERAL 10
141: #define CONTROL 12
142: #define CTL_POWERDOWN 0x2000
143: #define CTL_LE_ENABLE 0x80
144: #define CTL_CR_ENABLE 0x40
145: #define CTL_TE_ENABLE 0x0020
146: #define CTL_AUTO_RELEASE 0x0800
147: #define CTL_EPROM_ACCESS 0x0003 /* high if Eprom is being read */
148:
149: /* BANK 2 */
150: #define MMU_CMD 0
151: #define MC_BUSY 1 /* only readable bit in the register */
152: #define MC_NOP 0
153: #define MC_ALLOC 0x20 /* or with number of 256 byte packets */
154: #define MC_RESET 0x40
155: #define MC_REMOVE 0x60 /* remove the current rx packet */
156: #define MC_RELEASE 0x80 /* remove and release the current rx packet */
157: #define MC_FREEPKT 0xA0 /* Release packet in PNR register */
158: #define MC_ENQUEUE 0xC0 /* Enqueue the packet for transmit */
159:
160: #define PNR_ARR 2
161: #define FIFO_PORTS 4
162:
163: #define FP_RXEMPTY 0x8000
164: #define FP_TXEMPTY 0x80
165:
166: #define POINTER 6
167: #define PTR_READ 0x2000
168: #define PTR_RCV 0x8000
169: #define PTR_AUTOINC 0x4000
170: #define PTR_AUTO_INC 0x0040
171:
172: #define DATA_1 8
173: #define DATA_2 10
174: #define INTERRUPT 12
175:
176: #define INT_MASK 13
177: #define IM_RCV_INT 0x1
178: #define IM_TX_INT 0x2
179: #define IM_TX_EMPTY_INT 0x4
180: #define IM_ALLOC_INT 0x8
181: #define IM_RX_OVRN_INT 0x10
182: #define IM_EPH_INT 0x20
183: #define IM_ERCV_INT 0x40 /* not on SMC9192 */
184:
185: /* BANK 3 */
186: #define MULTICAST1 0
187: #define MULTICAST2 2
188: #define MULTICAST3 4
189: #define MULTICAST4 6
190: #define MGMT 8
191: #define REVISION 10 /* ( hi: chip id low: rev # ) */
192:
193: // Management Interface Register (MII)
194: #define MII_REG 0x0008
195: #define MII_MSK_CRS100 0x4000 // Disables CRS100 detection during tx half dup
196: #define MII_MDOE 0x0008 // MII Output Enable
197: #define MII_MCLK 0x0004 // MII Clock, pin MDCLK
198: #define MII_MDI 0x0002 // MII Input, pin MDI
199: #define MII_MDO 0x0001 // MII Output, pin MDO
200:
201: /* this is NOT on SMC9192 */
202: #define ERCV 12
203:
204: /* Note that 9194 and 9196 have the smame chip id,
205: * the 9196 will have revisions starting at 6 */
206: #define CHIP_9190 3
207: #define CHIP_9194 4
208: #define CHIP_9195 5
209: #define CHIP_9196 4
210: #define CHIP_91100 7
211: #define CHIP_91100FD 8
212:
213: #define REV_9196 6
214:
215: /*
216: * Transmit status bits
217: */
218: #define TS_SUCCESS 0x0001
219: #define TS_LOSTCAR 0x0400
220: #define TS_LATCOL 0x0200
221: #define TS_16COL 0x0010
222:
223: /*
224: * Receive status bits
225: */
226: #define RS_ALGNERR 0x8000
227: #define RS_BADCRC 0x2000
228: #define RS_ODDFRAME 0x1000
229: #define RS_TOOLONG 0x0800
230: #define RS_TOOSHORT 0x0400
231: #define RS_MULTICAST 0x0001
232: #define RS_ERRORS (RS_ALGNERR | RS_BADCRC | RS_TOOLONG | RS_TOOSHORT)
233:
234: // PHY Register Addresses (LAN91C111 Internal PHY)
235:
236: // PHY Control Register
237: #define PHY_CNTL_REG 0x00
238: #define PHY_CNTL_RST 0x8000 // 1=PHY Reset
239: #define PHY_CNTL_LPBK 0x4000 // 1=PHY Loopback
240: #define PHY_CNTL_SPEED 0x2000 // 1=100Mbps, 0=10Mpbs
241: #define PHY_CNTL_ANEG_EN 0x1000 // 1=Enable Auto negotiation
242: #define PHY_CNTL_PDN 0x0800 // 1=PHY Power Down mode
243: #define PHY_CNTL_MII_DIS 0x0400 // 1=MII 4 bit interface disabled
244: #define PHY_CNTL_ANEG_RST 0x0200 // 1=Reset Auto negotiate
245: #define PHY_CNTL_DPLX 0x0100 // 1=Full Duplex, 0=Half Duplex
246: #define PHY_CNTL_COLTST 0x0080 // 1= MII Colision Test
247:
248: // PHY Status Register
249: #define PHY_STAT_REG 0x01
250: #define PHY_STAT_CAP_T4 0x8000 // 1=100Base-T4 capable
251: #define PHY_STAT_CAP_TXF 0x4000 // 1=100Base-X full duplex capable
252: #define PHY_STAT_CAP_TXH 0x2000 // 1=100Base-X half duplex capable
253: #define PHY_STAT_CAP_TF 0x1000 // 1=10Mbps full duplex capable
254: #define PHY_STAT_CAP_TH 0x0800 // 1=10Mbps half duplex capable
255: #define PHY_STAT_CAP_SUPR 0x0040 // 1=recv mgmt frames with not preamble
256: #define PHY_STAT_ANEG_ACK 0x0020 // 1=ANEG has completed
257: #define PHY_STAT_REM_FLT 0x0010 // 1=Remote Fault detected
258: #define PHY_STAT_CAP_ANEG 0x0008 // 1=Auto negotiate capable
259: #define PHY_STAT_LINK 0x0004 // 1=valid link
260: #define PHY_STAT_JAB 0x0002 // 1=10Mbps jabber condition
261: #define PHY_STAT_EXREG 0x0001 // 1=extended registers implemented
262:
263: // PHY Identifier Registers
264: #define PHY_ID1_REG 0x02 // PHY Identifier 1
265: #define PHY_ID2_REG 0x03 // PHY Identifier 2
266:
267: // PHY Auto-Negotiation Advertisement Register
268: #define PHY_AD_REG 0x04
269: #define PHY_AD_NP 0x8000 // 1=PHY requests exchange of Next Page
270: #define PHY_AD_ACK 0x4000 // 1=got link code word from remote
271: #define PHY_AD_RF 0x2000 // 1=advertise remote fault
272: #define PHY_AD_T4 0x0200 // 1=PHY is capable of 100Base-T4
273: #define PHY_AD_TX_FDX 0x0100 // 1=PHY is capable of 100Base-TX FDPLX
274: #define PHY_AD_TX_HDX 0x0080 // 1=PHY is capable of 100Base-TX HDPLX
275: #define PHY_AD_10_FDX 0x0040 // 1=PHY is capable of 10Base-T FDPLX
276: #define PHY_AD_10_HDX 0x0020 // 1=PHY is capable of 10Base-T HDPLX
277: #define PHY_AD_CSMA 0x0001 // 1=PHY is capable of 802.3 CMSA
278:
279: // PHY Auto-negotiation Remote End Capability Register
280: #define PHY_RMT_REG 0x05
281: // Uses same bit definitions as PHY_AD_REG
282:
283: // PHY Configuration Register 1
284: #define PHY_CFG1_REG 0x10
285: #define PHY_CFG1_LNKDIS 0x8000 // 1=Rx Link Detect Function disabled
286: #define PHY_CFG1_XMTDIS 0x4000 // 1=TP Transmitter Disabled
287: #define PHY_CFG1_XMTPDN 0x2000 // 1=TP Transmitter Powered Down
288: #define PHY_CFG1_BYPSCR 0x0400 // 1=Bypass scrambler/descrambler
289: #define PHY_CFG1_UNSCDS 0x0200 // 1=Unscramble Idle Reception Disable
290: #define PHY_CFG1_EQLZR 0x0100 // 1=Rx Equalizer Disabled
291: #define PHY_CFG1_CABLE 0x0080 // 1=STP(150ohm), 0=UTP(100ohm)
292: #define PHY_CFG1_RLVL0 0x0040 // 1=Rx Squelch level reduced by 4.5db
293: #define PHY_CFG1_TLVL_SHIFT 2 // Transmit Output Level Adjust
294: #define PHY_CFG1_TLVL_MASK 0x003C
295: #define PHY_CFG1_TRF_MASK 0x0003 // Transmitter Rise/Fall time
296:
297:
298: // PHY Configuration Register 2
299: #define PHY_CFG2_REG 0x11
300: #define PHY_CFG2_APOLDIS 0x0020 // 1=Auto Polarity Correction disabled
301: #define PHY_CFG2_JABDIS 0x0010 // 1=Jabber disabled
302: #define PHY_CFG2_MREG 0x0008 // 1=Multiple register access (MII mgt)
303: #define PHY_CFG2_INTMDIO 0x0004 // 1=Interrupt signaled with MDIO pulseo
304:
305: // PHY Status Output (and Interrupt status) Register
306: #define PHY_INT_REG 0x12 // Status Output (Interrupt Status)
307: #define PHY_INT_INT 0x8000 // 1=bits have changed since last read
308: #define PHY_INT_LNKFAIL 0x4000 // 1=Link Not detected
309: #define PHY_INT_LOSSSYNC 0x2000 // 1=Descrambler has lost sync
310: #define PHY_INT_CWRD 0x1000 // 1=Invalid 4B5B code detected on rx
311: #define PHY_INT_SSD 0x0800 // 1=No Start Of Stream detected on rx
312: #define PHY_INT_ESD 0x0400 // 1=No End Of Stream detected on rx
313: #define PHY_INT_RPOL 0x0200 // 1=Reverse Polarity detected
314: #define PHY_INT_JAB 0x0100 // 1=Jabber detected
315: #define PHY_INT_SPDDET 0x0080 // 1=100Base-TX mode, 0=10Base-T mode
316: #define PHY_INT_DPLXDET 0x0040 // 1=Device in Full Duplex
317:
318: // PHY Interrupt/Status Mask Register
319: #define PHY_MASK_REG 0x13 // Interrupt Mask
320: // Uses the same bit definitions as PHY_INT_REG
321:
322:
323: // PHY Register Addresses (LAN91C111 Internal PHY)
324:
325: // PHY Control Register
326: #define PHY_CNTL_REG 0x00
327: #define PHY_CNTL_RST 0x8000 // 1=PHY Reset
328: #define PHY_CNTL_LPBK 0x4000 // 1=PHY Loopback
329: #define PHY_CNTL_SPEED 0x2000 // 1=100Mbps, 0=10Mpbs
330: #define PHY_CNTL_ANEG_EN 0x1000 // 1=Enable Auto negotiation
331: #define PHY_CNTL_PDN 0x0800 // 1=PHY Power Down mode
332: #define PHY_CNTL_MII_DIS 0x0400 // 1=MII 4 bit interface disabled
333: #define PHY_CNTL_ANEG_RST 0x0200 // 1=Reset Auto negotiate
334: #define PHY_CNTL_DPLX 0x0100 // 1=Full Duplex, 0=Half Duplex
335: #define PHY_CNTL_COLTST 0x0080 // 1= MII Colision Test
336:
337: // PHY Status Register
338: #define PHY_STAT_REG 0x01
339: #define PHY_STAT_CAP_T4 0x8000 // 1=100Base-T4 capable
340: #define PHY_STAT_CAP_TXF 0x4000 // 1=100Base-X full duplex capable
341: #define PHY_STAT_CAP_TXH 0x2000 // 1=100Base-X half duplex capable
342: #define PHY_STAT_CAP_TF 0x1000 // 1=10Mbps full duplex capable
343: #define PHY_STAT_CAP_TH 0x0800 // 1=10Mbps half duplex capable
344: #define PHY_STAT_CAP_SUPR 0x0040 // 1=recv mgmt frames with not preamble
345: #define PHY_STAT_ANEG_ACK 0x0020 // 1=ANEG has completed
346: #define PHY_STAT_REM_FLT 0x0010 // 1=Remote Fault detected
347: #define PHY_STAT_CAP_ANEG 0x0008 // 1=Auto negotiate capable
348: #define PHY_STAT_LINK 0x0004 // 1=valid link
349: #define PHY_STAT_JAB 0x0002 // 1=10Mbps jabber condition
350: #define PHY_STAT_EXREG 0x0001 // 1=extended registers implemented
351:
352: // PHY Identifier Registers
353: #define PHY_ID1_REG 0x02 // PHY Identifier 1
354: #define PHY_ID2_REG 0x03 // PHY Identifier 2
355:
356: // PHY Auto-Negotiation Advertisement Register
357: #define PHY_AD_REG 0x04
358: #define PHY_AD_NP 0x8000 // 1=PHY requests exchange of Next Page
359: #define PHY_AD_ACK 0x4000 // 1=got link code word from remote
360: #define PHY_AD_RF 0x2000 // 1=advertise remote fault
361: #define PHY_AD_T4 0x0200 // 1=PHY is capable of 100Base-T4
362: #define PHY_AD_TX_FDX 0x0100 // 1=PHY is capable of 100Base-TX FDPLX
363: #define PHY_AD_TX_HDX 0x0080 // 1=PHY is capable of 100Base-TX HDPLX
364: #define PHY_AD_10_FDX 0x0040 // 1=PHY is capable of 10Base-T FDPLX
365: #define PHY_AD_10_HDX 0x0020 // 1=PHY is capable of 10Base-T HDPLX
366: #define PHY_AD_CSMA 0x0001 // 1=PHY is capable of 802.3 CMSA
367:
368: // PHY Auto-negotiation Remote End Capability Register
369: #define PHY_RMT_REG 0x05
370: // Uses same bit definitions as PHY_AD_REG
371:
372: // PHY Configuration Register 1
373: #define PHY_CFG1_REG 0x10
374: #define PHY_CFG1_LNKDIS 0x8000 // 1=Rx Link Detect Function disabled
375: #define PHY_CFG1_XMTDIS 0x4000 // 1=TP Transmitter Disabled
376: #define PHY_CFG1_XMTPDN 0x2000 // 1=TP Transmitter Powered Down
377: #define PHY_CFG1_BYPSCR 0x0400 // 1=Bypass scrambler/descrambler
378: #define PHY_CFG1_UNSCDS 0x0200 // 1=Unscramble Idle Reception Disable
379: #define PHY_CFG1_EQLZR 0x0100 // 1=Rx Equalizer Disabled
380: #define PHY_CFG1_CABLE 0x0080 // 1=STP(150ohm), 0=UTP(100ohm)
381: #define PHY_CFG1_RLVL0 0x0040 // 1=Rx Squelch level reduced by 4.5db
382: #define PHY_CFG1_TLVL_SHIFT 2 // Transmit Output Level Adjust
383: #define PHY_CFG1_TLVL_MASK 0x003C
384: #define PHY_CFG1_TRF_MASK 0x0003 // Transmitter Rise/Fall time
385:
386:
387: // PHY Configuration Register 2
388: #define PHY_CFG2_REG 0x11
389: #define PHY_CFG2_APOLDIS 0x0020 // 1=Auto Polarity Correction disabled
390: #define PHY_CFG2_JABDIS 0x0010 // 1=Jabber disabled
391: #define PHY_CFG2_MREG 0x0008 // 1=Multiple register access (MII mgt)
392: #define PHY_CFG2_INTMDIO 0x0004 // 1=Interrupt signaled with MDIO pulseo
393:
394: // PHY Status Output (and Interrupt status) Register
395: #define PHY_INT_REG 0x12 // Status Output (Interrupt Status)
396: #define PHY_INT_INT 0x8000 // 1=bits have changed since last read
397: #define PHY_INT_LNKFAIL 0x4000 // 1=Link Not detected
398: #define PHY_INT_LOSSSYNC 0x2000 // 1=Descrambler has lost sync
399: #define PHY_INT_CWRD 0x1000 // 1=Invalid 4B5B code detected on rx
400: #define PHY_INT_SSD 0x0800 // 1=No Start Of Stream detected on rx
401: #define PHY_INT_ESD 0x0400 // 1=No End Of Stream detected on rx
402: #define PHY_INT_RPOL 0x0200 // 1=Reverse Polarity detected
403: #define PHY_INT_JAB 0x0100 // 1=Jabber detected
404: #define PHY_INT_SPDDET 0x0080 // 1=100Base-TX mode, 0=10Base-T mode
405: #define PHY_INT_DPLXDET 0x0040 // 1=Device in Full Duplex
406:
407: // PHY Interrupt/Status Mask Register
408: #define PHY_MASK_REG 0x13 // Interrupt Mask
409: // Uses the same bit definitions as PHY_INT_REG
410:
411:
412: /*-------------------------------------------------------------------------
413: * I define some macros to make it easier to do somewhat common
414: * or slightly complicated, repeated tasks.
415: --------------------------------------------------------------------------*/
416:
417: /* select a register bank, 0 to 3 */
418:
419: #define SMC_SELECT_BANK(x, y) { _outw( y, x + BANK_SELECT ); }
420:
421: /* define a small delay for the reset */
422: #define SMC_DELAY(x) { inw( x + RCR );\
423: inw( x + RCR );\
424: inw( x + RCR ); }
425:
426:
427: #endif /* _SMC_9000_H_ */
428:
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