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1.1 root 1: /* $Id$
2: * tg3.h: Definitions for Broadcom Tigon3 ethernet driver.
3: *
4: * Copyright (C) 2001, 2002 David S. Miller ([email protected])
5: * Copyright (C) 2001 Jeff Garzik ([email protected])
6: */
7:
8: FILE_LICENCE ( GPL2_ONLY );
9:
10: #ifndef _T3_H
11: #define _T3_H
12:
13: #include "stdint.h"
14:
15: typedef unsigned long dma_addr_t;
16:
17: /* From mii.h */
18:
19: /* Indicates what features are advertised by the interface. */
20: #define ADVERTISED_10baseT_Half (1 << 0)
21: #define ADVERTISED_10baseT_Full (1 << 1)
22: #define ADVERTISED_100baseT_Half (1 << 2)
23: #define ADVERTISED_100baseT_Full (1 << 3)
24: #define ADVERTISED_1000baseT_Half (1 << 4)
25: #define ADVERTISED_1000baseT_Full (1 << 5)
26: #define ADVERTISED_Autoneg (1 << 6)
27: #define ADVERTISED_TP (1 << 7)
28: #define ADVERTISED_AUI (1 << 8)
29: #define ADVERTISED_MII (1 << 9)
30: #define ADVERTISED_FIBRE (1 << 10)
31: #define ADVERTISED_BNC (1 << 11)
32:
33: /* The following are all involved in forcing a particular link
34: * mode for the device for setting things. When getting the
35: * devices settings, these indicate the current mode and whether
36: * it was foced up into this mode or autonegotiated.
37: */
38:
39: /* The forced speed, 10Mb, 100Mb, gigabit. */
40: #define SPEED_10 0
41: #define SPEED_100 1
42: #define SPEED_1000 2
43: #define SPEED_INVALID 3
44:
45:
46: /* Duplex, half or full. */
47: #define DUPLEX_HALF 0x00
48: #define DUPLEX_FULL 0x01
49: #define DUPLEX_INVALID 0x02
50:
51: /* Which connector port. */
52: #define PORT_TP 0x00
53: #define PORT_AUI 0x01
54: #define PORT_MII 0x02
55: #define PORT_FIBRE 0x03
56: #define PORT_BNC 0x04
57:
58: /* Which tranceiver to use. */
59: #define XCVR_INTERNAL 0x00
60: #define XCVR_EXTERNAL 0x01
61: #define XCVR_DUMMY1 0x02
62: #define XCVR_DUMMY2 0x03
63: #define XCVR_DUMMY3 0x04
64:
65: /* Enable or disable autonegotiation. If this is set to enable,
66: * the forced link modes above are completely ignored.
67: */
68: #define AUTONEG_DISABLE 0x00
69: #define AUTONEG_ENABLE 0x01
70:
71: /* Wake-On-Lan options. */
72: #define WAKE_PHY (1 << 0)
73: #define WAKE_UCAST (1 << 1)
74: #define WAKE_MCAST (1 << 2)
75: #define WAKE_BCAST (1 << 3)
76: #define WAKE_ARP (1 << 4)
77: #define WAKE_MAGIC (1 << 5)
78: #define WAKE_MAGICSECURE (1 << 6) /* only meaningful if WAKE_MAGIC */
79:
80: /* From tg3.h */
81:
82: #define TG3_64BIT_REG_HIGH 0x00UL
83: #define TG3_64BIT_REG_LOW 0x04UL
84:
85: /* Descriptor block info. */
86: #define TG3_BDINFO_HOST_ADDR 0x0UL /* 64-bit */
87: #define TG3_BDINFO_MAXLEN_FLAGS 0x8UL /* 32-bit */
88: #define BDINFO_FLAGS_USE_EXT_RECV 0x00000001 /* ext rx_buffer_desc */
89: #define BDINFO_FLAGS_DISABLED 0x00000002
90: #define BDINFO_FLAGS_MAXLEN_MASK 0xffff0000
91: #define BDINFO_FLAGS_MAXLEN_SHIFT 16
92: #define TG3_BDINFO_NIC_ADDR 0xcUL /* 32-bit */
93: #define TG3_BDINFO_SIZE 0x10UL
94:
95: #define RX_COPY_THRESHOLD 256
96:
97: #define RX_STD_MAX_SIZE 1536
98: #define RX_STD_MAX_SIZE_5705 512
99: #define RX_JUMBO_MAX_SIZE 0xdeadbeef /* XXX */
100:
101: /* First 256 bytes are a mirror of PCI config space. */
102: #define TG3PCI_VENDOR 0x00000000
103: #define TG3PCI_VENDOR_BROADCOM 0x14e4
104: #define TG3PCI_DEVICE 0x00000002
105: #define TG3PCI_DEVICE_TIGON3_1 0x1644 /* BCM5700 */
106: #define TG3PCI_DEVICE_TIGON3_2 0x1645 /* BCM5701 */
107: #define TG3PCI_DEVICE_TIGON3_3 0x1646 /* BCM5702 */
108: #define TG3PCI_DEVICE_TIGON3_4 0x1647 /* BCM5703 */
109: #define TG3PCI_COMMAND 0x00000004
110: #define TG3PCI_STATUS 0x00000006
111: #define TG3PCI_CCREVID 0x00000008
112: #define TG3PCI_CACHELINESZ 0x0000000c
113: #define TG3PCI_LATTIMER 0x0000000d
114: #define TG3PCI_HEADERTYPE 0x0000000e
115: #define TG3PCI_BIST 0x0000000f
116: #define TG3PCI_BASE0_LOW 0x00000010
117: #define TG3PCI_BASE0_HIGH 0x00000014
118: /* 0x18 --> 0x2c unused */
119: #define TG3PCI_SUBSYSVENID 0x0000002c
120: #define TG3PCI_SUBSYSID 0x0000002e
121: #define TG3PCI_ROMADDR 0x00000030
122: #define TG3PCI_CAPLIST 0x00000034
123: /* 0x35 --> 0x3c unused */
124: #define TG3PCI_IRQ_LINE 0x0000003c
125: #define TG3PCI_IRQ_PIN 0x0000003d
126: #define TG3PCI_MIN_GNT 0x0000003e
127: #define TG3PCI_MAX_LAT 0x0000003f
128: #define TG3PCI_X_CAPS 0x00000040
129: #define PCIX_CAPS_RELAXED_ORDERING 0x00020000
130: #define PCIX_CAPS_SPLIT_MASK 0x00700000
131: #define PCIX_CAPS_SPLIT_SHIFT 20
132: #define PCIX_CAPS_BURST_MASK 0x000c0000
133: #define PCIX_CAPS_BURST_SHIFT 18
134: #define PCIX_CAPS_MAX_BURST_CPIOB 2
135: #define TG3PCI_PM_CAP_PTR 0x00000041
136: #define TG3PCI_X_COMMAND 0x00000042
137: #define TG3PCI_X_STATUS 0x00000044
138: #define TG3PCI_PM_CAP_ID 0x00000048
139: #define TG3PCI_VPD_CAP_PTR 0x00000049
140: #define TG3PCI_PM_CAPS 0x0000004a
141: #define TG3PCI_PM_CTRL_STAT 0x0000004c
142: #define TG3PCI_BR_SUPP_EXT 0x0000004e
143: #define TG3PCI_PM_DATA 0x0000004f
144: #define TG3PCI_VPD_CAP_ID 0x00000050
145: #define TG3PCI_MSI_CAP_PTR 0x00000051
146: #define TG3PCI_VPD_ADDR_FLAG 0x00000052
147: #define VPD_ADDR_FLAG_WRITE 0x00008000
148: #define TG3PCI_VPD_DATA 0x00000054
149: #define TG3PCI_MSI_CAP_ID 0x00000058
150: #define TG3PCI_NXT_CAP_PTR 0x00000059
151: #define TG3PCI_MSI_CTRL 0x0000005a
152: #define TG3PCI_MSI_ADDR_LOW 0x0000005c
153: #define TG3PCI_MSI_ADDR_HIGH 0x00000060
154: #define TG3PCI_MSI_DATA 0x00000064
155: /* 0x66 --> 0x68 unused */
156: #define TG3PCI_MISC_HOST_CTRL 0x00000068
157: #define MISC_HOST_CTRL_CLEAR_INT 0x00000001
158: #define MISC_HOST_CTRL_MASK_PCI_INT 0x00000002
159: #define MISC_HOST_CTRL_BYTE_SWAP 0x00000004
160: #define MISC_HOST_CTRL_WORD_SWAP 0x00000008
161: #define MISC_HOST_CTRL_PCISTATE_RW 0x00000010
162: #define MISC_HOST_CTRL_CLKREG_RW 0x00000020
163: #define MISC_HOST_CTRL_REGWORD_SWAP 0x00000040
164: #define MISC_HOST_CTRL_INDIR_ACCESS 0x00000080
165: #define MISC_HOST_CTRL_IRQ_MASK_MODE 0x00000100
166: #define MISC_HOST_CTRL_TAGGED_STATUS 0x00000200
167: #define MISC_HOST_CTRL_CHIPREV 0xffff0000
168: #define MISC_HOST_CTRL_CHIPREV_SHIFT 16
169: #define GET_CHIP_REV_ID(MISC_HOST_CTRL) \
170: (((MISC_HOST_CTRL) & MISC_HOST_CTRL_CHIPREV) >> \
171: MISC_HOST_CTRL_CHIPREV_SHIFT)
172: #define CHIPREV_ID_5700_A0 0x7000
173: #define CHIPREV_ID_5700_A1 0x7001
174: #define CHIPREV_ID_5700_B0 0x7100
175: #define CHIPREV_ID_5700_B1 0x7101
176: #define CHIPREV_ID_5700_B3 0x7102
177: #define CHIPREV_ID_5700_ALTIMA 0x7104
178: #define CHIPREV_ID_5700_C0 0x7200
179: #define CHIPREV_ID_5701_A0 0x0000
180: #define CHIPREV_ID_5701_B0 0x0100
181: #define CHIPREV_ID_5701_B2 0x0102
182: #define CHIPREV_ID_5701_B5 0x0105
183: #define CHIPREV_ID_5703_A0 0x1000
184: #define CHIPREV_ID_5703_A1 0x1001
185: #define CHIPREV_ID_5703_A2 0x1002
186: #define CHIPREV_ID_5703_A3 0x1003
187: #define CHIPREV_ID_5704_A0 0x2000
188: #define CHIPREV_ID_5704_A1 0x2001
189: #define CHIPREV_ID_5704_A2 0x2002
190: #define CHIPREV_ID_5705_A0 0x3000
191: #define CHIPREV_ID_5705_A1 0x3001
192: #define CHIPREV_ID_5705_A2 0x3002
193: #define CHIPREV_ID_5705_A3 0x3003
194: #define CHIPREV_ID_5721 0x4101
195: #define CHIPREV_ID_5750_A0 0x4000
196: #define CHIPREV_ID_5750_A1 0x4001
197: #define CHIPREV_ID_5750_A3 0x4003
198: #define GET_ASIC_REV(CHIP_REV_ID) ((CHIP_REV_ID) >> 12)
199: #define ASIC_REV_5700 0x07
200: #define ASIC_REV_5701 0x00
201: #define ASIC_REV_5703 0x01
202: #define ASIC_REV_5704 0x02
203: #define ASIC_REV_5705 0x03
204: #define ASIC_REV_5750 0x04
205: #define ASIC_REV_5787 0x0b
206: #define GET_CHIP_REV(CHIP_REV_ID) ((CHIP_REV_ID) >> 8)
207: #define CHIPREV_5700_AX 0x70
208: #define CHIPREV_5700_BX 0x71
209: #define CHIPREV_5700_CX 0x72
210: #define CHIPREV_5701_AX 0x00
211: #define GET_METAL_REV(CHIP_REV_ID) ((CHIP_REV_ID) & 0xff)
212: #define METAL_REV_A0 0x00
213: #define METAL_REV_A1 0x01
214: #define METAL_REV_B0 0x00
215: #define METAL_REV_B1 0x01
216: #define METAL_REV_B2 0x02
217: #define TG3PCI_DMA_RW_CTRL 0x0000006c
218: #define DMA_RWCTRL_MIN_DMA 0x000000ff
219: #define DMA_RWCTRL_MIN_DMA_SHIFT 0
220: #define DMA_RWCTRL_READ_BNDRY_MASK 0x00000700
221: #define DMA_RWCTRL_READ_BNDRY_DISAB 0x00000000
222: #define DMA_RWCTRL_READ_BNDRY_16 0x00000100
223: #define DMA_RWCTRL_READ_BNDRY_32 0x00000200
224: #define DMA_RWCTRL_READ_BNDRY_64 0x00000300
225: #define DMA_RWCTRL_READ_BNDRY_128 0x00000400
226: #define DMA_RWCTRL_READ_BNDRY_256 0x00000500
227: #define DMA_RWCTRL_READ_BNDRY_512 0x00000600
228: #define DMA_RWCTRL_READ_BNDRY_1024 0x00000700
229: #define DMA_RWCTRL_WRITE_BNDRY_MASK 0x00003800
230: #define DMA_RWCTRL_WRITE_BNDRY_DISAB 0x00000000
231: #define DMA_RWCTRL_WRITE_BNDRY_16 0x00000800
232: #define DMA_RWCTRL_WRITE_BNDRY_32 0x00001000
233: #define DMA_RWCTRL_WRITE_BNDRY_64 0x00001800
234: #define DMA_RWCTRL_WRITE_BNDRY_128 0x00002000
235: #define DMA_RWCTRL_WRITE_BNDRY_256 0x00002800
236: #define DMA_RWCTRL_WRITE_BNDRY_512 0x00003000
237: #define DMA_RWCTRL_WRITE_BNDRY_1024 0x00003800
238: #define DMA_RWCTRL_ONE_DMA 0x00004000
239: #define DMA_RWCTRL_READ_WATER 0x00070000
240: #define DMA_RWCTRL_READ_WATER_SHIFT 16
241: #define DMA_RWCTRL_WRITE_WATER 0x00380000
242: #define DMA_RWCTRL_WRITE_WATER_SHIFT 19
243: #define DMA_RWCTRL_USE_MEM_READ_MULT 0x00400000
244: #define DMA_RWCTRL_ASSERT_ALL_BE 0x00800000
245: #define DMA_RWCTRL_PCI_READ_CMD 0x0f000000
246: #define DMA_RWCTRL_PCI_READ_CMD_SHIFT 24
247: #define DMA_RWCTRL_PCI_WRITE_CMD 0xf0000000
248: #define DMA_RWCTRL_PCI_WRITE_CMD_SHIFT 28
249: #define TG3PCI_PCISTATE 0x00000070
250: #define PCISTATE_FORCE_RESET 0x00000001
251: #define PCISTATE_INT_NOT_ACTIVE 0x00000002
252: #define PCISTATE_CONV_PCI_MODE 0x00000004
253: #define PCISTATE_BUS_SPEED_HIGH 0x00000008
254: #define PCISTATE_BUS_32BIT 0x00000010
255: #define PCISTATE_ROM_ENABLE 0x00000020
256: #define PCISTATE_ROM_RETRY_ENABLE 0x00000040
257: #define PCISTATE_FLAT_VIEW 0x00000100
258: #define PCISTATE_RETRY_SAME_DMA 0x00002000
259: #define TG3PCI_CLOCK_CTRL 0x00000074
260: #define CLOCK_CTRL_CORECLK_DISABLE 0x00000200
261: #define CLOCK_CTRL_RXCLK_DISABLE 0x00000400
262: #define CLOCK_CTRL_TXCLK_DISABLE 0x00000800
263: #define CLOCK_CTRL_ALTCLK 0x00001000
264: #define CLOCK_CTRL_PWRDOWN_PLL133 0x00008000
265: #define CLOCK_CTRL_44MHZ_CORE 0x00040000
266: #define CLOCK_CTRL_625_CORE 0x00100000
267: #define CLOCK_CTRL_FORCE_CLKRUN 0x00200000
268: #define CLOCK_CTRL_CLKRUN_OENABLE 0x00400000
269: #define CLOCK_CTRL_DELAY_PCI_GRANT 0x80000000
270: #define TG3PCI_REG_BASE_ADDR 0x00000078
271: #define TG3PCI_MEM_WIN_BASE_ADDR 0x0000007c
272: #define TG3PCI_REG_DATA 0x00000080
273: #define TG3PCI_MEM_WIN_DATA 0x00000084
274: #define TG3PCI_MODE_CTRL 0x00000088
275: #define TG3PCI_MISC_CFG 0x0000008c
276: #define TG3PCI_MISC_LOCAL_CTRL 0x00000090
277: /* 0x94 --> 0x98 unused */
278: #define TG3PCI_STD_RING_PROD_IDX 0x00000098 /* 64-bit */
279: #define TG3PCI_RCV_RET_RING_CON_IDX 0x000000a0 /* 64-bit */
280: #define TG3PCI_SND_PROD_IDX 0x000000a8 /* 64-bit */
281: /* 0xb0 --> 0x100 unused */
282:
283: /* 0x100 --> 0x200 unused */
284:
285: /* Mailbox registers */
286: #define MAILBOX_INTERRUPT_0 0x00000200 /* 64-bit */
287: #define MAILBOX_INTERRUPT_1 0x00000208 /* 64-bit */
288: #define MAILBOX_INTERRUPT_2 0x00000210 /* 64-bit */
289: #define MAILBOX_INTERRUPT_3 0x00000218 /* 64-bit */
290: #define MAILBOX_GENERAL_0 0x00000220 /* 64-bit */
291: #define MAILBOX_GENERAL_1 0x00000228 /* 64-bit */
292: #define MAILBOX_GENERAL_2 0x00000230 /* 64-bit */
293: #define MAILBOX_GENERAL_3 0x00000238 /* 64-bit */
294: #define MAILBOX_GENERAL_4 0x00000240 /* 64-bit */
295: #define MAILBOX_GENERAL_5 0x00000248 /* 64-bit */
296: #define MAILBOX_GENERAL_6 0x00000250 /* 64-bit */
297: #define MAILBOX_GENERAL_7 0x00000258 /* 64-bit */
298: #define MAILBOX_RELOAD_STAT 0x00000260 /* 64-bit */
299: #define MAILBOX_RCV_STD_PROD_IDX 0x00000268 /* 64-bit */
300: #define MAILBOX_RCV_JUMBO_PROD_IDX 0x00000270 /* 64-bit */
301: #define MAILBOX_RCV_MINI_PROD_IDX 0x00000278 /* 64-bit */
302: #define MAILBOX_RCVRET_CON_IDX_0 0x00000280 /* 64-bit */
303: #define MAILBOX_RCVRET_CON_IDX_1 0x00000288 /* 64-bit */
304: #define MAILBOX_RCVRET_CON_IDX_2 0x00000290 /* 64-bit */
305: #define MAILBOX_RCVRET_CON_IDX_3 0x00000298 /* 64-bit */
306: #define MAILBOX_RCVRET_CON_IDX_4 0x000002a0 /* 64-bit */
307: #define MAILBOX_RCVRET_CON_IDX_5 0x000002a8 /* 64-bit */
308: #define MAILBOX_RCVRET_CON_IDX_6 0x000002b0 /* 64-bit */
309: #define MAILBOX_RCVRET_CON_IDX_7 0x000002b8 /* 64-bit */
310: #define MAILBOX_RCVRET_CON_IDX_8 0x000002c0 /* 64-bit */
311: #define MAILBOX_RCVRET_CON_IDX_9 0x000002c8 /* 64-bit */
312: #define MAILBOX_RCVRET_CON_IDX_10 0x000002d0 /* 64-bit */
313: #define MAILBOX_RCVRET_CON_IDX_11 0x000002d8 /* 64-bit */
314: #define MAILBOX_RCVRET_CON_IDX_12 0x000002e0 /* 64-bit */
315: #define MAILBOX_RCVRET_CON_IDX_13 0x000002e8 /* 64-bit */
316: #define MAILBOX_RCVRET_CON_IDX_14 0x000002f0 /* 64-bit */
317: #define MAILBOX_RCVRET_CON_IDX_15 0x000002f8 /* 64-bit */
318: #define MAILBOX_SNDHOST_PROD_IDX_0 0x00000300 /* 64-bit */
319: #define MAILBOX_SNDHOST_PROD_IDX_1 0x00000308 /* 64-bit */
320: #define MAILBOX_SNDHOST_PROD_IDX_2 0x00000310 /* 64-bit */
321: #define MAILBOX_SNDHOST_PROD_IDX_3 0x00000318 /* 64-bit */
322: #define MAILBOX_SNDHOST_PROD_IDX_4 0x00000320 /* 64-bit */
323: #define MAILBOX_SNDHOST_PROD_IDX_5 0x00000328 /* 64-bit */
324: #define MAILBOX_SNDHOST_PROD_IDX_6 0x00000330 /* 64-bit */
325: #define MAILBOX_SNDHOST_PROD_IDX_7 0x00000338 /* 64-bit */
326: #define MAILBOX_SNDHOST_PROD_IDX_8 0x00000340 /* 64-bit */
327: #define MAILBOX_SNDHOST_PROD_IDX_9 0x00000348 /* 64-bit */
328: #define MAILBOX_SNDHOST_PROD_IDX_10 0x00000350 /* 64-bit */
329: #define MAILBOX_SNDHOST_PROD_IDX_11 0x00000358 /* 64-bit */
330: #define MAILBOX_SNDHOST_PROD_IDX_12 0x00000360 /* 64-bit */
331: #define MAILBOX_SNDHOST_PROD_IDX_13 0x00000368 /* 64-bit */
332: #define MAILBOX_SNDHOST_PROD_IDX_14 0x00000370 /* 64-bit */
333: #define MAILBOX_SNDHOST_PROD_IDX_15 0x00000378 /* 64-bit */
334: #define MAILBOX_SNDNIC_PROD_IDX_0 0x00000380 /* 64-bit */
335: #define MAILBOX_SNDNIC_PROD_IDX_1 0x00000388 /* 64-bit */
336: #define MAILBOX_SNDNIC_PROD_IDX_2 0x00000390 /* 64-bit */
337: #define MAILBOX_SNDNIC_PROD_IDX_3 0x00000398 /* 64-bit */
338: #define MAILBOX_SNDNIC_PROD_IDX_4 0x000003a0 /* 64-bit */
339: #define MAILBOX_SNDNIC_PROD_IDX_5 0x000003a8 /* 64-bit */
340: #define MAILBOX_SNDNIC_PROD_IDX_6 0x000003b0 /* 64-bit */
341: #define MAILBOX_SNDNIC_PROD_IDX_7 0x000003b8 /* 64-bit */
342: #define MAILBOX_SNDNIC_PROD_IDX_8 0x000003c0 /* 64-bit */
343: #define MAILBOX_SNDNIC_PROD_IDX_9 0x000003c8 /* 64-bit */
344: #define MAILBOX_SNDNIC_PROD_IDX_10 0x000003d0 /* 64-bit */
345: #define MAILBOX_SNDNIC_PROD_IDX_11 0x000003d8 /* 64-bit */
346: #define MAILBOX_SNDNIC_PROD_IDX_12 0x000003e0 /* 64-bit */
347: #define MAILBOX_SNDNIC_PROD_IDX_13 0x000003e8 /* 64-bit */
348: #define MAILBOX_SNDNIC_PROD_IDX_14 0x000003f0 /* 64-bit */
349: #define MAILBOX_SNDNIC_PROD_IDX_15 0x000003f8 /* 64-bit */
350:
351: /* MAC control registers */
352: #define MAC_MODE 0x00000400
353: #define MAC_MODE_RESET 0x00000001
354: #define MAC_MODE_HALF_DUPLEX 0x00000002
355: #define MAC_MODE_PORT_MODE_MASK 0x0000000c
356: #define MAC_MODE_PORT_MODE_TBI 0x0000000c
357: #define MAC_MODE_PORT_MODE_GMII 0x00000008
358: #define MAC_MODE_PORT_MODE_MII 0x00000004
359: #define MAC_MODE_PORT_MODE_NONE 0x00000000
360: #define MAC_MODE_PORT_INT_LPBACK 0x00000010
361: #define MAC_MODE_TAGGED_MAC_CTRL 0x00000080
362: #define MAC_MODE_TX_BURSTING 0x00000100
363: #define MAC_MODE_MAX_DEFER 0x00000200
364: #define MAC_MODE_LINK_POLARITY 0x00000400
365: #define MAC_MODE_RXSTAT_ENABLE 0x00000800
366: #define MAC_MODE_RXSTAT_CLEAR 0x00001000
367: #define MAC_MODE_RXSTAT_FLUSH 0x00002000
368: #define MAC_MODE_TXSTAT_ENABLE 0x00004000
369: #define MAC_MODE_TXSTAT_CLEAR 0x00008000
370: #define MAC_MODE_TXSTAT_FLUSH 0x00010000
371: #define MAC_MODE_SEND_CONFIGS 0x00020000
372: #define MAC_MODE_MAGIC_PKT_ENABLE 0x00040000
373: #define MAC_MODE_ACPI_ENABLE 0x00080000
374: #define MAC_MODE_MIP_ENABLE 0x00100000
375: #define MAC_MODE_TDE_ENABLE 0x00200000
376: #define MAC_MODE_RDE_ENABLE 0x00400000
377: #define MAC_MODE_FHDE_ENABLE 0x00800000
378: #define MAC_STATUS 0x00000404
379: #define MAC_STATUS_PCS_SYNCED 0x00000001
380: #define MAC_STATUS_SIGNAL_DET 0x00000002
381: #define MAC_STATUS_RCVD_CFG 0x00000004
382: #define MAC_STATUS_CFG_CHANGED 0x00000008
383: #define MAC_STATUS_SYNC_CHANGED 0x00000010
384: #define MAC_STATUS_PORT_DEC_ERR 0x00000400
385: #define MAC_STATUS_LNKSTATE_CHANGED 0x00001000
386: #define MAC_STATUS_MI_COMPLETION 0x00400000
387: #define MAC_STATUS_MI_INTERRUPT 0x00800000
388: #define MAC_STATUS_AP_ERROR 0x01000000
389: #define MAC_STATUS_ODI_ERROR 0x02000000
390: #define MAC_STATUS_RXSTAT_OVERRUN 0x04000000
391: #define MAC_STATUS_TXSTAT_OVERRUN 0x08000000
392: #define MAC_EVENT 0x00000408
393: #define MAC_EVENT_PORT_DECODE_ERR 0x00000400
394: #define MAC_EVENT_LNKSTATE_CHANGED 0x00001000
395: #define MAC_EVENT_MI_COMPLETION 0x00400000
396: #define MAC_EVENT_MI_INTERRUPT 0x00800000
397: #define MAC_EVENT_AP_ERROR 0x01000000
398: #define MAC_EVENT_ODI_ERROR 0x02000000
399: #define MAC_EVENT_RXSTAT_OVERRUN 0x04000000
400: #define MAC_EVENT_TXSTAT_OVERRUN 0x08000000
401: #define MAC_LED_CTRL 0x0000040c
402: #define LED_CTRL_LNKLED_OVERRIDE 0x00000001
403: #define LED_CTRL_1000MBPS_ON 0x00000002
404: #define LED_CTRL_100MBPS_ON 0x00000004
405: #define LED_CTRL_10MBPS_ON 0x00000008
406: #define LED_CTRL_TRAFFIC_OVERRIDE 0x00000010
407: #define LED_CTRL_TRAFFIC_BLINK 0x00000020
408: #define LED_CTRL_TRAFFIC_LED 0x00000040
409: #define LED_CTRL_1000MBPS_STATUS 0x00000080
410: #define LED_CTRL_100MBPS_STATUS 0x00000100
411: #define LED_CTRL_10MBPS_STATUS 0x00000200
412: #define LED_CTRL_TRAFFIC_STATUS 0x00000400
413: #define LED_CTRL_MAC_MODE 0x00000000
414: #define LED_CTRL_PHY_MODE_1 0x00000800
415: #define LED_CTRL_PHY_MODE_2 0x00001000
416: #define LED_CTRL_BLINK_RATE_MASK 0x7ff80000
417: #define LED_CTRL_BLINK_RATE_SHIFT 19
418: #define LED_CTRL_BLINK_PER_OVERRIDE 0x00080000
419: #define LED_CTRL_BLINK_RATE_OVERRIDE 0x80000000
420: #define MAC_ADDR_0_HIGH 0x00000410 /* upper 2 bytes */
421: #define MAC_ADDR_0_LOW 0x00000414 /* lower 4 bytes */
422: #define MAC_ADDR_1_HIGH 0x00000418 /* upper 2 bytes */
423: #define MAC_ADDR_1_LOW 0x0000041c /* lower 4 bytes */
424: #define MAC_ADDR_2_HIGH 0x00000420 /* upper 2 bytes */
425: #define MAC_ADDR_2_LOW 0x00000424 /* lower 4 bytes */
426: #define MAC_ADDR_3_HIGH 0x00000428 /* upper 2 bytes */
427: #define MAC_ADDR_3_LOW 0x0000042c /* lower 4 bytes */
428: #define MAC_ACPI_MBUF_PTR 0x00000430
429: #define MAC_ACPI_LEN_OFFSET 0x00000434
430: #define ACPI_LENOFF_LEN_MASK 0x0000ffff
431: #define ACPI_LENOFF_LEN_SHIFT 0
432: #define ACPI_LENOFF_OFF_MASK 0x0fff0000
433: #define ACPI_LENOFF_OFF_SHIFT 16
434: #define MAC_TX_BACKOFF_SEED 0x00000438
435: #define TX_BACKOFF_SEED_MASK 0x000003ff
436: #define MAC_RX_MTU_SIZE 0x0000043c
437: #define RX_MTU_SIZE_MASK 0x0000ffff
438: #define MAC_PCS_TEST 0x00000440
439: #define PCS_TEST_PATTERN_MASK 0x000fffff
440: #define PCS_TEST_PATTERN_SHIFT 0
441: #define PCS_TEST_ENABLE 0x00100000
442: #define MAC_TX_AUTO_NEG 0x00000444
443: #define TX_AUTO_NEG_MASK 0x0000ffff
444: #define TX_AUTO_NEG_SHIFT 0
445: #define MAC_RX_AUTO_NEG 0x00000448
446: #define RX_AUTO_NEG_MASK 0x0000ffff
447: #define RX_AUTO_NEG_SHIFT 0
448: #define MAC_MI_COM 0x0000044c
449: #define MI_COM_CMD_MASK 0x0c000000
450: #define MI_COM_CMD_WRITE 0x04000000
451: #define MI_COM_CMD_READ 0x08000000
452: #define MI_COM_READ_FAILED 0x10000000
453: #define MI_COM_START 0x20000000
454: #define MI_COM_BUSY 0x20000000
455: #define MI_COM_PHY_ADDR_MASK 0x03e00000
456: #define MI_COM_PHY_ADDR_SHIFT 21
457: #define MI_COM_REG_ADDR_MASK 0x001f0000
458: #define MI_COM_REG_ADDR_SHIFT 16
459: #define MI_COM_DATA_MASK 0x0000ffff
460: #define MAC_MI_STAT 0x00000450
461: #define MAC_MI_STAT_LNKSTAT_ATTN_ENAB 0x00000001
462: #define MAC_MI_MODE 0x00000454
463: #define MAC_MI_MODE_CLK_10MHZ 0x00000001
464: #define MAC_MI_MODE_SHORT_PREAMBLE 0x00000002
465: #define MAC_MI_MODE_AUTO_POLL 0x00000010
466: #define MAC_MI_MODE_CORE_CLK_62MHZ 0x00008000
467: #define MAC_MI_MODE_BASE 0x000c0000 /* XXX magic values XXX */
468: #define MAC_AUTO_POLL_STATUS 0x00000458
469: #define MAC_AUTO_POLL_ERROR 0x00000001
470: #define MAC_TX_MODE 0x0000045c
471: #define TX_MODE_RESET 0x00000001
472: #define TX_MODE_ENABLE 0x00000002
473: #define TX_MODE_FLOW_CTRL_ENABLE 0x00000010
474: #define TX_MODE_BIG_BCKOFF_ENABLE 0x00000020
475: #define TX_MODE_LONG_PAUSE_ENABLE 0x00000040
476: #define MAC_TX_STATUS 0x00000460
477: #define TX_STATUS_XOFFED 0x00000001
478: #define TX_STATUS_SENT_XOFF 0x00000002
479: #define TX_STATUS_SENT_XON 0x00000004
480: #define TX_STATUS_LINK_UP 0x00000008
481: #define TX_STATUS_ODI_UNDERRUN 0x00000010
482: #define TX_STATUS_ODI_OVERRUN 0x00000020
483: #define MAC_TX_LENGTHS 0x00000464
484: #define TX_LENGTHS_SLOT_TIME_MASK 0x000000ff
485: #define TX_LENGTHS_SLOT_TIME_SHIFT 0
486: #define TX_LENGTHS_IPG_MASK 0x00000f00
487: #define TX_LENGTHS_IPG_SHIFT 8
488: #define TX_LENGTHS_IPG_CRS_MASK 0x00003000
489: #define TX_LENGTHS_IPG_CRS_SHIFT 12
490: #define MAC_RX_MODE 0x00000468
491: #define RX_MODE_RESET 0x00000001
492: #define RX_MODE_ENABLE 0x00000002
493: #define RX_MODE_FLOW_CTRL_ENABLE 0x00000004
494: #define RX_MODE_KEEP_MAC_CTRL 0x00000008
495: #define RX_MODE_KEEP_PAUSE 0x00000010
496: #define RX_MODE_ACCEPT_OVERSIZED 0x00000020
497: #define RX_MODE_ACCEPT_RUNTS 0x00000040
498: #define RX_MODE_LEN_CHECK 0x00000080
499: #define RX_MODE_PROMISC 0x00000100
500: #define RX_MODE_NO_CRC_CHECK 0x00000200
501: #define RX_MODE_KEEP_VLAN_TAG 0x00000400
502: #define MAC_RX_STATUS 0x0000046c
503: #define RX_STATUS_REMOTE_TX_XOFFED 0x00000001
504: #define RX_STATUS_XOFF_RCVD 0x00000002
505: #define RX_STATUS_XON_RCVD 0x00000004
506: #define MAC_HASH_REG_0 0x00000470
507: #define MAC_HASH_REG_1 0x00000474
508: #define MAC_HASH_REG_2 0x00000478
509: #define MAC_HASH_REG_3 0x0000047c
510: #define MAC_RCV_RULE_0 0x00000480
511: #define MAC_RCV_VALUE_0 0x00000484
512: #define MAC_RCV_RULE_1 0x00000488
513: #define MAC_RCV_VALUE_1 0x0000048c
514: #define MAC_RCV_RULE_2 0x00000490
515: #define MAC_RCV_VALUE_2 0x00000494
516: #define MAC_RCV_RULE_3 0x00000498
517: #define MAC_RCV_VALUE_3 0x0000049c
518: #define MAC_RCV_RULE_4 0x000004a0
519: #define MAC_RCV_VALUE_4 0x000004a4
520: #define MAC_RCV_RULE_5 0x000004a8
521: #define MAC_RCV_VALUE_5 0x000004ac
522: #define MAC_RCV_RULE_6 0x000004b0
523: #define MAC_RCV_VALUE_6 0x000004b4
524: #define MAC_RCV_RULE_7 0x000004b8
525: #define MAC_RCV_VALUE_7 0x000004bc
526: #define MAC_RCV_RULE_8 0x000004c0
527: #define MAC_RCV_VALUE_8 0x000004c4
528: #define MAC_RCV_RULE_9 0x000004c8
529: #define MAC_RCV_VALUE_9 0x000004cc
530: #define MAC_RCV_RULE_10 0x000004d0
531: #define MAC_RCV_VALUE_10 0x000004d4
532: #define MAC_RCV_RULE_11 0x000004d8
533: #define MAC_RCV_VALUE_11 0x000004dc
534: #define MAC_RCV_RULE_12 0x000004e0
535: #define MAC_RCV_VALUE_12 0x000004e4
536: #define MAC_RCV_RULE_13 0x000004e8
537: #define MAC_RCV_VALUE_13 0x000004ec
538: #define MAC_RCV_RULE_14 0x000004f0
539: #define MAC_RCV_VALUE_14 0x000004f4
540: #define MAC_RCV_RULE_15 0x000004f8
541: #define MAC_RCV_VALUE_15 0x000004fc
542: #define RCV_RULE_DISABLE_MASK 0x7fffffff
543: #define MAC_RCV_RULE_CFG 0x00000500
544: #define RCV_RULE_CFG_DEFAULT_CLASS 0x00000008
545: #define MAC_LOW_WMARK_MAX_RX_FRAME 0x00000504
546: /* 0x508 --> 0x520 unused */
547: #define MAC_HASHREGU_0 0x00000520
548: #define MAC_HASHREGU_1 0x00000524
549: #define MAC_HASHREGU_2 0x00000528
550: #define MAC_HASHREGU_3 0x0000052c
551: #define MAC_EXTADDR_0_HIGH 0x00000530
552: #define MAC_EXTADDR_0_LOW 0x00000534
553: #define MAC_EXTADDR_1_HIGH 0x00000538
554: #define MAC_EXTADDR_1_LOW 0x0000053c
555: #define MAC_EXTADDR_2_HIGH 0x00000540
556: #define MAC_EXTADDR_2_LOW 0x00000544
557: #define MAC_EXTADDR_3_HIGH 0x00000548
558: #define MAC_EXTADDR_3_LOW 0x0000054c
559: #define MAC_EXTADDR_4_HIGH 0x00000550
560: #define MAC_EXTADDR_4_LOW 0x00000554
561: #define MAC_EXTADDR_5_HIGH 0x00000558
562: #define MAC_EXTADDR_5_LOW 0x0000055c
563: #define MAC_EXTADDR_6_HIGH 0x00000560
564: #define MAC_EXTADDR_6_LOW 0x00000564
565: #define MAC_EXTADDR_7_HIGH 0x00000568
566: #define MAC_EXTADDR_7_LOW 0x0000056c
567: #define MAC_EXTADDR_8_HIGH 0x00000570
568: #define MAC_EXTADDR_8_LOW 0x00000574
569: #define MAC_EXTADDR_9_HIGH 0x00000578
570: #define MAC_EXTADDR_9_LOW 0x0000057c
571: #define MAC_EXTADDR_10_HIGH 0x00000580
572: #define MAC_EXTADDR_10_LOW 0x00000584
573: #define MAC_EXTADDR_11_HIGH 0x00000588
574: #define MAC_EXTADDR_11_LOW 0x0000058c
575: #define MAC_SERDES_CFG 0x00000590
576: #define MAC_SERDES_STAT 0x00000594
577: /* 0x598 --> 0x600 unused */
578: #define MAC_TX_MAC_STATE_BASE 0x00000600 /* 16 bytes */
579: #define MAC_RX_MAC_STATE_BASE 0x00000610 /* 20 bytes */
580: /* 0x624 --> 0x800 unused */
581: #define MAC_TX_STATS_OCTETS 0x00000800
582: #define MAC_TX_STATS_RESV1 0x00000804
583: #define MAC_TX_STATS_COLLISIONS 0x00000808
584: #define MAC_TX_STATS_XON_SENT 0x0000080c
585: #define MAC_TX_STATS_XOFF_SENT 0x00000810
586: #define MAC_TX_STATS_RESV2 0x00000814
587: #define MAC_TX_STATS_MAC_ERRORS 0x00000818
588: #define MAC_TX_STATS_SINGLE_COLLISIONS 0x0000081c
589: #define MAC_TX_STATS_MULT_COLLISIONS 0x00000820
590: #define MAC_TX_STATS_DEFERRED 0x00000824
591: #define MAC_TX_STATS_RESV3 0x00000828
592: #define MAC_TX_STATS_EXCESSIVE_COL 0x0000082c
593: #define MAC_TX_STATS_LATE_COL 0x00000830
594: #define MAC_TX_STATS_RESV4_1 0x00000834
595: #define MAC_TX_STATS_RESV4_2 0x00000838
596: #define MAC_TX_STATS_RESV4_3 0x0000083c
597: #define MAC_TX_STATS_RESV4_4 0x00000840
598: #define MAC_TX_STATS_RESV4_5 0x00000844
599: #define MAC_TX_STATS_RESV4_6 0x00000848
600: #define MAC_TX_STATS_RESV4_7 0x0000084c
601: #define MAC_TX_STATS_RESV4_8 0x00000850
602: #define MAC_TX_STATS_RESV4_9 0x00000854
603: #define MAC_TX_STATS_RESV4_10 0x00000858
604: #define MAC_TX_STATS_RESV4_11 0x0000085c
605: #define MAC_TX_STATS_RESV4_12 0x00000860
606: #define MAC_TX_STATS_RESV4_13 0x00000864
607: #define MAC_TX_STATS_RESV4_14 0x00000868
608: #define MAC_TX_STATS_UCAST 0x0000086c
609: #define MAC_TX_STATS_MCAST 0x00000870
610: #define MAC_TX_STATS_BCAST 0x00000874
611: #define MAC_TX_STATS_RESV5_1 0x00000878
612: #define MAC_TX_STATS_RESV5_2 0x0000087c
613: #define MAC_RX_STATS_OCTETS 0x00000880
614: #define MAC_RX_STATS_RESV1 0x00000884
615: #define MAC_RX_STATS_FRAGMENTS 0x00000888
616: #define MAC_RX_STATS_UCAST 0x0000088c
617: #define MAC_RX_STATS_MCAST 0x00000890
618: #define MAC_RX_STATS_BCAST 0x00000894
619: #define MAC_RX_STATS_FCS_ERRORS 0x00000898
620: #define MAC_RX_STATS_ALIGN_ERRORS 0x0000089c
621: #define MAC_RX_STATS_XON_PAUSE_RECVD 0x000008a0
622: #define MAC_RX_STATS_XOFF_PAUSE_RECVD 0x000008a4
623: #define MAC_RX_STATS_MAC_CTRL_RECVD 0x000008a8
624: #define MAC_RX_STATS_XOFF_ENTERED 0x000008ac
625: #define MAC_RX_STATS_FRAME_TOO_LONG 0x000008b0
626: #define MAC_RX_STATS_JABBERS 0x000008b4
627: #define MAC_RX_STATS_UNDERSIZE 0x000008b8
628: /* 0x8bc --> 0xc00 unused */
629:
630: /* Send data initiator control registers */
631: #define SNDDATAI_MODE 0x00000c00
632: #define SNDDATAI_MODE_RESET 0x00000001
633: #define SNDDATAI_MODE_ENABLE 0x00000002
634: #define SNDDATAI_MODE_STAT_OFLOW_ENAB 0x00000004
635: #define SNDDATAI_STATUS 0x00000c04
636: #define SNDDATAI_STATUS_STAT_OFLOW 0x00000004
637: #define SNDDATAI_STATSCTRL 0x00000c08
638: #define SNDDATAI_SCTRL_ENABLE 0x00000001
639: #define SNDDATAI_SCTRL_FASTUPD 0x00000002
640: #define SNDDATAI_SCTRL_CLEAR 0x00000004
641: #define SNDDATAI_SCTRL_FLUSH 0x00000008
642: #define SNDDATAI_SCTRL_FORCE_ZERO 0x00000010
643: #define SNDDATAI_STATSENAB 0x00000c0c
644: #define SNDDATAI_STATSINCMASK 0x00000c10
645: /* 0xc14 --> 0xc80 unused */
646: #define SNDDATAI_COS_CNT_0 0x00000c80
647: #define SNDDATAI_COS_CNT_1 0x00000c84
648: #define SNDDATAI_COS_CNT_2 0x00000c88
649: #define SNDDATAI_COS_CNT_3 0x00000c8c
650: #define SNDDATAI_COS_CNT_4 0x00000c90
651: #define SNDDATAI_COS_CNT_5 0x00000c94
652: #define SNDDATAI_COS_CNT_6 0x00000c98
653: #define SNDDATAI_COS_CNT_7 0x00000c9c
654: #define SNDDATAI_COS_CNT_8 0x00000ca0
655: #define SNDDATAI_COS_CNT_9 0x00000ca4
656: #define SNDDATAI_COS_CNT_10 0x00000ca8
657: #define SNDDATAI_COS_CNT_11 0x00000cac
658: #define SNDDATAI_COS_CNT_12 0x00000cb0
659: #define SNDDATAI_COS_CNT_13 0x00000cb4
660: #define SNDDATAI_COS_CNT_14 0x00000cb8
661: #define SNDDATAI_COS_CNT_15 0x00000cbc
662: #define SNDDATAI_DMA_RDQ_FULL_CNT 0x00000cc0
663: #define SNDDATAI_DMA_PRIO_RDQ_FULL_CNT 0x00000cc4
664: #define SNDDATAI_SDCQ_FULL_CNT 0x00000cc8
665: #define SNDDATAI_NICRNG_SSND_PIDX_CNT 0x00000ccc
666: #define SNDDATAI_STATS_UPDATED_CNT 0x00000cd0
667: #define SNDDATAI_INTERRUPTS_CNT 0x00000cd4
668: #define SNDDATAI_AVOID_INTERRUPTS_CNT 0x00000cd8
669: #define SNDDATAI_SND_THRESH_HIT_CNT 0x00000cdc
670: /* 0xce0 --> 0x1000 unused */
671:
672: /* Send data completion control registers */
673: #define SNDDATAC_MODE 0x00001000
674: #define SNDDATAC_MODE_RESET 0x00000001
675: #define SNDDATAC_MODE_ENABLE 0x00000002
676: /* 0x1004 --> 0x1400 unused */
677:
678: /* Send BD ring selector */
679: #define SNDBDS_MODE 0x00001400
680: #define SNDBDS_MODE_RESET 0x00000001
681: #define SNDBDS_MODE_ENABLE 0x00000002
682: #define SNDBDS_MODE_ATTN_ENABLE 0x00000004
683: #define SNDBDS_STATUS 0x00001404
684: #define SNDBDS_STATUS_ERROR_ATTN 0x00000004
685: #define SNDBDS_HWDIAG 0x00001408
686: /* 0x140c --> 0x1440 */
687: #define SNDBDS_SEL_CON_IDX_0 0x00001440
688: #define SNDBDS_SEL_CON_IDX_1 0x00001444
689: #define SNDBDS_SEL_CON_IDX_2 0x00001448
690: #define SNDBDS_SEL_CON_IDX_3 0x0000144c
691: #define SNDBDS_SEL_CON_IDX_4 0x00001450
692: #define SNDBDS_SEL_CON_IDX_5 0x00001454
693: #define SNDBDS_SEL_CON_IDX_6 0x00001458
694: #define SNDBDS_SEL_CON_IDX_7 0x0000145c
695: #define SNDBDS_SEL_CON_IDX_8 0x00001460
696: #define SNDBDS_SEL_CON_IDX_9 0x00001464
697: #define SNDBDS_SEL_CON_IDX_10 0x00001468
698: #define SNDBDS_SEL_CON_IDX_11 0x0000146c
699: #define SNDBDS_SEL_CON_IDX_12 0x00001470
700: #define SNDBDS_SEL_CON_IDX_13 0x00001474
701: #define SNDBDS_SEL_CON_IDX_14 0x00001478
702: #define SNDBDS_SEL_CON_IDX_15 0x0000147c
703: /* 0x1480 --> 0x1800 unused */
704:
705: /* Send BD initiator control registers */
706: #define SNDBDI_MODE 0x00001800
707: #define SNDBDI_MODE_RESET 0x00000001
708: #define SNDBDI_MODE_ENABLE 0x00000002
709: #define SNDBDI_MODE_ATTN_ENABLE 0x00000004
710: #define SNDBDI_STATUS 0x00001804
711: #define SNDBDI_STATUS_ERROR_ATTN 0x00000004
712: #define SNDBDI_IN_PROD_IDX_0 0x00001808
713: #define SNDBDI_IN_PROD_IDX_1 0x0000180c
714: #define SNDBDI_IN_PROD_IDX_2 0x00001810
715: #define SNDBDI_IN_PROD_IDX_3 0x00001814
716: #define SNDBDI_IN_PROD_IDX_4 0x00001818
717: #define SNDBDI_IN_PROD_IDX_5 0x0000181c
718: #define SNDBDI_IN_PROD_IDX_6 0x00001820
719: #define SNDBDI_IN_PROD_IDX_7 0x00001824
720: #define SNDBDI_IN_PROD_IDX_8 0x00001828
721: #define SNDBDI_IN_PROD_IDX_9 0x0000182c
722: #define SNDBDI_IN_PROD_IDX_10 0x00001830
723: #define SNDBDI_IN_PROD_IDX_11 0x00001834
724: #define SNDBDI_IN_PROD_IDX_12 0x00001838
725: #define SNDBDI_IN_PROD_IDX_13 0x0000183c
726: #define SNDBDI_IN_PROD_IDX_14 0x00001840
727: #define SNDBDI_IN_PROD_IDX_15 0x00001844
728: /* 0x1848 --> 0x1c00 unused */
729:
730: /* Send BD completion control registers */
731: #define SNDBDC_MODE 0x00001c00
732: #define SNDBDC_MODE_RESET 0x00000001
733: #define SNDBDC_MODE_ENABLE 0x00000002
734: #define SNDBDC_MODE_ATTN_ENABLE 0x00000004
735: /* 0x1c04 --> 0x2000 unused */
736:
737: /* Receive list placement control registers */
738: #define RCVLPC_MODE 0x00002000
739: #define RCVLPC_MODE_RESET 0x00000001
740: #define RCVLPC_MODE_ENABLE 0x00000002
741: #define RCVLPC_MODE_CLASS0_ATTN_ENAB 0x00000004
742: #define RCVLPC_MODE_MAPOOR_AATTN_ENAB 0x00000008
743: #define RCVLPC_MODE_STAT_OFLOW_ENAB 0x00000010
744: #define RCVLPC_STATUS 0x00002004
745: #define RCVLPC_STATUS_CLASS0 0x00000004
746: #define RCVLPC_STATUS_MAPOOR 0x00000008
747: #define RCVLPC_STATUS_STAT_OFLOW 0x00000010
748: #define RCVLPC_LOCK 0x00002008
749: #define RCVLPC_LOCK_REQ_MASK 0x0000ffff
750: #define RCVLPC_LOCK_REQ_SHIFT 0
751: #define RCVLPC_LOCK_GRANT_MASK 0xffff0000
752: #define RCVLPC_LOCK_GRANT_SHIFT 16
753: #define RCVLPC_NON_EMPTY_BITS 0x0000200c
754: #define RCVLPC_NON_EMPTY_BITS_MASK 0x0000ffff
755: #define RCVLPC_CONFIG 0x00002010
756: #define RCVLPC_STATSCTRL 0x00002014
757: #define RCVLPC_STATSCTRL_ENABLE 0x00000001
758: #define RCVLPC_STATSCTRL_FASTUPD 0x00000002
759: #define RCVLPC_STATS_ENABLE 0x00002018
760: #define RCVLPC_STATSENAB_LNGBRST_RFIX 0x00400000
761: #define RCVLPC_STATS_INCMASK 0x0000201c
762: /* 0x2020 --> 0x2100 unused */
763: #define RCVLPC_SELLST_BASE 0x00002100 /* 16 16-byte entries */
764: #define SELLST_TAIL 0x00000004
765: #define SELLST_CONT 0x00000008
766: #define SELLST_UNUSED 0x0000000c
767: #define RCVLPC_COS_CNTL_BASE 0x00002200 /* 16 4-byte entries */
768: #define RCVLPC_DROP_FILTER_CNT 0x00002240
769: #define RCVLPC_DMA_WQ_FULL_CNT 0x00002244
770: #define RCVLPC_DMA_HIPRIO_WQ_FULL_CNT 0x00002248
771: #define RCVLPC_NO_RCV_BD_CNT 0x0000224c
772: #define RCVLPC_IN_DISCARDS_CNT 0x00002250
773: #define RCVLPC_IN_ERRORS_CNT 0x00002254
774: #define RCVLPC_RCV_THRESH_HIT_CNT 0x00002258
775: /* 0x225c --> 0x2400 unused */
776:
777: /* Receive Data and Receive BD Initiator Control */
778: #define RCVDBDI_MODE 0x00002400
779: #define RCVDBDI_MODE_RESET 0x00000001
780: #define RCVDBDI_MODE_ENABLE 0x00000002
781: #define RCVDBDI_MODE_JUMBOBD_NEEDED 0x00000004
782: #define RCVDBDI_MODE_FRM_TOO_BIG 0x00000008
783: #define RCVDBDI_MODE_INV_RING_SZ 0x00000010
784: #define RCVDBDI_STATUS 0x00002404
785: #define RCVDBDI_STATUS_JUMBOBD_NEEDED 0x00000004
786: #define RCVDBDI_STATUS_FRM_TOO_BIG 0x00000008
787: #define RCVDBDI_STATUS_INV_RING_SZ 0x00000010
788: #define RCVDBDI_SPLIT_FRAME_MINSZ 0x00002408
789: /* 0x240c --> 0x2440 unused */
790: #define RCVDBDI_JUMBO_BD 0x00002440 /* TG3_BDINFO_... */
791: #define RCVDBDI_STD_BD 0x00002450 /* TG3_BDINFO_... */
792: #define RCVDBDI_MINI_BD 0x00002460 /* TG3_BDINFO_... */
793: #define RCVDBDI_JUMBO_CON_IDX 0x00002470
794: #define RCVDBDI_STD_CON_IDX 0x00002474
795: #define RCVDBDI_MINI_CON_IDX 0x00002478
796: /* 0x247c --> 0x2480 unused */
797: #define RCVDBDI_BD_PROD_IDX_0 0x00002480
798: #define RCVDBDI_BD_PROD_IDX_1 0x00002484
799: #define RCVDBDI_BD_PROD_IDX_2 0x00002488
800: #define RCVDBDI_BD_PROD_IDX_3 0x0000248c
801: #define RCVDBDI_BD_PROD_IDX_4 0x00002490
802: #define RCVDBDI_BD_PROD_IDX_5 0x00002494
803: #define RCVDBDI_BD_PROD_IDX_6 0x00002498
804: #define RCVDBDI_BD_PROD_IDX_7 0x0000249c
805: #define RCVDBDI_BD_PROD_IDX_8 0x000024a0
806: #define RCVDBDI_BD_PROD_IDX_9 0x000024a4
807: #define RCVDBDI_BD_PROD_IDX_10 0x000024a8
808: #define RCVDBDI_BD_PROD_IDX_11 0x000024ac
809: #define RCVDBDI_BD_PROD_IDX_12 0x000024b0
810: #define RCVDBDI_BD_PROD_IDX_13 0x000024b4
811: #define RCVDBDI_BD_PROD_IDX_14 0x000024b8
812: #define RCVDBDI_BD_PROD_IDX_15 0x000024bc
813: #define RCVDBDI_HWDIAG 0x000024c0
814: /* 0x24c4 --> 0x2800 unused */
815:
816: /* Receive Data Completion Control */
817: #define RCVDCC_MODE 0x00002800
818: #define RCVDCC_MODE_RESET 0x00000001
819: #define RCVDCC_MODE_ENABLE 0x00000002
820: #define RCVDCC_MODE_ATTN_ENABLE 0x00000004
821: /* 0x2804 --> 0x2c00 unused */
822:
823: /* Receive BD Initiator Control Registers */
824: #define RCVBDI_MODE 0x00002c00
825: #define RCVBDI_MODE_RESET 0x00000001
826: #define RCVBDI_MODE_ENABLE 0x00000002
827: #define RCVBDI_MODE_RCB_ATTN_ENAB 0x00000004
828: #define RCVBDI_STATUS 0x00002c04
829: #define RCVBDI_STATUS_RCB_ATTN 0x00000004
830: #define RCVBDI_JUMBO_PROD_IDX 0x00002c08
831: #define RCVBDI_STD_PROD_IDX 0x00002c0c
832: #define RCVBDI_MINI_PROD_IDX 0x00002c10
833: #define RCVBDI_MINI_THRESH 0x00002c14
834: #define RCVBDI_STD_THRESH 0x00002c18
835: #define RCVBDI_JUMBO_THRESH 0x00002c1c
836: /* 0x2c20 --> 0x3000 unused */
837:
838: /* Receive BD Completion Control Registers */
839: #define RCVCC_MODE 0x00003000
840: #define RCVCC_MODE_RESET 0x00000001
841: #define RCVCC_MODE_ENABLE 0x00000002
842: #define RCVCC_MODE_ATTN_ENABLE 0x00000004
843: #define RCVCC_STATUS 0x00003004
844: #define RCVCC_STATUS_ERROR_ATTN 0x00000004
845: #define RCVCC_JUMP_PROD_IDX 0x00003008
846: #define RCVCC_STD_PROD_IDX 0x0000300c
847: #define RCVCC_MINI_PROD_IDX 0x00003010
848: /* 0x3014 --> 0x3400 unused */
849:
850: /* Receive list selector control registers */
851: #define RCVLSC_MODE 0x00003400
852: #define RCVLSC_MODE_RESET 0x00000001
853: #define RCVLSC_MODE_ENABLE 0x00000002
854: #define RCVLSC_MODE_ATTN_ENABLE 0x00000004
855: #define RCVLSC_STATUS 0x00003404
856: #define RCVLSC_STATUS_ERROR_ATTN 0x00000004
857: /* 0x3408 --> 0x3800 unused */
858:
859: /* Mbuf cluster free registers */
860: #define MBFREE_MODE 0x00003800
861: #define MBFREE_MODE_RESET 0x00000001
862: #define MBFREE_MODE_ENABLE 0x00000002
863: #define MBFREE_STATUS 0x00003804
864: /* 0x3808 --> 0x3c00 unused */
865:
866: /* Host coalescing control registers */
867: #define HOSTCC_MODE 0x00003c00
868: #define HOSTCC_MODE_RESET 0x00000001
869: #define HOSTCC_MODE_ENABLE 0x00000002
870: #define HOSTCC_MODE_ATTN 0x00000004
871: #define HOSTCC_MODE_NOW 0x00000008
872: #define HOSTCC_MODE_FULL_STATUS 0x00000000
873: #define HOSTCC_MODE_64BYTE 0x00000080
874: #define HOSTCC_MODE_32BYTE 0x00000100
875: #define HOSTCC_MODE_CLRTICK_RXBD 0x00000200
876: #define HOSTCC_MODE_CLRTICK_TXBD 0x00000400
877: #define HOSTCC_MODE_NOINT_ON_NOW 0x00000800
878: #define HOSTCC_MODE_NOINT_ON_FORCE 0x00001000
879: #define HOSTCC_STATUS 0x00003c04
880: #define HOSTCC_STATUS_ERROR_ATTN 0x00000004
881: #define HOSTCC_RXCOL_TICKS 0x00003c08
882: #define LOW_RXCOL_TICKS 0x00000032
883: #define DEFAULT_RXCOL_TICKS 0x00000048
884: #define HIGH_RXCOL_TICKS 0x00000096
885: #define HOSTCC_TXCOL_TICKS 0x00003c0c
886: #define LOW_TXCOL_TICKS 0x00000096
887: #define DEFAULT_TXCOL_TICKS 0x0000012c
888: #define HIGH_TXCOL_TICKS 0x00000145
889: #define HOSTCC_RXMAX_FRAMES 0x00003c10
890: #define LOW_RXMAX_FRAMES 0x00000005
891: #define DEFAULT_RXMAX_FRAMES 0x00000008
892: #define HIGH_RXMAX_FRAMES 0x00000012
893: #define HOSTCC_TXMAX_FRAMES 0x00003c14
894: #define LOW_TXMAX_FRAMES 0x00000035
895: #define DEFAULT_TXMAX_FRAMES 0x0000004b
896: #define HIGH_TXMAX_FRAMES 0x00000052
897: #define HOSTCC_RXCOAL_TICK_INT 0x00003c18
898: #define DEFAULT_RXCOAL_TICK_INT 0x00000019
899: #define HOSTCC_TXCOAL_TICK_INT 0x00003c1c
900: #define DEFAULT_TXCOAL_TICK_INT 0x00000019
901: #define HOSTCC_RXCOAL_MAXF_INT 0x00003c20
902: #define DEFAULT_RXCOAL_MAXF_INT 0x00000005
903: #define HOSTCC_TXCOAL_MAXF_INT 0x00003c24
904: #define DEFAULT_TXCOAL_MAXF_INT 0x00000005
905: #define HOSTCC_STAT_COAL_TICKS 0x00003c28
906: #define DEFAULT_STAT_COAL_TICKS 0x000f4240
907: /* 0x3c2c --> 0x3c30 unused */
908: #define HOSTCC_STATS_BLK_HOST_ADDR 0x00003c30 /* 64-bit */
909: #define HOSTCC_STATUS_BLK_HOST_ADDR 0x00003c38 /* 64-bit */
910: #define HOSTCC_STATS_BLK_NIC_ADDR 0x00003c40
911: #define HOSTCC_STATUS_BLK_NIC_ADDR 0x00003c44
912: #define HOSTCC_FLOW_ATTN 0x00003c48
913: /* 0x3c4c --> 0x3c50 unused */
914: #define HOSTCC_JUMBO_CON_IDX 0x00003c50
915: #define HOSTCC_STD_CON_IDX 0x00003c54
916: #define HOSTCC_MINI_CON_IDX 0x00003c58
917: /* 0x3c5c --> 0x3c80 unused */
918: #define HOSTCC_RET_PROD_IDX_0 0x00003c80
919: #define HOSTCC_RET_PROD_IDX_1 0x00003c84
920: #define HOSTCC_RET_PROD_IDX_2 0x00003c88
921: #define HOSTCC_RET_PROD_IDX_3 0x00003c8c
922: #define HOSTCC_RET_PROD_IDX_4 0x00003c90
923: #define HOSTCC_RET_PROD_IDX_5 0x00003c94
924: #define HOSTCC_RET_PROD_IDX_6 0x00003c98
925: #define HOSTCC_RET_PROD_IDX_7 0x00003c9c
926: #define HOSTCC_RET_PROD_IDX_8 0x00003ca0
927: #define HOSTCC_RET_PROD_IDX_9 0x00003ca4
928: #define HOSTCC_RET_PROD_IDX_10 0x00003ca8
929: #define HOSTCC_RET_PROD_IDX_11 0x00003cac
930: #define HOSTCC_RET_PROD_IDX_12 0x00003cb0
931: #define HOSTCC_RET_PROD_IDX_13 0x00003cb4
932: #define HOSTCC_RET_PROD_IDX_14 0x00003cb8
933: #define HOSTCC_RET_PROD_IDX_15 0x00003cbc
934: #define HOSTCC_SND_CON_IDX_0 0x00003cc0
935: #define HOSTCC_SND_CON_IDX_1 0x00003cc4
936: #define HOSTCC_SND_CON_IDX_2 0x00003cc8
937: #define HOSTCC_SND_CON_IDX_3 0x00003ccc
938: #define HOSTCC_SND_CON_IDX_4 0x00003cd0
939: #define HOSTCC_SND_CON_IDX_5 0x00003cd4
940: #define HOSTCC_SND_CON_IDX_6 0x00003cd8
941: #define HOSTCC_SND_CON_IDX_7 0x00003cdc
942: #define HOSTCC_SND_CON_IDX_8 0x00003ce0
943: #define HOSTCC_SND_CON_IDX_9 0x00003ce4
944: #define HOSTCC_SND_CON_IDX_10 0x00003ce8
945: #define HOSTCC_SND_CON_IDX_11 0x00003cec
946: #define HOSTCC_SND_CON_IDX_12 0x00003cf0
947: #define HOSTCC_SND_CON_IDX_13 0x00003cf4
948: #define HOSTCC_SND_CON_IDX_14 0x00003cf8
949: #define HOSTCC_SND_CON_IDX_15 0x00003cfc
950: /* 0x3d00 --> 0x4000 unused */
951:
952: /* Memory arbiter control registers */
953: #define MEMARB_MODE 0x00004000
954: #define MEMARB_MODE_RESET 0x00000001
955: #define MEMARB_MODE_ENABLE 0x00000002
956: #define MEMARB_STATUS 0x00004004
957: #define MEMARB_TRAP_ADDR_LOW 0x00004008
958: #define MEMARB_TRAP_ADDR_HIGH 0x0000400c
959: /* 0x4010 --> 0x4400 unused */
960:
961: /* Buffer manager control registers */
962: #define BUFMGR_MODE 0x00004400
963: #define BUFMGR_MODE_RESET 0x00000001
964: #define BUFMGR_MODE_ENABLE 0x00000002
965: #define BUFMGR_MODE_ATTN_ENABLE 0x00000004
966: #define BUFMGR_MODE_BM_TEST 0x00000008
967: #define BUFMGR_MODE_MBLOW_ATTN_ENAB 0x00000010
968: #define BUFMGR_STATUS 0x00004404
969: #define BUFMGR_STATUS_ERROR 0x00000004
970: #define BUFMGR_STATUS_MBLOW 0x00000010
971: #define BUFMGR_MB_POOL_ADDR 0x00004408
972: #define BUFMGR_MB_POOL_SIZE 0x0000440c
973: #define BUFMGR_MB_RDMA_LOW_WATER 0x00004410
974: #define DEFAULT_MB_RDMA_LOW_WATER 0x00000050
975: #define DEFAULT_MB_RDMA_LOW_WATER_5705 0x00000000
976: #define DEFAULT_MB_RDMA_LOW_WATER_JUMBO 0x00000130
977: #define BUFMGR_MB_MACRX_LOW_WATER 0x00004414
978: #define DEFAULT_MB_MACRX_LOW_WATER 0x00000020
979: #define DEFAULT_MB_MACRX_LOW_WATER_5705 0x00000010
980: #define DEFAULT_MB_MACRX_LOW_WATER_JUMBO 0x00000098
981: #define BUFMGR_MB_HIGH_WATER 0x00004418
982: #define DEFAULT_MB_HIGH_WATER 0x00000060
983: #define DEFAULT_MB_HIGH_WATER_5705 0x00000060
984: #define DEFAULT_MB_HIGH_WATER_JUMBO 0x0000017c
985: #define BUFMGR_RX_MB_ALLOC_REQ 0x0000441c
986: #define BUFMGR_MB_ALLOC_BIT 0x10000000
987: #define BUFMGR_RX_MB_ALLOC_RESP 0x00004420
988: #define BUFMGR_TX_MB_ALLOC_REQ 0x00004424
989: #define BUFMGR_TX_MB_ALLOC_RESP 0x00004428
990: #define BUFMGR_DMA_DESC_POOL_ADDR 0x0000442c
991: #define BUFMGR_DMA_DESC_POOL_SIZE 0x00004430
992: #define BUFMGR_DMA_LOW_WATER 0x00004434
993: #define DEFAULT_DMA_LOW_WATER 0x00000005
994: #define BUFMGR_DMA_HIGH_WATER 0x00004438
995: #define DEFAULT_DMA_HIGH_WATER 0x0000000a
996: #define BUFMGR_RX_DMA_ALLOC_REQ 0x0000443c
997: #define BUFMGR_RX_DMA_ALLOC_RESP 0x00004440
998: #define BUFMGR_TX_DMA_ALLOC_REQ 0x00004444
999: #define BUFMGR_TX_DMA_ALLOC_RESP 0x00004448
1000: #define BUFMGR_HWDIAG_0 0x0000444c
1001: #define BUFMGR_HWDIAG_1 0x00004450
1002: #define BUFMGR_HWDIAG_2 0x00004454
1003: /* 0x4458 --> 0x4800 unused */
1004:
1005: /* Read DMA control registers */
1006: #define RDMAC_MODE 0x00004800
1007: #define RDMAC_MODE_RESET 0x00000001
1008: #define RDMAC_MODE_ENABLE 0x00000002
1009: #define RDMAC_MODE_TGTABORT_ENAB 0x00000004
1010: #define RDMAC_MODE_MSTABORT_ENAB 0x00000008
1011: #define RDMAC_MODE_PARITYERR_ENAB 0x00000010
1012: #define RDMAC_MODE_ADDROFLOW_ENAB 0x00000020
1013: #define RDMAC_MODE_FIFOOFLOW_ENAB 0x00000040
1014: #define RDMAC_MODE_FIFOURUN_ENAB 0x00000080
1015: #define RDMAC_MODE_FIFOOREAD_ENAB 0x00000100
1016: #define RDMAC_MODE_LNGREAD_ENAB 0x00000200
1017: #define RDMAC_MODE_SPLIT_ENABLE 0x00000800
1018: #define RDMAC_MODE_SPLIT_RESET 0x00001000
1019: #define RDMAC_MODE_FIFO_SIZE_128 0x00020000
1020: #define RDMAC_MODE_FIFO_LONG_BURST 0x00030000
1021: #define RDMAC_STATUS 0x00004804
1022: #define RDMAC_STATUS_TGTABORT 0x00000004
1023: #define RDMAC_STATUS_MSTABORT 0x00000008
1024: #define RDMAC_STATUS_PARITYERR 0x00000010
1025: #define RDMAC_STATUS_ADDROFLOW 0x00000020
1026: #define RDMAC_STATUS_FIFOOFLOW 0x00000040
1027: #define RDMAC_STATUS_FIFOURUN 0x00000080
1028: #define RDMAC_STATUS_FIFOOREAD 0x00000100
1029: #define RDMAC_STATUS_LNGREAD 0x00000200
1030: /* 0x4808 --> 0x4c00 unused */
1031:
1032: /* Write DMA control registers */
1033: #define WDMAC_MODE 0x00004c00
1034: #define WDMAC_MODE_RESET 0x00000001
1035: #define WDMAC_MODE_ENABLE 0x00000002
1036: #define WDMAC_MODE_TGTABORT_ENAB 0x00000004
1037: #define WDMAC_MODE_MSTABORT_ENAB 0x00000008
1038: #define WDMAC_MODE_PARITYERR_ENAB 0x00000010
1039: #define WDMAC_MODE_ADDROFLOW_ENAB 0x00000020
1040: #define WDMAC_MODE_FIFOOFLOW_ENAB 0x00000040
1041: #define WDMAC_MODE_FIFOURUN_ENAB 0x00000080
1042: #define WDMAC_MODE_FIFOOREAD_ENAB 0x00000100
1043: #define WDMAC_MODE_LNGREAD_ENAB 0x00000200
1044: #define WDMAC_MODE_RX_ACCEL 0x00000400
1045: #define WDMAC_STATUS 0x00004c04
1046: #define WDMAC_STATUS_TGTABORT 0x00000004
1047: #define WDMAC_STATUS_MSTABORT 0x00000008
1048: #define WDMAC_STATUS_PARITYERR 0x00000010
1049: #define WDMAC_STATUS_ADDROFLOW 0x00000020
1050: #define WDMAC_STATUS_FIFOOFLOW 0x00000040
1051: #define WDMAC_STATUS_FIFOURUN 0x00000080
1052: #define WDMAC_STATUS_FIFOOREAD 0x00000100
1053: #define WDMAC_STATUS_LNGREAD 0x00000200
1054: /* 0x4c08 --> 0x5000 unused */
1055:
1056: /* Per-cpu register offsets (arm9) */
1057: #define CPU_MODE 0x00000000
1058: #define CPU_MODE_RESET 0x00000001
1059: #define CPU_MODE_HALT 0x00000400
1060: #define CPU_STATE 0x00000004
1061: #define CPU_EVTMASK 0x00000008
1062: /* 0xc --> 0x1c reserved */
1063: #define CPU_PC 0x0000001c
1064: #define CPU_INSN 0x00000020
1065: #define CPU_SPAD_UFLOW 0x00000024
1066: #define CPU_WDOG_CLEAR 0x00000028
1067: #define CPU_WDOG_VECTOR 0x0000002c
1068: #define CPU_WDOG_PC 0x00000030
1069: #define CPU_HW_BP 0x00000034
1070: /* 0x38 --> 0x44 unused */
1071: #define CPU_WDOG_SAVED_STATE 0x00000044
1072: #define CPU_LAST_BRANCH_ADDR 0x00000048
1073: #define CPU_SPAD_UFLOW_SET 0x0000004c
1074: /* 0x50 --> 0x200 unused */
1075: #define CPU_R0 0x00000200
1076: #define CPU_R1 0x00000204
1077: #define CPU_R2 0x00000208
1078: #define CPU_R3 0x0000020c
1079: #define CPU_R4 0x00000210
1080: #define CPU_R5 0x00000214
1081: #define CPU_R6 0x00000218
1082: #define CPU_R7 0x0000021c
1083: #define CPU_R8 0x00000220
1084: #define CPU_R9 0x00000224
1085: #define CPU_R10 0x00000228
1086: #define CPU_R11 0x0000022c
1087: #define CPU_R12 0x00000230
1088: #define CPU_R13 0x00000234
1089: #define CPU_R14 0x00000238
1090: #define CPU_R15 0x0000023c
1091: #define CPU_R16 0x00000240
1092: #define CPU_R17 0x00000244
1093: #define CPU_R18 0x00000248
1094: #define CPU_R19 0x0000024c
1095: #define CPU_R20 0x00000250
1096: #define CPU_R21 0x00000254
1097: #define CPU_R22 0x00000258
1098: #define CPU_R23 0x0000025c
1099: #define CPU_R24 0x00000260
1100: #define CPU_R25 0x00000264
1101: #define CPU_R26 0x00000268
1102: #define CPU_R27 0x0000026c
1103: #define CPU_R28 0x00000270
1104: #define CPU_R29 0x00000274
1105: #define CPU_R30 0x00000278
1106: #define CPU_R31 0x0000027c
1107: /* 0x280 --> 0x400 unused */
1108:
1109: #define RX_CPU_BASE 0x00005000
1110: #define TX_CPU_BASE 0x00005400
1111:
1112: /* Mailboxes */
1113: #define GRCMBOX_INTERRUPT_0 0x00005800 /* 64-bit */
1114: #define GRCMBOX_INTERRUPT_1 0x00005808 /* 64-bit */
1115: #define GRCMBOX_INTERRUPT_2 0x00005810 /* 64-bit */
1116: #define GRCMBOX_INTERRUPT_3 0x00005818 /* 64-bit */
1117: #define GRCMBOX_GENERAL_0 0x00005820 /* 64-bit */
1118: #define GRCMBOX_GENERAL_1 0x00005828 /* 64-bit */
1119: #define GRCMBOX_GENERAL_2 0x00005830 /* 64-bit */
1120: #define GRCMBOX_GENERAL_3 0x00005838 /* 64-bit */
1121: #define GRCMBOX_GENERAL_4 0x00005840 /* 64-bit */
1122: #define GRCMBOX_GENERAL_5 0x00005848 /* 64-bit */
1123: #define GRCMBOX_GENERAL_6 0x00005850 /* 64-bit */
1124: #define GRCMBOX_GENERAL_7 0x00005858 /* 64-bit */
1125: #define GRCMBOX_RELOAD_STAT 0x00005860 /* 64-bit */
1126: #define GRCMBOX_RCVSTD_PROD_IDX 0x00005868 /* 64-bit */
1127: #define GRCMBOX_RCVJUMBO_PROD_IDX 0x00005870 /* 64-bit */
1128: #define GRCMBOX_RCVMINI_PROD_IDX 0x00005878 /* 64-bit */
1129: #define GRCMBOX_RCVRET_CON_IDX_0 0x00005880 /* 64-bit */
1130: #define GRCMBOX_RCVRET_CON_IDX_1 0x00005888 /* 64-bit */
1131: #define GRCMBOX_RCVRET_CON_IDX_2 0x00005890 /* 64-bit */
1132: #define GRCMBOX_RCVRET_CON_IDX_3 0x00005898 /* 64-bit */
1133: #define GRCMBOX_RCVRET_CON_IDX_4 0x000058a0 /* 64-bit */
1134: #define GRCMBOX_RCVRET_CON_IDX_5 0x000058a8 /* 64-bit */
1135: #define GRCMBOX_RCVRET_CON_IDX_6 0x000058b0 /* 64-bit */
1136: #define GRCMBOX_RCVRET_CON_IDX_7 0x000058b8 /* 64-bit */
1137: #define GRCMBOX_RCVRET_CON_IDX_8 0x000058c0 /* 64-bit */
1138: #define GRCMBOX_RCVRET_CON_IDX_9 0x000058c8 /* 64-bit */
1139: #define GRCMBOX_RCVRET_CON_IDX_10 0x000058d0 /* 64-bit */
1140: #define GRCMBOX_RCVRET_CON_IDX_11 0x000058d8 /* 64-bit */
1141: #define GRCMBOX_RCVRET_CON_IDX_12 0x000058e0 /* 64-bit */
1142: #define GRCMBOX_RCVRET_CON_IDX_13 0x000058e8 /* 64-bit */
1143: #define GRCMBOX_RCVRET_CON_IDX_14 0x000058f0 /* 64-bit */
1144: #define GRCMBOX_RCVRET_CON_IDX_15 0x000058f8 /* 64-bit */
1145: #define GRCMBOX_SNDHOST_PROD_IDX_0 0x00005900 /* 64-bit */
1146: #define GRCMBOX_SNDHOST_PROD_IDX_1 0x00005908 /* 64-bit */
1147: #define GRCMBOX_SNDHOST_PROD_IDX_2 0x00005910 /* 64-bit */
1148: #define GRCMBOX_SNDHOST_PROD_IDX_3 0x00005918 /* 64-bit */
1149: #define GRCMBOX_SNDHOST_PROD_IDX_4 0x00005920 /* 64-bit */
1150: #define GRCMBOX_SNDHOST_PROD_IDX_5 0x00005928 /* 64-bit */
1151: #define GRCMBOX_SNDHOST_PROD_IDX_6 0x00005930 /* 64-bit */
1152: #define GRCMBOX_SNDHOST_PROD_IDX_7 0x00005938 /* 64-bit */
1153: #define GRCMBOX_SNDHOST_PROD_IDX_8 0x00005940 /* 64-bit */
1154: #define GRCMBOX_SNDHOST_PROD_IDX_9 0x00005948 /* 64-bit */
1155: #define GRCMBOX_SNDHOST_PROD_IDX_10 0x00005950 /* 64-bit */
1156: #define GRCMBOX_SNDHOST_PROD_IDX_11 0x00005958 /* 64-bit */
1157: #define GRCMBOX_SNDHOST_PROD_IDX_12 0x00005960 /* 64-bit */
1158: #define GRCMBOX_SNDHOST_PROD_IDX_13 0x00005968 /* 64-bit */
1159: #define GRCMBOX_SNDHOST_PROD_IDX_14 0x00005970 /* 64-bit */
1160: #define GRCMBOX_SNDHOST_PROD_IDX_15 0x00005978 /* 64-bit */
1161: #define GRCMBOX_SNDNIC_PROD_IDX_0 0x00005980 /* 64-bit */
1162: #define GRCMBOX_SNDNIC_PROD_IDX_1 0x00005988 /* 64-bit */
1163: #define GRCMBOX_SNDNIC_PROD_IDX_2 0x00005990 /* 64-bit */
1164: #define GRCMBOX_SNDNIC_PROD_IDX_3 0x00005998 /* 64-bit */
1165: #define GRCMBOX_SNDNIC_PROD_IDX_4 0x000059a0 /* 64-bit */
1166: #define GRCMBOX_SNDNIC_PROD_IDX_5 0x000059a8 /* 64-bit */
1167: #define GRCMBOX_SNDNIC_PROD_IDX_6 0x000059b0 /* 64-bit */
1168: #define GRCMBOX_SNDNIC_PROD_IDX_7 0x000059b8 /* 64-bit */
1169: #define GRCMBOX_SNDNIC_PROD_IDX_8 0x000059c0 /* 64-bit */
1170: #define GRCMBOX_SNDNIC_PROD_IDX_9 0x000059c8 /* 64-bit */
1171: #define GRCMBOX_SNDNIC_PROD_IDX_10 0x000059d0 /* 64-bit */
1172: #define GRCMBOX_SNDNIC_PROD_IDX_11 0x000059d8 /* 64-bit */
1173: #define GRCMBOX_SNDNIC_PROD_IDX_12 0x000059e0 /* 64-bit */
1174: #define GRCMBOX_SNDNIC_PROD_IDX_13 0x000059e8 /* 64-bit */
1175: #define GRCMBOX_SNDNIC_PROD_IDX_14 0x000059f0 /* 64-bit */
1176: #define GRCMBOX_SNDNIC_PROD_IDX_15 0x000059f8 /* 64-bit */
1177: #define GRCMBOX_HIGH_PRIO_EV_VECTOR 0x00005a00
1178: #define GRCMBOX_HIGH_PRIO_EV_MASK 0x00005a04
1179: #define GRCMBOX_LOW_PRIO_EV_VEC 0x00005a08
1180: #define GRCMBOX_LOW_PRIO_EV_MASK 0x00005a0c
1181: /* 0x5a10 --> 0x5c00 */
1182:
1183: /* Flow Through queues */
1184: #define FTQ_RESET 0x00005c00
1185: #define FTQ_RESET_DMA_READ_QUEUE (1 << 1)
1186: #define FTQ_RESET_DMA_HIGH_PRI_READ (1 << 2)
1187: #define FTQ_RESET_SEND_BD_COMPLETION (1 << 4)
1188: #define FTQ_RESET_DMA_WRITE (1 << 6)
1189: #define FTQ_RESET_DMA_HIGH_PRI_WRITE (1 << 7)
1190: #define FTQ_RESET_SEND_DATA_COMPLETION (1 << 9)
1191: #define FTQ_RESET_HOST_COALESCING (1 << 10)
1192: #define FTQ_RESET_MAC_TX (1 << 11)
1193: #define FTQ_RESET_RX_BD_COMPLETE (1 << 13)
1194: #define FTQ_RESET_RX_LIST_PLCMT (1 << 14)
1195: #define FTQ_RESET_RX_DATA_COMPLETION (1 << 16)
1196: /* 0x5c04 --> 0x5c10 unused */
1197: #define FTQ_DMA_NORM_READ_CTL 0x00005c10
1198: #define FTQ_DMA_NORM_READ_FULL_CNT 0x00005c14
1199: #define FTQ_DMA_NORM_READ_FIFO_ENQDEQ 0x00005c18
1200: #define FTQ_DMA_NORM_READ_WRITE_PEEK 0x00005c1c
1201: #define FTQ_DMA_HIGH_READ_CTL 0x00005c20
1202: #define FTQ_DMA_HIGH_READ_FULL_CNT 0x00005c24
1203: #define FTQ_DMA_HIGH_READ_FIFO_ENQDEQ 0x00005c28
1204: #define FTQ_DMA_HIGH_READ_WRITE_PEEK 0x00005c2c
1205: #define FTQ_DMA_COMP_DISC_CTL 0x00005c30
1206: #define FTQ_DMA_COMP_DISC_FULL_CNT 0x00005c34
1207: #define FTQ_DMA_COMP_DISC_FIFO_ENQDEQ 0x00005c38
1208: #define FTQ_DMA_COMP_DISC_WRITE_PEEK 0x00005c3c
1209: #define FTQ_SEND_BD_COMP_CTL 0x00005c40
1210: #define FTQ_SEND_BD_COMP_FULL_CNT 0x00005c44
1211: #define FTQ_SEND_BD_COMP_FIFO_ENQDEQ 0x00005c48
1212: #define FTQ_SEND_BD_COMP_WRITE_PEEK 0x00005c4c
1213: #define FTQ_SEND_DATA_INIT_CTL 0x00005c50
1214: #define FTQ_SEND_DATA_INIT_FULL_CNT 0x00005c54
1215: #define FTQ_SEND_DATA_INIT_FIFO_ENQDEQ 0x00005c58
1216: #define FTQ_SEND_DATA_INIT_WRITE_PEEK 0x00005c5c
1217: #define FTQ_DMA_NORM_WRITE_CTL 0x00005c60
1218: #define FTQ_DMA_NORM_WRITE_FULL_CNT 0x00005c64
1219: #define FTQ_DMA_NORM_WRITE_FIFO_ENQDEQ 0x00005c68
1220: #define FTQ_DMA_NORM_WRITE_WRITE_PEEK 0x00005c6c
1221: #define FTQ_DMA_HIGH_WRITE_CTL 0x00005c70
1222: #define FTQ_DMA_HIGH_WRITE_FULL_CNT 0x00005c74
1223: #define FTQ_DMA_HIGH_WRITE_FIFO_ENQDEQ 0x00005c78
1224: #define FTQ_DMA_HIGH_WRITE_WRITE_PEEK 0x00005c7c
1225: #define FTQ_SWTYPE1_CTL 0x00005c80
1226: #define FTQ_SWTYPE1_FULL_CNT 0x00005c84
1227: #define FTQ_SWTYPE1_FIFO_ENQDEQ 0x00005c88
1228: #define FTQ_SWTYPE1_WRITE_PEEK 0x00005c8c
1229: #define FTQ_SEND_DATA_COMP_CTL 0x00005c90
1230: #define FTQ_SEND_DATA_COMP_FULL_CNT 0x00005c94
1231: #define FTQ_SEND_DATA_COMP_FIFO_ENQDEQ 0x00005c98
1232: #define FTQ_SEND_DATA_COMP_WRITE_PEEK 0x00005c9c
1233: #define FTQ_HOST_COAL_CTL 0x00005ca0
1234: #define FTQ_HOST_COAL_FULL_CNT 0x00005ca4
1235: #define FTQ_HOST_COAL_FIFO_ENQDEQ 0x00005ca8
1236: #define FTQ_HOST_COAL_WRITE_PEEK 0x00005cac
1237: #define FTQ_MAC_TX_CTL 0x00005cb0
1238: #define FTQ_MAC_TX_FULL_CNT 0x00005cb4
1239: #define FTQ_MAC_TX_FIFO_ENQDEQ 0x00005cb8
1240: #define FTQ_MAC_TX_WRITE_PEEK 0x00005cbc
1241: #define FTQ_MB_FREE_CTL 0x00005cc0
1242: #define FTQ_MB_FREE_FULL_CNT 0x00005cc4
1243: #define FTQ_MB_FREE_FIFO_ENQDEQ 0x00005cc8
1244: #define FTQ_MB_FREE_WRITE_PEEK 0x00005ccc
1245: #define FTQ_RCVBD_COMP_CTL 0x00005cd0
1246: #define FTQ_RCVBD_COMP_FULL_CNT 0x00005cd4
1247: #define FTQ_RCVBD_COMP_FIFO_ENQDEQ 0x00005cd8
1248: #define FTQ_RCVBD_COMP_WRITE_PEEK 0x00005cdc
1249: #define FTQ_RCVLST_PLMT_CTL 0x00005ce0
1250: #define FTQ_RCVLST_PLMT_FULL_CNT 0x00005ce4
1251: #define FTQ_RCVLST_PLMT_FIFO_ENQDEQ 0x00005ce8
1252: #define FTQ_RCVLST_PLMT_WRITE_PEEK 0x00005cec
1253: #define FTQ_RCVDATA_INI_CTL 0x00005cf0
1254: #define FTQ_RCVDATA_INI_FULL_CNT 0x00005cf4
1255: #define FTQ_RCVDATA_INI_FIFO_ENQDEQ 0x00005cf8
1256: #define FTQ_RCVDATA_INI_WRITE_PEEK 0x00005cfc
1257: #define FTQ_RCVDATA_COMP_CTL 0x00005d00
1258: #define FTQ_RCVDATA_COMP_FULL_CNT 0x00005d04
1259: #define FTQ_RCVDATA_COMP_FIFO_ENQDEQ 0x00005d08
1260: #define FTQ_RCVDATA_COMP_WRITE_PEEK 0x00005d0c
1261: #define FTQ_SWTYPE2_CTL 0x00005d10
1262: #define FTQ_SWTYPE2_FULL_CNT 0x00005d14
1263: #define FTQ_SWTYPE2_FIFO_ENQDEQ 0x00005d18
1264: #define FTQ_SWTYPE2_WRITE_PEEK 0x00005d1c
1265: /* 0x5d20 --> 0x6000 unused */
1266:
1267: /* Message signaled interrupt registers */
1268: #define MSGINT_MODE 0x00006000
1269: #define MSGINT_MODE_RESET 0x00000001
1270: #define MSGINT_MODE_ENABLE 0x00000002
1271: #define MSGINT_STATUS 0x00006004
1272: #define MSGINT_FIFO 0x00006008
1273: /* 0x600c --> 0x6400 unused */
1274:
1275: /* DMA completion registers */
1276: #define DMAC_MODE 0x00006400
1277: #define DMAC_MODE_RESET 0x00000001
1278: #define DMAC_MODE_ENABLE 0x00000002
1279: /* 0x6404 --> 0x6800 unused */
1280:
1281: /* GRC registers */
1282: #define GRC_MODE 0x00006800
1283: #define GRC_MODE_UPD_ON_COAL 0x00000001
1284: #define GRC_MODE_BSWAP_NONFRM_DATA 0x00000002
1285: #define GRC_MODE_WSWAP_NONFRM_DATA 0x00000004
1286: #define GRC_MODE_BSWAP_DATA 0x00000010
1287: #define GRC_MODE_WSWAP_DATA 0x00000020
1288: #define GRC_MODE_SPLITHDR 0x00000100
1289: #define GRC_MODE_NOFRM_CRACKING 0x00000200
1290: #define GRC_MODE_INCL_CRC 0x00000400
1291: #define GRC_MODE_ALLOW_BAD_FRMS 0x00000800
1292: #define GRC_MODE_NOIRQ_ON_SENDS 0x00002000
1293: #define GRC_MODE_NOIRQ_ON_RCV 0x00004000
1294: #define GRC_MODE_FORCE_PCI32BIT 0x00008000
1295: #define GRC_MODE_HOST_STACKUP 0x00010000
1296: #define GRC_MODE_HOST_SENDBDS 0x00020000
1297: #define GRC_MODE_NO_TX_PHDR_CSUM 0x00100000
1298: #define GRC_MODE_NO_RX_PHDR_CSUM 0x00800000
1299: #define GRC_MODE_IRQ_ON_TX_CPU_ATTN 0x01000000
1300: #define GRC_MODE_IRQ_ON_RX_CPU_ATTN 0x02000000
1301: #define GRC_MODE_IRQ_ON_MAC_ATTN 0x04000000
1302: #define GRC_MODE_IRQ_ON_DMA_ATTN 0x08000000
1303: #define GRC_MODE_IRQ_ON_FLOW_ATTN 0x10000000
1304: #define GRC_MODE_4X_NIC_SEND_RINGS 0x20000000
1305: #define GRC_MODE_MCAST_FRM_ENABLE 0x40000000
1306: #define GRC_MISC_CFG 0x00006804
1307: #define GRC_MISC_CFG_CORECLK_RESET 0x00000001
1308: #define GRC_MISC_CFG_PRESCALAR_MASK 0x000000fe
1309: #define GRC_MISC_CFG_PRESCALAR_SHIFT 1
1310: #define GRC_MISC_CFG_BOARD_ID_MASK 0x0001e000
1311: #define GRC_MISC_CFG_BOARD_ID_5700 0x0001e000
1312: #define GRC_MISC_CFG_BOARD_ID_5701 0x00000000
1313: #define GRC_MISC_CFG_BOARD_ID_5702FE 0x00004000
1314: #define GRC_MISC_CFG_BOARD_ID_5703 0x00000000
1315: #define GRC_MISC_CFG_BOARD_ID_5703S 0x00002000
1316: #define GRC_MISC_CFG_BOARD_ID_5704 0x00000000
1317: #define GRC_MISC_CFG_BOARD_ID_5704CIOBE 0x00004000
1318: #define GRC_MISC_CFG_BOARD_ID_5704_A2 0x00008000
1319: #define GRC_MISC_CFG_BOARD_ID_5788 0x00010000
1320: #define GRC_MISC_CFG_BOARD_ID_5788M 0x00018000
1321: #define GRC_MISC_CFG_BOARD_ID_AC91002A1 0x00018000
1322: #define GRC_MISC_CFG_KEEP_GPHY_POWER 0x04000000
1323: #define GRC_LOCAL_CTRL 0x00006808
1324: #define GRC_LCLCTRL_INT_ACTIVE 0x00000001
1325: #define GRC_LCLCTRL_CLEARINT 0x00000002
1326: #define GRC_LCLCTRL_SETINT 0x00000004
1327: #define GRC_LCLCTRL_INT_ON_ATTN 0x00000008
1328: #define GRC_LCLCTRL_GPIO_INPUT0 0x00000100
1329: #define GRC_LCLCTRL_GPIO_INPUT1 0x00000200
1330: #define GRC_LCLCTRL_GPIO_INPUT2 0x00000400
1331: #define GRC_LCLCTRL_GPIO_OE0 0x00000800
1332: #define GRC_LCLCTRL_GPIO_OE1 0x00001000
1333: #define GRC_LCLCTRL_GPIO_OE2 0x00002000
1334: #define GRC_LCLCTRL_GPIO_OUTPUT0 0x00004000
1335: #define GRC_LCLCTRL_GPIO_OUTPUT1 0x00008000
1336: #define GRC_LCLCTRL_GPIO_OUTPUT2 0x00010000
1337: #define GRC_LCLCTRL_EXTMEM_ENABLE 0x00020000
1338: #define GRC_LCLCTRL_MEMSZ_MASK 0x001c0000
1339: #define GRC_LCLCTRL_MEMSZ_256K 0x00000000
1340: #define GRC_LCLCTRL_MEMSZ_512K 0x00040000
1341: #define GRC_LCLCTRL_MEMSZ_1M 0x00080000
1342: #define GRC_LCLCTRL_MEMSZ_2M 0x000c0000
1343: #define GRC_LCLCTRL_MEMSZ_4M 0x00100000
1344: #define GRC_LCLCTRL_MEMSZ_8M 0x00140000
1345: #define GRC_LCLCTRL_MEMSZ_16M 0x00180000
1346: #define GRC_LCLCTRL_BANK_SELECT 0x00200000
1347: #define GRC_LCLCTRL_SSRAM_TYPE 0x00400000
1348: #define GRC_LCLCTRL_AUTO_SEEPROM 0x01000000
1349: #define GRC_TIMER 0x0000680c
1350: #define GRC_RX_CPU_EVENT 0x00006810
1351: #define GRC_RX_TIMER_REF 0x00006814
1352: #define GRC_RX_CPU_SEM 0x00006818
1353: #define GRC_REMOTE_RX_CPU_ATTN 0x0000681c
1354: #define GRC_TX_CPU_EVENT 0x00006820
1355: #define GRC_TX_TIMER_REF 0x00006824
1356: #define GRC_TX_CPU_SEM 0x00006828
1357: #define GRC_REMOTE_TX_CPU_ATTN 0x0000682c
1358: #define GRC_MEM_POWER_UP 0x00006830 /* 64-bit */
1359: #define GRC_EEPROM_ADDR 0x00006838
1360: #define EEPROM_ADDR_WRITE 0x00000000
1361: #define EEPROM_ADDR_READ 0x80000000
1362: #define EEPROM_ADDR_COMPLETE 0x40000000
1363: #define EEPROM_ADDR_FSM_RESET 0x20000000
1364: #define EEPROM_ADDR_DEVID_MASK 0x1c000000
1365: #define EEPROM_ADDR_DEVID_SHIFT 26
1366: #define EEPROM_ADDR_START 0x02000000
1367: #define EEPROM_ADDR_CLKPERD_SHIFT 16
1368: #define EEPROM_ADDR_ADDR_MASK 0x0000ffff
1369: #define EEPROM_ADDR_ADDR_SHIFT 0
1370: #define EEPROM_DEFAULT_CLOCK_PERIOD 0x60
1371: #define EEPROM_CHIP_SIZE (64 * 1024)
1372: #define GRC_EEPROM_DATA 0x0000683c
1373: #define GRC_EEPROM_CTRL 0x00006840
1374: #define GRC_MDI_CTRL 0x00006844
1375: #define GRC_SEEPROM_DELAY 0x00006848
1376: /* 0x684c --> 0x6c00 unused */
1377:
1378: /* 0x6c00 --> 0x7000 unused */
1379:
1380: /* NVRAM Control registers */
1381: #define NVRAM_CMD 0x00007000
1382: #define NVRAM_CMD_RESET 0x00000001
1383: #define NVRAM_CMD_DONE 0x00000008
1384: #define NVRAM_CMD_GO 0x00000010
1385: #define NVRAM_CMD_WR 0x00000020
1386: #define NVRAM_CMD_RD 0x00000000
1387: #define NVRAM_CMD_ERASE 0x00000040
1388: #define NVRAM_CMD_FIRST 0x00000080
1389: #define NVRAM_CMD_LAST 0x00000100
1390: #define NVRAM_STAT 0x00007004
1391: #define NVRAM_WRDATA 0x00007008
1392: #define NVRAM_ADDR 0x0000700c
1393: #define NVRAM_ADDR_MSK 0x00ffffff
1394: #define NVRAM_RDDATA 0x00007010
1395: #define NVRAM_CFG1 0x00007014
1396: #define NVRAM_CFG1_FLASHIF_ENAB 0x00000001
1397: #define NVRAM_CFG1_BUFFERED_MODE 0x00000002
1398: #define NVRAM_CFG1_PASS_THRU 0x00000004
1399: #define NVRAM_CFG1_BIT_BANG 0x00000008
1400: #define NVRAM_CFG1_COMPAT_BYPASS 0x80000000
1401: #define NVRAM_CFG2 0x00007018
1402: #define NVRAM_CFG3 0x0000701c
1403: #define NVRAM_SWARB 0x00007020
1404: #define SWARB_REQ_SET0 0x00000001
1405: #define SWARB_REQ_SET1 0x00000002
1406: #define SWARB_REQ_SET2 0x00000004
1407: #define SWARB_REQ_SET3 0x00000008
1408: #define SWARB_REQ_CLR0 0x00000010
1409: #define SWARB_REQ_CLR1 0x00000020
1410: #define SWARB_REQ_CLR2 0x00000040
1411: #define SWARB_REQ_CLR3 0x00000080
1412: #define SWARB_GNT0 0x00000100
1413: #define SWARB_GNT1 0x00000200
1414: #define SWARB_GNT2 0x00000400
1415: #define SWARB_GNT3 0x00000800
1416: #define SWARB_REQ0 0x00001000
1417: #define SWARB_REQ1 0x00002000
1418: #define SWARB_REQ2 0x00004000
1419: #define SWARB_REQ3 0x00008000
1420: #define NVRAM_BUFFERED_PAGE_SIZE 264
1421: #define NVRAM_BUFFERED_PAGE_POS 9
1422: /* 0x7024 --> 0x7400 unused */
1423:
1424: /* 0x7400 --> 0x8000 unused */
1425:
1426: /* 32K Window into NIC internal memory */
1427: #define NIC_SRAM_WIN_BASE 0x00008000
1428:
1429: /* Offsets into first 32k of NIC internal memory. */
1430: #define NIC_SRAM_PAGE_ZERO 0x00000000
1431: #define NIC_SRAM_SEND_RCB 0x00000100 /* 16 * TG3_BDINFO_... */
1432: #define NIC_SRAM_RCV_RET_RCB 0x00000200 /* 16 * TG3_BDINFO_... */
1433: #define NIC_SRAM_STATS_BLK 0x00000300
1434: #define NIC_SRAM_STATUS_BLK 0x00000b00
1435:
1436: #define NIC_SRAM_FIRMWARE_MBOX 0x00000b50
1437: #define NIC_SRAM_FIRMWARE_MBOX_MAGIC1 0x4B657654
1438: #define NIC_SRAM_FIRMWARE_MBOX_MAGIC2 0x4861764b /* !dma on linkchg */
1439:
1440: #define NIC_SRAM_DATA_SIG 0x00000b54
1441: #define NIC_SRAM_DATA_SIG_MAGIC 0x4b657654 /* ascii for 'KevT' */
1442:
1443: #define NIC_SRAM_DATA_CFG 0x00000b58
1444: #define NIC_SRAM_DATA_CFG_LED_MODE_MASK 0x0000000c
1445: #define NIC_SRAM_DATA_CFG_LED_MODE_UNKNOWN 0x00000000
1446: #define NIC_SRAM_DATA_CFG_LED_TRIPLE_SPD 0x00000004
1447: #define NIC_SRAM_DATA_CFG_LED_OPEN_DRAIN 0x00000004
1448: #define NIC_SRAM_DATA_CFG_LED_LINK_SPD 0x00000008
1449: #define NIC_SRAM_DATA_CFG_LED_OUTPUT 0x00000008
1450: #define NIC_SRAM_DATA_CFG_PHY_TYPE_MASK 0x00000030
1451: #define NIC_SRAM_DATA_CFG_PHY_TYPE_UNKNOWN 0x00000000
1452: #define NIC_SRAM_DATA_CFG_PHY_TYPE_COPPER 0x00000010
1453: #define NIC_SRAM_DATA_CFG_PHY_TYPE_FIBER 0x00000020
1454: #define NIC_SRAM_DATA_CFG_WOL_ENABLE 0x00000040
1455: #define NIC_SRAM_DATA_CFG_ASF_ENABLE 0x00000080
1456: #define NIC_SRAM_DATA_CFG_EEPROM_WP 0x00000100
1457: #define NIC_SRAM_DATA_CFG_MINI_PCI 0x00001000
1458: #define NIC_SRAM_DATA_CFG_FIBER_WOL 0x00004000
1459:
1460: #define NIC_SRAM_DATA_PHY_ID 0x00000b74
1461: #define NIC_SRAM_DATA_PHY_ID1_MASK 0xffff0000
1462: #define NIC_SRAM_DATA_PHY_ID2_MASK 0x0000ffff
1463:
1464: #define NIC_SRAM_FW_CMD_MBOX 0x00000b78
1465: #define FWCMD_NICDRV_ALIVE 0x00000001
1466: #define FWCMD_NICDRV_PAUSE_FW 0x00000002
1467: #define FWCMD_NICDRV_IPV4ADDR_CHG 0x00000003
1468: #define FWCMD_NICDRV_IPV6ADDR_CHG 0x00000004
1469: #define FWCMD_NICDRV_FIX_DMAR 0x00000005
1470: #define FWCMD_NICDRV_FIX_DMAW 0x00000006
1471: #define NIC_SRAM_FW_CMD_LEN_MBOX 0x00000b7c
1472: #define NIC_SRAM_FW_CMD_DATA_MBOX 0x00000b80
1473: #define NIC_SRAM_FW_ASF_STATUS_MBOX 0x00000c00
1474: #define NIC_SRAM_FW_DRV_STATE_MBOX 0x00000c04
1475: #define DRV_STATE_START 0x00000001
1476: #define DRV_STATE_UNLOAD 0x00000002
1477: #define DRV_STATE_WOL 0x00000003
1478: #define DRV_STATE_SUSPEND 0x00000004
1479:
1480: #define NIC_SRAM_FW_RESET_TYPE_MBOX 0x00000c08
1481:
1482: #define NIC_SRAM_MAC_ADDR_HIGH_MBOX 0x00000c14
1483: #define NIC_SRAM_MAC_ADDR_LOW_MBOX 0x00000c18
1484:
1485: #define NIC_SRAM_RX_MINI_BUFFER_DESC 0x00001000
1486:
1487: #define NIC_SRAM_DMA_DESC_POOL_BASE 0x00002000
1488: #define NIC_SRAM_DMA_DESC_POOL_SIZE 0x00002000
1489: #define NIC_SRAM_TX_BUFFER_DESC 0x00004000 /* 512 entries */
1490: #define NIC_SRAM_RX_BUFFER_DESC 0x00006000 /* 256 entries */
1491: #define NIC_SRAM_RX_JUMBO_BUFFER_DESC 0x00007000 /* 256 entries */
1492: #define NIC_SRAM_MBUF_POOL_BASE 0x00008000
1493: #define NIC_SRAM_MBUF_POOL_SIZE96 0x00018000
1494: #define NIC_SRAM_MBUF_POOL_SIZE64 0x00010000
1495: #define NIC_SRAM_MBUF_POOL_BASE5705 0x00010000
1496: #define NIC_SRAM_MBUF_POOL_SIZE5705 0x0000e000
1497:
1498: /* Currently this is fixed. */
1499: #define PHY_ADDR 0x01
1500:
1501: /* Tigon3 specific PHY MII registers. */
1502: #define TG3_BMCR_SPEED1000 0x0040
1503:
1504: #define MII_TG3_CTRL 0x09 /* 1000-baseT control register */
1505: #define MII_TG3_CTRL_ADV_1000_HALF 0x0100
1506: #define MII_TG3_CTRL_ADV_1000_FULL 0x0200
1507: #define MII_TG3_CTRL_AS_MASTER 0x0800
1508: #define MII_TG3_CTRL_ENABLE_AS_MASTER 0x1000
1509:
1510: #define MII_TG3_EXT_CTRL 0x10 /* Extended control register */
1511: #define MII_TG3_EXT_CTRL_LNK3_LED_MODE 0x0002
1512: #define MII_TG3_EXT_CTRL_TBI 0x8000
1513:
1514: #define MII_TG3_EXT_STAT 0x11 /* Extended status register */
1515: #define MII_TG3_EXT_STAT_LPASS 0x0100
1516:
1517: #define MII_TG3_DSP_RW_PORT 0x15 /* DSP coefficient read/write port */
1518:
1519: #define MII_TG3_DSP_ADDRESS 0x17 /* DSP address register */
1520:
1521: #define MII_TG3_AUX_CTRL 0x18 /* auxilliary control register */
1522:
1523: #define MII_TG3_AUX_STAT 0x19 /* auxilliary status register */
1524: #define MII_TG3_AUX_STAT_LPASS 0x0004
1525: #define MII_TG3_AUX_STAT_SPDMASK 0x0700
1526: #define MII_TG3_AUX_STAT_10HALF 0x0100
1527: #define MII_TG3_AUX_STAT_10FULL 0x0200
1528: #define MII_TG3_AUX_STAT_100HALF 0x0300
1529: #define MII_TG3_AUX_STAT_100_4 0x0400
1530: #define MII_TG3_AUX_STAT_100FULL 0x0500
1531: #define MII_TG3_AUX_STAT_1000HALF 0x0600
1532: #define MII_TG3_AUX_STAT_1000FULL 0x0700
1533:
1534: #define MII_TG3_ISTAT 0x1a /* IRQ status register */
1535: #define MII_TG3_IMASK 0x1b /* IRQ mask register */
1536:
1537: /* ISTAT/IMASK event bits */
1538: #define MII_TG3_INT_LINKCHG 0x0002
1539: #define MII_TG3_INT_SPEEDCHG 0x0004
1540: #define MII_TG3_INT_DUPLEXCHG 0x0008
1541: #define MII_TG3_INT_ANEG_PAGE_RX 0x0400
1542:
1543:
1544: /* There are two ways to manage the TX descriptors on the tigon3.
1545: * Either the descriptors are in host DMA'able memory, or they
1546: * exist only in the cards on-chip SRAM. All 16 send bds are under
1547: * the same mode, they may not be configured individually.
1548: *
1549: * The mode we use is controlled by TG3_FLAG_HOST_TXDS in tp->tg3_flags.
1550: *
1551: * To use host memory TX descriptors:
1552: * 1) Set GRC_MODE_HOST_SENDBDS in GRC_MODE register.
1553: * Make sure GRC_MODE_4X_NIC_SEND_RINGS is clear.
1554: * 2) Allocate DMA'able memory.
1555: * 3) In NIC_SRAM_SEND_RCB (of desired index) of on-chip SRAM:
1556: * a) Set TG3_BDINFO_HOST_ADDR to DMA address of memory
1557: * obtained in step 2
1558: * b) Set TG3_BDINFO_NIC_ADDR to NIC_SRAM_TX_BUFFER_DESC.
1559: * c) Set len field of TG3_BDINFO_MAXLEN_FLAGS to number
1560: * of TX descriptors. Leave flags field clear.
1561: * 4) Access TX descriptors via host memory. The chip
1562: * will refetch into local SRAM as needed when producer
1563: * index mailboxes are updated.
1564: *
1565: * To use on-chip TX descriptors:
1566: * 1) Set GRC_MODE_4X_NIC_SEND_RINGS in GRC_MODE register.
1567: * Make sure GRC_MODE_HOST_SENDBDS is clear.
1568: * 2) In NIC_SRAM_SEND_RCB (of desired index) of on-chip SRAM:
1569: * a) Set TG3_BDINFO_HOST_ADDR to zero.
1570: * b) Set TG3_BDINFO_NIC_ADDR to NIC_SRAM_TX_BUFFER_DESC
1571: * c) TG3_BDINFO_MAXLEN_FLAGS is don't care.
1572: * 3) Access TX descriptors directly in on-chip SRAM
1573: * using normal {read,write}l(). (and not using
1574: * pointer dereferencing of ioremap()'d memory like
1575: * the broken Broadcom driver does)
1576: *
1577: * Note that BDINFO_FLAGS_DISABLED should be set in the flags field of
1578: * TG3_BDINFO_MAXLEN_FLAGS of all unused SEND_RCB indices.
1579: */
1580: struct tg3_tx_buffer_desc {
1581: uint32_t addr_hi;
1582: uint32_t addr_lo;
1583:
1584: uint32_t len_flags;
1585: #define TXD_FLAG_TCPUDP_CSUM 0x0001
1586: #define TXD_FLAG_IP_CSUM 0x0002
1587: #define TXD_FLAG_END 0x0004
1588: #define TXD_FLAG_IP_FRAG 0x0008
1589: #define TXD_FLAG_IP_FRAG_END 0x0010
1590: #define TXD_FLAG_VLAN 0x0040
1591: #define TXD_FLAG_COAL_NOW 0x0080
1592: #define TXD_FLAG_CPU_PRE_DMA 0x0100
1593: #define TXD_FLAG_CPU_POST_DMA 0x0200
1594: #define TXD_FLAG_ADD_SRC_ADDR 0x1000
1595: #define TXD_FLAG_CHOOSE_SRC_ADDR 0x6000
1596: #define TXD_FLAG_NO_CRC 0x8000
1597: #define TXD_LEN_SHIFT 16
1598:
1599: uint32_t vlan_tag;
1600: #define TXD_VLAN_TAG_SHIFT 0
1601: #define TXD_MSS_SHIFT 16
1602: };
1603:
1604: #define TXD_ADDR 0x00UL /* 64-bit */
1605: #define TXD_LEN_FLAGS 0x08UL /* 32-bit (upper 16-bits are len) */
1606: #define TXD_VLAN_TAG 0x0cUL /* 32-bit (upper 16-bits are tag) */
1607: #define TXD_SIZE 0x10UL
1608:
1609: struct tg3_rx_buffer_desc {
1610: uint32_t addr_hi;
1611: uint32_t addr_lo;
1612:
1613: uint32_t idx_len;
1614: #define RXD_IDX_MASK 0xffff0000
1615: #define RXD_IDX_SHIFT 16
1616: #define RXD_LEN_MASK 0x0000ffff
1617: #define RXD_LEN_SHIFT 0
1618:
1619: uint32_t type_flags;
1620: #define RXD_TYPE_SHIFT 16
1621: #define RXD_FLAGS_SHIFT 0
1622:
1623: #define RXD_FLAG_END 0x0004
1624: #define RXD_FLAG_MINI 0x0800
1625: #define RXD_FLAG_JUMBO 0x0020
1626: #define RXD_FLAG_VLAN 0x0040
1627: #define RXD_FLAG_ERROR 0x0400
1628: #define RXD_FLAG_IP_CSUM 0x1000
1629: #define RXD_FLAG_TCPUDP_CSUM 0x2000
1630: #define RXD_FLAG_IS_TCP 0x4000
1631:
1632: uint32_t ip_tcp_csum;
1633: #define RXD_IPCSUM_MASK 0xffff0000
1634: #define RXD_IPCSUM_SHIFT 16
1635: #define RXD_TCPCSUM_MASK 0x0000ffff
1636: #define RXD_TCPCSUM_SHIFT 0
1637:
1638: uint32_t err_vlan;
1639:
1640: #define RXD_VLAN_MASK 0x0000ffff
1641:
1642: #define RXD_ERR_BAD_CRC 0x00010000
1643: #define RXD_ERR_COLLISION 0x00020000
1644: #define RXD_ERR_LINK_LOST 0x00040000
1645: #define RXD_ERR_PHY_DECODE 0x00080000
1646: #define RXD_ERR_ODD_NIBBLE_RCVD_MII 0x00100000
1647: #define RXD_ERR_MAC_ABRT 0x00200000
1648: #define RXD_ERR_TOO_SMALL 0x00400000
1649: #define RXD_ERR_NO_RESOURCES 0x00800000
1650: #define RXD_ERR_HUGE_FRAME 0x01000000
1651: #define RXD_ERR_MASK 0xffff0000
1652:
1653: uint32_t reserved;
1654: uint32_t opaque;
1655: #define RXD_OPAQUE_INDEX_MASK 0x0000ffff
1656: #define RXD_OPAQUE_INDEX_SHIFT 0
1657: #define RXD_OPAQUE_RING_STD 0x00010000
1658: #define RXD_OPAQUE_RING_JUMBO 0x00020000
1659: #define RXD_OPAQUE_RING_MINI 0x00040000
1660: #define RXD_OPAQUE_RING_MASK 0x00070000
1661: };
1662:
1663: struct tg3_ext_rx_buffer_desc {
1664: struct {
1665: uint32_t addr_hi;
1666: uint32_t addr_lo;
1667: } addrlist[3];
1668: uint32_t len2_len1;
1669: uint32_t resv_len3;
1670: struct tg3_rx_buffer_desc std;
1671: };
1672:
1673: /* We only use this when testing out the DMA engine
1674: * at probe time. This is the internal format of buffer
1675: * descriptors used by the chip at NIC_SRAM_DMA_DESCS.
1676: */
1677: struct tg3_internal_buffer_desc {
1678: uint32_t addr_hi;
1679: uint32_t addr_lo;
1680: uint32_t nic_mbuf;
1681: /* XXX FIX THIS */
1682: #if __BYTE_ORDER == __BIG_ENDIAN
1683: uint16_t cqid_sqid;
1684: uint16_t len;
1685: #else
1686: uint16_t len;
1687: uint16_t cqid_sqid;
1688: #endif
1689: uint32_t flags;
1690: uint32_t __cookie1;
1691: uint32_t __cookie2;
1692: uint32_t __cookie3;
1693: };
1694:
1695: #define TG3_HW_STATUS_SIZE 0x50
1696: struct tg3_hw_status {
1697: uint32_t status;
1698: #define SD_STATUS_UPDATED 0x00000001
1699: #define SD_STATUS_LINK_CHG 0x00000002
1700: #define SD_STATUS_ERROR 0x00000004
1701:
1702: uint32_t status_tag;
1703:
1704: #if __BYTE_ORDER == __BIG_ENDIAN
1705: uint16_t rx_consumer;
1706: uint16_t rx_jumbo_consumer;
1707: #else
1708: uint16_t rx_jumbo_consumer;
1709: uint16_t rx_consumer;
1710: #endif
1711:
1712: #if __BYTE_ORDER == __BIG_ENDIAN
1713: uint16_t reserved;
1714: uint16_t rx_mini_consumer;
1715: #else
1716: uint16_t rx_mini_consumer;
1717: uint16_t reserved;
1718: #endif
1719: struct {
1720: #if __BYTE_ORDER == __BIG_ENDIAN
1721: uint16_t tx_consumer;
1722: uint16_t rx_producer;
1723: #else
1724: uint16_t rx_producer;
1725: uint16_t tx_consumer;
1726: #endif
1727: } idx[16];
1728: };
1729:
1730: typedef struct {
1731: uint32_t high, low;
1732: } tg3_stat64_t;
1733:
1734: struct tg3_hw_stats {
1735: uint8_t __reserved0[0x400-0x300];
1736:
1737: /* Statistics maintained by Receive MAC. */
1738: tg3_stat64_t rx_octets;
1739: uint64_t __reserved1;
1740: tg3_stat64_t rx_fragments;
1741: tg3_stat64_t rx_ucast_packets;
1742: tg3_stat64_t rx_mcast_packets;
1743: tg3_stat64_t rx_bcast_packets;
1744: tg3_stat64_t rx_fcs_errors;
1745: tg3_stat64_t rx_align_errors;
1746: tg3_stat64_t rx_xon_pause_rcvd;
1747: tg3_stat64_t rx_xoff_pause_rcvd;
1748: tg3_stat64_t rx_mac_ctrl_rcvd;
1749: tg3_stat64_t rx_xoff_entered;
1750: tg3_stat64_t rx_frame_too_long_errors;
1751: tg3_stat64_t rx_jabbers;
1752: tg3_stat64_t rx_undersize_packets;
1753: tg3_stat64_t rx_in_length_errors;
1754: tg3_stat64_t rx_out_length_errors;
1755: tg3_stat64_t rx_64_or_less_octet_packets;
1756: tg3_stat64_t rx_65_to_127_octet_packets;
1757: tg3_stat64_t rx_128_to_255_octet_packets;
1758: tg3_stat64_t rx_256_to_511_octet_packets;
1759: tg3_stat64_t rx_512_to_1023_octet_packets;
1760: tg3_stat64_t rx_1024_to_1522_octet_packets;
1761: tg3_stat64_t rx_1523_to_2047_octet_packets;
1762: tg3_stat64_t rx_2048_to_4095_octet_packets;
1763: tg3_stat64_t rx_4096_to_8191_octet_packets;
1764: tg3_stat64_t rx_8192_to_9022_octet_packets;
1765:
1766: uint64_t __unused0[37];
1767:
1768: /* Statistics maintained by Transmit MAC. */
1769: tg3_stat64_t tx_octets;
1770: uint64_t __reserved2;
1771: tg3_stat64_t tx_collisions;
1772: tg3_stat64_t tx_xon_sent;
1773: tg3_stat64_t tx_xoff_sent;
1774: tg3_stat64_t tx_flow_control;
1775: tg3_stat64_t tx_mac_errors;
1776: tg3_stat64_t tx_single_collisions;
1777: tg3_stat64_t tx_mult_collisions;
1778: tg3_stat64_t tx_deferred;
1779: uint64_t __reserved3;
1780: tg3_stat64_t tx_excessive_collisions;
1781: tg3_stat64_t tx_late_collisions;
1782: tg3_stat64_t tx_collide_2times;
1783: tg3_stat64_t tx_collide_3times;
1784: tg3_stat64_t tx_collide_4times;
1785: tg3_stat64_t tx_collide_5times;
1786: tg3_stat64_t tx_collide_6times;
1787: tg3_stat64_t tx_collide_7times;
1788: tg3_stat64_t tx_collide_8times;
1789: tg3_stat64_t tx_collide_9times;
1790: tg3_stat64_t tx_collide_10times;
1791: tg3_stat64_t tx_collide_11times;
1792: tg3_stat64_t tx_collide_12times;
1793: tg3_stat64_t tx_collide_13times;
1794: tg3_stat64_t tx_collide_14times;
1795: tg3_stat64_t tx_collide_15times;
1796: tg3_stat64_t tx_ucast_packets;
1797: tg3_stat64_t tx_mcast_packets;
1798: tg3_stat64_t tx_bcast_packets;
1799: tg3_stat64_t tx_carrier_sense_errors;
1800: tg3_stat64_t tx_discards;
1801: tg3_stat64_t tx_errors;
1802:
1803: uint64_t __unused1[31];
1804:
1805: /* Statistics maintained by Receive List Placement. */
1806: tg3_stat64_t COS_rx_packets[16];
1807: tg3_stat64_t COS_rx_filter_dropped;
1808: tg3_stat64_t dma_writeq_full;
1809: tg3_stat64_t dma_write_prioq_full;
1810: tg3_stat64_t rxbds_empty;
1811: tg3_stat64_t rx_discards;
1812: tg3_stat64_t rx_errors;
1813: tg3_stat64_t rx_threshold_hit;
1814:
1815: uint64_t __unused2[9];
1816:
1817: /* Statistics maintained by Send Data Initiator. */
1818: tg3_stat64_t COS_out_packets[16];
1819: tg3_stat64_t dma_readq_full;
1820: tg3_stat64_t dma_read_prioq_full;
1821: tg3_stat64_t tx_comp_queue_full;
1822:
1823: /* Statistics maintained by Host Coalescing. */
1824: tg3_stat64_t ring_set_send_prod_index;
1825: tg3_stat64_t ring_status_update;
1826: tg3_stat64_t nic_irqs;
1827: tg3_stat64_t nic_avoided_irqs;
1828: tg3_stat64_t nic_tx_threshold_hit;
1829:
1830: uint8_t __reserved4[0xb00-0x9c0];
1831: };
1832:
1833: enum phy_led_mode {
1834: led_mode_auto,
1835: led_mode_three_link,
1836: led_mode_link10
1837: };
1838:
1839: #if 0
1840: /* 'mapping' is superfluous as the chip does not write into
1841: * the tx/rx post rings so we could just fetch it from there.
1842: * But the cache behavior is better how we are doing it now.
1843: */
1844: struct ring_info {
1845: struct sk_buff *skb;
1846: DECLARE_PCI_UNMAP_ADDR(mapping)
1847: };
1848:
1849: struct tx_ring_info {
1850: struct sk_buff *skb;
1851: DECLARE_PCI_UNMAP_ADDR(mapping)
1852: uint32_t prev_vlan_tag;
1853: };
1854: #endif
1855:
1856: struct tg3_config_info {
1857: uint32_t flags;
1858: };
1859:
1860: struct tg3_link_config {
1861: /* Describes what we're trying to get. */
1862: uint32_t advertising;
1863: #if 0
1864: uint16_t speed;
1865: uint8_t duplex;
1866: uint8_t autoneg;
1867: #define SPEED_INVALID 0xffff
1868: #define DUPLEX_INVALID 0xff
1869: #define AUTONEG_INVALID 0xff
1870: #endif
1871:
1872: /* Describes what we actually have. */
1873: uint8_t active_speed;
1874: uint8_t active_duplex;
1875:
1876: /* When we go in and out of low power mode we need
1877: * to swap with this state.
1878: */
1879: #if 0
1880: int phy_is_low_power;
1881: uint16_t orig_speed;
1882: uint8_t orig_duplex;
1883: uint8_t orig_autoneg;
1884: #endif
1885: };
1886:
1887: struct tg3_bufmgr_config {
1888: uint32_t mbuf_read_dma_low_water;
1889: uint32_t mbuf_mac_rx_low_water;
1890: uint32_t mbuf_high_water;
1891:
1892: uint32_t mbuf_read_dma_low_water_jumbo;
1893: uint32_t mbuf_mac_rx_low_water_jumbo;
1894: uint32_t mbuf_high_water_jumbo;
1895:
1896: uint32_t dma_low_water;
1897: uint32_t dma_high_water;
1898: };
1899:
1900: struct tg3 {
1901: #if 0
1902: /* SMP locking strategy:
1903: *
1904: * lock: Held during all operations except TX packet
1905: * processing.
1906: *
1907: * tx_lock: Held during tg3_start_xmit{,_4gbug} and tg3_tx
1908: *
1909: * If you want to shut up all asynchronous processing you must
1910: * acquire both locks, 'lock' taken before 'tx_lock'. IRQs must
1911: * be disabled to take 'lock' but only softirq disabling is
1912: * necessary for acquisition of 'tx_lock'.
1913: */
1914: spinlock_t lock;
1915: spinlock_t tx_lock;
1916: #endif
1917:
1918: uint32_t tx_prod;
1919: #if 0
1920: uint32_t tx_cons;
1921: #endif
1922: uint32_t rx_rcb_ptr;
1923: uint32_t rx_std_ptr;
1924: #if 0
1925: uint32_t rx_jumbo_ptr;
1926: spinlock_t indirect_lock;
1927:
1928: struct net_device_stats net_stats;
1929: struct net_device_stats net_stats_prev;
1930: #endif
1931: unsigned long phy_crc_errors;
1932:
1933: #if 0
1934: uint32_t rx_offset;
1935: #endif
1936: uint32_t tg3_flags;
1937: #if 0
1938: #define TG3_FLAG_HOST_TXDS 0x00000001
1939: #endif
1940: #define TG3_FLAG_TXD_MBOX_HWBUG 0x00000002
1941: #define TG3_FLAG_RX_CHECKSUMS 0x00000004
1942: #define TG3_FLAG_USE_LINKCHG_REG 0x00000008
1943: #define TG3_FLAG_USE_MI_INTERRUPT 0x00000010
1944: #define TG3_FLAG_ENABLE_ASF 0x00000020
1945: #define TG3_FLAG_5701_REG_WRITE_BUG 0x00000040
1946: #define TG3_FLAG_POLL_SERDES 0x00000080
1947: #define TG3_FLAG_MBOX_WRITE_REORDER 0x00000100
1948: #define TG3_FLAG_PCIX_TARGET_HWBUG 0x00000200
1949: #define TG3_FLAG_WOL_SPEED_100MB 0x00000400
1950: #define TG3_FLAG_WOL_ENABLE 0x00000800
1951: #define TG3_FLAG_EEPROM_WRITE_PROT 0x00001000
1952: #define TG3_FLAG_NVRAM 0x00002000
1953: #define TG3_FLAG_NVRAM_BUFFERED 0x00004000
1954: #define TG3_FLAG_RX_PAUSE 0x00008000
1955: #define TG3_FLAG_TX_PAUSE 0x00010000
1956: #define TG3_FLAG_PCIX_MODE 0x00020000
1957: #define TG3_FLAG_PCI_HIGH_SPEED 0x00040000
1958: #define TG3_FLAG_PCI_32BIT 0x00080000
1959: #define TG3_FLAG_NO_TX_PSEUDO_CSUM 0x00100000
1960: #define TG3_FLAG_NO_RX_PSEUDO_CSUM 0x00200000
1961: #define TG3_FLAG_SERDES_WOL_CAP 0x00400000
1962: #define TG3_FLAG_JUMBO_ENABLE 0x00800000
1963: #define TG3_FLAG_10_100_ONLY 0x01000000
1964: #define TG3_FLAG_PAUSE_AUTONEG 0x02000000
1965: #define TG3_FLAG_PAUSE_RX 0x04000000
1966: #define TG3_FLAG_PAUSE_TX 0x08000000
1967: #define TG3_FLAG_BROKEN_CHECKSUMS 0x10000000
1968: #define TG3_FLAG_GOT_SERDES_FLOWCTL 0x20000000
1969: #define TG3_FLAG_SPLIT_MODE 0x40000000
1970: #define TG3_FLAG_INIT_COMPLETE 0x80000000
1971:
1972: uint32_t tg3_flags2;
1973: #define TG3_FLG2_RESTART_TIMER 0x00000001
1974: #define TG3_FLG2_SUN_5704 0x00000002
1975: #define TG3_FLG2_NO_ETH_WIRE_SPEED 0x00000004
1976: #define TG3_FLG2_IS_5788 0x00000008
1977: #define TG3_FLG2_MAX_RXPEND_64 0x00000010
1978: #define TG3_FLG2_TSO_CAPABLE 0x00000020
1979: // Alf: Hope I'm not breaking anything here !
1980: #define TG3_FLG2_PCI_EXPRESS 0x00000040
1981:
1982:
1983:
1984: uint32_t split_mode_max_reqs;
1985: #define SPLIT_MODE_5704_MAX_REQ 3
1986:
1987: #if 0
1988: struct timer_list timer;
1989: uint16_t timer_counter;
1990: uint16_t timer_multiplier;
1991: uint32_t timer_offset;
1992: uint16_t asf_counter;
1993: uint16_t asf_multiplier;
1994: #endif
1995:
1996: struct tg3_link_config link_config;
1997: struct tg3_bufmgr_config bufmgr_config;
1998:
1999: #if 0
2000: uint32_t rx_pending;
2001: uint32_t rx_jumbo_pending;
2002: uint32_t tx_pending;
2003: #endif
2004:
2005: /* cache h/w values, often passed straight to h/w */
2006: uint32_t rx_mode;
2007: uint32_t tx_mode;
2008: uint32_t mac_mode;
2009: uint32_t mi_mode;
2010: uint32_t misc_host_ctrl;
2011: uint32_t grc_mode;
2012: uint32_t grc_local_ctrl;
2013: uint32_t dma_rwctrl;
2014: #if 0
2015: uint32_t coalesce_mode;
2016: #endif
2017:
2018: /* PCI block */
2019: uint16_t pci_chip_rev_id;
2020: #if 0
2021: uint8_t pci_cacheline_sz;
2022: uint8_t pci_lat_timer;
2023: uint8_t pci_hdr_type;
2024: uint8_t pci_bist;
2025: #endif
2026: uint32_t pci_cfg_state[64 / sizeof(uint32_t)];
2027:
2028: int pm_cap;
2029:
2030: /* PHY info */
2031: uint32_t phy_id;
2032: #define PHY_ID_MASK 0xfffffff0
2033: #define PHY_ID_BCM5400 0x60008040
2034: #define PHY_ID_BCM5401 0x60008050
2035: #define PHY_ID_BCM5411 0x60008070
2036: #define PHY_ID_BCM5701 0x60008110
2037: #define PHY_ID_BCM5703 0x60008160
2038: #define PHY_ID_BCM5704 0x60008190
2039: #define PHY_ID_BCM5705 0x600081a0
2040: #define PHY_ID_BCM5750 0x60008180
2041: #define PHY_ID_BCM5787 0xbc050ce0
2042: #define PHY_ID_BCM8002 0x60010140
2043: #define PHY_ID_BCM5751 0x00206180
2044: #define PHY_ID_SERDES 0xfeedbee0
2045: #define PHY_ID_INVALID 0xffffffff
2046: #define PHY_ID_REV_MASK 0x0000000f
2047: #define PHY_REV_BCM5401_B0 0x1
2048: #define PHY_REV_BCM5401_B2 0x3
2049: #define PHY_REV_BCM5401_C0 0x6
2050: #define PHY_REV_BCM5411_X0 0x1 /* Found on Netgear GA302T */
2051:
2052: enum phy_led_mode led_mode;
2053:
2054: char board_part_number[24];
2055: uint32_t nic_sram_data_cfg;
2056: uint32_t pci_clock_ctrl;
2057: #if 0
2058: struct pci_device *pdev_peer;
2059: #endif
2060:
2061: /* This macro assumes the passed PHY ID is already masked
2062: * with PHY_ID_MASK.
2063: */
2064: #define KNOWN_PHY_ID(X) \
2065: ((X) == PHY_ID_BCM5400 || (X) == PHY_ID_BCM5401 || \
2066: (X) == PHY_ID_BCM5411 || (X) == PHY_ID_BCM5701 || \
2067: (X) == PHY_ID_BCM5703 || (X) == PHY_ID_BCM5704 || \
2068: (X) == PHY_ID_BCM5705 || (X) == PHY_ID_BCM5750 || \
2069: (X) == PHY_ID_BCM5751 || (X) == PHY_ID_BCM5787 || \
2070: (X) == PHY_ID_BCM8002 || (X) == PHY_ID_SERDES)
2071:
2072: unsigned long regs;
2073: struct pci_device *pdev;
2074: struct nic *nic;
2075: #if 0
2076: struct net_device *dev;
2077: #endif
2078: #if TG3_VLAN_TAG_USED
2079: struct vlan_group *vlgrp;
2080: #endif
2081:
2082: struct tg3_rx_buffer_desc *rx_std;
2083: #if 0
2084: struct ring_info *rx_std_buffers;
2085: dma_addr_t rx_std_mapping;
2086: struct tg3_rx_buffer_desc *rx_jumbo;
2087: struct ring_info *rx_jumbo_buffers;
2088: dma_addr_t rx_jumbo_mapping;
2089: #endif
2090:
2091: struct tg3_rx_buffer_desc *rx_rcb;
2092: #if 0
2093: dma_addr_t rx_rcb_mapping;
2094: #endif
2095:
2096: /* TX descs are only used if TG3_FLAG_HOST_TXDS is set. */
2097: struct tg3_tx_buffer_desc *tx_ring;
2098: #if 0
2099: struct tx_ring_info *tx_buffers;
2100: dma_addr_t tx_desc_mapping;
2101: #endif
2102:
2103: struct tg3_hw_status *hw_status;
2104: #if 0
2105: dma_addr_t status_mapping;
2106: #endif
2107: #if 0
2108: uint32_t msg_enable;
2109: #endif
2110:
2111: struct tg3_hw_stats *hw_stats;
2112: #if 0
2113: dma_addr_t stats_mapping;
2114: #endif
2115:
2116: int carrier_ok;
2117: uint16_t subsystem_vendor;
2118: uint16_t subsystem_device;
2119: };
2120:
2121: #endif /* !(_T3_H) */
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