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1.1 root 1: /*
2: * i82365.h 1.15 1999/10/25 20:03:34
3: *
4: * The contents of this file may be used under the
5: * terms of the GNU General Public License version 2 (the "GPL").
6: *
7: * Software distributed under the License is distributed on an "AS IS"
8: * basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See
9: * the License for the specific language governing rights and
10: * limitations under the License.
11: *
12: * The initial developer of the original code is David A. Hinds
13: * <[email protected]>. Portions created by David A. Hinds
14: * are Copyright (C) 1999 David A. Hinds. All Rights Reserved.
15: */
16:
17: FILE_LICENCE ( GPL2_ONLY );
18:
19: #ifndef _LINUX_I82365_H
20: #define _LINUX_I82365_H
21:
22: /* register definitions for the Intel 82365SL PCMCIA controller */
23:
24: /* Offsets for PCIC registers */
25: #define I365_IDENT 0x00 /* Identification and revision */
26: #define I365_STATUS 0x01 /* Interface status */
27: #define I365_POWER 0x02 /* Power and RESETDRV control */
28: #define I365_INTCTL 0x03 /* Interrupt and general control */
29: #define I365_CSC 0x04 /* Card status change */
30: #define I365_CSCINT 0x05 /* Card status change interrupt control */
31: #define I365_ADDRWIN 0x06 /* Address window enable */
32: #define I365_IOCTL 0x07 /* I/O control */
33: #define I365_GENCTL 0x16 /* Card detect and general control */
34: #define I365_GBLCTL 0x1E /* Global control register */
35:
36: /* Offsets for I/O and memory window registers */
37: #define I365_IO(map) (0x08+((map)<<2))
38: #define I365_MEM(map) (0x10+((map)<<3))
39: #define I365_W_START 0
40: #define I365_W_STOP 2
41: #define I365_W_OFF 4
42:
43: /* Flags for I365_STATUS */
44: #define I365_CS_BVD1 0x01
45: #define I365_CS_STSCHG 0x01
46: #define I365_CS_BVD2 0x02
47: #define I365_CS_SPKR 0x02
48: #define I365_CS_DETECT 0x0C
49: #define I365_CS_WRPROT 0x10
50: #define I365_CS_READY 0x20 /* Inverted */
51: #define I365_CS_POWERON 0x40
52: #define I365_CS_GPI 0x80
53:
54: /* Flags for I365_POWER */
55: #define I365_PWR_OFF 0x00 /* Turn off the socket */
56: #define I365_PWR_OUT 0x80 /* Output enable */
57: #define I365_PWR_NORESET 0x40 /* Disable RESETDRV on resume */
58: #define I365_PWR_AUTO 0x20 /* Auto pwr switch enable */
59: #define I365_VCC_MASK 0x18 /* Mask for turning off Vcc */
60: /* There are different layouts for B-step and DF-step chips: the B
61: step has independent Vpp1/Vpp2 control, and the DF step has only
62: Vpp1 control, plus 3V control */
63: #define I365_VCC_5V 0x10 /* Vcc = 5.0v */
64: #define I365_VCC_3V 0x18 /* Vcc = 3.3v */
65: #define I365_VPP2_MASK 0x0c /* Mask for turning off Vpp2 */
66: #define I365_VPP2_5V 0x04 /* Vpp2 = 5.0v */
67: #define I365_VPP2_12V 0x08 /* Vpp2 = 12.0v */
68: #define I365_VPP1_MASK 0x03 /* Mask for turning off Vpp1 */
69: #define I365_VPP1_5V 0x01 /* Vpp2 = 5.0v */
70: #define I365_VPP1_12V 0x02 /* Vpp2 = 12.0v */
71:
72: /* Flags for I365_INTCTL */
73: #define I365_RING_ENA 0x80
74: #define I365_PC_RESET 0x40
75: #define I365_PC_IOCARD 0x20
76: #define I365_INTR_ENA 0x10
77: #define I365_IRQ_MASK 0x0F
78:
79: /* Flags for I365_CSC and I365_CSCINT*/
80: #define I365_CSC_BVD1 0x01
81: #define I365_CSC_STSCHG 0x01
82: #define I365_CSC_BVD2 0x02
83: #define I365_CSC_READY 0x04
84: #define I365_CSC_DETECT 0x08
85: #define I365_CSC_ANY 0x0F
86: #define I365_CSC_GPI 0x10
87:
88: /* Flags for I365_ADDRWIN */
89: #define I365_ENA_IO(map) (0x40 << (map))
90: #define I365_ENA_MEM(map) (0x01 << (map))
91:
92: /* Flags for I365_IOCTL */
93: #define I365_IOCTL_MASK(map) (0x0F << (map<<2))
94: #define I365_IOCTL_WAIT(map) (0x08 << (map<<2))
95: #define I365_IOCTL_0WS(map) (0x04 << (map<<2))
96: #define I365_IOCTL_IOCS16(map) (0x02 << (map<<2))
97: #define I365_IOCTL_16BIT(map) (0x01 << (map<<2))
98:
99: /* Flags for I365_GENCTL */
100: #define I365_CTL_16DELAY 0x01
101: #define I365_CTL_RESET 0x02
102: #define I365_CTL_GPI_ENA 0x04
103: #define I365_CTL_GPI_CTL 0x08
104: #define I365_CTL_RESUME 0x10
105: #define I365_CTL_SW_IRQ 0x20
106:
107: /* Flags for I365_GBLCTL */
108: #define I365_GBL_PWRDOWN 0x01
109: #define I365_GBL_CSC_LEV 0x02
110: #define I365_GBL_WRBACK 0x04
111: #define I365_GBL_IRQ_0_LEV 0x08
112: #define I365_GBL_IRQ_1_LEV 0x10
113:
114: /* Flags for memory window registers */
115: #define I365_MEM_16BIT 0x8000 /* In memory start high byte */
116: #define I365_MEM_0WS 0x4000
117: #define I365_MEM_WS1 0x8000 /* In memory stop high byte */
118: #define I365_MEM_WS0 0x4000
119: #define I365_MEM_WRPROT 0x8000 /* In offset high byte */
120: #define I365_MEM_REG 0x4000
121:
122: #define I365_REG(slot, reg) (((slot) << 6) + reg)
123:
124: #endif /* _LINUX_I82365_H */
125:
126: //*****************************************************************************
127: //*****************************************************************************
128: //*****************************************************************************
129: //*****************************************************************************
130: //*****************************************************************************
131: // Beginning vg468.h (for VADEM chipset)
132:
133: #ifndef _LINUX_VG468_H
134: #define _LINUX_VG468_H
135:
136: /* Special bit in I365_IDENT used for Vadem chip detection */
137: #define I365_IDENT_VADEM 0x08
138:
139: /* Special definitions in I365_POWER */
140: #define VG468_VPP2_MASK 0x0c
141: #define VG468_VPP2_5V 0x04
142: #define VG468_VPP2_12V 0x08
143:
144: /* Unique Vadem registers */
145: #define VG469_VSENSE 0x1f /* Card voltage sense */
146: #define VG469_VSELECT 0x2f /* Card voltage select */
147: #define VG468_CTL 0x38 /* Control register */
148: #define VG468_TIMER 0x39 /* Timer control */
149: #define VG468_MISC 0x3a /* Miscellaneous */
150: #define VG468_GPIO_CFG 0x3b /* GPIO configuration */
151: #define VG469_EXT_MODE 0x3c /* Extended mode register */
152: #define VG468_SELECT 0x3d /* Programmable chip select */
153: #define VG468_SELECT_CFG 0x3e /* Chip select configuration */
154: #define VG468_ATA 0x3f /* ATA control */
155:
156: /* Flags for VG469_VSENSE */
157: #define VG469_VSENSE_A_VS1 0x01
158: #define VG469_VSENSE_A_VS2 0x02
159: #define VG469_VSENSE_B_VS1 0x04
160: #define VG469_VSENSE_B_VS2 0x08
161:
162: /* Flags for VG469_VSELECT */
163: #define VG469_VSEL_VCC 0x03
164: #define VG469_VSEL_5V 0x00
165: #define VG469_VSEL_3V 0x03
166: #define VG469_VSEL_MAX 0x0c
167: #define VG469_VSEL_EXT_STAT 0x10
168: #define VG469_VSEL_EXT_BUS 0x20
169: #define VG469_VSEL_MIXED 0x40
170: #define VG469_VSEL_ISA 0x80
171:
172: /* Flags for VG468_CTL */
173: #define VG468_CTL_SLOW 0x01 /* 600ns memory timing */
174: #define VG468_CTL_ASYNC 0x02 /* Asynchronous bus clocking */
175: #define VG468_CTL_TSSI 0x08 /* Tri-state some outputs */
176: #define VG468_CTL_DELAY 0x10 /* Card detect debounce */
177: #define VG468_CTL_INPACK 0x20 /* Obey INPACK signal? */
178: #define VG468_CTL_POLARITY 0x40 /* VCCEN polarity */
179: #define VG468_CTL_COMPAT 0x80 /* Compatibility stuff */
180:
181: #define VG469_CTL_WS_COMPAT 0x04 /* Wait state compatibility */
182: #define VG469_CTL_STRETCH 0x10 /* LED stretch */
183:
184: /* Flags for VG468_TIMER */
185: #define VG468_TIMER_ZEROPWR 0x10 /* Zero power control */
186: #define VG468_TIMER_SIGEN 0x20 /* Power up */
187: #define VG468_TIMER_STATUS 0x40 /* Activity timer status */
188: #define VG468_TIMER_RES 0x80 /* Timer resolution */
189: #define VG468_TIMER_MASK 0x0f /* Activity timer timeout */
190:
191: /* Flags for VG468_MISC */
192: #define VG468_MISC_GPIO 0x04 /* General-purpose IO */
193: #define VG468_MISC_DMAWSB 0x08 /* DMA wait state control */
194: #define VG469_MISC_LEDENA 0x10 /* LED enable */
195: #define VG468_MISC_VADEMREV 0x40 /* Vadem revision control */
196: #define VG468_MISC_UNLOCK 0x80 /* Unique register lock */
197:
198: /* Flags for VG469_EXT_MODE_A */
199: #define VG469_MODE_VPPST 0x03 /* Vpp steering control */
200: #define VG469_MODE_INT_SENSE 0x04 /* Internal voltage sense */
201: #define VG469_MODE_CABLE 0x08
202: #define VG469_MODE_COMPAT 0x10 /* i82365sl B or DF step */
203: #define VG469_MODE_TEST 0x20
204: #define VG469_MODE_RIO 0x40 /* Steer RIO to INTR? */
205:
206: /* Flags for VG469_EXT_MODE_B */
207: #define VG469_MODE_B_3V 0x01 /* 3.3v for socket B */
208:
209: #endif /* _LINUX_VG468_H */
210:
211:
212: //*****************************************************************************
213: //*****************************************************************************
214: //*****************************************************************************
215: //*****************************************************************************
216: //*****************************************************************************
217: // Beginning ricoh.h (RICOH chipsets)
218:
219: #ifndef _LINUX_RICOH_H
220: #define _LINUX_RICOH_H
221:
222:
223: #define RF5C_MODE_CTL 0x1f /* Mode control */
224: #define RF5C_PWR_CTL 0x2f /* Mixed voltage control */
225: #define RF5C_CHIP_ID 0x3a /* Chip identification */
226: #define RF5C_MODE_CTL_3 0x3b /* Mode control 3 */
227:
228: /* I/O window address offset */
229: #define RF5C_IO_OFF(w) (0x36+((w)<<1))
230:
231: /* Flags for RF5C_MODE_CTL */
232: #define RF5C_MODE_ATA 0x01 /* ATA mode */
233: #define RF5C_MODE_LED_ENA 0x02 /* IRQ 12 is LED */
234: #define RF5C_MODE_CA21 0x04
235: #define RF5C_MODE_CA22 0x08
236: #define RF5C_MODE_CA23 0x10
237: #define RF5C_MODE_CA24 0x20
238: #define RF5C_MODE_CA25 0x40
239: #define RF5C_MODE_3STATE_BIT7 0x80
240:
241: /* Flags for RF5C_PWR_CTL */
242: #define RF5C_PWR_VCC_3V 0x01
243: #define RF5C_PWR_IREQ_HIGH 0x02
244: #define RF5C_PWR_INPACK_ENA 0x04
245: #define RF5C_PWR_5V_DET 0x08
246: #define RF5C_PWR_TC_SEL 0x10 /* Terminal Count: irq 11 or 15 */
247: #define RF5C_PWR_DREQ_LOW 0x20
248: #define RF5C_PWR_DREQ_OFF 0x00 /* DREQ steering control */
249: #define RF5C_PWR_DREQ_INPACK 0x40
250: #define RF5C_PWR_DREQ_SPKR 0x80
251: #define RF5C_PWR_DREQ_IOIS16 0xc0
252:
253: /* Values for RF5C_CHIP_ID */
254: #define RF5C_CHIP_RF5C296 0x32
255: #define RF5C_CHIP_RF5C396 0xb2
256:
257: /* Flags for RF5C_MODE_CTL_3 */
258: #define RF5C_MCTL3_DISABLE 0x01 /* Disable PCMCIA interface */
259: #define RF5C_MCTL3_DMA_ENA 0x02
260:
261: /* Register definitions for Ricoh PCI-to-CardBus bridges */
262:
263: /* Extra bits in CB_BRIDGE_CONTROL */
264: #define RL5C46X_BCR_3E0_ENA 0x0800
265: #define RL5C46X_BCR_3E2_ENA 0x1000
266:
267: /* Bridge Configuration Register */
268: #define RL5C4XX_CONFIG 0x80 /* 16 bit */
269: #define RL5C4XX_CONFIG_IO_1_MODE 0x0200
270: #define RL5C4XX_CONFIG_IO_0_MODE 0x0100
271: #define RL5C4XX_CONFIG_PREFETCH 0x0001
272:
273:
274: /* Misc Control Register */
275: #define RL5C4XX_MISC 0x0082 /* 16 bit */
276: #define RL5C4XX_MISC_HW_SUSPEND_ENA 0x0002
277: #define RL5C4XX_MISC_VCCEN_POL 0x0100
278: #define RL5C4XX_MISC_VPPEN_POL 0x0200
279: #define RL5C46X_MISC_SUSPEND 0x0001
280: #define RL5C46X_MISC_PWR_SAVE_2 0x0004
281: #define RL5C46X_MISC_IFACE_BUSY 0x0008
282: #define RL5C46X_MISC_B_LOCK 0x0010
283: #define RL5C46X_MISC_A_LOCK 0x0020
284: #define RL5C46X_MISC_PCI_LOCK 0x0040
285: #define RL5C47X_MISC_IFACE_BUSY 0x0004
286: #define RL5C47X_MISC_PCI_INT_MASK 0x0018
287: #define RL5C47X_MISC_PCI_INT_DIS 0x0020
288: #define RL5C47X_MISC_SUBSYS_WR 0x0040
289: #define RL5C47X_MISC_SRIRQ_ENA 0x0080
290: #define RL5C47X_MISC_5V_DISABLE 0x0400
291: #define RL5C47X_MISC_LED_POL 0x0800
292:
293: /* 16-bit Interface Control Register */
294: #define RL5C4XX_16BIT_CTL 0x0084 /* 16 bit */
295: #define RL5C4XX_16CTL_IO_TIMING 0x0100
296: #define RL5C4XX_16CTL_MEM_TIMING 0x0200
297: #define RL5C46X_16CTL_LEVEL_1 0x0010
298: #define RL5C46X_16CTL_LEVEL_2 0x0020
299:
300: /* 16-bit IO and memory timing registers */
301: #define RL5C4XX_16BIT_IO_0 0x0088 /* 16 bit */
302: #define RL5C4XX_16BIT_MEM_0 0x0088 /* 16 bit */
303: #define RL5C4XX_SETUP_MASK 0x0007
304: #define RL5C4XX_SETUP_SHIFT 0
305: #define RL5C4XX_CMD_MASK 0x01f0
306: #define RL5C4XX_CMD_SHIFT 4
307: #define RL5C4XX_HOLD_MASK 0x1c00
308: #define RL5C4XX_HOLD_SHIFT 10
309: #define RL5C4XX_MISC_CONTROL 0x2F /* 8 bit */
310: #define RL5C4XX_ZV_ENABLE 0x08
311:
312: #endif /* _LINUX_RICOH_H */
313:
314:
315: //*****************************************************************************
316: //*****************************************************************************
317: //*****************************************************************************
318: //*****************************************************************************
319: //*****************************************************************************
320: // Beginning cirrus.h (CIRRUS chipsets)
321:
322: #ifndef _LINUX_CIRRUS_H
323: #define _LINUX_CIRRUS_H
324:
325: #ifndef PCI_VENDOR_ID_CIRRUS
326: #define PCI_VENDOR_ID_CIRRUS 0x1013
327: #endif
328: #ifndef PCI_DEVICE_ID_CIRRUS_6729
329: #define PCI_DEVICE_ID_CIRRUS_6729 0x1100
330: #endif
331: #ifndef PCI_DEVICE_ID_CIRRUS_6832
332: #define PCI_DEVICE_ID_CIRRUS_6832 0x1110
333: #endif
334:
335: #define PD67_MISC_CTL_1 0x16 /* Misc control 1 */
336: #define PD67_FIFO_CTL 0x17 /* FIFO control */
337: #define PD67_MISC_CTL_2 0x1E /* Misc control 2 */
338: #define PD67_CHIP_INFO 0x1f /* Chip information */
339: #define PD67_ATA_CTL 0x026 /* 6730: ATA control */
340: #define PD67_EXT_INDEX 0x2e /* Extension index */
341: #define PD67_EXT_DATA 0x2f /* Extension data */
342:
343: /* PD6722 extension registers -- indexed in PD67_EXT_INDEX */
344: #define PD67_DATA_MASK0 0x01 /* Data mask 0 */
345: #define PD67_DATA_MASK1 0x02 /* Data mask 1 */
346: #define PD67_DMA_CTL 0x03 /* DMA control */
347:
348: /* PD6730 extension registers -- indexed in PD67_EXT_INDEX */
349: #define PD67_EXT_CTL_1 0x03 /* Extension control 1 */
350: #define PD67_MEM_PAGE(n) ((n)+5) /* PCI window bits 31:24 */
351: #define PD67_EXTERN_DATA 0x0a
352: #define PD67_MISC_CTL_3 0x25
353: #define PD67_SMB_PWR_CTL 0x26
354:
355: /* I/O window address offset */
356: #define PD67_IO_OFF(w) (0x36+((w)<<1))
357:
358: /* Timing register sets */
359: #define PD67_TIME_SETUP(n) (0x3a + 3*(n))
360: #define PD67_TIME_CMD(n) (0x3b + 3*(n))
361: #define PD67_TIME_RECOV(n) (0x3c + 3*(n))
362:
363: /* Flags for PD67_MISC_CTL_1 */
364: #define PD67_MC1_5V_DET 0x01 /* 5v detect */
365: #define PD67_MC1_MEDIA_ENA 0x01 /* 6730: Multimedia enable */
366: #define PD67_MC1_VCC_3V 0x02 /* 3.3v Vcc */
367: #define PD67_MC1_PULSE_MGMT 0x04
368: #define PD67_MC1_PULSE_IRQ 0x08
369: #define PD67_MC1_SPKR_ENA 0x10
370: #define PD67_MC1_INPACK_ENA 0x80
371:
372: /* Flags for PD67_FIFO_CTL */
373: #define PD67_FIFO_EMPTY 0x80
374:
375: /* Flags for PD67_MISC_CTL_2 */
376: #define PD67_MC2_FREQ_BYPASS 0x01
377: #define PD67_MC2_DYNAMIC_MODE 0x02
378: #define PD67_MC2_SUSPEND 0x04
379: #define PD67_MC2_5V_CORE 0x08
380: #define PD67_MC2_LED_ENA 0x10 /* IRQ 12 is LED enable */
381: #define PD67_MC2_FAST_PCI 0x10 /* 6729: PCI bus > 25 MHz */
382: #define PD67_MC2_3STATE_BIT7 0x20 /* Floppy change bit */
383: #define PD67_MC2_DMA_MODE 0x40
384: #define PD67_MC2_IRQ15_RI 0x80 /* IRQ 15 is ring enable */
385:
386: /* Flags for PD67_CHIP_INFO */
387: #define PD67_INFO_SLOTS 0x20 /* 0 = 1 slot, 1 = 2 slots */
388: #define PD67_INFO_CHIP_ID 0xc0
389: #define PD67_INFO_REV 0x1c
390:
391: /* Fields in PD67_TIME_* registers */
392: #define PD67_TIME_SCALE 0xc0
393: #define PD67_TIME_SCALE_1 0x00
394: #define PD67_TIME_SCALE_16 0x40
395: #define PD67_TIME_SCALE_256 0x80
396: #define PD67_TIME_SCALE_4096 0xc0
397: #define PD67_TIME_MULT 0x3f
398:
399: /* Fields in PD67_DMA_CTL */
400: #define PD67_DMA_MODE 0xc0
401: #define PD67_DMA_OFF 0x00
402: #define PD67_DMA_DREQ_INPACK 0x40
403: #define PD67_DMA_DREQ_WP 0x80
404: #define PD67_DMA_DREQ_BVD2 0xc0
405: #define PD67_DMA_PULLUP 0x20 /* Disable socket pullups? */
406:
407: /* Fields in PD67_EXT_CTL_1 */
408: #define PD67_EC1_VCC_PWR_LOCK 0x01
409: #define PD67_EC1_AUTO_PWR_CLEAR 0x02
410: #define PD67_EC1_LED_ENA 0x04
411: #define PD67_EC1_INV_CARD_IRQ 0x08
412: #define PD67_EC1_INV_MGMT_IRQ 0x10
413: #define PD67_EC1_PULLUP_CTL 0x20
414:
415: /* Fields in PD67_MISC_CTL_3 */
416: #define PD67_MC3_IRQ_MASK 0x03
417: #define PD67_MC3_IRQ_PCPCI 0x00
418: #define PD67_MC3_IRQ_EXTERN 0x01
419: #define PD67_MC3_IRQ_PCIWAY 0x02
420: #define PD67_MC3_IRQ_PCI 0x03
421: #define PD67_MC3_PWR_MASK 0x0c
422: #define PD67_MC3_PWR_SERIAL 0x00
423: #define PD67_MC3_PWR_TI2202 0x08
424: #define PD67_MC3_PWR_SMB 0x0c
425:
426: /* Register definitions for Cirrus PD6832 PCI-to-CardBus bridge */
427:
428: /* PD6832 extension registers -- indexed in PD67_EXT_INDEX */
429: #define PD68_EXT_CTL_2 0x0b
430: #define PD68_PCI_SPACE 0x22
431: #define PD68_PCCARD_SPACE 0x23
432: #define PD68_WINDOW_TYPE 0x24
433: #define PD68_EXT_CSC 0x2e
434: #define PD68_MISC_CTL_4 0x2f
435: #define PD68_MISC_CTL_5 0x30
436: #define PD68_MISC_CTL_6 0x31
437:
438: /* Extra flags in PD67_MISC_CTL_3 */
439: #define PD68_MC3_HW_SUSP 0x10
440: #define PD68_MC3_MM_EXPAND 0x40
441: #define PD68_MC3_MM_ARM 0x80
442:
443: /* Bridge Control Register */
444: #define PD6832_BCR_MGMT_IRQ_ENA 0x0800
445:
446: /* Socket Number Register */
447: #define PD6832_SOCKET_NUMBER 0x004c /* 8 bit */
448:
449: #endif /* _LINUX_CIRRUS_H */
450:
451:
452:
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