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Annotation of qemu/roms/openbios/arch/ppc/misc.S, revision 1.1.1.1

1.1       root        1: /*
                      2:  *   Creation Date: <2002/10/20 15:54:50 samuel>
                      3:  *   Time-stamp: <2002/10/20 15:57:21 samuel>
                      4:  *
                      5:  *     <misc.S>
                      6:  *
                      7:  *     Low-level stuff
                      8:  *
                      9:  *   Copyright (C) 2002, 2003 Samuel Rydh ([email protected])
                     10:  *
                     11:  *   Based upon misc.S from the the linux kernel with the following
                     12:  *   copyrights:
                     13:  *
                     14:  *   Copyright (C) 1995-1996 Gary Thomas ([email protected]),
                     15:  *   Cort Dougan ([email protected]), Paul Mackerras
                     16:  *
                     17:  *   This program is free software; you can redistribute it and/or
                     18:  *   modify it under the terms of the GNU General Public License
                     19:  *   as published by the Free Software Foundation
                     20:  *
                     21:  */
                     22: 
                     23: #include "asm/asmdefs.h"
                     24: #include "asm/processor.h"
                     25: 
                     26: 
                     27: /*
                     28:  * Extended precision shifts.
                     29:  *
                     30:  * Updated to be valid for shift counts from 0 to 63 inclusive.
                     31:  * -- Gabriel
                     32:  *
                     33:  * R3/R4 has 64 bit value
                     34:  * R5    has shift count
                     35:  * result in R3/R4
                     36:  *
                     37:  *  ashrdi3: arithmetic right shift (sign propagation)
                     38:  *  lshrdi3: logical right shift
                     39:  *  ashldi3: left shift
                     40:  */
                     41: GLOBL(__ashrdi3):
                     42:        subfic  r6,r5,32
                     43:        srw     r4,r4,r5        # LSW = count > 31 ? 0 : LSW >> count
                     44:        addi    r7,r5,32        # could be xori, or addi with -32
                     45:        slw     r6,r3,r6        # t1 = count > 31 ? 0 : MSW << (32-count)
                     46:        rlwinm  r8,r7,0,32      # t3 = (count < 32) ? 32 : 0
                     47:        sraw    r7,r3,r7        # t2 = MSW >> (count-32)
                     48:        or      r4,r4,r6        # LSW |= t1
                     49:        slw     r7,r7,r8        # t2 = (count < 32) ? 0 : t2
                     50:        sraw    r3,r3,r5        # MSW = MSW >> count
                     51:        or      r4,r4,r7        # LSW |= t2
                     52:        blr
                     53: 
                     54: GLOBL(__ashldi3):
                     55:        subfic  r6,r5,32
                     56:        slw     r3,r3,r5        # MSW = count > 31 ? 0 : MSW << count
                     57:        addi    r7,r5,32        # could be xori, or addi with -32
                     58:        srw     r6,r4,r6        # t1 = count > 31 ? 0 : LSW >> (32-count)
                     59:        slw     r7,r4,r7        # t2 = count < 32 ? 0 : LSW << (count-32)
                     60:        or      r3,r3,r6        # MSW |= t1
                     61:        slw     r4,r4,r5        # LSW = LSW << count
                     62:        or      r3,r3,r7        # MSW |= t2
                     63:        blr
                     64: 
                     65: GLOBL(__lshrdi3):
                     66:        subfic  r6,r5,32
                     67:        srw     r4,r4,r5        # LSW = count > 31 ? 0 : LSW >> count
                     68:        addi    r7,r5,32        # could be xori, or addi with -32
                     69:        slw     r6,r3,r6        # t1 = count > 31 ? 0 : MSW << (32-count)
                     70:        srw     r7,r3,r7        # t2 = count < 32 ? 0 : MSW >> (count-32)
                     71:        or      r4,r4,r6        # LSW |= t1
                     72:        srw     r3,r3,r5        # MSW = MSW >> count
                     73:        or      r4,r4,r7        # LSW |= t2
                     74:        blr

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