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1.1 root 1: /* iommu.h: Definitions for the sun4m IOMMU.
2: *
3: * Copyright (C) 1996 David S. Miller ([email protected])
4: * Adapted for Proll by Pete Zaitcev in 1999 (== made worse than original).
5: */
6:
7: /* #include <asm/page.h> */
8:
9: /* The iommu handles all virtual to physical address translations
10: * that occur between the SBUS and physical memory. Access by
11: * the cpu to IO registers and similar go over the mbus so are
12: * translated by the on chip SRMMU. The iommu and the srmmu do
13: * not need to have the same translations at all, in fact most
14: * of the time the translations they handle are a disjunct set.
15: * Basically the iommu handles all dvma sbus activity.
16: */
17:
18: /* The IOMMU registers occupy three pages in IO space. */
19: struct iommu_regs {
20: /* First page */
21: volatile unsigned long control; /* IOMMU control */
22: volatile unsigned long base; /* Physical base of iopte page table */
23: volatile unsigned long _unused1[3];
24: volatile unsigned long tlbflush; /* write only */
25: volatile unsigned long pageflush; /* write only */
26: volatile unsigned long _unused2[1017];
27: /* Second page */
28: volatile unsigned long afsr; /* Async-fault status register */
29: volatile unsigned long afar; /* Async-fault physical address */
30: volatile unsigned long _unused3[2];
31: volatile unsigned long sbuscfg0; /* SBUS configuration registers, per-slot */
32: volatile unsigned long sbuscfg1;
33: volatile unsigned long sbuscfg2;
34: volatile unsigned long sbuscfg3;
35: volatile unsigned long mfsr; /* Memory-fault status register */
36: volatile unsigned long mfar; /* Memory-fault physical address */
37: volatile unsigned long _unused4[1014];
38: /* Third page */
39: volatile unsigned long mid; /* IOMMU module-id */
40: };
41:
42: #define IOMMU_CTRL_IMPL 0xf0000000 /* Implementation */
43: #define IOMMU_CTRL_VERS 0x0f000000 /* Version */
44: #define IOMMU_CTRL_RNGE 0x0000001c /* Mapping RANGE */
45: #define IOMMU_RNGE_16MB 0x00000000 /* 0xff000000 -> 0xffffffff */
46: #define IOMMU_RNGE_32MB 0x00000004 /* 0xfe000000 -> 0xffffffff */
47: #define IOMMU_RNGE_64MB 0x00000008 /* 0xfc000000 -> 0xffffffff */
48: #define IOMMU_RNGE_128MB 0x0000000c /* 0xf8000000 -> 0xffffffff */
49: #define IOMMU_RNGE_256MB 0x00000010 /* 0xf0000000 -> 0xffffffff */
50: #define IOMMU_RNGE_512MB 0x00000014 /* 0xe0000000 -> 0xffffffff */
51: #define IOMMU_RNGE_1GB 0x00000018 /* 0xc0000000 -> 0xffffffff */
52: #define IOMMU_RNGE_2GB 0x0000001c /* 0x80000000 -> 0xffffffff */
53: #define IOMMU_CTRL_ENAB 0x00000001 /* IOMMU Enable */
54:
55: #define IOMMU_AFSR_ERR 0x80000000 /* LE, TO, or BE asserted */
56: #define IOMMU_AFSR_LE 0x40000000 /* SBUS reports error after transaction */
57: #define IOMMU_AFSR_TO 0x20000000 /* Write access took more than 12.8 us. */
58: #define IOMMU_AFSR_BE 0x10000000 /* Write access received error acknowledge */
59: #define IOMMU_AFSR_SIZE 0x0e000000 /* Size of transaction causing error */
60: #define IOMMU_AFSR_S 0x01000000 /* Sparc was in supervisor mode */
61: #define IOMMU_AFSR_RESV 0x00f00000 /* Reserver, forced to 0x8 by hardware */
62: #define IOMMU_AFSR_ME 0x00080000 /* Multiple errors occurred */
63: #define IOMMU_AFSR_RD 0x00040000 /* A read operation was in progress */
64: #define IOMMU_AFSR_FAV 0x00020000 /* IOMMU afar has valid contents */
65:
66: #define IOMMU_SBCFG_SAB30 0x00010000 /* Phys-address bit 30 when bypass enabled */
67: #define IOMMU_SBCFG_BA16 0x00000004 /* Slave supports 16 byte bursts */
68: #define IOMMU_SBCFG_BA8 0x00000002 /* Slave supports 8 byte bursts */
69: #define IOMMU_SBCFG_BYPASS 0x00000001 /* Bypass IOMMU, treat all addresses
70: produced by this device as pure
71: physical. */
72:
73: #define IOMMU_MFSR_ERR 0x80000000 /* One or more of PERR1 or PERR0 */
74: #define IOMMU_MFSR_S 0x01000000 /* Sparc was in supervisor mode */
75: #define IOMMU_MFSR_CPU 0x00800000 /* CPU transaction caused parity error */
76: #define IOMMU_MFSR_ME 0x00080000 /* Multiple parity errors occurred */
77: #define IOMMU_MFSR_PERR 0x00006000 /* high bit indicates parity error occurred
78: on the even word of the access, low bit
79: indicated odd word caused the parity error */
80: #define IOMMU_MFSR_BM 0x00001000 /* Error occurred while in boot mode */
81: #define IOMMU_MFSR_C 0x00000800 /* Address causing error was marked cacheable */
82: #define IOMMU_MFSR_RTYP 0x000000f0 /* Memory request transaction type */
83:
84: #define IOMMU_MID_SBAE 0x001f0000 /* SBus arbitration enable */
85: #define IOMMU_MID_SE 0x00100000 /* Enables SCSI/ETHERNET arbitration */
86: #define IOMMU_MID_SB3 0x00080000 /* Enable SBUS device 3 arbitration */
87: #define IOMMU_MID_SB2 0x00040000 /* Enable SBUS device 2 arbitration */
88: #define IOMMU_MID_SB1 0x00020000 /* Enable SBUS device 1 arbitration */
89: #define IOMMU_MID_SB0 0x00010000 /* Enable SBUS device 0 arbitration */
90: #define IOMMU_MID_MID 0x0000000f /* Module-id, hardcoded to 0x8 */
91:
92: /* The format of an iopte in the page tables */
93: #define IOPTE_PAGE 0x07ffff00 /* Physical page number (PA[30:12]) */
94: #define IOPTE_CACHE 0x00000080 /* Cached (in vme IOCACHE or Viking/MXCC) */
95: #define IOPTE_WRITE 0x00000004 /* Writeable */
96: #define IOPTE_VALID 0x00000002 /* IOPTE is valid */
97: #define IOPTE_WAZ 0x00000001 /* Write as zeros */
98:
99: #define IOPERM (IOPTE_CACHE | IOPTE_WRITE | IOPTE_VALID)
100: #define MKIOPTE(phys) (((((phys)>>4) & IOPTE_PAGE) | IOPERM) & ~IOPTE_WAZ)
101:
102: #define IOMMU_REGS 0x300
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