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Annotation of qemu/roms/openbios/drivers/obio.h, revision 1.1

1.1     ! root        1: /* Addresses, interrupt numbers, register sizes */
        !             2: 
        !             3: #define SLAVIO_ZS        0x00000000ULL
        !             4: #define SLAVIO_ZS1       0x00100000ULL
        !             5: #define ZS_INTR          0x2c
        !             6: 
        !             7: #define SLAVIO_NVRAM     0x00200000ULL
        !             8: #define NVRAM_SIZE       0x2000
        !             9: #define NVRAM_IDPROM     0x1fd8
        !            10: 
        !            11: #define SLAVIO_FD        0x00400000ULL
        !            12: #define FD_REGS          15
        !            13: #define FD_INTR          0x2b
        !            14: 
        !            15: #define SLAVIO_SCONFIG   0x00800000ULL
        !            16: #define SCONFIG_REGS     1
        !            17: 
        !            18: #define AUXIO_REGS       1
        !            19: 
        !            20: #define AUXIO2_REGS      1
        !            21: #define AUXIO2_INTR      0x22
        !            22: 
        !            23: #define SLAVIO_COUNTER   0x00d00000ULL
        !            24: #define COUNTER_REGS     0x10
        !            25: 
        !            26: #define SLAVIO_INTERRUPT 0x00e00000ULL
        !            27: #define INTERRUPT_REGS   0x10
        !            28: 
        !            29: #define SLAVIO_RESET     0x00f00000ULL
        !            30: #define RESET_REGS       1
        !            31: 
        !            32: #define ECC_BASE         0xf00000000ULL
        !            33: #define ECC_SIZE         0x20
        !            34: 
        !            35: #define SLAVIO_SIZE      0x01000000
        !            36: 
        !            37: #define SUN4M_NCPUS      16
        !            38: 
        !            39: #define CFG_ADDR         0xd00000510ULL
        !            40: #define CFG_SIZE         3
        !            41: 
        !            42: /* linux/include/asm-sparc/timer.h */
        !            43: 
        !            44: /* A sun4m has two blocks of registers which are probably of the same
        !            45:  * structure. LSI Logic's L64851 is told to _decrement_ from the limit
        !            46:  * value. Aurora behaves similarly but its limit value is compacted in
        !            47:  * other fashion (it's wider). Documented fields are defined here.
        !            48:  */
        !            49: 
        !            50: /* As with the interrupt register, we have two classes of timer registers
        !            51:  * which are per-cpu and master.  Per-cpu timers only hit that cpu and are
        !            52:  * only level 14 ticks, master timer hits all cpus and is level 10.
        !            53:  */
        !            54: 
        !            55: #define SUN4M_PRM_CNT_L       0x80000000
        !            56: #define SUN4M_PRM_CNT_LVALUE  0x7FFFFC00
        !            57: 
        !            58: struct sun4m_timer_percpu_info {
        !            59:   __volatile__ unsigned int l14_timer_limit;    /* Initial value is 0x009c4000 */
        !            60:   __volatile__ unsigned int l14_cur_count;
        !            61: 
        !            62:   /* This register appears to be write only and/or inaccessible
        !            63:    * on Uni-Processor sun4m machines.
        !            64:    */
        !            65:   __volatile__ unsigned int l14_limit_noclear;  /* Data access error is here */
        !            66: 
        !            67:   __volatile__ unsigned int cntrl;            /* =1 after POST on Aurora */
        !            68:   __volatile__ unsigned char space[PAGE_SIZE - 16];
        !            69: };
        !            70: 
        !            71: struct sun4m_timer_regs {
        !            72:        struct sun4m_timer_percpu_info cpu_timers[SUN4M_NCPUS];
        !            73:        volatile unsigned int l10_timer_limit;
        !            74:        volatile unsigned int l10_cur_count;
        !            75: 
        !            76:        /* Again, this appears to be write only and/or inaccessible
        !            77:         * on uni-processor sun4m machines.
        !            78:         */
        !            79:        volatile unsigned int l10_limit_noclear;
        !            80: 
        !            81:        /* This register too, it must be magic. */
        !            82:        volatile unsigned int foobar;
        !            83: 
        !            84:        volatile unsigned int cfg;     /* equals zero at boot time... */
        !            85: };
        !            86: 
        !            87: /*
        !            88:  * Registers of hardware timer in sun4m.
        !            89:  */
        !            90: struct sun4m_timer_percpu {
        !            91:     volatile unsigned int l14_timer_limit; /* Initial value is 0x009c4000 */
        !            92:     volatile unsigned int l14_cur_count;
        !            93: };
        !            94: 
        !            95: struct sun4m_timer_global {
        !            96:     volatile unsigned int l10_timer_limit;
        !            97:     volatile unsigned int l10_cur_count;
        !            98: };
        !            99: 
        !           100: /* linux/include/asm-sparc/irq.h */
        !           101: 
        !           102: /* These registers are used for sending/receiving irqs from/to
        !           103:  * different cpu's.
        !           104:  */
        !           105: struct sun4m_intreg_percpu {
        !           106:     unsigned int tbt;        /* Interrupts still pending for this cpu. */
        !           107: 
        !           108:     /* These next two registers are WRITE-ONLY and are only
        !           109:      * "on bit" sensitive, "off bits" written have NO affect.
        !           110:      */
        !           111:     unsigned int clear;  /* Clear this cpus irqs here. */
        !           112:     unsigned int set;    /* Set this cpus irqs here. */
        !           113:     unsigned char space[PAGE_SIZE - 12];
        !           114: };
        !           115: 
        !           116: /*
        !           117:  * djhr
        !           118:  * Actually the clear and set fields in this struct are misleading..
        !           119:  * according to the SLAVIO manual (and the same applies for the SEC)
        !           120:  * the clear field clears bits in the mask which will ENABLE that IRQ
        !           121:  * the set field sets bits in the mask to DISABLE the IRQ.
        !           122:  *
        !           123:  * Also the undirected_xx address in the SLAVIO is defined as
        !           124:  * RESERVED and write only..
        !           125:  *
        !           126:  * DAVEM_NOTE: The SLAVIO only specifies behavior on uniprocessor
        !           127:  *             sun4m machines, for MP the layout makes more sense.
        !           128:  */
        !           129: struct sun4m_intregs {
        !           130:     struct sun4m_intreg_percpu cpu_intregs[SUN4M_NCPUS];
        !           131:     unsigned int tbt;                /* IRQ's that are still pending. */
        !           132:     unsigned int irqs;               /* Master IRQ bits. */
        !           133: 
        !           134:     /* Again, like the above, two these registers are WRITE-ONLY. */
        !           135:     unsigned int clear;              /* Clear master IRQ's by setting bits here. */
        !           136:     unsigned int set;                /* Set master IRQ's by setting bits here. */
        !           137: 
        !           138:     /* This register is both READ and WRITE. */
        !           139:     unsigned int undirected_target;  /* Which cpu gets undirected irqs. */
        !           140: };
        !           141: 
        !           142: /* Dave Redman ([email protected])
        !           143:  * The sun4m interrupt registers.
        !           144:  */
        !           145: #define SUN4M_INT_ENABLE       0x80000000
        !           146: #define SUN4M_INT_E14          0x00000080
        !           147: #define SUN4M_INT_E10          0x00080000
        !           148: 
        !           149: #define SUN4M_HARD_INT(x)      (0x000000001 << (x))
        !           150: #define SUN4M_SOFT_INT(x)      (0x000010000 << (x))
        !           151: 
        !           152: #define        SUN4M_INT_MASKALL       0x80000000        /* mask all interrupts */
        !           153: #define        SUN4M_INT_MODULE_ERR    0x40000000        /* module error */
        !           154: #define        SUN4M_INT_M2S_WRITE     0x20000000        /* write buffer error */
        !           155: #define        SUN4M_INT_ECC           0x10000000        /* ecc memory error */
        !           156: #define        SUN4M_INT_FLOPPY        0x00400000        /* floppy disk */
        !           157: #define        SUN4M_INT_MODULE        0x00200000        /* module interrupt */
        !           158: #define        SUN4M_INT_VIDEO         0x00100000        /* onboard video */
        !           159: #define        SUN4M_INT_REALTIME      0x00080000        /* system timer */
        !           160: #define        SUN4M_INT_SCSI          0x00040000        /* onboard scsi */
        !           161: #define        SUN4M_INT_AUDIO         0x00020000        /* audio/isdn */
        !           162: #define        SUN4M_INT_ETHERNET      0x00010000        /* onboard ethernet */
        !           163: #define        SUN4M_INT_SERIAL        0x00008000        /* serial ports */
        !           164: #define        SUN4M_INT_KBDMS         0x00004000        /* keyboard/mouse */
        !           165: #define        SUN4M_INT_SBUSBITS      0x00003F80        /* sbus int bits */

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