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Annotation of qemu/roms/openbios/include/arch/ppc/pci.h, revision 1.1.1.1

1.1       root        1: #ifndef PPC_PCI_H
                      2: #define PPC_PCI_H
                      3: 
                      4: #include "asm/io.h"
                      5: 
                      6: #if !(defined(PCI_CONFIG_1) || defined(PCI_CONFIG_2))
                      7: #define PCI_CONFIG_1 1 /* default */
                      8: #endif
                      9: 
                     10: #ifdef PCI_CONFIG_1
                     11: 
                     12: /* PCI Configuration Mechanism #1 */
                     13: 
                     14: #define PCI_ADDR(bus, dev, fn) \
                     15:     ((pci_addr) (arch->cfg_base \
                     16:                | (uint32_t) (bus) << 16 \
                     17:                | (uint32_t) (dev) << 11 \
                     18:                | (uint32_t) (fn) << 8))
                     19: 
                     20: #define PCI_BUS(pcidev) ((uint8_t) ((pcidev) >> 16))
                     21: #define PCI_DEV(pcidev) ((uint8_t) ((pcidev) >> 11) & 0x1f)
                     22: #define PCI_FN(pcidev) ((uint8_t) ((pcidev) >> 8) & 7)
                     23: 
                     24: static inline uint8_t pci_config_read8(pci_addr dev, uint8_t reg)
                     25: {
                     26:        uint8_t res;
                     27:        out_le32((unsigned *)arch->cfg_addr, dev | (reg & ~3));
                     28:        res = in_8((unsigned char*)(arch->cfg_data + (reg & 3)));
                     29:        return res;
                     30: }
                     31: 
                     32: static inline uint16_t pci_config_read16(pci_addr dev, uint8_t reg)
                     33: {
                     34:        uint16_t res;
                     35:        out_le32((unsigned *)arch->cfg_addr, dev | (reg & ~3));
                     36:        res = in_le16((unsigned short*)(arch->cfg_data + (reg & 2)));
                     37:        return res;
                     38: }
                     39: 
                     40: static inline uint32_t pci_config_read32(pci_addr dev, uint8_t reg)
                     41: {
                     42:        uint32_t res;
                     43:        out_le32((unsigned *)arch->cfg_addr, dev | reg);
                     44:        res = in_le32((unsigned *)(arch->cfg_data + reg));
                     45:        return res;
                     46: }
                     47: 
                     48: static inline void pci_config_write8(pci_addr dev, uint8_t reg, uint8_t val)
                     49: {
                     50:        out_le32((unsigned *)arch->cfg_addr, dev | (reg & ~3));
                     51:        out_8((unsigned char*)(arch->cfg_data + (reg & 3)), val);
                     52: }
                     53: 
                     54: static inline void pci_config_write16(pci_addr dev, uint8_t reg, uint16_t val)
                     55: {
                     56:        out_le32((unsigned *)arch->cfg_addr, dev | (reg & ~3));
                     57:        out_le16((unsigned short *)(arch->cfg_data + (reg & 2)), val);
                     58: }
                     59: 
                     60: static inline void pci_config_write32(pci_addr dev, uint8_t reg, uint32_t val)
                     61: {
                     62:        out_le32((unsigned *)arch->cfg_addr, dev | reg);
                     63:        out_le32((unsigned *)(arch->cfg_data + reg), val);
                     64: }
                     65: #else /* !PCI_CONFIG_1 */
                     66: #error PCI Configuration Mechanism is not specified or implemented
                     67: #endif
                     68: 
                     69: #endif /* PPC_PCI_H */

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