![[BACK]](/cvsweb/icons/back.gif){kind=icon}
Return to pci.h CVS log ![[TXT]](/cvsweb/icons/text.gif){kind=icon}
![[DIR]](/cvsweb/icons/dir.gif){kind=icon}
Up to [Qemu by Fabrice Bellard] / qemu / roms / openbios / include / drivers|
Return to pci.h CVS log | Up to [Qemu by Fabrice Bellard] / qemu / roms / openbios / include / drivers |
1.1 root 1: #ifndef _H_PCI
2: #define _H_PCI
3:
4: typedef uint32_t pci_addr;
5:
6: typedef struct pci_arch_t pci_arch_t;
7:
8: struct pci_arch_t {
9: const char * name;
10: uint16_t vendor_id;
11: uint16_t device_id;
12: unsigned long cfg_addr;
13: unsigned long cfg_data;
14: unsigned long cfg_base;
15: unsigned long cfg_len;
16: unsigned long host_mem_base; /* in host memory space */
17: unsigned long pci_mem_base; /* in PCI memory space */
18: unsigned long mem_len;
19: unsigned long io_base;
20: unsigned long io_len;
21: unsigned long rbase;
22: unsigned long rlen;
23: uint8_t irqs[4];
24: };
25:
26: extern const pci_arch_t *arch;
27:
28: /* Device tree offsets */
29:
30: #define PCI_INT_MAP_PCI0 0
31: #define PCI_INT_MAP_PCI1 1
32: #define PCI_INT_MAP_PCI2 2
33: #define PCI_INT_MAP_PCI_INT 3
34: #define PCI_INT_MAP_PIC_HANDLE 4
35: #define PCI_INT_MAP_PIC_INT 5
36: #define PCI_INT_MAP_PIC_POL 6
37:
38: /* Device classes and subclasses */
39:
40: #define PCI_BASE_CLASS_STORAGE 0x01
41: #define PCI_SUBCLASS_STORAGE_SCSI 0x00
42: #define PCI_SUBCLASS_STORAGE_IDE 0x01
43: #define PCI_SUBCLASS_STORAGE_FLOPPY 0x02
44: #define PCI_SUBCLASS_STORAGE_IPI 0x03
45: #define PCI_SUBCLASS_STORAGE_RAID 0x04
46: #define PCI_SUBCLASS_STORAGE_ATA 0x05
47: #define PCI_SUBCLASS_STORAGE_SAS 0x07
48: #define PCI_SUBCLASS_STORAGE_OTHER 0x80
49:
50: #define PCI_BASE_CLASS_NETWORK 0x02
51: #define PCI_SUBCLASS_NETWORK_ETHERNET 0x00
52: #define PCI_SUBCLASS_NETWORK_TOKEN_RING 0x01
53: #define PCI_SUBCLASS_NETWORK_FDDI 0x02
54: #define PCI_SUBCLASS_NETWORK_ATM 0x03
55: #define PCI_SUBCLASS_NETWORK_ISDN 0x04
56: #define PCI_SUBCLASS_NETWORK_WORDFIP 0x05
57: #define PCI_SUBCLASS_NETWORK_PICMG214 0x06
58: #define PCI_SUBCLASS_NETWORK_OTHER 0x80
59:
60: #define PCI_BASE_CLASS_DISPLAY 0x03
61: #define PCI_SUBCLASS_DISPLAY_VGA 0x00
62: #define PCI_SUBCLASS_DISPLAY_XGA 0x01
63: #define PCI_SUBCLASS_DISPLAY_3D 0x02
64: #define PCI_SUBCLASS_DISPLAY_OTHER 0x80
65:
66: #define PCI_BASE_CLASS_MULTIMEDIA 0x04
67: #define PCI_SUBCLASS_MULTIMEDIA_VIDEO 0x00
68: #define PCI_SUBCLASS_MULTIMEDIA_AUDIO 0x01
69: #define PCI_SUBCLASS_MULTIMEDIA_PHONE 0x02
70: #define PCI_SUBCLASS_MULTIMEDIA_OTHER 0x80
71:
72: #define PCI_BASE_CLASS_MEMORY 0x05
73: #define PCI_SUBCLASS_MEMORY_RAM 0x00
74: #define PCI_SUBCLASS_MEMORY_FLASH 0x01
75:
76: #define PCI_BASE_CLASS_BRIDGE 0x06
77: #define PCI_SUBCLASS_BRIDGE_HOST 0x00
78: #define PCI_SUBCLASS_BRIDGE_ISA 0x01
79: #define PCI_SUBCLASS_BRIDGE_EISA 0x02
80: #define PCI_SUBCLASS_BRIDGE_MC 0x03
81: #define PCI_SUBCLASS_BRIDGE_PCI 0x04
82: #define PCI_SUBCLASS_BRIDGE_PCMCIA 0x05
83: #define PCI_SUBCLASS_BRIDGE_NUBUS 0x06
84: #define PCI_SUBCLASS_BRIDGE_CARDBUS 0x07
85: #define PCI_SUBCLASS_BRIDGE_RACEWAY 0x08
86: #define PCI_SUBCLASS_BRIDGE_PCI_SEMITP 0x09
87: #define PCI_SUBCLASS_BRIDGE_IB_PCI 0x0a
88: #define PCI_SUBCLASS_BRIDGE_OTHER 0x80
89:
90: #define PCI_BASE_CLASS_COMMUNICATION 0x07
91: #define PCI_SUBCLASS_COMMUNICATION_SERIAL 0x00
92: #define PCI_SUBCLASS_COMMUNICATION_PARALLEL 0x01
93: #define PCI_SUBCLASS_COMMUNICATION_MULTISERIAL 0x02
94: #define PCI_SUBCLASS_COMMUNICATION_MODEM 0x03
95: #define PCI_SUBCLASS_COMMUNICATION_GPIB 0x04
96: #define PCI_SUBCLASS_COMMUNICATION_SC 0x05
97: #define PCI_SUBCLASS_COMMUNICATION_OTHER 0x80
98:
99: #define PCI_BASE_CLASS_SYSTEM 0x08
100: #define PCI_SUBCLASS_SYSTEM_PIC 0x00
101: #define PCI_SUBCLASS_SYSTEM_DMA 0x01
102: #define PCI_SUBCLASS_SYSTEM_TIMER 0x02
103: #define PCI_SUBCLASS_SYSTEM_RTC 0x03
104: #define PCI_SUBCLASS_SYSTEM_PCI_HOTPLUG 0x04
105: #define PCI_SUBCLASS_SYSTEM_OTHER 0x80
106:
107: #define PCI_BASE_CLASS_INPUT 0x09
108: #define PCI_SUBCLASS_INPUT_KEYBOARD 0x00
109: #define PCI_SUBCLASS_INPUT_PEN 0x01
110: #define PCI_SUBCLASS_INPUT_MOUSE 0x02
111: #define PCI_SUBCLASS_INPUT_SCANNER 0x03
112: #define PCI_SUBCLASS_INPUT_GAMEPORT 0x04
113: #define PCI_SUBCLASS_INPUT_OTHER 0x80
114:
115: #define PCI_BASE_CLASS_DOCKING 0x0a
116: #define PCI_SUBCLASS_DOCKING_GENERIC 0x00
117: #define PCI_SUBCLASS_DOCKING_OTHER 0x80
118:
119: #define PCI_BASE_CLASS_PROCESSOR 0x0b
120: #define PCI_SUBCLASS_PROCESSOR_386 0x00
121: #define PCI_SUBCLASS_PROCESSOR_486 0x01
122: #define PCI_SUBCLASS_PROCESSOR_PENTIUM 0x02
123: #define PCI_SUBCLASS_PROCESSOR_ALPHA 0x10
124: #define PCI_SUBCLASS_PROCESSOR_POWERPC 0x20
125: #define PCI_SUBCLASS_PROCESSOR_MIPS 0x30
126: #define PCI_SUBCLASS_PROCESSOR_CO 0x40
127:
128: #define PCI_BASE_CLASS_SERIAL 0x0c
129: #define PCI_SUBCLASS_SERIAL_FIREWIRE 0x00
130: #define PCI_SUBCLASS_SERIAL_ACCESS 0x01
131: #define PCI_SUBCLASS_SERIAL_SSA 0x02
132: #define PCI_SUBCLASS_SERIAL_USB 0x03
133: #define PCI_SUBCLASS_SERIAL_FIBER 0x04
134: #define PCI_SUBCLASS_SERIAL_SMBUS 0x05
135: #define PCI_SUBCLASS_SERIAL_IB 0x06
136: #define PCI_SUBCLASS_SERIAL_IPMI 0x07
137: #define PCI_SUBCLASS_SERIAL_SERCOS 0x08
138: #define PCI_SUBCLASS_SERIAL_CANBUS 0x09
139:
140: #define PCI_BASE_CLASS_WIRELESS 0x0d
141: #define PCI_SUBCLASS_WIRELESS_IRDA 0x00
142: #define PCI_SUBCLASS_WIRELESS_CIR 0x01
143: #define PCI_SUBCLASS_WIRELESS_RF_CONTROLLER 0x10
144: #define PCI_SUBCLASS_WIRELESS_BLUETOOTH 0x11
145: #define PCI_SUBCLASS_WIRELESS_BROADBAND 0x12
146: #define PCI_SUBCLASS_WIRELESS_OTHER 0x80
147:
148: #define PCI_BASE_CLASS_SATELLITE 0x0f
149: #define PCI_SUBCLASS_SATELLITE_TV 0x00
150: #define PCI_SUBCLASS_SATELLITE_AUDIO 0x01
151: #define PCI_SUBCLASS_SATELLITE_VOICE 0x03
152: #define PCI_SUBCLASS_SATELLITE_DATA 0x04
153:
154: #define PCI_BASE_CLASS_CRYPT 0x10
155: #define PCI_SUBCLASS_CRYPT_NETWORK 0x00
156: #define PCI_SUBCLASS_CRYPT_ENTERTAINMENT 0x01
157: #define PCI_SUBCLASS_CRYPT_OTHER 0x80
158:
159: #define PCI_BASE_CLASS_SIGNAL_PROCESSING 0x11
160: #define PCI_SUBCLASS_SP_DPIO 0x00
161: #define PCI_SUBCLASS_SP_PERF 0x01
162: #define PCI_SUBCLASS_SP_SYNCH 0x10
163: #define PCI_SUBCLASS_SP_MANAGEMENT 0x20
164: #define PCI_SUBCLASS_SP_OTHER 0x80
165:
166: #define PCI_CLASS_OTHERS 0xff
167:
168: /* Vendors and devices. */
169:
170: #define PCI_VENDOR_ID_ATI 0x1002
171: #define PCI_DEVICE_ID_ATI_RAGE128_PF 0x5046
172:
173: #define PCI_VENDOR_ID_DEC 0x1011
174: #define PCI_DEVICE_ID_DEC_21154 0x0026
175:
176: #define PCI_VENDOR_ID_IBM 0x1014
177: #define PCI_DEVICE_ID_IBM_OPENPIC 0x0002
178: #define PCI_DEVICE_ID_IBM_OPENPIC2 0xffff
179:
180: #define PCI_VENDOR_ID_MOTOROLA 0x1057
181: #define PCI_DEVICE_ID_MOTOROLA_MPC106 0x0002
182: #define PCI_DEVICE_ID_MOTOROLA_RAVEN 0x4801
183:
184: #define PCI_VENDOR_ID_APPLE 0x106b
185: #define PCI_DEVICE_ID_APPLE_343S1201 0x0010
186: #define PCI_DEVICE_ID_APPLE_343S1211 0x0017
187: #define PCI_DEVICE_ID_APPLE_UNI_N_I_PCI 0x001e
188: #define PCI_DEVICE_ID_APPLE_UNI_N_PCI 0x001f
189: #define PCI_DEVICE_ID_APPLE_UNI_N_AGP 0x0020
190: #define PCI_DEVICE_ID_APPLE_UNI_N_KEYL 0x0022
191: #define PCI_DEVICE_ID_APPLE_U3_AGP 0x004b
192:
193: #define PCI_VENDOR_ID_SUN 0x108e
194: #define PCI_DEVICE_ID_SUN_EBUS 0x1000
195: #define PCI_DEVICE_ID_SUN_SIMBA 0x5000
196: #define PCI_DEVICE_ID_SUN_PBM 0x8000
197: #define PCI_DEVICE_ID_SUN_SABRE 0xa000
198:
199: #define PCI_VENDOR_ID_CMD 0x1095
200: #define PCI_DEVICE_ID_CMD_646 0x0646
201:
202: #define PCI_VENDOR_ID_REALTEK 0x10ec
203: #define PCI_DEVICE_ID_REALTEK_RTL8029 0x8029
204:
205: #define PCI_VENDOR_ID_QEMU 0x1234
206: #define PCI_DEVICE_ID_QEMU_VGA 0x1111
207:
208: #define PCI_VENDOR_ID_INTEL 0x8086
209: #define PCI_DEVICE_ID_INTEL_82441 0x1237
210:
211: #endif /* _H_PCI */
This archive runs on limited infrastructure. Preserving old code on modern bandwidth. Automated agents are requested to crawl responsibly.