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1.1 root 1: // Support for generating ACPI tables (on emulators)
2: //
3: // Copyright (C) 2008,2009 Kevin O'Connor <[email protected]>
4: // Copyright (C) 2006 Fabrice Bellard
5: //
6: // This file may be distributed under the terms of the GNU LGPLv3 license.
7:
8: #include "acpi.h" // struct rsdp_descriptor
9: #include "util.h" // memcpy
10: #include "pci.h" // pci_find_device
11: #include "biosvar.h" // GET_EBDA
12: #include "pci_ids.h" // PCI_VENDOR_ID_INTEL
13: #include "pci_regs.h" // PCI_INTERRUPT_LINE
14: #include "paravirt.h"
15:
16: /****************************************************/
17: /* ACPI tables init */
18:
19: /* Table structure from Linux kernel (the ACPI tables are under the
20: BSD license) */
21:
22: #define ACPI_TABLE_HEADER_DEF /* ACPI common table header */ \
23: u32 signature; /* ACPI signature (4 ASCII characters) */ \
24: u32 length; /* Length of table, in bytes, including header */ \
25: u8 revision; /* ACPI Specification minor version # */ \
26: u8 checksum; /* To make sum of entire table == 0 */ \
27: u8 oem_id [6]; /* OEM identification */ \
28: u8 oem_table_id [8]; /* OEM table identification */ \
29: u32 oem_revision; /* OEM revision number */ \
30: u8 asl_compiler_id [4]; /* ASL compiler vendor ID */ \
31: u32 asl_compiler_revision; /* ASL compiler revision number */
32:
33:
34: struct acpi_table_header /* ACPI common table header */
35: {
36: ACPI_TABLE_HEADER_DEF
37: } PACKED;
38:
39: /*
40: * ACPI 1.0 Root System Description Table (RSDT)
41: */
42: #define RSDT_SIGNATURE 0x54445352 // RSDT
43: struct rsdt_descriptor_rev1
44: {
45: ACPI_TABLE_HEADER_DEF /* ACPI common table header */
46: u32 table_offset_entry[0]; /* Array of pointers to other */
47: /* ACPI tables */
48: } PACKED;
49:
50: /*
51: * ACPI 1.0 Firmware ACPI Control Structure (FACS)
52: */
53: #define FACS_SIGNATURE 0x53434146 // FACS
54: struct facs_descriptor_rev1
55: {
56: u32 signature; /* ACPI Signature */
57: u32 length; /* Length of structure, in bytes */
58: u32 hardware_signature; /* Hardware configuration signature */
59: u32 firmware_waking_vector; /* ACPI OS waking vector */
60: u32 global_lock; /* Global Lock */
61: u32 S4bios_f : 1; /* Indicates if S4BIOS support is present */
62: u32 reserved1 : 31; /* Must be 0 */
63: u8 resverved3 [40]; /* Reserved - must be zero */
64: } PACKED;
65:
66:
67: /*
68: * ACPI 1.0 Fixed ACPI Description Table (FADT)
69: */
70: #define FACP_SIGNATURE 0x50434146 // FACP
71: struct fadt_descriptor_rev1
72: {
73: ACPI_TABLE_HEADER_DEF /* ACPI common table header */
74: u32 firmware_ctrl; /* Physical address of FACS */
75: u32 dsdt; /* Physical address of DSDT */
76: u8 model; /* System Interrupt Model */
77: u8 reserved1; /* Reserved */
78: u16 sci_int; /* System vector of SCI interrupt */
79: u32 smi_cmd; /* Port address of SMI command port */
80: u8 acpi_enable; /* Value to write to smi_cmd to enable ACPI */
81: u8 acpi_disable; /* Value to write to smi_cmd to disable ACPI */
82: u8 S4bios_req; /* Value to write to SMI CMD to enter S4BIOS state */
83: u8 reserved2; /* Reserved - must be zero */
84: u32 pm1a_evt_blk; /* Port address of Power Mgt 1a acpi_event Reg Blk */
85: u32 pm1b_evt_blk; /* Port address of Power Mgt 1b acpi_event Reg Blk */
86: u32 pm1a_cnt_blk; /* Port address of Power Mgt 1a Control Reg Blk */
87: u32 pm1b_cnt_blk; /* Port address of Power Mgt 1b Control Reg Blk */
88: u32 pm2_cnt_blk; /* Port address of Power Mgt 2 Control Reg Blk */
89: u32 pm_tmr_blk; /* Port address of Power Mgt Timer Ctrl Reg Blk */
90: u32 gpe0_blk; /* Port addr of General Purpose acpi_event 0 Reg Blk */
91: u32 gpe1_blk; /* Port addr of General Purpose acpi_event 1 Reg Blk */
92: u8 pm1_evt_len; /* Byte length of ports at pm1_x_evt_blk */
93: u8 pm1_cnt_len; /* Byte length of ports at pm1_x_cnt_blk */
94: u8 pm2_cnt_len; /* Byte Length of ports at pm2_cnt_blk */
95: u8 pm_tmr_len; /* Byte Length of ports at pm_tm_blk */
96: u8 gpe0_blk_len; /* Byte Length of ports at gpe0_blk */
97: u8 gpe1_blk_len; /* Byte Length of ports at gpe1_blk */
98: u8 gpe1_base; /* Offset in gpe model where gpe1 events start */
99: u8 reserved3; /* Reserved */
100: u16 plvl2_lat; /* Worst case HW latency to enter/exit C2 state */
101: u16 plvl3_lat; /* Worst case HW latency to enter/exit C3 state */
102: u16 flush_size; /* Size of area read to flush caches */
103: u16 flush_stride; /* Stride used in flushing caches */
104: u8 duty_offset; /* Bit location of duty cycle field in p_cnt reg */
105: u8 duty_width; /* Bit width of duty cycle field in p_cnt reg */
106: u8 day_alrm; /* Index to day-of-month alarm in RTC CMOS RAM */
107: u8 mon_alrm; /* Index to month-of-year alarm in RTC CMOS RAM */
108: u8 century; /* Index to century in RTC CMOS RAM */
109: u8 reserved4; /* Reserved */
110: u8 reserved4a; /* Reserved */
111: u8 reserved4b; /* Reserved */
112: #if 0
113: u32 wb_invd : 1; /* The wbinvd instruction works properly */
114: u32 wb_invd_flush : 1; /* The wbinvd flushes but does not invalidate */
115: u32 proc_c1 : 1; /* All processors support C1 state */
116: u32 plvl2_up : 1; /* C2 state works on MP system */
117: u32 pwr_button : 1; /* Power button is handled as a generic feature */
118: u32 sleep_button : 1; /* Sleep button is handled as a generic feature, or not present */
119: u32 fixed_rTC : 1; /* RTC wakeup stat not in fixed register space */
120: u32 rtcs4 : 1; /* RTC wakeup stat not possible from S4 */
121: u32 tmr_val_ext : 1; /* The tmr_val width is 32 bits (0 = 24 bits) */
122: u32 reserved5 : 23; /* Reserved - must be zero */
123: #else
124: u32 flags;
125: #endif
126: } PACKED;
127:
128: /*
129: * MADT values and structures
130: */
131:
132: /* Values for MADT PCATCompat */
133:
134: #define DUAL_PIC 0
135: #define MULTIPLE_APIC 1
136:
137:
138: /* Master MADT */
139:
140: #define APIC_SIGNATURE 0x43495041 // APIC
141: struct multiple_apic_table
142: {
143: ACPI_TABLE_HEADER_DEF /* ACPI common table header */
144: u32 local_apic_address; /* Physical address of local APIC */
145: #if 0
146: u32 PCATcompat : 1; /* A one indicates system also has dual 8259s */
147: u32 reserved1 : 31;
148: #else
149: u32 flags;
150: #endif
151: } PACKED;
152:
153:
154: /* Values for Type in APIC sub-headers */
155:
156: #define APIC_PROCESSOR 0
157: #define APIC_IO 1
158: #define APIC_XRUPT_OVERRIDE 2
159: #define APIC_NMI 3
160: #define APIC_LOCAL_NMI 4
161: #define APIC_ADDRESS_OVERRIDE 5
162: #define APIC_IO_SAPIC 6
163: #define APIC_LOCAL_SAPIC 7
164: #define APIC_XRUPT_SOURCE 8
165: #define APIC_RESERVED 9 /* 9 and greater are reserved */
166:
167: /*
168: * MADT sub-structures (Follow MULTIPLE_APIC_DESCRIPTION_TABLE)
169: */
170: #define ACPI_SUB_HEADER_DEF /* Common ACPI sub-structure header */\
171: u8 type; \
172: u8 length;
173:
174: /* Sub-structures for MADT */
175:
176: struct madt_processor_apic
177: {
178: ACPI_SUB_HEADER_DEF
179: u8 processor_id; /* ACPI processor id */
180: u8 local_apic_id; /* Processor's local APIC id */
181: #if 0
182: u32 processor_enabled: 1; /* Processor is usable if set */
183: u32 reserved2 : 31; /* Reserved, must be zero */
184: #else
185: u32 flags;
186: #endif
187: } PACKED;
188:
189: struct madt_io_apic
190: {
191: ACPI_SUB_HEADER_DEF
192: u8 io_apic_id; /* I/O APIC ID */
193: u8 reserved; /* Reserved - must be zero */
194: u32 address; /* APIC physical address */
195: u32 interrupt; /* Global system interrupt where INTI
196: * lines start */
197: } PACKED;
198:
199: /* IRQs 5,9,10,11 */
200: #define PCI_ISA_IRQ_MASK 0x0e20
201:
202: struct madt_intsrcovr {
203: ACPI_SUB_HEADER_DEF
204: u8 bus;
205: u8 source;
206: u32 gsi;
207: u16 flags;
208: } PACKED;
209:
210: /*
211: * ACPI 2.0 Generic Address Space definition.
212: */
213: struct acpi_20_generic_address {
214: u8 address_space_id;
215: u8 register_bit_width;
216: u8 register_bit_offset;
217: u8 reserved;
218: u64 address;
219: } PACKED;
220:
221: /*
222: * HPET Description Table
223: */
224: struct acpi_20_hpet {
225: ACPI_TABLE_HEADER_DEF /* ACPI common table header */
226: u32 timer_block_id;
227: struct acpi_20_generic_address addr;
228: u8 hpet_number;
229: u16 min_tick;
230: u8 page_protect;
231: } PACKED;
232: #define ACPI_HPET_ADDRESS 0xFED00000UL
233:
234: /*
235: * SRAT (NUMA topology description) table
236: */
237:
238: #define SRAT_PROCESSOR 0
239: #define SRAT_MEMORY 1
240:
241: struct system_resource_affinity_table
242: {
243: ACPI_TABLE_HEADER_DEF
244: u32 reserved1;
245: u32 reserved2[2];
246: } PACKED;
247:
248: struct srat_processor_affinity
249: {
250: ACPI_SUB_HEADER_DEF
251: u8 proximity_lo;
252: u8 local_apic_id;
253: u32 flags;
254: u8 local_sapic_eid;
255: u8 proximity_hi[3];
256: u32 reserved;
257: } PACKED;
258:
259: struct srat_memory_affinity
260: {
261: ACPI_SUB_HEADER_DEF
262: u8 proximity[4];
263: u16 reserved1;
264: u32 base_addr_low,base_addr_high;
265: u32 length_low,length_high;
266: u32 reserved2;
267: u32 flags;
268: u32 reserved3[2];
269: } PACKED;
270:
271: #include "acpi-dsdt.hex"
272:
273: static inline u16 cpu_to_le16(u16 x)
274: {
275: return x;
276: }
277:
278: static inline u32 cpu_to_le32(u32 x)
279: {
280: return x;
281: }
282:
283: static void
284: build_header(struct acpi_table_header *h, u32 sig, int len, u8 rev)
285: {
286: h->signature = sig;
287: h->length = cpu_to_le32(len);
288: h->revision = rev;
289: memcpy(h->oem_id, CONFIG_APPNAME6, 6);
290: memcpy(h->oem_table_id, CONFIG_APPNAME4, 4);
291: memcpy(h->asl_compiler_id, CONFIG_APPNAME4, 4);
292: memcpy(h->oem_table_id + 4, (void*)&sig, 4);
293: h->oem_revision = cpu_to_le32(1);
294: h->asl_compiler_revision = cpu_to_le32(1);
295: h->checksum -= checksum(h, len);
296: }
297:
298: static void*
299: build_fadt(int bdf)
300: {
301: struct fadt_descriptor_rev1 *fadt = malloc_high(sizeof(*fadt));
302: struct facs_descriptor_rev1 *facs = memalign_high(64, sizeof(*facs));
303: void *dsdt = malloc_high(sizeof(AmlCode));
304:
305: if (!fadt || !facs || !dsdt) {
1.1.1.4 ! root 306: warn_noalloc();
1.1 root 307: return NULL;
308: }
309:
310: /* FACS */
311: memset(facs, 0, sizeof(*facs));
312: facs->signature = FACS_SIGNATURE;
313: facs->length = cpu_to_le32(sizeof(*facs));
314:
315: /* DSDT */
316: memcpy(dsdt, AmlCode, sizeof(AmlCode));
317:
318: /* FADT */
319: memset(fadt, 0, sizeof(*fadt));
320: fadt->firmware_ctrl = cpu_to_le32((u32)facs);
321: fadt->dsdt = cpu_to_le32((u32)dsdt);
322: fadt->model = 1;
323: fadt->reserved1 = 0;
324: int pm_sci_int = pci_config_readb(bdf, PCI_INTERRUPT_LINE);
325: fadt->sci_int = cpu_to_le16(pm_sci_int);
326: fadt->smi_cmd = cpu_to_le32(PORT_SMI_CMD);
327: fadt->acpi_enable = 0xf1;
328: fadt->acpi_disable = 0xf0;
329: fadt->pm1a_evt_blk = cpu_to_le32(PORT_ACPI_PM_BASE);
330: fadt->pm1a_cnt_blk = cpu_to_le32(PORT_ACPI_PM_BASE + 0x04);
331: fadt->pm_tmr_blk = cpu_to_le32(PORT_ACPI_PM_BASE + 0x08);
332: fadt->pm1_evt_len = 4;
333: fadt->pm1_cnt_len = 2;
334: fadt->pm_tmr_len = 4;
335: fadt->plvl2_lat = cpu_to_le16(0xfff); // C2 state not supported
336: fadt->plvl3_lat = cpu_to_le16(0xfff); // C3 state not supported
337: fadt->gpe0_blk = cpu_to_le32(0xafe0);
338: fadt->gpe0_blk_len = 4;
339: /* WBINVD + PROC_C1 + SLP_BUTTON + FIX_RTC */
340: fadt->flags = cpu_to_le32((1 << 0) | (1 << 2) | (1 << 5) | (1 << 6));
341:
342: build_header((void*)fadt, FACP_SIGNATURE, sizeof(*fadt), 1);
343:
344: return fadt;
345: }
346:
347: static void*
348: build_madt(void)
349: {
350: int madt_size = (sizeof(struct multiple_apic_table)
351: + sizeof(struct madt_processor_apic) * MaxCountCPUs
352: + sizeof(struct madt_io_apic)
353: + sizeof(struct madt_intsrcovr) * 16);
354: struct multiple_apic_table *madt = malloc_high(madt_size);
355: if (!madt) {
1.1.1.4 ! root 356: warn_noalloc();
1.1 root 357: return NULL;
358: }
359: memset(madt, 0, madt_size);
360: madt->local_apic_address = cpu_to_le32(BUILD_APIC_ADDR);
361: madt->flags = cpu_to_le32(1);
362: struct madt_processor_apic *apic = (void*)&madt[1];
363: int i;
364: for (i=0; i<MaxCountCPUs; i++) {
365: apic->type = APIC_PROCESSOR;
366: apic->length = sizeof(*apic);
367: apic->processor_id = i;
368: apic->local_apic_id = i;
369: if (i < CountCPUs)
370: apic->flags = cpu_to_le32(1);
371: else
372: apic->flags = cpu_to_le32(0);
373: apic++;
374: }
375: struct madt_io_apic *io_apic = (void*)apic;
376: io_apic->type = APIC_IO;
377: io_apic->length = sizeof(*io_apic);
378: io_apic->io_apic_id = CountCPUs;
379: io_apic->address = cpu_to_le32(BUILD_IOAPIC_ADDR);
380: io_apic->interrupt = cpu_to_le32(0);
381:
382: struct madt_intsrcovr *intsrcovr = (void*)&io_apic[1];
383: if (qemu_cfg_irq0_override()) {
384: memset(intsrcovr, 0, sizeof(*intsrcovr));
385: intsrcovr->type = APIC_XRUPT_OVERRIDE;
386: intsrcovr->length = sizeof(*intsrcovr);
387: intsrcovr->source = 0;
388: intsrcovr->gsi = 2;
389: intsrcovr->flags = 0; /* conforms to bus specifications */
390: intsrcovr++;
391: }
392: for (i = 1; i < 16; i++) {
393: if (!(PCI_ISA_IRQ_MASK & (1 << i)))
394: /* No need for a INT source override structure. */
395: continue;
396: memset(intsrcovr, 0, sizeof(*intsrcovr));
397: intsrcovr->type = APIC_XRUPT_OVERRIDE;
398: intsrcovr->length = sizeof(*intsrcovr);
399: intsrcovr->source = i;
400: intsrcovr->gsi = i;
401: intsrcovr->flags = 0xd; /* active high, level triggered */
402: intsrcovr++;
403: }
404:
405: build_header((void*)madt, APIC_SIGNATURE, (void*)intsrcovr - (void*)madt, 1);
406: return madt;
407: }
408:
409: #define SSDT_SIGNATURE 0x54445353 // SSDT
410: static void*
411: build_ssdt(void)
412: {
413: int acpi_cpus = MaxCountCPUs > 0xff ? 0xff : MaxCountCPUs;
414: // calculate the length of processor block and scope block
415: // excluding PkgLength
416: int cpu_length = 13 * acpi_cpus + 4;
417:
418: int length = sizeof(struct acpi_table_header) + 3 + cpu_length;
419: u8 *ssdt = malloc_high(length);
420: if (! ssdt) {
1.1.1.4 ! root 421: warn_noalloc();
1.1 root 422: return NULL;
423: }
424:
425: u8 *ssdt_ptr = ssdt;
426: ssdt_ptr[9] = 0; // checksum;
427: ssdt_ptr += sizeof(struct acpi_table_header);
428:
429: // build processor scope header
430: *(ssdt_ptr++) = 0x10; // ScopeOp
431: if (cpu_length <= 0x3e) {
1.1.1.3 root 432: /* Handle 1-4 CPUs with one byte encoding */
1.1 root 433: *(ssdt_ptr++) = cpu_length + 1;
434: } else {
1.1.1.3 root 435: /* Handle 5-314 CPUs with two byte encoding */
436: *(ssdt_ptr++) = 0x40 | ((cpu_length + 2) & 0xf);
437: *(ssdt_ptr++) = (cpu_length + 2) >> 4;
1.1 root 438: }
439: *(ssdt_ptr++) = '_'; // Name
440: *(ssdt_ptr++) = 'P';
441: *(ssdt_ptr++) = 'R';
442: *(ssdt_ptr++) = '_';
443:
444: // build object for each processor
445: int i;
446: for (i=0; i<acpi_cpus; i++) {
447: *(ssdt_ptr++) = 0x5B; // ProcessorOp
448: *(ssdt_ptr++) = 0x83;
449: *(ssdt_ptr++) = 0x0B; // Length
450: *(ssdt_ptr++) = 'C'; // Name (CPUxx)
451: *(ssdt_ptr++) = 'P';
452: if ((i & 0xf0) != 0)
453: *(ssdt_ptr++) = (i >> 4) < 0xa ? (i >> 4) + '0' : (i >> 4) + 'A' - 0xa;
454: else
455: *(ssdt_ptr++) = 'U';
456: *(ssdt_ptr++) = (i & 0xf) < 0xa ? (i & 0xf) + '0' : (i & 0xf) + 'A' - 0xa;
457: *(ssdt_ptr++) = i;
458: *(ssdt_ptr++) = 0x10; // Processor block address
459: *(ssdt_ptr++) = 0xb0;
460: *(ssdt_ptr++) = 0;
461: *(ssdt_ptr++) = 0;
462: *(ssdt_ptr++) = 6; // Processor block length
463: }
464:
465: build_header((void*)ssdt, SSDT_SIGNATURE, ssdt_ptr - ssdt, 1);
466:
467: return ssdt;
468: }
469:
470: #define HPET_SIGNATURE 0x54455048 //HPET
471: static void*
472: build_hpet(void)
473: {
474: struct acpi_20_hpet *hpet = malloc_high(sizeof(*hpet));
475: if (!hpet) {
1.1.1.4 ! root 476: warn_noalloc();
1.1 root 477: return NULL;
478: }
479:
480: memset(hpet, 0, sizeof(*hpet));
481: /* Note timer_block_id value must be kept in sync with value advertised by
482: * emulated hpet
483: */
484: hpet->timer_block_id = cpu_to_le32(0x8086a201);
485: hpet->addr.address = cpu_to_le32(ACPI_HPET_ADDRESS);
486: build_header((void*)hpet, HPET_SIGNATURE, sizeof(*hpet), 1);
487:
488: return hpet;
489: }
490:
491: static void
492: acpi_build_srat_memory(struct srat_memory_affinity *numamem,
493: u64 base, u64 len, int node, int enabled)
494: {
495: numamem->type = SRAT_MEMORY;
496: numamem->length = sizeof(*numamem);
497: memset (numamem->proximity, 0 ,4);
498: numamem->proximity[0] = node;
499: numamem->flags = cpu_to_le32(!!enabled);
500: numamem->base_addr_low = base & 0xFFFFFFFF;
501: numamem->base_addr_high = base >> 32;
502: numamem->length_low = len & 0xFFFFFFFF;
503: numamem->length_high = len >> 32;
504: }
505:
506: #define SRAT_SIGNATURE 0x54415253 //HPET
507: static void *
508: build_srat(void)
509: {
510: int nb_numa_nodes = qemu_cfg_get_numa_nodes();
511:
512: if (nb_numa_nodes == 0)
513: return NULL;
514:
515: u64 *numadata = malloc_tmphigh(sizeof(u64) * (MaxCountCPUs + nb_numa_nodes));
516: if (!numadata) {
1.1.1.4 ! root 517: warn_noalloc();
1.1 root 518: return NULL;
519: }
520:
521: qemu_cfg_get_numa_data(numadata, MaxCountCPUs + nb_numa_nodes);
522:
523: struct system_resource_affinity_table *srat;
524: int srat_size = sizeof(*srat) +
525: sizeof(struct srat_processor_affinity) * MaxCountCPUs +
526: sizeof(struct srat_memory_affinity) * (nb_numa_nodes + 2);
527:
528: srat = malloc_high(srat_size);
529: if (!srat) {
1.1.1.4 ! root 530: warn_noalloc();
! 531: free(numadata);
1.1 root 532: return NULL;
533: }
534:
535: memset(srat, 0, srat_size);
536: srat->reserved1=1;
537: struct srat_processor_affinity *core = (void*)(srat + 1);
538: int i;
539: u64 curnode;
540:
541: for (i = 0; i < MaxCountCPUs; ++i) {
542: core->type = SRAT_PROCESSOR;
543: core->length = sizeof(*core);
544: core->local_apic_id = i;
545: curnode = *numadata++;
546: core->proximity_lo = curnode;
547: memset(core->proximity_hi, 0, 3);
548: core->local_sapic_eid = 0;
549: if (i < CountCPUs)
550: core->flags = cpu_to_le32(1);
551: else
552: core->flags = 0;
553: core++;
554: }
555:
556:
557: /* the memory map is a bit tricky, it contains at least one hole
558: * from 640k-1M and possibly another one from 3.5G-4G.
559: */
560: struct srat_memory_affinity *numamem = (void*)core;
561: int slots = 0;
562: u64 mem_len, mem_base, next_base = 0;
563:
564: acpi_build_srat_memory(numamem, 0, 640*1024, 0, 1);
565: next_base = 1024 * 1024;
566: numamem++;
567: slots++;
568: for (i = 1; i < nb_numa_nodes + 1; ++i) {
569: mem_base = next_base;
570: mem_len = *numadata++;
571: if (i == 1)
572: mem_len -= 1024 * 1024;
573: next_base = mem_base + mem_len;
574:
575: /* Cut out the PCI hole */
576: if (mem_base <= RamSize && next_base > RamSize) {
577: mem_len -= next_base - RamSize;
578: if (mem_len > 0) {
579: acpi_build_srat_memory(numamem, mem_base, mem_len, i-1, 1);
580: numamem++;
581: slots++;
582: }
583: mem_base = 1ULL << 32;
584: mem_len = next_base - RamSize;
585: next_base += (1ULL << 32) - RamSize;
586: }
587: acpi_build_srat_memory(numamem, mem_base, mem_len, i-1, 1);
588: numamem++;
589: slots++;
590: }
591: for (; slots < nb_numa_nodes + 2; slots++) {
592: acpi_build_srat_memory(numamem, 0, 0, 0, 0);
593: numamem++;
594: }
595:
596: build_header((void*)srat, SRAT_SIGNATURE, srat_size, 1);
597:
1.1.1.4 ! root 598: free(numadata);
1.1 root 599: return srat;
600: }
601:
602: struct rsdp_descriptor *RsdpAddr;
603:
604: #define MAX_ACPI_TABLES 20
605: void
606: acpi_bios_init(void)
607: {
608: if (! CONFIG_ACPI)
609: return;
610:
611: dprintf(3, "init ACPI tables\n");
612:
613: // This code is hardcoded for PIIX4 Power Management device.
614: int bdf = pci_find_device(PCI_VENDOR_ID_INTEL
615: , PCI_DEVICE_ID_INTEL_82371AB_3);
616: if (bdf < 0)
617: // Device not found
618: return;
619:
620: // Create initial rsdt table
621: struct rsdp_descriptor *rsdp = malloc_fseg(sizeof(*rsdp));
622: if (!rsdp) {
1.1.1.4 ! root 623: warn_noalloc();
1.1 root 624: return;
625: }
626:
627: u32 tables[MAX_ACPI_TABLES], tbl_idx = 0;
628:
629: #define ACPI_INIT_TABLE(X) \
630: do { \
631: tables[tbl_idx] = (u32)(X); \
632: if (tables[tbl_idx]) \
633: tbl_idx++; \
634: } while(0)
635:
636: // Add tables
637: ACPI_INIT_TABLE(build_fadt(bdf));
638: ACPI_INIT_TABLE(build_ssdt());
639: ACPI_INIT_TABLE(build_madt());
640: ACPI_INIT_TABLE(build_hpet());
641: ACPI_INIT_TABLE(build_srat());
642:
643: u16 i, external_tables = qemu_cfg_acpi_additional_tables();
644:
645: for(i = 0; i < external_tables; i++) {
646: u16 len = qemu_cfg_next_acpi_table_len();
647: void *addr = malloc_high(len);
648: if (!addr) {
1.1.1.4 ! root 649: warn_noalloc();
1.1 root 650: continue;
651: }
652: ACPI_INIT_TABLE(qemu_cfg_next_acpi_table_load(addr, len));
653: if (tbl_idx == MAX_ACPI_TABLES) {
1.1.1.4 ! root 654: warn_noalloc();
1.1 root 655: break;
656: }
657: }
658:
659: struct rsdt_descriptor_rev1 *rsdt;
660: size_t rsdt_len = sizeof(*rsdt) + sizeof(u32) * tbl_idx;
661: rsdt = malloc_high(rsdt_len);
662:
663: if (!rsdt) {
1.1.1.4 ! root 664: warn_noalloc();
1.1 root 665: return;
666: }
667: memset(rsdt, 0, rsdt_len);
668: memcpy(rsdt->table_offset_entry, tables, sizeof(u32) * tbl_idx);
669:
670: build_header((void*)rsdt, RSDT_SIGNATURE, rsdt_len, 1);
671:
672: // Build rsdp pointer table
673: memset(rsdp, 0, sizeof(*rsdp));
674: rsdp->signature = RSDP_SIGNATURE;
675: memcpy(rsdp->oem_id, CONFIG_APPNAME6, 6);
676: rsdp->rsdt_physical_address = cpu_to_le32((u32)rsdt);
677: rsdp->checksum -= checksum(rsdp, 20);
678: RsdpAddr = rsdp;
679: dprintf(1, "ACPI tables: RSDP=%p RSDT=%p\n", rsdp, rsdt);
680: }
681:
682: u32
1.1.1.2 root 683: find_resume_vector(void)
1.1 root 684: {
685: dprintf(4, "rsdp=%p\n", RsdpAddr);
686: if (!RsdpAddr || RsdpAddr->signature != RSDP_SIGNATURE)
687: return 0;
688: struct rsdt_descriptor_rev1 *rsdt = (void*)RsdpAddr->rsdt_physical_address;
689: dprintf(4, "rsdt=%p\n", rsdt);
690: if (!rsdt || rsdt->signature != RSDT_SIGNATURE)
691: return 0;
692: void *end = (void*)rsdt + rsdt->length;
693: int i;
694: for (i=0; (void*)&rsdt->table_offset_entry[i] < end; i++) {
695: struct fadt_descriptor_rev1 *fadt = (void*)rsdt->table_offset_entry[i];
696: if (!fadt || fadt->signature != FACP_SIGNATURE)
697: continue;
698: dprintf(4, "fadt=%p\n", fadt);
699: struct facs_descriptor_rev1 *facs = (void*)fadt->firmware_ctrl;
700: dprintf(4, "facs=%p\n", facs);
701: if (! facs || facs->signature != FACS_SIGNATURE)
702: return 0;
703: // Found it.
704: dprintf(4, "resume addr=%d\n", facs->firmware_waking_vector);
705: return facs->firmware_waking_vector;
706: }
707: return 0;
708: }
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