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1.1 root 1: // 16bit code to handle system clocks.
2: //
1.1.1.4 ! root 3: // Copyright (C) 2008-2010 Kevin O'Connor <[email protected]>
1.1 root 4: // Copyright (C) 2002 MandrakeSoft S.A.
5: //
6: // This file may be distributed under the terms of the GNU LGPLv3 license.
7:
8: #include "biosvar.h" // SET_BDA
9: #include "util.h" // debug_enter
10: #include "disk.h" // floppy_tick
11: #include "cmos.h" // inb_cmos
12: #include "pic.h" // eoi_pic1
13: #include "bregs.h" // struct bregs
14: #include "biosvar.h" // GET_GLOBAL
1.1.1.3 root 15: #include "usb-hid.h" // usb_check_event
1.1 root 16:
17: // RTC register flags
18: #define RTC_A_UIP 0x80
19:
20: #define RTC_B_SET 0x80
21: #define RTC_B_PIE 0x40
22: #define RTC_B_AIE 0x20
23: #define RTC_B_UIE 0x10
24: #define RTC_B_BIN 0x04
25: #define RTC_B_24HR 0x02
26: #define RTC_B_DSE 0x01
27:
28:
29: // Bits for PORT_PS2_CTRLB
30: #define PPCB_T2GATE (1<<0)
31: #define PPCB_SPKR (1<<1)
32: #define PPCB_T2OUT (1<<5)
33:
34: // Bits for PORT_PIT_MODE
35: #define PM_SEL_TIMER0 (0<<6)
36: #define PM_SEL_TIMER1 (1<<6)
37: #define PM_SEL_TIMER2 (2<<6)
38: #define PM_SEL_READBACK (3<<6)
39: #define PM_ACCESS_LATCH (0<<4)
40: #define PM_ACCESS_LOBYTE (1<<4)
41: #define PM_ACCESS_HIBYTE (2<<4)
42: #define PM_ACCESS_WORD (3<<4)
43: #define PM_MODE0 (0<<1)
44: #define PM_MODE1 (1<<1)
45: #define PM_MODE2 (2<<1)
46: #define PM_MODE3 (3<<1)
47: #define PM_MODE4 (4<<1)
48: #define PM_MODE5 (5<<1)
49: #define PM_CNT_BINARY (0<<0)
50: #define PM_CNT_BCD (1<<0)
51:
52:
53: /****************************************************************
54: * TSC timer
55: ****************************************************************/
56:
57: #define CALIBRATE_COUNT 0x800 // Approx 1.7ms
58:
59: u32 cpu_khz VAR16VISIBLE;
60:
61: static void
1.1.1.2 root 62: calibrate_tsc(void)
1.1 root 63: {
64: // Setup "timer2"
65: u8 orig = inb(PORT_PS2_CTRLB);
66: outb((orig & ~PPCB_SPKR) | PPCB_T2GATE, PORT_PS2_CTRLB);
67: /* binary, mode 0, LSB/MSB, Ch 2 */
68: outb(PM_SEL_TIMER2|PM_ACCESS_WORD|PM_MODE0|PM_CNT_BINARY, PORT_PIT_MODE);
69: /* LSB of ticks */
70: outb(CALIBRATE_COUNT & 0xFF, PORT_PIT_COUNTER2);
71: /* MSB of ticks */
72: outb(CALIBRATE_COUNT >> 8, PORT_PIT_COUNTER2);
73:
74: u64 start = rdtscll();
75: while ((inb(PORT_PS2_CTRLB) & PPCB_T2OUT) == 0)
76: ;
77: u64 end = rdtscll();
78:
79: // Restore PORT_PS2_CTRLB
80: outb(orig, PORT_PS2_CTRLB);
81:
82: // Store calibrated cpu khz.
83: u64 diff = end - start;
84: dprintf(6, "tsc calibrate start=%u end=%u diff=%u\n"
85: , (u32)start, (u32)end, (u32)diff);
86: u32 hz = diff * PIT_TICK_RATE / CALIBRATE_COUNT;
87: SET_GLOBAL(cpu_khz, hz / 1000);
88:
89: dprintf(1, "CPU Mhz=%u\n", hz / 1000000);
90: }
91:
92: static void
93: tscdelay(u64 diff)
94: {
95: u64 start = rdtscll();
96: u64 end = start + diff;
1.1.1.3 root 97: while (!check_tsc(end))
1.1 root 98: cpu_relax();
99: }
100:
101: static void
102: tscsleep(u64 diff)
103: {
104: u64 start = rdtscll();
105: u64 end = start + diff;
1.1.1.3 root 106: while (!check_tsc(end))
1.1 root 107: yield();
108: }
109:
110: void ndelay(u32 count) {
111: tscdelay(count * GET_GLOBAL(cpu_khz) / 1000000);
112: }
113: void udelay(u32 count) {
114: tscdelay(count * GET_GLOBAL(cpu_khz) / 1000);
115: }
116: void mdelay(u32 count) {
117: tscdelay(count * GET_GLOBAL(cpu_khz));
118: }
119:
120: void nsleep(u32 count) {
121: tscsleep(count * GET_GLOBAL(cpu_khz) / 1000000);
122: }
123: void usleep(u32 count) {
124: tscsleep(count * GET_GLOBAL(cpu_khz) / 1000);
125: }
126: void msleep(u32 count) {
127: tscsleep(count * GET_GLOBAL(cpu_khz));
128: }
129:
130: // Return the TSC value that is 'msecs' time in the future.
131: u64
132: calc_future_tsc(u32 msecs)
133: {
134: u32 khz = GET_GLOBAL(cpu_khz);
135: return rdtscll() + ((u64)khz * msecs);
136: }
137: u64
138: calc_future_tsc_usec(u32 usecs)
139: {
140: u32 khz = GET_GLOBAL(cpu_khz);
141: return rdtscll() + ((u64)(khz/1000) * usecs);
142: }
143:
144:
145: /****************************************************************
146: * Init
147: ****************************************************************/
148:
149: static int
1.1.1.2 root 150: rtc_updating(void)
1.1 root 151: {
152: // This function checks to see if the update-in-progress bit
153: // is set in CMOS Status Register A. If not, it returns 0.
154: // If it is set, it tries to wait until there is a transition
155: // to 0, and will return 0 if such a transition occurs. A -1
156: // is returned only after timing out. The maximum period
157: // that this bit should be set is constrained to (1984+244)
1.1.1.3 root 158: // useconds, but we wait for longer just to be sure.
1.1 root 159:
160: if ((inb_cmos(CMOS_STATUS_A) & RTC_A_UIP) == 0)
161: return 0;
1.1.1.3 root 162: u64 end = calc_future_tsc(15);
163: for (;;) {
1.1 root 164: if ((inb_cmos(CMOS_STATUS_A) & RTC_A_UIP) == 0)
165: return 0;
1.1.1.3 root 166: if (check_tsc(end))
167: // update-in-progress never transitioned to 0
168: return -1;
169: yield();
170: }
1.1 root 171: }
172:
173: static void
1.1.1.2 root 174: pit_setup(void)
1.1 root 175: {
176: // timer0: binary count, 16bit count, mode 2
177: outb(PM_SEL_TIMER0|PM_ACCESS_WORD|PM_MODE2|PM_CNT_BINARY, PORT_PIT_MODE);
178: // maximum count of 0000H = 18.2Hz
179: outb(0x0, PORT_PIT_COUNTER0);
180: outb(0x0, PORT_PIT_COUNTER0);
181: }
182:
183: static void
1.1.1.2 root 184: init_rtc(void)
1.1 root 185: {
186: outb_cmos(0x26, CMOS_STATUS_A); // 32,768Khz src, 976.5625us updates
187: u8 regB = inb_cmos(CMOS_STATUS_B);
188: outb_cmos((regB & RTC_B_DSE) | RTC_B_24HR, CMOS_STATUS_B);
189: inb_cmos(CMOS_STATUS_C);
190: inb_cmos(CMOS_STATUS_D);
191: }
192:
193: static u32
194: bcd2bin(u8 val)
195: {
196: return (val & 0xf) + ((val >> 4) * 10);
197: }
198:
199: void
1.1.1.2 root 200: timer_setup(void)
1.1 root 201: {
202: dprintf(3, "init timer\n");
203: calibrate_tsc();
204: pit_setup();
205:
206: init_rtc();
207: rtc_updating();
208: u32 seconds = bcd2bin(inb_cmos(CMOS_RTC_SECONDS));
209: u32 minutes = bcd2bin(inb_cmos(CMOS_RTC_MINUTES));
210: u32 hours = bcd2bin(inb_cmos(CMOS_RTC_HOURS));
211: u32 ticks = (hours * 60 + minutes) * 60 + seconds;
212: ticks = ((u64)ticks * PIT_TICK_RATE) / PIT_TICK_INTERVAL;
213: SET_BDA(timer_counter, ticks);
214: SET_BDA(timer_rollover, 0);
215:
1.1.1.4 ! root 216: enable_hwirq(0, FUNC16(entry_08));
! 217: enable_hwirq(8, FUNC16(entry_70));
1.1 root 218: }
219:
220:
221: /****************************************************************
222: * Standard clock functions
223: ****************************************************************/
224:
1.1.1.3 root 225: #define TICKS_PER_DAY (u32)((u64)60*60*24*PIT_TICK_RATE / PIT_TICK_INTERVAL)
226:
227: // Calculate the timer value at 'count' number of full timer ticks in
228: // the future.
229: u32
230: calc_future_timer_ticks(u32 count)
231: {
232: return (GET_BDA(timer_counter) + count + 1) % TICKS_PER_DAY;
233: }
234:
235: // Return the timer value that is 'msecs' time in the future.
236: u32
237: calc_future_timer(u32 msecs)
238: {
239: if (!msecs)
240: return GET_BDA(timer_counter);
1.1.1.4 ! root 241: u32 kticks = DIV_ROUND_UP((u64)msecs * PIT_TICK_RATE, PIT_TICK_INTERVAL);
1.1.1.3 root 242: u32 ticks = DIV_ROUND_UP(kticks, 1000);
243: return calc_future_timer_ticks(ticks);
244: }
245:
246: // Check if the given timer value has passed.
247: int
248: check_timer(u32 end)
249: {
250: return (((GET_BDA(timer_counter) + TICKS_PER_DAY - end) % TICKS_PER_DAY)
251: < (TICKS_PER_DAY/2));
252: }
253:
1.1 root 254: // get current clock count
255: static void
256: handle_1a00(struct bregs *regs)
257: {
1.1.1.3 root 258: yield();
1.1 root 259: u32 ticks = GET_BDA(timer_counter);
260: regs->cx = ticks >> 16;
261: regs->dx = ticks;
262: regs->al = GET_BDA(timer_rollover);
263: SET_BDA(timer_rollover, 0); // reset flag
264: set_success(regs);
265: }
266:
267: // Set Current Clock Count
268: static void
269: handle_1a01(struct bregs *regs)
270: {
271: u32 ticks = (regs->cx << 16) | regs->dx;
272: SET_BDA(timer_counter, ticks);
273: SET_BDA(timer_rollover, 0); // reset flag
274: // XXX - should use set_code_success()?
275: regs->ah = 0;
276: set_success(regs);
277: }
278:
279: // Read CMOS Time
280: static void
281: handle_1a02(struct bregs *regs)
282: {
283: if (rtc_updating()) {
284: set_invalid(regs);
285: return;
286: }
287:
288: regs->dh = inb_cmos(CMOS_RTC_SECONDS);
289: regs->cl = inb_cmos(CMOS_RTC_MINUTES);
290: regs->ch = inb_cmos(CMOS_RTC_HOURS);
291: regs->dl = inb_cmos(CMOS_STATUS_B) & RTC_B_DSE;
292: regs->ah = 0;
293: regs->al = regs->ch;
294: set_success(regs);
295: }
296:
297: // Set CMOS Time
298: static void
299: handle_1a03(struct bregs *regs)
300: {
301: // Using a debugger, I notice the following masking/setting
302: // of bits in Status Register B, by setting Reg B to
303: // a few values and getting its value after INT 1A was called.
304: //
305: // try#1 try#2 try#3
306: // before 1111 1101 0111 1101 0000 0000
307: // after 0110 0010 0110 0010 0000 0010
308: //
309: // Bit4 in try#1 flipped in hardware (forced low) due to bit7=1
310: // My assumption: RegB = ((RegB & 01100000b) | 00000010b)
311: if (rtc_updating()) {
312: init_rtc();
313: // fall through as if an update were not in progress
314: }
315: outb_cmos(regs->dh, CMOS_RTC_SECONDS);
316: outb_cmos(regs->cl, CMOS_RTC_MINUTES);
317: outb_cmos(regs->ch, CMOS_RTC_HOURS);
318: // Set Daylight Savings time enabled bit to requested value
319: u8 val8 = ((inb_cmos(CMOS_STATUS_B) & (RTC_B_PIE|RTC_B_AIE))
320: | RTC_B_24HR | (regs->dl & RTC_B_DSE));
321: outb_cmos(val8, CMOS_STATUS_B);
322: regs->ah = 0;
323: regs->al = val8; // val last written to Reg B
324: set_success(regs);
325: }
326:
327: // Read CMOS Date
328: static void
329: handle_1a04(struct bregs *regs)
330: {
331: regs->ah = 0;
332: if (rtc_updating()) {
333: set_invalid(regs);
334: return;
335: }
336: regs->cl = inb_cmos(CMOS_RTC_YEAR);
337: regs->dh = inb_cmos(CMOS_RTC_MONTH);
338: regs->dl = inb_cmos(CMOS_RTC_DAY_MONTH);
339: if (CONFIG_COREBOOT) {
340: if (regs->cl > 0x80)
341: regs->ch = 0x19;
342: else
343: regs->ch = 0x20;
344: } else {
345: regs->ch = inb_cmos(CMOS_CENTURY);
346: }
347: regs->al = regs->ch;
348: set_success(regs);
349: }
350:
351: // Set CMOS Date
352: static void
353: handle_1a05(struct bregs *regs)
354: {
355: // Using a debugger, I notice the following masking/setting
356: // of bits in Status Register B, by setting Reg B to
357: // a few values and getting its value after INT 1A was called.
358: //
359: // try#1 try#2 try#3 try#4
360: // before 1111 1101 0111 1101 0000 0010 0000 0000
361: // after 0110 1101 0111 1101 0000 0010 0000 0000
362: //
363: // Bit4 in try#1 flipped in hardware (forced low) due to bit7=1
364: // My assumption: RegB = (RegB & 01111111b)
365: if (rtc_updating()) {
366: init_rtc();
367: set_invalid(regs);
368: return;
369: }
370: outb_cmos(regs->cl, CMOS_RTC_YEAR);
371: outb_cmos(regs->dh, CMOS_RTC_MONTH);
372: outb_cmos(regs->dl, CMOS_RTC_DAY_MONTH);
373: if (!CONFIG_COREBOOT)
374: outb_cmos(regs->ch, CMOS_CENTURY);
375: // clear halt-clock bit
376: u8 val8 = inb_cmos(CMOS_STATUS_B) & ~RTC_B_SET;
377: outb_cmos(val8, CMOS_STATUS_B);
378: regs->ah = 0;
379: regs->al = val8; // AL = val last written to Reg B
380: set_success(regs);
381: }
382:
383: // Set Alarm Time in CMOS
384: static void
385: handle_1a06(struct bregs *regs)
386: {
387: // Using a debugger, I notice the following masking/setting
388: // of bits in Status Register B, by setting Reg B to
389: // a few values and getting its value after INT 1A was called.
390: //
391: // try#1 try#2 try#3
392: // before 1101 1111 0101 1111 0000 0000
393: // after 0110 1111 0111 1111 0010 0000
394: //
395: // Bit4 in try#1 flipped in hardware (forced low) due to bit7=1
396: // My assumption: RegB = ((RegB & 01111111b) | 00100000b)
397: u8 val8 = inb_cmos(CMOS_STATUS_B); // Get Status Reg B
398: regs->ax = 0;
399: if (val8 & RTC_B_AIE) {
400: // Alarm interrupt enabled already
401: set_invalid(regs);
402: return;
403: }
404: if (rtc_updating()) {
405: init_rtc();
406: // fall through as if an update were not in progress
407: }
408: outb_cmos(regs->dh, CMOS_RTC_SECONDS_ALARM);
409: outb_cmos(regs->cl, CMOS_RTC_MINUTES_ALARM);
410: outb_cmos(regs->ch, CMOS_RTC_HOURS_ALARM);
411: // enable Status Reg B alarm bit, clear halt clock bit
412: outb_cmos((val8 & ~RTC_B_SET) | RTC_B_AIE, CMOS_STATUS_B);
413: set_success(regs);
414: }
415:
416: // Turn off Alarm
417: static void
418: handle_1a07(struct bregs *regs)
419: {
420: // Using a debugger, I notice the following masking/setting
421: // of bits in Status Register B, by setting Reg B to
422: // a few values and getting its value after INT 1A was called.
423: //
424: // try#1 try#2 try#3 try#4
425: // before 1111 1101 0111 1101 0010 0000 0010 0010
426: // after 0100 0101 0101 0101 0000 0000 0000 0010
427: //
428: // Bit4 in try#1 flipped in hardware (forced low) due to bit7=1
429: // My assumption: RegB = (RegB & 01010111b)
430: u8 val8 = inb_cmos(CMOS_STATUS_B); // Get Status Reg B
431: // clear clock-halt bit, disable alarm bit
432: outb_cmos(val8 & ~(RTC_B_SET|RTC_B_AIE), CMOS_STATUS_B);
433: regs->ah = 0;
434: regs->al = val8; // val last written to Reg B
435: set_success(regs);
436: }
437:
438: // Unsupported
439: static void
440: handle_1aXX(struct bregs *regs)
441: {
442: set_unimplemented(regs);
443: }
444:
445: // INT 1Ah Time-of-day Service Entry Point
446: void VISIBLE16
447: handle_1a(struct bregs *regs)
448: {
449: debug_enter(regs, DEBUG_HDL_1a);
450: switch (regs->ah) {
451: case 0x00: handle_1a00(regs); break;
452: case 0x01: handle_1a01(regs); break;
453: case 0x02: handle_1a02(regs); break;
454: case 0x03: handle_1a03(regs); break;
455: case 0x04: handle_1a04(regs); break;
456: case 0x05: handle_1a05(regs); break;
457: case 0x06: handle_1a06(regs); break;
458: case 0x07: handle_1a07(regs); break;
459: case 0xb1: handle_1ab1(regs); break;
460: default: handle_1aXX(regs); break;
461: }
462: }
463:
464: // INT 08h System Timer ISR Entry Point
465: void VISIBLE16
1.1.1.2 root 466: handle_08(void)
1.1 root 467: {
468: debug_isr(DEBUG_ISR_08);
469:
470: floppy_tick();
471:
472: u32 counter = GET_BDA(timer_counter);
473: counter++;
474: // compare to one days worth of timer ticks at 18.2 hz
475: if (counter >= TICKS_PER_DAY) {
476: // there has been a midnight rollover at this point
477: counter = 0;
478: SET_BDA(timer_rollover, GET_BDA(timer_rollover) + 1);
479: }
480:
481: SET_BDA(timer_counter, counter);
482:
1.1.1.3 root 483: usb_check_event();
1.1 root 484:
485: // chain to user timer tick INT #0x1c
486: u32 eax=0, flags;
487: call16_simpint(0x1c, &eax, &flags);
488:
489: eoi_pic1();
490: }
491:
492:
493: /****************************************************************
494: * Periodic timer
495: ****************************************************************/
496:
497: void
1.1.1.2 root 498: useRTC(void)
1.1 root 499: {
500: u16 ebda_seg = get_ebda_seg();
501: int count = GET_EBDA2(ebda_seg, RTCusers);
502: SET_EBDA2(ebda_seg, RTCusers, count+1);
503: if (count)
504: return;
505: // Turn on the Periodic Interrupt timer
506: u8 bRegister = inb_cmos(CMOS_STATUS_B);
507: outb_cmos(bRegister | RTC_B_PIE, CMOS_STATUS_B);
508: }
509:
510: void
1.1.1.2 root 511: releaseRTC(void)
1.1 root 512: {
513: u16 ebda_seg = get_ebda_seg();
514: int count = GET_EBDA2(ebda_seg, RTCusers);
515: SET_EBDA2(ebda_seg, RTCusers, count-1);
516: if (count != 1)
517: return;
518: // Clear the Periodic Interrupt.
519: u8 bRegister = inb_cmos(CMOS_STATUS_B);
520: outb_cmos(bRegister & ~RTC_B_PIE, CMOS_STATUS_B);
521: }
522:
523: static int
524: set_usertimer(u32 usecs, u16 seg, u16 offset)
525: {
526: if (GET_BDA(rtc_wait_flag) & RWS_WAIT_PENDING)
527: return -1;
528:
529: // Interval not already set.
530: SET_BDA(rtc_wait_flag, RWS_WAIT_PENDING); // Set status byte.
531: SET_BDA(user_wait_complete_flag, SEGOFF(seg, offset));
532: SET_BDA(user_wait_timeout, usecs);
533: useRTC();
534: return 0;
535: }
536:
537: static void
1.1.1.2 root 538: clear_usertimer(void)
1.1 root 539: {
540: if (!(GET_BDA(rtc_wait_flag) & RWS_WAIT_PENDING))
541: return;
542: // Turn off status byte.
543: SET_BDA(rtc_wait_flag, 0);
544: releaseRTC();
545: }
546:
547: #define RET_ECLOCKINUSE 0x83
548:
549: // Wait for CX:DX microseconds
550: void
551: handle_1586(struct bregs *regs)
552: {
553: // Use the rtc to wait for the specified time.
554: u8 statusflag = 0;
555: u32 count = (regs->cx << 16) | regs->dx;
556: int ret = set_usertimer(count, GET_SEG(SS), (u32)&statusflag);
557: if (ret) {
558: set_code_invalid(regs, RET_ECLOCKINUSE);
559: return;
560: }
561: while (!statusflag)
562: wait_irq();
563: set_success(regs);
564: }
565:
566: // Set Interval requested.
567: static void
568: handle_158300(struct bregs *regs)
569: {
570: int ret = set_usertimer((regs->cx << 16) | regs->dx, regs->es, regs->bx);
571: if (ret)
572: // Interval already set.
573: set_code_invalid(regs, RET_EUNSUPPORTED);
574: else
575: set_success(regs);
576: }
577:
578: // Clear interval requested
579: static void
580: handle_158301(struct bregs *regs)
581: {
582: clear_usertimer();
583: set_success(regs);
584: }
585:
586: static void
587: handle_1583XX(struct bregs *regs)
588: {
589: set_code_unimplemented(regs, RET_EUNSUPPORTED);
590: regs->al--;
591: }
592:
593: void
594: handle_1583(struct bregs *regs)
595: {
596: switch (regs->al) {
597: case 0x00: handle_158300(regs); break;
598: case 0x01: handle_158301(regs); break;
599: default: handle_1583XX(regs); break;
600: }
601: }
602:
603: #define USEC_PER_RTC DIV_ROUND_CLOSEST(1000000, 1024)
604:
605: // int70h: IRQ8 - CMOS RTC
606: void VISIBLE16
1.1.1.2 root 607: handle_70(void)
1.1 root 608: {
609: debug_isr(DEBUG_ISR_70);
610:
611: // Check which modes are enabled and have occurred.
612: u8 registerB = inb_cmos(CMOS_STATUS_B);
613: u8 registerC = inb_cmos(CMOS_STATUS_C);
614:
615: if (!(registerB & (RTC_B_PIE|RTC_B_AIE)))
616: goto done;
617: if (registerC & RTC_B_AIE) {
618: // Handle Alarm Interrupt.
619: u32 eax=0, flags;
620: call16_simpint(0x4a, &eax, &flags);
621: }
622: if (!(registerC & RTC_B_PIE))
623: goto done;
624:
625: // Handle Periodic Interrupt.
626:
627: check_preempt();
628:
629: if (!GET_BDA(rtc_wait_flag))
630: goto done;
631:
632: // Wait Interval (Int 15, AH=83) active.
633: u32 time = GET_BDA(user_wait_timeout); // Time left in microseconds.
634: if (time < USEC_PER_RTC) {
635: // Done waiting - write to specified flag byte.
636: struct segoff_s segoff = GET_BDA(user_wait_complete_flag);
637: u16 ptr_seg = segoff.seg;
638: u8 *ptr_far = (u8*)(segoff.offset+0);
639: u8 oldval = GET_FARVAR(ptr_seg, *ptr_far);
640: SET_FARVAR(ptr_seg, *ptr_far, oldval | 0x80);
641:
642: clear_usertimer();
643: } else {
644: // Continue waiting.
645: time -= USEC_PER_RTC;
646: SET_BDA(user_wait_timeout, time);
647: }
648:
649: done:
650: eoi_pic2();
651: }
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